1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * drivers/net/ethernet/ibm/emac/core.h
4  *
5  * Driver for PowerPC 4xx on-chip ethernet controller.
6  *
7  * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
8  *                <benh@kernel.crashing.org>
9  *
10  * Based on the arch/ppc version of the driver:
11  *
12  * Copyright (c) 2004, 2005 Zultys Technologies.
13  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
14  *
15  * Based on original work by
16  *      Armin Kuster <akuster@mvista.com>
17  * 	Johnnie Peters <jpeters@mvista.com>
18  *      Copyright 2000, 2001 MontaVista Softare Inc.
19  */
20 #ifndef __IBM_NEWEMAC_CORE_H
21 #define __IBM_NEWEMAC_CORE_H
22 
23 #include <linux/module.h>
24 #include <linux/list.h>
25 #include <linux/kernel.h>
26 #include <linux/interrupt.h>
27 #include <linux/netdevice.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/spinlock.h>
30 #include <linux/slab.h>
31 
32 #include <asm/io.h>
33 #include <asm/dcr.h>
34 
35 #include "emac.h"
36 #include "phy.h"
37 #include "zmii.h"
38 #include "rgmii.h"
39 #include "mal.h"
40 #include "tah.h"
41 #include "debug.h"
42 
43 #define NUM_TX_BUFF			CONFIG_IBM_EMAC_TXB
44 #define NUM_RX_BUFF			CONFIG_IBM_EMAC_RXB
45 
46 /* Simple sanity check */
47 #if NUM_TX_BUFF > 256 || NUM_RX_BUFF > 256
48 #error Invalid number of buffer descriptors (greater than 256)
49 #endif
50 
51 #define EMAC_MIN_MTU			46
52 
53 /* Maximum L2 header length (VLAN tagged, no FCS) */
54 #define EMAC_MTU_OVERHEAD		(6 * 2 + 2 + 4)
55 
56 /* RX BD size for the given MTU */
emac_rx_size(int mtu)57 static inline int emac_rx_size(int mtu)
58 {
59 	if (mtu > ETH_DATA_LEN)
60 		return MAL_MAX_RX_SIZE;
61 	else
62 		return mal_rx_size(ETH_DATA_LEN + EMAC_MTU_OVERHEAD);
63 }
64 
65 /* Size of RX skb for the given MTU */
emac_rx_skb_size(int mtu)66 static inline int emac_rx_skb_size(int mtu)
67 {
68 	int size = max(mtu + EMAC_MTU_OVERHEAD, emac_rx_size(mtu));
69 
70 	return SKB_DATA_ALIGN(size + NET_IP_ALIGN) + NET_SKB_PAD;
71 }
72 
73 /* RX DMA sync size */
emac_rx_sync_size(int mtu)74 static inline int emac_rx_sync_size(int mtu)
75 {
76 	return SKB_DATA_ALIGN(emac_rx_size(mtu) + NET_IP_ALIGN);
77 }
78 
79 /* Driver statistcs is split into two parts to make it more cache friendly:
80  *   - normal statistics (packet count, etc)
81  *   - error statistics
82  *
83  * When statistics is requested by ethtool, these parts are concatenated,
84  * normal one goes first.
85  *
86  * Please, keep these structures in sync with emac_stats_keys.
87  */
88 
89 /* Normal TX/RX Statistics */
90 struct emac_stats {
91 	u64 rx_packets;
92 	u64 rx_bytes;
93 	u64 tx_packets;
94 	u64 tx_bytes;
95 	u64 rx_packets_csum;
96 	u64 tx_packets_csum;
97 };
98 
99 /* Error statistics */
100 struct emac_error_stats {
101 	u64 tx_undo;
102 
103 	/* Software RX Errors */
104 	u64 rx_dropped_stack;
105 	u64 rx_dropped_oom;
106 	u64 rx_dropped_error;
107 	u64 rx_dropped_resize;
108 	u64 rx_dropped_mtu;
109 	u64 rx_stopped;
110 	/* BD reported RX errors */
111 	u64 rx_bd_errors;
112 	u64 rx_bd_overrun;
113 	u64 rx_bd_bad_packet;
114 	u64 rx_bd_runt_packet;
115 	u64 rx_bd_short_event;
116 	u64 rx_bd_alignment_error;
117 	u64 rx_bd_bad_fcs;
118 	u64 rx_bd_packet_too_long;
119 	u64 rx_bd_out_of_range;
120 	u64 rx_bd_in_range;
121 	/* EMAC IRQ reported RX errors */
122 	u64 rx_parity;
123 	u64 rx_fifo_overrun;
124 	u64 rx_overrun;
125 	u64 rx_bad_packet;
126 	u64 rx_runt_packet;
127 	u64 rx_short_event;
128 	u64 rx_alignment_error;
129 	u64 rx_bad_fcs;
130 	u64 rx_packet_too_long;
131 	u64 rx_out_of_range;
132 	u64 rx_in_range;
133 
134 	/* Software TX Errors */
135 	u64 tx_dropped;
136 	/* BD reported TX errors */
137 	u64 tx_bd_errors;
138 	u64 tx_bd_bad_fcs;
139 	u64 tx_bd_carrier_loss;
140 	u64 tx_bd_excessive_deferral;
141 	u64 tx_bd_excessive_collisions;
142 	u64 tx_bd_late_collision;
143 	u64 tx_bd_multple_collisions;
144 	u64 tx_bd_single_collision;
145 	u64 tx_bd_underrun;
146 	u64 tx_bd_sqe;
147 	/* EMAC IRQ reported TX errors */
148 	u64 tx_parity;
149 	u64 tx_underrun;
150 	u64 tx_sqe;
151 	u64 tx_errors;
152 };
153 
154 #define EMAC_ETHTOOL_STATS_COUNT	((sizeof(struct emac_stats) + \
155 					  sizeof(struct emac_error_stats)) \
156 					 / sizeof(u64))
157 
158 struct emac_instance {
159 	struct net_device		*ndev;
160 	struct emac_regs		__iomem *emacp;
161 	struct platform_device		*ofdev;
162 	struct device_node		**blist; /* bootlist entry */
163 
164 	/* MAL linkage */
165 	u32				mal_ph;
166 	struct platform_device		*mal_dev;
167 	u32				mal_rx_chan;
168 	u32				mal_tx_chan;
169 	struct mal_instance		*mal;
170 	struct mal_commac		commac;
171 
172 	/* PHY infos */
173 	phy_interface_t			phy_mode;
174 	u32				phy_map;
175 	u32				phy_address;
176 	u32				phy_feat_exc;
177 	struct mii_phy			phy;
178 	struct mutex			link_lock;
179 	struct delayed_work		link_work;
180 	int				link_polling;
181 
182 	/* GPCS PHY infos */
183 	u32				gpcs_address;
184 
185 	/* Shared MDIO if any */
186 	u32				mdio_ph;
187 	struct platform_device		*mdio_dev;
188 	struct emac_instance		*mdio_instance;
189 	struct mutex			mdio_lock;
190 
191 	/* Device-tree based phy configuration */
192 	struct mii_bus			*mii_bus;
193 	struct phy_device		*phy_dev;
194 
195 	/* ZMII infos if any */
196 	u32				zmii_ph;
197 	u32				zmii_port;
198 	struct platform_device		*zmii_dev;
199 
200 	/* RGMII infos if any */
201 	u32				rgmii_ph;
202 	u32				rgmii_port;
203 	struct platform_device		*rgmii_dev;
204 
205 	/* TAH infos if any */
206 	u32				tah_ph;
207 	u32				tah_port;
208 	struct platform_device		*tah_dev;
209 
210 	/* IRQs */
211 	int				wol_irq;
212 	int				emac_irq;
213 
214 	/* OPB bus frequency in Mhz */
215 	u32				opb_bus_freq;
216 
217 	/* Cell index within an ASIC (for clk mgmnt) */
218 	u32				cell_index;
219 
220 	/* Max supported MTU */
221 	u32				max_mtu;
222 
223 	/* Feature bits (from probe table) */
224 	unsigned int			features;
225 
226 	/* Tx and Rx fifo sizes & other infos in bytes */
227 	u32				tx_fifo_size;
228 	u32				tx_fifo_size_gige;
229 	u32				rx_fifo_size;
230 	u32				rx_fifo_size_gige;
231 	u32				fifo_entry_size;
232 	u32				mal_burst_size; /* move to MAL ? */
233 
234 	/* IAHT and GAHT filter parameterization */
235 	u32				xaht_slots_shift;
236 	u32				xaht_width_shift;
237 
238 	/* Descriptor management
239 	 */
240 	struct mal_descriptor		*tx_desc;
241 	int				tx_cnt;
242 	int				tx_slot;
243 	int				ack_slot;
244 
245 	struct mal_descriptor		*rx_desc;
246 	int				rx_slot;
247 	struct sk_buff			*rx_sg_skb;	/* 1 */
248 	int 				rx_skb_size;
249 	int				rx_sync_size;
250 
251 	struct sk_buff			*tx_skb[NUM_TX_BUFF];
252 	struct sk_buff			*rx_skb[NUM_RX_BUFF];
253 
254 	/* Stats
255 	 */
256 	struct emac_error_stats		estats;
257 	struct emac_stats 		stats;
258 
259 	/* Misc
260 	 */
261 	int				reset_failed;
262 	int				stop_timeout;	/* in us */
263 	int				no_mcast;
264 	int				mcast_pending;
265 	int				opened;
266 	struct work_struct		reset_work;
267 	spinlock_t			lock;
268 };
269 
270 /*
271  * Features of various EMAC implementations
272  */
273 
274 /*
275  * No flow control on 40x according to the original driver
276  */
277 #define EMAC_FTR_NO_FLOW_CONTROL_40x	0x00000001
278 /*
279  * Cell is an EMAC4
280  */
281 #define EMAC_FTR_EMAC4			0x00000002
282 /*
283  * For the 440SPe, AMCC inexplicably changed the polarity of
284  * the "operation complete" bit in the MII control register.
285  */
286 #define EMAC_FTR_STACR_OC_INVERT	0x00000004
287 /*
288  * Set if we have a TAH.
289  */
290 #define EMAC_FTR_HAS_TAH		0x00000008
291 /*
292  * Set if we have a ZMII.
293  */
294 #define EMAC_FTR_HAS_ZMII		0x00000010
295 /*
296  * Set if we have a RGMII.
297  */
298 #define EMAC_FTR_HAS_RGMII		0x00000020
299 /*
300  * Set if we have new type STACR with STAOPC
301  */
302 #define EMAC_FTR_HAS_NEW_STACR		0x00000040
303 /*
304  * Set if we need phy clock workaround for 440gx
305  */
306 #define EMAC_FTR_440GX_PHY_CLK_FIX	0x00000080
307 /*
308  * Set if we need phy clock workaround for 440ep or 440gr
309  */
310 #define EMAC_FTR_440EP_PHY_CLK_FIX	0x00000100
311 /*
312  * The 405EX and 460EX contain the EMAC4SYNC core
313  */
314 #define EMAC_FTR_EMAC4SYNC		0x00000200
315 /*
316  * Set if we need phy clock workaround for 460ex or 460gt
317  */
318 #define EMAC_FTR_460EX_PHY_CLK_FIX	0x00000400
319 /*
320  * APM821xx requires Jumbo frame size set explicitly
321  */
322 #define EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE	0x00000800
323 /*
324  * APM821xx does not support Half Duplex mode
325  */
326 #define EMAC_FTR_APM821XX_NO_HALF_DUPLEX	0x00001000
327 
328 /* Right now, we don't quite handle the always/possible masks on the
329  * most optimal way as we don't have a way to say something like
330  * always EMAC4. Patches welcome.
331  */
332 enum {
333 	EMAC_FTRS_ALWAYS	= 0,
334 
335 	EMAC_FTRS_POSSIBLE	=
336 #ifdef CONFIG_IBM_EMAC_EMAC4
337 	    EMAC_FTR_EMAC4	| EMAC_FTR_EMAC4SYNC	|
338 	    EMAC_FTR_HAS_NEW_STACR	|
339 	    EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX |
340 #endif
341 #ifdef CONFIG_IBM_EMAC_TAH
342 	    EMAC_FTR_HAS_TAH	|
343 #endif
344 #ifdef CONFIG_IBM_EMAC_ZMII
345 	    EMAC_FTR_HAS_ZMII	|
346 #endif
347 #ifdef CONFIG_IBM_EMAC_RGMII
348 	    EMAC_FTR_HAS_RGMII	|
349 #endif
350 #ifdef CONFIG_IBM_EMAC_NO_FLOW_CTRL
351 	    EMAC_FTR_NO_FLOW_CONTROL_40x |
352 #endif
353 	EMAC_FTR_460EX_PHY_CLK_FIX |
354 	EMAC_FTR_440EP_PHY_CLK_FIX |
355 	EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
356 	EMAC_FTR_APM821XX_NO_HALF_DUPLEX,
357 };
358 
emac_has_feature(struct emac_instance * dev,unsigned long feature)359 static inline int emac_has_feature(struct emac_instance *dev,
360 				   unsigned long feature)
361 {
362 	return (EMAC_FTRS_ALWAYS & feature) ||
363 	       (EMAC_FTRS_POSSIBLE & dev->features & feature);
364 }
365 
366 /*
367  * Various instances of the EMAC core have varying 1) number of
368  * address match slots, 2) width of the registers for handling address
369  * match slots, 3) number of registers for handling address match
370  * slots and 4) base offset for those registers.
371  *
372  * These macros and inlines handle these differences based on
373  * parameters supplied by the device structure which are, in turn,
374  * initialized based on the "compatible" entry in the device tree.
375  */
376 
377 #define	EMAC4_XAHT_SLOTS_SHIFT		6
378 #define	EMAC4_XAHT_WIDTH_SHIFT		4
379 
380 #define	EMAC4SYNC_XAHT_SLOTS_SHIFT	8
381 #define	EMAC4SYNC_XAHT_WIDTH_SHIFT	5
382 
383 /* The largest span between slots and widths above is 3 */
384 #define	EMAC_XAHT_MAX_REGS		(1 << 3)
385 
386 #define	EMAC_XAHT_SLOTS(dev)         	(1 << (dev)->xaht_slots_shift)
387 #define	EMAC_XAHT_WIDTH(dev)         	(1 << (dev)->xaht_width_shift)
388 #define	EMAC_XAHT_REGS(dev)          	(1 << ((dev)->xaht_slots_shift - \
389 					       (dev)->xaht_width_shift))
390 
391 #define	EMAC_XAHT_CRC_TO_SLOT(dev, crc)			\
392 	((EMAC_XAHT_SLOTS(dev) - 1) -			\
393 	 ((crc) >> ((sizeof (u32) * BITS_PER_BYTE) -	\
394 		    (dev)->xaht_slots_shift)))
395 
396 #define	EMAC_XAHT_SLOT_TO_REG(dev, slot)		\
397 	((slot) >> (dev)->xaht_width_shift)
398 
399 #define	EMAC_XAHT_SLOT_TO_MASK(dev, slot)		\
400 	((u32)(1 << (EMAC_XAHT_WIDTH(dev) - 1)) >>	\
401 	 ((slot) & (u32)(EMAC_XAHT_WIDTH(dev) - 1)))
402 
emac_xaht_base(struct emac_instance * dev)403 static inline u32 *emac_xaht_base(struct emac_instance *dev)
404 {
405 	struct emac_regs __iomem *p = dev->emacp;
406 	int offset;
407 
408 	/* The first IAHT entry always is the base of the block of
409 	 * IAHT and GAHT registers.
410 	 */
411 	if (emac_has_feature(dev, EMAC_FTR_EMAC4SYNC))
412 		offset = offsetof(struct emac_regs, u1.emac4sync.iaht1);
413 	else
414 		offset = offsetof(struct emac_regs, u0.emac4.iaht1);
415 
416 	return (u32 *)((ptrdiff_t)p + offset);
417 }
418 
emac_gaht_base(struct emac_instance * dev)419 static inline u32 *emac_gaht_base(struct emac_instance *dev)
420 {
421 	/* GAHT registers always come after an identical number of
422 	 * IAHT registers.
423 	 */
424 	return emac_xaht_base(dev) + EMAC_XAHT_REGS(dev);
425 }
426 
emac_iaht_base(struct emac_instance * dev)427 static inline u32 *emac_iaht_base(struct emac_instance *dev)
428 {
429 	/* IAHT registers always come before an identical number of
430 	 * GAHT registers.
431 	 */
432 	return emac_xaht_base(dev);
433 }
434 
435 /* Ethtool get_regs complex data.
436  * We want to get not just EMAC registers, but also MAL, ZMII, RGMII, TAH
437  * when available.
438  *
439  * Returned BLOB consists of the ibm_emac_ethtool_regs_hdr,
440  * MAL registers, EMAC registers and optional ZMII, RGMII, TAH registers.
441  * Each register component is preceded with emac_ethtool_regs_subhdr.
442  * Order of the optional headers follows their relative bit posititions
443  * in emac_ethtool_regs_hdr.components
444  */
445 #define EMAC_ETHTOOL_REGS_ZMII		0x00000001
446 #define EMAC_ETHTOOL_REGS_RGMII		0x00000002
447 #define EMAC_ETHTOOL_REGS_TAH		0x00000004
448 
449 struct emac_ethtool_regs_hdr {
450 	u32 components;
451 };
452 
453 struct emac_ethtool_regs_subhdr {
454 	u32 version;
455 	u32 index;
456 };
457 
458 #define EMAC_ETHTOOL_REGS_VER		3
459 #define EMAC4_ETHTOOL_REGS_VER		4
460 #define EMAC4SYNC_ETHTOOL_REGS_VER	5
461 
462 #endif /* __IBM_NEWEMAC_CORE_H */
463