1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004 Maciej W. Rozycki
13 */
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/mm.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/smp_lock.h>
21 #include <linux/spinlock.h>
22
23 #include <asm/bootinfo.h>
24 #include <asm/branch.h>
25 #include <asm/break.h>
26 #include <asm/cpu.h>
27 #include <asm/fpu.h>
28 #include <asm/module.h>
29 #include <asm/pgtable.h>
30 #include <asm/io.h>
31 #include <asm/ptrace.h>
32 #include <asm/watch.h>
33 #include <asm/system.h>
34 #include <asm/tlbdebug.h>
35 #include <asm/traps.h>
36 #include <asm/uaccess.h>
37 #include <asm/mmu_context.h>
38 #include <asm/cachectl.h>
39 #include <asm/types.h>
40
41 extern asmlinkage void __xtlb_mod(void);
42 extern asmlinkage void __xtlb_tlbl(void);
43 extern asmlinkage void __xtlb_tlbs(void);
44 extern asmlinkage void handle_adel(void);
45 extern asmlinkage void handle_ades(void);
46 extern asmlinkage void handle_ibe(void);
47 extern asmlinkage void handle_dbe(void);
48 extern asmlinkage void handle_sys(void);
49 extern asmlinkage void handle_bp(void);
50 extern asmlinkage void handle_ri(void);
51 extern asmlinkage void handle_cpu(void);
52 extern asmlinkage void handle_ov(void);
53 extern asmlinkage void handle_tr(void);
54 extern asmlinkage void handle_fpe(void);
55 extern asmlinkage void handle_mdmx(void);
56 extern asmlinkage void handle_watch(void);
57 extern asmlinkage void handle_mcheck(void);
58 extern asmlinkage void handle_reserved(void);
59
60 extern int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
61 struct mips_fpu_soft_struct *ctx);
62
63 void (*board_be_init)(void);
64 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
65
66 int kstack_depth_to_print = 24;
67
68 /*
69 * These constant is for searching for possible module text segments.
70 * MODULE_RANGE is a guess of how much space is likely to be vmalloced.
71 */
72 #define MODULE_RANGE (8*1024*1024)
73
74 /*
75 * If the address is either in the .text section of the
76 * kernel, or in the vmalloc'ed module regions, it *may*
77 * be the address of a calling routine
78 */
79
80 #ifdef CONFIG_MODULES
81
82 extern struct module *module_list;
83 extern struct module kernel_module;
84
kernel_text_address(long addr)85 static inline int kernel_text_address(long addr)
86 {
87 extern char _stext, _etext;
88 int retval = 0;
89 struct module *mod;
90
91 if (addr >= (long) &_stext && addr <= (long) &_etext)
92 return 1;
93
94 for (mod = module_list; mod != &kernel_module; mod = mod->next) {
95 /* mod_bound tests for addr being inside the vmalloc'ed
96 * module area. Of course it'd be better to test only
97 * for the .text subset... */
98 if (mod_bound(addr, 0, mod)) {
99 retval = 1;
100 break;
101 }
102 }
103
104 return retval;
105 }
106
107 #else
108
kernel_text_address(long addr)109 static inline int kernel_text_address(long addr)
110 {
111 extern char _stext, _etext;
112
113 return (addr >= (long) &_stext && addr <= (long) &_etext);
114 }
115
116 #endif
117
118 /*
119 * This routine abuses get_user()/put_user() to reference pointers
120 * with at least a bit of error checking ...
121 */
show_stack(long * sp)122 void show_stack(long *sp)
123 {
124 int i;
125 long stackdata;
126
127 printk("Stack:");
128 i = 0;
129 while ((long) sp & (PAGE_SIZE - 1)) {
130 if (i && ((i % 4) == 0))
131 printk("\n ");
132 if (i > 40) {
133 printk(" ...");
134 break;
135 }
136
137 if (__get_user(stackdata, sp++)) {
138 printk(" (Bad stack address)");
139 break;
140 }
141
142 printk(" %016lx", stackdata);
143 i++;
144 }
145 printk("\n");
146 }
147
show_trace(long * sp)148 void show_trace(long *sp)
149 {
150 int i;
151 long addr;
152
153 printk("Call Trace:");
154 i = 0;
155 while ((long) sp & (PAGE_SIZE - 1)) {
156
157 if (__get_user(addr, sp++)) {
158 if (i && ((i % 3) == 0))
159 printk("\n ");
160 printk(" (Bad stack address)\n");
161 break;
162 }
163
164 /*
165 * If the address is either in the text segment of the
166 * kernel, or in the region which contains vmalloc'ed
167 * memory, it *may* be the address of a calling
168 * routine; if so, print it so that someone tracing
169 * down the cause of the crash will be able to figure
170 * out the call path that was taken.
171 */
172
173 if (kernel_text_address(addr)) {
174 if (i && ((i % 3) == 0))
175 printk("\n ");
176 if (i > 40) {
177 printk(" ...");
178 break;
179 }
180
181 printk(" [<%016lx>]", addr);
182 i++;
183 }
184 }
185 printk("\n");
186 }
187
show_trace_task(struct task_struct * tsk)188 void show_trace_task(struct task_struct *tsk)
189 {
190 show_trace((long *)tsk->thread.reg29);
191 }
192
show_code(unsigned int * pc)193 void show_code(unsigned int *pc)
194 {
195 long i;
196
197 printk("\nCode:");
198
199 for(i = -3 ; i < 6 ; i++) {
200 unsigned int insn;
201 if (__get_user(insn, pc + i)) {
202 printk(" (Bad address in epc)\n");
203 break;
204 }
205 printk("%c%08x%c",(i?' ':'<'),insn,(i?' ':'>'));
206 }
207 }
208
show_regs(struct pt_regs * regs)209 void show_regs(struct pt_regs *regs)
210 {
211 printk("Cpu %d\n", smp_processor_id());
212 /* Saved main processor registers. */
213 printk("$0 : %016lx %016lx %016lx %016lx\n",
214 0UL, regs->regs[1], regs->regs[2], regs->regs[3]);
215 printk("$4 : %016lx %016lx %016lx %016lx\n",
216 regs->regs[4], regs->regs[5], regs->regs[6], regs->regs[7]);
217 printk("$8 : %016lx %016lx %016lx %016lx\n",
218 regs->regs[8], regs->regs[9], regs->regs[10], regs->regs[11]);
219 printk("$12 : %016lx %016lx %016lx %016lx\n",
220 regs->regs[12], regs->regs[13], regs->regs[14], regs->regs[15]);
221 printk("$16 : %016lx %016lx %016lx %016lx\n",
222 regs->regs[16], regs->regs[17], regs->regs[18], regs->regs[19]);
223 printk("$20 : %016lx %016lx %016lx %016lx\n",
224 regs->regs[20], regs->regs[21], regs->regs[22], regs->regs[23]);
225 printk("$24 : %016lx %016lx\n",
226 regs->regs[24], regs->regs[25]);
227 printk("$28 : %016lx %016lx %016lx %016lx\n",
228 regs->regs[28], regs->regs[29], regs->regs[30], regs->regs[31]);
229 printk("Hi : %016lx\n", regs->hi);
230 printk("Lo : %016lx\n", regs->lo);
231
232 /* Saved cp0 registers. */
233 printk("epc : %016lx %s\nbadvaddr: %016lx\n",
234 regs->cp0_epc, print_tainted(), regs->cp0_badvaddr);
235 printk("Status : %08x [ ", (unsigned int) regs->cp0_status);
236
237 if (regs->cp0_status & ST0_KX) printk("KX ");
238 if (regs->cp0_status & ST0_SX) printk("SX ");
239 if (regs->cp0_status & ST0_UX) printk("UX ");
240 switch (regs->cp0_status & ST0_KSU) {
241 case KSU_USER: printk("USER "); break;
242 case KSU_SUPERVISOR: printk("SUPERVISOR "); break;
243 case KSU_KERNEL: printk("KERNEL "); break;
244 default: printk("BAD_MODE "); break;
245 }
246 if (regs->cp0_status & ST0_ERL) printk("ERL ");
247 if (regs->cp0_status & ST0_EXL) printk("EXL ");
248 if (regs->cp0_status & ST0_IE) printk("IE ");
249 printk("]\n");
250
251 printk("Cause : %08x\n", (unsigned int) regs->cp0_cause);
252 printk("PrId : %08x\n", read_c0_prid());
253 }
254
show_registers(struct pt_regs * regs)255 void show_registers(struct pt_regs *regs)
256 {
257 show_regs(regs);
258 printk("Process %s (pid: %d, stackpage=%016lx)\n",
259 current->comm, current->pid, (unsigned long) current);
260 show_stack((long *) regs->regs[29]);
261 show_trace((long *) regs->regs[29]);
262 show_code((unsigned int *) regs->cp0_epc);
263 printk("\n");
264 }
265
266 static spinlock_t die_lock = SPIN_LOCK_UNLOCKED;
267
__die(const char * str,struct pt_regs * regs,const char * file,const char * func,unsigned long line)268 void __die(const char * str, struct pt_regs * regs, const char * file,
269 const char * func, unsigned long line)
270 {
271 console_verbose();
272 spin_lock_irq(&die_lock);
273 printk("%s", str);
274 if (file && func)
275 printk(" in %s:%s, line %ld", file, func, line);
276 printk(":\n");
277 show_registers(regs);
278 spin_unlock_irq(&die_lock);
279 do_exit(SIGSEGV);
280 }
281
__die_if_kernel(const char * str,struct pt_regs * regs,const char * file,const char * func,unsigned long line)282 void __die_if_kernel(const char * str, struct pt_regs * regs,
283 const char * file, const char * func, unsigned long line)
284 {
285 if (!user_mode(regs))
286 __die(str, regs, file, func, line);
287 }
288
289 extern const struct exception_table_entry __start___dbe_table[];
290 extern const struct exception_table_entry __stop___dbe_table[];
291
__declare_dbe_table(void)292 void __declare_dbe_table(void)
293 {
294 __asm__ __volatile__(
295 ".section\t__dbe_table,\"a\"\n\t"
296 ".previous"
297 );
298 }
299
300 static inline unsigned long
search_one_table(const struct exception_table_entry * first,const struct exception_table_entry * last,unsigned long value)301 search_one_table(const struct exception_table_entry *first,
302 const struct exception_table_entry *last,
303 unsigned long value)
304 {
305 const struct exception_table_entry *mid;
306 long diff;
307
308 while (first < last) {
309 mid = (last - first) / 2 + first;
310 diff = mid->insn - value;
311 if (diff < 0)
312 first = mid + 1;
313 else
314 last = mid;
315 }
316 return (first == last && first->insn == value) ? first->nextinsn : 0;
317 }
318
319 extern spinlock_t modlist_lock;
320
321 static inline unsigned long
search_dbe_table(unsigned long addr)322 search_dbe_table(unsigned long addr)
323 {
324 unsigned long ret = 0;
325
326 #ifndef CONFIG_MODULES
327 /* There is only the kernel to search. */
328 ret = search_one_table(__start___dbe_table, __stop___dbe_table-1, addr);
329 return ret;
330 #else
331 unsigned long flags;
332
333 /* The kernel is the last "module" -- no need to treat it special. */
334 struct module *mp;
335 struct archdata *ap;
336
337 spin_lock_irqsave(&modlist_lock, flags);
338 for (mp = module_list; mp != NULL; mp = mp->next) {
339 if (!mod_member_present(mp, archdata_end) ||
340 !mod_archdata_member_present(mp, struct archdata,
341 dbe_table_end))
342 continue;
343 ap = (struct archdata *)(mp->archdata_start);
344
345 if (ap->dbe_table_start == NULL ||
346 !(mp->flags & (MOD_RUNNING | MOD_INITIALIZING)))
347 continue;
348 ret = search_one_table(ap->dbe_table_start,
349 ap->dbe_table_end - 1, addr);
350 if (ret)
351 break;
352 }
353 spin_unlock_irqrestore(&modlist_lock, flags);
354 return ret;
355 #endif
356 }
357
do_be(struct pt_regs * regs)358 asmlinkage void do_be(struct pt_regs *regs)
359 {
360 unsigned long new_epc;
361 unsigned long fixup = 0;
362 int data = regs->cp0_cause & 4;
363 int action = MIPS_BE_FATAL;
364
365 if (data && !user_mode(regs))
366 fixup = search_dbe_table(exception_epc(regs));
367
368 if (fixup)
369 action = MIPS_BE_FIXUP;
370
371 if (board_be_handler)
372 action = board_be_handler(regs, fixup != 0);
373
374 switch (action) {
375 case MIPS_BE_DISCARD:
376 return;
377 case MIPS_BE_FIXUP:
378 if (fixup) {
379 new_epc = fixup_exception(dpf_reg, fixup,
380 regs->cp0_epc);
381 regs->cp0_epc = new_epc;
382 return;
383 }
384 break;
385 default:
386 break;
387 }
388
389 /*
390 * Assume it would be too dangerous to continue ...
391 */
392 printk(KERN_ALERT "%s bus error, epc == %08lx, ra == %08lx\n",
393 data ? "Data" : "Instruction",
394 regs->cp0_epc, regs->regs[31]);
395 die_if_kernel("Oops", regs);
396 force_sig(SIGBUS, current);
397 }
398
get_insn_opcode(struct pt_regs * regs,unsigned int * opcode)399 static inline int get_insn_opcode(struct pt_regs *regs, unsigned int *opcode)
400 {
401 unsigned int *epc;
402
403 epc = (unsigned int *) regs->cp0_epc +
404 ((regs->cp0_cause & CAUSEF_BD) != 0);
405 if (!get_user(*opcode, epc))
406 return 0;
407
408 force_sig(SIGSEGV, current);
409 return 1;
410 }
411
412 /*
413 * ll/sc emulation
414 */
415
416 #define OPCODE 0xfc000000
417 #define BASE 0x03e00000
418 #define RT 0x001f0000
419 #define OFFSET 0x0000ffff
420 #define LL 0xc0000000
421 #define SC 0xe0000000
422
423 /*
424 * The ll_bit is cleared by r*_switch.S
425 */
426
427 unsigned long ll_bit;
428
429 static struct task_struct *ll_task = NULL;
430
simulate_ll(struct pt_regs * regs,unsigned int opcode)431 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
432 {
433 unsigned long value, *vaddr;
434 long offset;
435 int signal = 0;
436
437 /*
438 * analyse the ll instruction that just caused a ri exception
439 * and put the referenced address to addr.
440 */
441
442 /* sign extend offset */
443 offset = opcode & OFFSET;
444 offset <<= 16;
445 offset >>= 16;
446
447 vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset);
448
449 if ((unsigned long)vaddr & 3) {
450 signal = SIGBUS;
451 goto sig;
452 }
453 if (get_user(value, vaddr)) {
454 signal = SIGSEGV;
455 goto sig;
456 }
457
458 if (ll_task == NULL || ll_task == current) {
459 ll_bit = 1;
460 } else {
461 ll_bit = 0;
462 }
463 ll_task = current;
464
465 regs->regs[(opcode & RT) >> 16] = value;
466
467 compute_return_epc(regs);
468 return;
469
470 sig:
471 force_sig(signal, current);
472 }
473
simulate_sc(struct pt_regs * regs,unsigned int opcode)474 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
475 {
476 unsigned long *vaddr, reg;
477 long offset;
478 int signal = 0;
479
480 /*
481 * analyse the sc instruction that just caused a ri exception
482 * and put the referenced address to addr.
483 */
484
485 /* sign extend offset */
486 offset = opcode & OFFSET;
487 offset <<= 16;
488 offset >>= 16;
489
490 vaddr = (unsigned long *)((long)(regs->regs[(opcode & BASE) >> 21]) + offset);
491 reg = (opcode & RT) >> 16;
492
493 if ((unsigned long)vaddr & 3) {
494 signal = SIGBUS;
495 goto sig;
496 }
497 if (ll_bit == 0 || ll_task != current) {
498 regs->regs[reg] = 0;
499 compute_return_epc(regs);
500 return;
501 }
502
503 if (put_user(regs->regs[reg], vaddr)) {
504 signal = SIGSEGV;
505 goto sig;
506 }
507
508 regs->regs[reg] = 1;
509
510 compute_return_epc(regs);
511 return;
512
513 sig:
514 force_sig(signal, current);
515 }
516
517 /*
518 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
519 * opcodes are supposed to result in coprocessor unusable exceptions if
520 * executed on ll/sc-less processors. That's the theory. In practice a
521 * few processors such as NEC's VR4100 throw reserved instruction exceptions
522 * instead, so we're doing the emulation thing in both exception handlers.
523 */
simulate_llsc(struct pt_regs * regs)524 static inline int simulate_llsc(struct pt_regs *regs)
525 {
526 unsigned int opcode;
527
528 if (unlikely(get_insn_opcode(regs, &opcode)))
529 return -EFAULT;
530
531 if ((opcode & OPCODE) == LL) {
532 simulate_ll(regs, opcode);
533 return 0;
534 }
535 if ((opcode & OPCODE) == SC) {
536 simulate_sc(regs, opcode);
537 return 0;
538 }
539
540 return -EFAULT; /* Strange things going on ... */
541 }
542
do_ov(struct pt_regs * regs)543 asmlinkage void do_ov(struct pt_regs *regs)
544 {
545 siginfo_t info;
546
547 info.si_code = FPE_INTOVF;
548 info.si_signo = SIGFPE;
549 info.si_errno = 0;
550 info.si_addr = (void *)regs->cp0_epc;
551 force_sig_info(SIGFPE, &info, current);
552 }
553
554 /*
555 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
556 */
do_fpe(struct pt_regs * regs,unsigned long fcr31)557 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
558 {
559 if (fcr31 & FPU_CSR_UNI_X) {
560 int sig;
561
562 /*
563 * Unimplemented operation exception. If we've got the full
564 * software emulator on-board, let's use it...
565 *
566 * Force FPU to dump state into task/thread context. We're
567 * moving a lot of data here for what is probably a single
568 * instruction, but the alternative is to pre-decode the FP
569 * register operands before invoking the emulator, which seems
570 * a bit extreme for what should be an infrequent event.
571 */
572 save_fp(current);
573
574 /* Run the emulator */
575 sig = fpu_emulator_cop1Handler (0, regs,
576 ¤t->thread.fpu.soft);
577
578 /*
579 * We can't allow the emulated instruction to leave any of
580 * the cause bit set in $fcr31.
581 */
582 current->thread.fpu.soft.sr &= ~FPU_CSR_ALL_X;
583
584 /* Restore the hardware register state */
585 restore_fp(current);
586
587 /* If something went wrong, signal */
588 if (sig)
589 force_sig(sig, current);
590
591 return;
592 }
593
594 force_sig(SIGFPE, current);
595 }
596
do_bp(struct pt_regs * regs)597 asmlinkage void do_bp(struct pt_regs *regs)
598 {
599 unsigned int opcode, bcode;
600 siginfo_t info;
601
602 die_if_kernel("Break instruction in kernel code", regs);
603
604 if (get_insn_opcode(regs, &opcode))
605 return;
606
607 /*
608 * There is the ancient bug in the MIPS assemblers that the break
609 * code starts left to bit 16 instead to bit 6 in the opcode.
610 * Gas is bug-compatible, but not always, grrr...
611 * We handle both cases with a simple heuristics. --macro
612 */
613 bcode = ((opcode >> 6) & ((1 << 20) - 1));
614 if (bcode < (1 << 10))
615 bcode <<= 10;
616
617 /*
618 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
619 * insns, even for break codes that indicate arithmetic failures.
620 * Weird ...)
621 * But should we continue the brokenness??? --macro
622 */
623 switch (bcode) {
624 case BRK_OVERFLOW << 10:
625 case BRK_DIVZERO << 10:
626 if (bcode == (BRK_DIVZERO << 10))
627 info.si_code = FPE_INTDIV;
628 else
629 info.si_code = FPE_INTOVF;
630 info.si_signo = SIGFPE;
631 info.si_errno = 0;
632 info.si_addr = (void *)regs->cp0_epc;
633 force_sig_info(SIGFPE, &info, current);
634 break;
635 default:
636 force_sig(SIGTRAP, current);
637 }
638 }
639
do_tr(struct pt_regs * regs)640 asmlinkage void do_tr(struct pt_regs *regs)
641 {
642 unsigned int opcode, tcode = 0;
643 siginfo_t info;
644
645 if (get_insn_opcode(regs, &opcode))
646 return;
647
648 /* Immediate versions don't provide a code. */
649 if (!(opcode & OPCODE))
650 tcode = ((opcode >> 6) & ((1 << 10) - 1));
651
652 /*
653 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
654 * insns, even for trap codes that indicate arithmetic failures.
655 * Weird ...)
656 * But should we continue the brokenness??? --macro
657 */
658 switch (tcode) {
659 case BRK_OVERFLOW:
660 case BRK_DIVZERO:
661 if (tcode == BRK_DIVZERO)
662 info.si_code = FPE_INTDIV;
663 else
664 info.si_code = FPE_INTOVF;
665 info.si_signo = SIGFPE;
666 info.si_errno = 0;
667 info.si_addr = (void *)regs->cp0_epc;
668 force_sig_info(SIGFPE, &info, current);
669 break;
670 default:
671 force_sig(SIGTRAP, current);
672 }
673 }
674
do_ri(struct pt_regs * regs)675 asmlinkage void do_ri(struct pt_regs *regs)
676 {
677 die_if_kernel("Reserved instruction in kernel code", regs);
678
679 if (!cpu_has_llsc)
680 if (!simulate_llsc(regs))
681 return;
682
683 force_sig(SIGILL, current);
684 }
685
do_cpu(struct pt_regs * regs)686 asmlinkage void do_cpu(struct pt_regs *regs)
687 {
688 unsigned int cpid;
689
690 die_if_kernel("do_cpu invoked from kernel context!", regs);
691
692 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
693
694 switch (cpid) {
695 case 0:
696 if (cpu_has_llsc)
697 break;
698
699 if (!simulate_llsc(regs))
700 return;
701 break;
702
703 case 1:
704 own_fpu();
705 if (current->used_math) { /* Using the FPU again. */
706 restore_fp(current);
707 } else { /* First time FPU user. */
708 init_fpu();
709 current->used_math = 1;
710 }
711
712 if (!cpu_has_fpu) {
713 int sig = fpu_emulator_cop1Handler(0, regs,
714 ¤t->thread.fpu.soft);
715 if (sig)
716 force_sig(sig, current);
717 }
718
719 return;
720
721 case 2:
722 case 3:
723 break;
724 }
725
726 force_sig(SIGILL, current);
727 }
728
do_mdmx(struct pt_regs * regs)729 asmlinkage void do_mdmx(struct pt_regs *regs)
730 {
731 force_sig(SIGILL, current);
732 }
733
do_watch(struct pt_regs * regs)734 asmlinkage void do_watch(struct pt_regs *regs)
735 {
736 /*
737 * We use the watch exception where available to detect stack
738 * overflows.
739 */
740 dump_tlb_all();
741 show_regs(regs);
742 panic("Caught WATCH exception - probably caused by stack overflow.");
743 }
744
do_mcheck(struct pt_regs * regs)745 asmlinkage void do_mcheck(struct pt_regs *regs)
746 {
747 show_regs(regs);
748 dump_tlb_all();
749 /*
750 * Some chips may have other causes of machine check (e.g. SB1
751 * graduation timer)
752 */
753 panic("Caught Machine Check exception - %scaused by multiple "
754 "matching entries in the TLB.",
755 (regs->cp0_status & ST0_TS) ? "" : "not ");
756 }
757
do_reserved(struct pt_regs * regs)758 asmlinkage void do_reserved(struct pt_regs *regs)
759 {
760 /*
761 * Game over - no way to handle this if it ever occurs. Most probably
762 * caused by a new unknown cpu type or after another deadly
763 * hard/software error.
764 */
765 show_regs(regs);
766 panic("Caught reserved exception %ld - should not happen.",
767 (regs->cp0_cause & 0x7f) >> 2);
768 }
769
770 unsigned long exception_handlers[32];
771
772 /*
773 * As a side effect of the way this is implemented we're limited
774 * to interrupt handlers in the address range from
775 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
776 */
set_except_vector(int n,void * addr)777 void *set_except_vector(int n, void *addr)
778 {
779 unsigned long handler = (unsigned long) addr;
780 unsigned long old_handler = exception_handlers[n];
781
782 exception_handlers[n] = handler;
783 if (n == 0 && cpu_has_divec) {
784 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
785 (0x03ffffff & (handler >> 2));
786 flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
787 }
788 return (void *)old_handler;
789 }
790
791 asmlinkage int (*save_fp_context)(struct sigcontext *sc);
792 asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
793
794 asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
795 asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
796
797 extern asmlinkage int _save_fp_context(struct sigcontext *sc);
798 extern asmlinkage int _restore_fp_context(struct sigcontext *sc);
799
800 extern asmlinkage int _save_fp_context32(struct sigcontext32 *sc);
801 extern asmlinkage int _restore_fp_context32(struct sigcontext32 *sc);
802
803 extern asmlinkage int fpu_emulator_save_context(struct sigcontext *sc);
804 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext *sc);
805
806 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 *sc);
807 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 *sc);
808
per_cpu_trap_init(void)809 void __init per_cpu_trap_init(void)
810 {
811 unsigned int cpu = smp_processor_id();
812
813 /* Some firmware leaves the BEV flag set, clear it. */
814 clear_c0_status(ST0_CU1|ST0_CU2|ST0_CU3|ST0_BEV);
815 set_c0_status(ST0_CU0|ST0_FR|ST0_KX|ST0_SX|ST0_UX);
816
817 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
818 set_c0_status(ST0_XX);
819
820 /*
821 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
822 * interrupt processing overhead. Use it where available.
823 */
824 if (cpu_has_divec)
825 set_c0_cause(CAUSEF_IV);
826
827 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
828 write_c0_context(((long)(&pgd_current[cpu])) << 23);
829 write_c0_wired(0);
830
831 atomic_inc(&init_mm.mm_count);
832 current->active_mm = &init_mm;
833 if (current->mm)
834 BUG();
835 enter_lazy_tlb(&init_mm, current, cpu);
836 }
837
trap_init(void)838 void __init trap_init(void)
839 {
840 extern char except_vec0_generic;
841 extern char except_vec3_generic, except_vec3_r4000;
842 extern char except_vec4;
843 unsigned long i;
844
845 per_cpu_trap_init();
846
847 /* Copy the generic exception handlers to their final destination. */
848 memcpy((void *) KSEG0 , &except_vec0_generic, 0x80);
849 memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
850
851 /*
852 * Setup default vectors
853 */
854 for (i = 0; i <= 31; i++)
855 set_except_vector(i, handle_reserved);
856
857 /*
858 * Only some CPUs have the watch exceptions.
859 */
860 if (cpu_has_watch)
861 set_except_vector(23, handle_watch);
862
863 /*
864 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
865 * interrupt processing overhead. Use it where available.
866 */
867 if (cpu_has_divec)
868 memcpy((void *)(KSEG0 + 0x200), &except_vec4, 0x8);
869
870 /*
871 * The Data Bus Errors / Instruction Bus Errors are signaled
872 * by external hardware. Therefore these two exceptions
873 * may have board specific handlers.
874 */
875 if (board_be_init)
876 board_be_init();
877
878 set_except_vector(1, __xtlb_mod);
879 set_except_vector(2, __xtlb_tlbl);
880 set_except_vector(3, __xtlb_tlbs);
881 set_except_vector(4, handle_adel);
882 set_except_vector(5, handle_ades);
883
884 set_except_vector(6, handle_ibe);
885 set_except_vector(7, handle_dbe);
886
887 set_except_vector(8, handle_sys);
888 set_except_vector(9, handle_bp);
889 set_except_vector(10, handle_ri);
890 set_except_vector(11, handle_cpu);
891 set_except_vector(12, handle_ov);
892 set_except_vector(13, handle_tr);
893 set_except_vector(22, handle_mdmx);
894
895 if (cpu_has_fpu && !cpu_has_nofpuex)
896 set_except_vector(15, handle_fpe);
897
898 if (cpu_has_mcheck)
899 set_except_vector(24, handle_mcheck);
900
901 if (cpu_has_vce)
902 memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x100);
903 else if (cpu_has_4kex)
904 memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
905 else
906 memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80);
907
908 if (current_cpu_data.cputype == CPU_R6000 ||
909 current_cpu_data.cputype == CPU_R6000A) {
910 /*
911 * The R6000 is the only R-series CPU that features a machine
912 * check exception (similar to the R4000 cache error) and
913 * unaligned ldc1/sdc1 exception. The handlers have not been
914 * written yet. Well, anyway there is no R6000 machine on the
915 * current list of targets for Linux/MIPS.
916 * (Duh, crap, there is someone with a tripple R6k machine)
917 */
918 //set_except_vector(14, handle_mc);
919 //set_except_vector(15, handle_ndc);
920 }
921
922 if (cpu_has_fpu) {
923 save_fp_context = _save_fp_context;
924 restore_fp_context = _restore_fp_context;
925 save_fp_context32 = _save_fp_context32;
926 restore_fp_context32 = _restore_fp_context32;
927 } else {
928 save_fp_context = fpu_emulator_save_context;
929 restore_fp_context = fpu_emulator_restore_context;
930 save_fp_context32 = fpu_emulator_save_context32;
931 restore_fp_context32 = fpu_emulator_restore_context32;
932 }
933
934 flush_icache_range(KSEG0, KSEG0 + 0x400);
935
936 atomic_inc(&init_mm.mm_count); /* XXX UP? */
937 current->active_mm = &init_mm;
938 }
939