1 /*
2  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
3  *
4  * Copyright (c) 2008-2009 USI Co., Ltd.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification.
13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14  *    substantially similar to the "NO WARRANTY" disclaimer below
15  *    ("Disclaimer") and any redistribution must be conditioned upon
16  *    including a substantially similar Disclaimer requirement for further
17  *    binary redistribution.
18  * 3. Neither the names of the above-listed copyright holders nor the names
19  *    of any contributors may be used to endorse or promote products derived
20  *    from this software without specific prior written permission.
21  *
22  * Alternatively, this software may be distributed under the terms of the
23  * GNU General Public License ("GPL") version 2 as published by the Free
24  * Software Foundation.
25  *
26  * NO WARRANTY
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37  * POSSIBILITY OF SUCH DAMAGES.
38  *
39  */
40  #include <linux/slab.h>
41  #include "pm8001_sas.h"
42  #include "pm8001_hwi.h"
43  #include "pm8001_chips.h"
44  #include "pm8001_ctl.h"
45  #include "pm80xx_tracepoints.h"
46 
47 /**
48  * read_main_config_table - read the configure table and save it.
49  * @pm8001_ha: our hba card information
50  */
read_main_config_table(struct pm8001_hba_info * pm8001_ha)51 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
52 {
53 	void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
54 	pm8001_ha->main_cfg_tbl.pm8001_tbl.signature	=
55 				pm8001_mr32(address, 0x00);
56 	pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
57 				pm8001_mr32(address, 0x04);
58 	pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev	=
59 				pm8001_mr32(address, 0x08);
60 	pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io	=
61 				pm8001_mr32(address, 0x0C);
62 	pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl	=
63 				pm8001_mr32(address, 0x10);
64 	pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
65 				pm8001_mr32(address, 0x14);
66 	pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset	=
67 				pm8001_mr32(address, 0x18);
68 	pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
69 		pm8001_mr32(address, MAIN_IBQ_OFFSET);
70 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
71 		pm8001_mr32(address, MAIN_OBQ_OFFSET);
72 	pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag	=
73 		pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
74 
75 	/* read analog Setting offset from the configuration table */
76 	pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
77 		pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
78 
79 	/* read Error Dump Offset and Length */
80 	pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
81 		pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
82 	pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
83 		pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
84 	pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
85 		pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
86 	pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
87 		pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
88 }
89 
90 /**
91  * read_general_status_table - read the general status table and save it.
92  * @pm8001_ha: our hba card information
93  */
read_general_status_table(struct pm8001_hba_info * pm8001_ha)94 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
95 {
96 	void __iomem *address = pm8001_ha->general_stat_tbl_addr;
97 	pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate	=
98 				pm8001_mr32(address, 0x00);
99 	pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0	=
100 				pm8001_mr32(address, 0x04);
101 	pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1	=
102 				pm8001_mr32(address, 0x08);
103 	pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt		=
104 				pm8001_mr32(address, 0x0C);
105 	pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt		=
106 				pm8001_mr32(address, 0x10);
107 	pm8001_ha->gs_tbl.pm8001_tbl.rsvd		=
108 				pm8001_mr32(address, 0x14);
109 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0]	=
110 				pm8001_mr32(address, 0x18);
111 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1]	=
112 				pm8001_mr32(address, 0x1C);
113 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2]	=
114 				pm8001_mr32(address, 0x20);
115 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3]	=
116 				pm8001_mr32(address, 0x24);
117 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4]	=
118 				pm8001_mr32(address, 0x28);
119 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5]	=
120 				pm8001_mr32(address, 0x2C);
121 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6]	=
122 				pm8001_mr32(address, 0x30);
123 	pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7]	=
124 				pm8001_mr32(address, 0x34);
125 	pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val	=
126 				pm8001_mr32(address, 0x38);
127 	pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0]		=
128 				pm8001_mr32(address, 0x3C);
129 	pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1]		=
130 				pm8001_mr32(address, 0x40);
131 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0]	=
132 				pm8001_mr32(address, 0x44);
133 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1]	=
134 				pm8001_mr32(address, 0x48);
135 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2]	=
136 				pm8001_mr32(address, 0x4C);
137 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3]	=
138 				pm8001_mr32(address, 0x50);
139 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4]	=
140 				pm8001_mr32(address, 0x54);
141 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5]	=
142 				pm8001_mr32(address, 0x58);
143 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6]	=
144 				pm8001_mr32(address, 0x5C);
145 	pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7]	=
146 				pm8001_mr32(address, 0x60);
147 }
148 
149 /**
150  * read_inbnd_queue_table - read the inbound queue table and save it.
151  * @pm8001_ha: our hba card information
152  */
read_inbnd_queue_table(struct pm8001_hba_info * pm8001_ha)153 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
154 {
155 	int i;
156 	void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
157 	for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
158 		u32 offset = i * 0x20;
159 		pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
160 		      get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
161 		pm8001_ha->inbnd_q_tbl[i].pi_offset =
162 			pm8001_mr32(address, (offset + 0x18));
163 	}
164 }
165 
166 /**
167  * read_outbnd_queue_table - read the outbound queue table and save it.
168  * @pm8001_ha: our hba card information
169  */
read_outbnd_queue_table(struct pm8001_hba_info * pm8001_ha)170 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
171 {
172 	int i;
173 	void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
174 	for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
175 		u32 offset = i * 0x24;
176 		pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
177 		      get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
178 		pm8001_ha->outbnd_q_tbl[i].ci_offset =
179 			pm8001_mr32(address, (offset + 0x18));
180 	}
181 }
182 
183 /**
184  * init_default_table_values - init the default table.
185  * @pm8001_ha: our hba card information
186  */
init_default_table_values(struct pm8001_hba_info * pm8001_ha)187 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
188 {
189 	int i;
190 	u32 offsetib, offsetob;
191 	void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
192 	void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
193 	u32 ib_offset = pm8001_ha->ib_offset;
194 	u32 ob_offset = pm8001_ha->ob_offset;
195 	u32 ci_offset = pm8001_ha->ci_offset;
196 	u32 pi_offset = pm8001_ha->pi_offset;
197 
198 	pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd		= 0;
199 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3	= 0;
200 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7	= 0;
201 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3	= 0;
202 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7	= 0;
203 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
204 									 0;
205 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
206 									 0;
207 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
208 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
209 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
210 	pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
211 
212 	pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr		=
213 		pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
214 	pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr		=
215 		pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
216 	pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size		=
217 		PM8001_EVENT_LOG_SIZE;
218 	pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option		= 0x01;
219 	pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr	=
220 		pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
221 	pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr	=
222 		pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
223 	pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size		=
224 		PM8001_EVENT_LOG_SIZE;
225 	pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option		= 0x01;
226 	pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt		= 0x01;
227 	for (i = 0; i < pm8001_ha->max_q_num; i++) {
228 		pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt	=
229 			PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
230 		pm8001_ha->inbnd_q_tbl[i].upper_base_addr	=
231 			pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
232 		pm8001_ha->inbnd_q_tbl[i].lower_base_addr	=
233 		pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
234 		pm8001_ha->inbnd_q_tbl[i].base_virt		=
235 		  (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
236 		pm8001_ha->inbnd_q_tbl[i].total_length		=
237 			pm8001_ha->memoryMap.region[ib_offset + i].total_len;
238 		pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr	=
239 			pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
240 		pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr	=
241 			pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
242 		pm8001_ha->inbnd_q_tbl[i].ci_virt		=
243 			pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
244 		pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);
245 		offsetib = i * 0x20;
246 		pm8001_ha->inbnd_q_tbl[i].pi_pci_bar		=
247 			get_pci_bar_index(pm8001_mr32(addressib,
248 				(offsetib + 0x14)));
249 		pm8001_ha->inbnd_q_tbl[i].pi_offset		=
250 			pm8001_mr32(addressib, (offsetib + 0x18));
251 		pm8001_ha->inbnd_q_tbl[i].producer_idx		= 0;
252 		pm8001_ha->inbnd_q_tbl[i].consumer_index	= 0;
253 	}
254 	for (i = 0; i < pm8001_ha->max_q_num; i++) {
255 		pm8001_ha->outbnd_q_tbl[i].element_size_cnt	=
256 			PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
257 		pm8001_ha->outbnd_q_tbl[i].upper_base_addr	=
258 			pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
259 		pm8001_ha->outbnd_q_tbl[i].lower_base_addr	=
260 			pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
261 		pm8001_ha->outbnd_q_tbl[i].base_virt		=
262 		  (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
263 		pm8001_ha->outbnd_q_tbl[i].total_length		=
264 			pm8001_ha->memoryMap.region[ob_offset + i].total_len;
265 		pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr	=
266 			pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
267 		pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr	=
268 			pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
269 		pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay	=
270 			0 | (10 << 16) | (i << 24);
271 		pm8001_ha->outbnd_q_tbl[i].pi_virt		=
272 			pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
273 		pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0);
274 		offsetob = i * 0x24;
275 		pm8001_ha->outbnd_q_tbl[i].ci_pci_bar		=
276 			get_pci_bar_index(pm8001_mr32(addressob,
277 			offsetob + 0x14));
278 		pm8001_ha->outbnd_q_tbl[i].ci_offset		=
279 			pm8001_mr32(addressob, (offsetob + 0x18));
280 		pm8001_ha->outbnd_q_tbl[i].consumer_idx		= 0;
281 		pm8001_ha->outbnd_q_tbl[i].producer_index	= 0;
282 	}
283 }
284 
285 /**
286  * update_main_config_table - update the main default table to the HBA.
287  * @pm8001_ha: our hba card information
288  */
update_main_config_table(struct pm8001_hba_info * pm8001_ha)289 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
290 {
291 	void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
292 	pm8001_mw32(address, 0x24,
293 		pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
294 	pm8001_mw32(address, 0x28,
295 		pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
296 	pm8001_mw32(address, 0x2C,
297 		pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
298 	pm8001_mw32(address, 0x30,
299 		pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
300 	pm8001_mw32(address, 0x34,
301 		pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
302 	pm8001_mw32(address, 0x38,
303 		pm8001_ha->main_cfg_tbl.pm8001_tbl.
304 					outbound_tgt_ITNexus_event_pid0_3);
305 	pm8001_mw32(address, 0x3C,
306 		pm8001_ha->main_cfg_tbl.pm8001_tbl.
307 					outbound_tgt_ITNexus_event_pid4_7);
308 	pm8001_mw32(address, 0x40,
309 		pm8001_ha->main_cfg_tbl.pm8001_tbl.
310 					outbound_tgt_ssp_event_pid0_3);
311 	pm8001_mw32(address, 0x44,
312 		pm8001_ha->main_cfg_tbl.pm8001_tbl.
313 					outbound_tgt_ssp_event_pid4_7);
314 	pm8001_mw32(address, 0x48,
315 		pm8001_ha->main_cfg_tbl.pm8001_tbl.
316 					outbound_tgt_smp_event_pid0_3);
317 	pm8001_mw32(address, 0x4C,
318 		pm8001_ha->main_cfg_tbl.pm8001_tbl.
319 					outbound_tgt_smp_event_pid4_7);
320 	pm8001_mw32(address, 0x50,
321 		pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
322 	pm8001_mw32(address, 0x54,
323 		pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
324 	pm8001_mw32(address, 0x58,
325 		pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
326 	pm8001_mw32(address, 0x5C,
327 		pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
328 	pm8001_mw32(address, 0x60,
329 		pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
330 	pm8001_mw32(address, 0x64,
331 		pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
332 	pm8001_mw32(address, 0x68,
333 		pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
334 	pm8001_mw32(address, 0x6C,
335 		pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
336 	pm8001_mw32(address, 0x70,
337 		pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
338 }
339 
340 /**
341  * update_inbnd_queue_table - update the inbound queue table to the HBA.
342  * @pm8001_ha: our hba card information
343  * @number: entry in the queue
344  */
update_inbnd_queue_table(struct pm8001_hba_info * pm8001_ha,int number)345 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
346 				     int number)
347 {
348 	void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
349 	u16 offset = number * 0x20;
350 	pm8001_mw32(address, offset + 0x00,
351 		pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
352 	pm8001_mw32(address, offset + 0x04,
353 		pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
354 	pm8001_mw32(address, offset + 0x08,
355 		pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
356 	pm8001_mw32(address, offset + 0x0C,
357 		pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
358 	pm8001_mw32(address, offset + 0x10,
359 		pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
360 }
361 
362 /**
363  * update_outbnd_queue_table - update the outbound queue table to the HBA.
364  * @pm8001_ha: our hba card information
365  * @number: entry in the queue
366  */
update_outbnd_queue_table(struct pm8001_hba_info * pm8001_ha,int number)367 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
368 				      int number)
369 {
370 	void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
371 	u16 offset = number * 0x24;
372 	pm8001_mw32(address, offset + 0x00,
373 		pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
374 	pm8001_mw32(address, offset + 0x04,
375 		pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
376 	pm8001_mw32(address, offset + 0x08,
377 		pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
378 	pm8001_mw32(address, offset + 0x0C,
379 		pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
380 	pm8001_mw32(address, offset + 0x10,
381 		pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
382 	pm8001_mw32(address, offset + 0x1C,
383 		pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
384 }
385 
386 /**
387  * pm8001_bar4_shift - function is called to shift BAR base address
388  * @pm8001_ha : our hba card information
389  * @shiftValue : shifting value in memory bar.
390  */
pm8001_bar4_shift(struct pm8001_hba_info * pm8001_ha,u32 shiftValue)391 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
392 {
393 	u32 regVal;
394 	unsigned long start;
395 
396 	/* program the inbound AXI translation Lower Address */
397 	pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
398 
399 	/* confirm the setting is written */
400 	start = jiffies + HZ; /* 1 sec */
401 	do {
402 		regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
403 	} while ((regVal != shiftValue) && time_before(jiffies, start));
404 
405 	if (regVal != shiftValue) {
406 		pm8001_dbg(pm8001_ha, INIT,
407 			   "TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n",
408 			   regVal);
409 		return -1;
410 	}
411 	return 0;
412 }
413 
414 /**
415  * mpi_set_phys_g3_with_ssc
416  * @pm8001_ha: our hba card information
417  * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
418  */
mpi_set_phys_g3_with_ssc(struct pm8001_hba_info * pm8001_ha,u32 SSCbit)419 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
420 				     u32 SSCbit)
421 {
422 	u32 offset, i;
423 	unsigned long flags;
424 
425 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
426 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
427 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
428 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
429 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
430 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
431 #define SNW3_PHY_CAPABILITIES_PARITY 31
432 
433    /*
434     * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
435     * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
436     */
437 	spin_lock_irqsave(&pm8001_ha->lock, flags);
438 	if (-1 == pm8001_bar4_shift(pm8001_ha,
439 				SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
440 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
441 		return;
442 	}
443 
444 	for (i = 0; i < 4; i++) {
445 		offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
446 		pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
447 	}
448 	/* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
449 	if (-1 == pm8001_bar4_shift(pm8001_ha,
450 				SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
451 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
452 		return;
453 	}
454 	for (i = 4; i < 8; i++) {
455 		offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
456 		pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
457 	}
458 	/*************************************************************
459 	Change the SSC upspreading value to 0x0 so that upspreading is disabled.
460 	Device MABC SMOD0 Controls
461 	Address: (via MEMBASE-III):
462 	Using shifted destination address 0x0_0000: with Offset 0xD8
463 
464 	31:28 R/W Reserved Do not change
465 	27:24 R/W SAS_SMOD_SPRDUP 0000
466 	23:20 R/W SAS_SMOD_SPRDDN 0000
467 	19:0  R/W  Reserved Do not change
468 	Upon power-up this register will read as 0x8990c016,
469 	and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
470 	so that the written value will be 0x8090c016.
471 	This will ensure only down-spreading SSC is enabled on the SPC.
472 	*************************************************************/
473 	pm8001_cr32(pm8001_ha, 2, 0xd8);
474 	pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
475 
476 	/*set the shifted destination address to 0x0 to avoid error operation */
477 	pm8001_bar4_shift(pm8001_ha, 0x0);
478 	spin_unlock_irqrestore(&pm8001_ha->lock, flags);
479 	return;
480 }
481 
482 /**
483  * mpi_set_open_retry_interval_reg
484  * @pm8001_ha: our hba card information
485  * @interval: interval time for each OPEN_REJECT (RETRY). The units are in 1us.
486  */
mpi_set_open_retry_interval_reg(struct pm8001_hba_info * pm8001_ha,u32 interval)487 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
488 					    u32 interval)
489 {
490 	u32 offset;
491 	u32 value;
492 	u32 i;
493 	unsigned long flags;
494 
495 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
496 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
497 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
498 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
499 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
500 
501 	value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
502 	spin_lock_irqsave(&pm8001_ha->lock, flags);
503 	/* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
504 	if (-1 == pm8001_bar4_shift(pm8001_ha,
505 			     OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
506 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
507 		return;
508 	}
509 	for (i = 0; i < 4; i++) {
510 		offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
511 		pm8001_cw32(pm8001_ha, 2, offset, value);
512 	}
513 
514 	if (-1 == pm8001_bar4_shift(pm8001_ha,
515 			     OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
516 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
517 		return;
518 	}
519 	for (i = 4; i < 8; i++) {
520 		offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
521 		pm8001_cw32(pm8001_ha, 2, offset, value);
522 	}
523 	/*set the shifted destination address to 0x0 to avoid error operation */
524 	pm8001_bar4_shift(pm8001_ha, 0x0);
525 	spin_unlock_irqrestore(&pm8001_ha->lock, flags);
526 	return;
527 }
528 
529 /**
530  * mpi_init_check - check firmware initialization status.
531  * @pm8001_ha: our hba card information
532  */
mpi_init_check(struct pm8001_hba_info * pm8001_ha)533 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
534 {
535 	u32 max_wait_count;
536 	u32 value;
537 	u32 gst_len_mpistate;
538 	/* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
539 	table is updated */
540 	pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
541 	/* wait until Inbound DoorBell Clear Register toggled */
542 	max_wait_count = 1 * 1000 * 1000;/* 1 sec */
543 	do {
544 		udelay(1);
545 		value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
546 		value &= SPC_MSGU_CFG_TABLE_UPDATE;
547 	} while ((value != 0) && (--max_wait_count));
548 
549 	if (!max_wait_count)
550 		return -1;
551 	/* check the MPI-State for initialization */
552 	gst_len_mpistate =
553 		pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
554 		GST_GSTLEN_MPIS_OFFSET);
555 	if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
556 		return -1;
557 	/* check MPI Initialization error */
558 	gst_len_mpistate = gst_len_mpistate >> 16;
559 	if (0x0000 != gst_len_mpistate)
560 		return -1;
561 	return 0;
562 }
563 
564 /**
565  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
566  * @pm8001_ha: our hba card information
567  */
check_fw_ready(struct pm8001_hba_info * pm8001_ha)568 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
569 {
570 	u32 value, value1;
571 	u32 max_wait_count;
572 	/* check error state */
573 	value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
574 	value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
575 	/* check AAP error */
576 	if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
577 		/* error state */
578 		value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
579 		return -1;
580 	}
581 
582 	/* check IOP error */
583 	if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
584 		/* error state */
585 		value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
586 		return -1;
587 	}
588 
589 	/* bit 4-31 of scratch pad1 should be zeros if it is not
590 	in error state*/
591 	if (value & SCRATCH_PAD1_STATE_MASK) {
592 		/* error case */
593 		pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
594 		return -1;
595 	}
596 
597 	/* bit 2, 4-31 of scratch pad2 should be zeros if it is not
598 	in error state */
599 	if (value1 & SCRATCH_PAD2_STATE_MASK) {
600 		/* error case */
601 		return -1;
602 	}
603 
604 	max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
605 
606 	/* wait until scratch pad 1 and 2 registers in ready state  */
607 	do {
608 		udelay(1);
609 		value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
610 			& SCRATCH_PAD1_RDY;
611 		value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
612 			& SCRATCH_PAD2_RDY;
613 		if ((--max_wait_count) == 0)
614 			return -1;
615 	} while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
616 	return 0;
617 }
618 
init_pci_device_addresses(struct pm8001_hba_info * pm8001_ha)619 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
620 {
621 	void __iomem *base_addr;
622 	u32	value;
623 	u32	offset;
624 	u32	pcibar;
625 	u32	pcilogic;
626 
627 	value = pm8001_cr32(pm8001_ha, 0, 0x44);
628 	offset = value & 0x03FFFFFF;
629 	pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 Offset: %x\n", offset);
630 	pcilogic = (value & 0xFC000000) >> 26;
631 	pcibar = get_pci_bar_index(pcilogic);
632 	pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
633 	pm8001_ha->main_cfg_tbl_addr = base_addr =
634 		pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
635 	pm8001_ha->general_stat_tbl_addr =
636 		base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
637 	pm8001_ha->inbnd_q_tbl_addr =
638 		base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
639 	pm8001_ha->outbnd_q_tbl_addr =
640 		base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
641 }
642 
643 /**
644  * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
645  * @pm8001_ha: our hba card information
646  */
pm8001_chip_init(struct pm8001_hba_info * pm8001_ha)647 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
648 {
649 	u32 i = 0;
650 	u16 deviceid;
651 	pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
652 	/* 8081 controllers need BAR shift to access MPI space
653 	* as this is shared with BIOS data */
654 	if (deviceid == 0x8081 || deviceid == 0x0042) {
655 		if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
656 			pm8001_dbg(pm8001_ha, FAIL,
657 				   "Shift Bar4 to 0x%x failed\n",
658 				   GSM_SM_BASE);
659 			return -1;
660 		}
661 	}
662 	/* check the firmware status */
663 	if (-1 == check_fw_ready(pm8001_ha)) {
664 		pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
665 		return -EBUSY;
666 	}
667 
668 	/* Initialize pci space address eg: mpi offset */
669 	init_pci_device_addresses(pm8001_ha);
670 	init_default_table_values(pm8001_ha);
671 	read_main_config_table(pm8001_ha);
672 	read_general_status_table(pm8001_ha);
673 	read_inbnd_queue_table(pm8001_ha);
674 	read_outbnd_queue_table(pm8001_ha);
675 	/* update main config table ,inbound table and outbound table */
676 	update_main_config_table(pm8001_ha);
677 	for (i = 0; i < pm8001_ha->max_q_num; i++)
678 		update_inbnd_queue_table(pm8001_ha, i);
679 	for (i = 0; i < pm8001_ha->max_q_num; i++)
680 		update_outbnd_queue_table(pm8001_ha, i);
681 	/* 8081 controller donot require these operations */
682 	if (deviceid != 0x8081 && deviceid != 0x0042) {
683 		mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
684 		/* 7->130ms, 34->500ms, 119->1.5s */
685 		mpi_set_open_retry_interval_reg(pm8001_ha, 119);
686 	}
687 	/* notify firmware update finished and check initialization status */
688 	if (0 == mpi_init_check(pm8001_ha)) {
689 		pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
690 	} else
691 		return -EBUSY;
692 	/*This register is a 16-bit timer with a resolution of 1us. This is the
693 	timer used for interrupt delay/coalescing in the PCIe Application Layer.
694 	Zero is not a valid value. A value of 1 in the register will cause the
695 	interrupts to be normal. A value greater than 1 will cause coalescing
696 	delays.*/
697 	pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
698 	pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
699 	return 0;
700 }
701 
mpi_uninit_check(struct pm8001_hba_info * pm8001_ha)702 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
703 {
704 	u32 max_wait_count;
705 	u32 value;
706 	u32 gst_len_mpistate;
707 	u16 deviceid;
708 	pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
709 	if (deviceid == 0x8081 || deviceid == 0x0042) {
710 		if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
711 			pm8001_dbg(pm8001_ha, FAIL,
712 				   "Shift Bar4 to 0x%x failed\n",
713 				   GSM_SM_BASE);
714 			return -1;
715 		}
716 	}
717 	init_pci_device_addresses(pm8001_ha);
718 	/* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
719 	table is stop */
720 	pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
721 
722 	/* wait until Inbound DoorBell Clear Register toggled */
723 	max_wait_count = 1 * 1000 * 1000;/* 1 sec */
724 	do {
725 		udelay(1);
726 		value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
727 		value &= SPC_MSGU_CFG_TABLE_RESET;
728 	} while ((value != 0) && (--max_wait_count));
729 
730 	if (!max_wait_count) {
731 		pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=0x%x\n",
732 			   value);
733 		return -1;
734 	}
735 
736 	/* check the MPI-State for termination in progress */
737 	/* wait until Inbound DoorBell Clear Register toggled */
738 	max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
739 	do {
740 		udelay(1);
741 		gst_len_mpistate =
742 			pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
743 			GST_GSTLEN_MPIS_OFFSET);
744 		if (GST_MPI_STATE_UNINIT ==
745 			(gst_len_mpistate & GST_MPI_STATE_MASK))
746 			break;
747 	} while (--max_wait_count);
748 	if (!max_wait_count) {
749 		pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
750 			   gst_len_mpistate & GST_MPI_STATE_MASK);
751 		return -1;
752 	}
753 	return 0;
754 }
755 
756 /**
757  * soft_reset_ready_check - Function to check FW is ready for soft reset.
758  * @pm8001_ha: our hba card information
759  */
soft_reset_ready_check(struct pm8001_hba_info * pm8001_ha)760 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
761 {
762 	u32 regVal, regVal1, regVal2;
763 	if (mpi_uninit_check(pm8001_ha) != 0) {
764 		pm8001_dbg(pm8001_ha, FAIL, "MPI state is not ready\n");
765 		return -1;
766 	}
767 	/* read the scratch pad 2 register bit 2 */
768 	regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
769 		& SCRATCH_PAD2_FWRDY_RST;
770 	if (regVal == SCRATCH_PAD2_FWRDY_RST) {
771 		pm8001_dbg(pm8001_ha, INIT, "Firmware is ready for reset.\n");
772 	} else {
773 		unsigned long flags;
774 		/* Trigger NMI twice via RB6 */
775 		spin_lock_irqsave(&pm8001_ha->lock, flags);
776 		if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
777 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
778 			pm8001_dbg(pm8001_ha, FAIL,
779 				   "Shift Bar4 to 0x%x failed\n",
780 				   RB6_ACCESS_REG);
781 			return -1;
782 		}
783 		pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
784 			RB6_MAGIC_NUMBER_RST);
785 		pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
786 		/* wait for 100 ms */
787 		mdelay(100);
788 		regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
789 			SCRATCH_PAD2_FWRDY_RST;
790 		if (regVal != SCRATCH_PAD2_FWRDY_RST) {
791 			regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
792 			regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
793 			pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
794 				   regVal1, regVal2);
795 			pm8001_dbg(pm8001_ha, FAIL,
796 				   "SCRATCH_PAD0 value = 0x%x\n",
797 				   pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
798 			pm8001_dbg(pm8001_ha, FAIL,
799 				   "SCRATCH_PAD3 value = 0x%x\n",
800 				   pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
801 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
802 			return -1;
803 		}
804 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
805 	}
806 	return 0;
807 }
808 
809 /**
810  * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
811  * the FW register status to the originated status.
812  * @pm8001_ha: our hba card information
813  */
814 static int
pm8001_chip_soft_rst(struct pm8001_hba_info * pm8001_ha)815 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
816 {
817 	u32	regVal, toggleVal;
818 	u32	max_wait_count;
819 	u32	regVal1, regVal2, regVal3;
820 	u32	signature = 0x252acbcd; /* for host scratch pad0 */
821 	unsigned long flags;
822 
823 	/* step1: Check FW is ready for soft reset */
824 	if (soft_reset_ready_check(pm8001_ha) != 0) {
825 		pm8001_dbg(pm8001_ha, FAIL, "FW is not ready\n");
826 		return -1;
827 	}
828 
829 	/* step 2: clear NMI status register on AAP1 and IOP, write the same
830 	value to clear */
831 	/* map 0x60000 to BAR4(0x20), BAR2(win) */
832 	spin_lock_irqsave(&pm8001_ha->lock, flags);
833 	if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
834 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
835 		pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
836 			   MBIC_AAP1_ADDR_BASE);
837 		return -1;
838 	}
839 	regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
840 	pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (IOP)= 0x%x\n",
841 		   regVal);
842 	pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
843 	/* map 0x70000 to BAR4(0x20), BAR2(win) */
844 	if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
845 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
846 		pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
847 			   MBIC_IOP_ADDR_BASE);
848 		return -1;
849 	}
850 	regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
851 	pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n",
852 		   regVal);
853 	pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
854 
855 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
856 	pm8001_dbg(pm8001_ha, INIT, "PCIE -Event Interrupt Enable = 0x%x\n",
857 		   regVal);
858 	pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
859 
860 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
861 	pm8001_dbg(pm8001_ha, INIT, "PCIE - Event Interrupt  = 0x%x\n",
862 		   regVal);
863 	pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
864 
865 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
866 	pm8001_dbg(pm8001_ha, INIT, "PCIE -Error Interrupt Enable = 0x%x\n",
867 		   regVal);
868 	pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
869 
870 	regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
871 	pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal);
872 	pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
873 
874 	/* read the scratch pad 1 register bit 2 */
875 	regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
876 		& SCRATCH_PAD1_RST;
877 	toggleVal = regVal ^ SCRATCH_PAD1_RST;
878 
879 	/* set signature in host scratch pad0 register to tell SPC that the
880 	host performs the soft reset */
881 	pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
882 
883 	/* read required registers for confirmming */
884 	/* map 0x0700000 to BAR4(0x20), BAR2(win) */
885 	if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
886 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
887 		pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
888 			   GSM_ADDR_BASE);
889 		return -1;
890 	}
891 	pm8001_dbg(pm8001_ha, INIT,
892 		   "GSM 0x0(0x00007b88)-GSM Configuration and Reset = 0x%x\n",
893 		   pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
894 
895 	/* step 3: host read GSM Configuration and Reset register */
896 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
897 	/* Put those bits to low */
898 	/* GSM XCBI offset = 0x70 0000
899 	0x00 Bit 13 COM_SLV_SW_RSTB 1
900 	0x00 Bit 12 QSSP_SW_RSTB 1
901 	0x00 Bit 11 RAAE_SW_RSTB 1
902 	0x00 Bit 9 RB_1_SW_RSTB 1
903 	0x00 Bit 8 SM_SW_RSTB 1
904 	*/
905 	regVal &= ~(0x00003b00);
906 	/* host write GSM Configuration and Reset register */
907 	pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
908 	pm8001_dbg(pm8001_ha, INIT,
909 		   "GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n",
910 		   pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
911 
912 	/* step 4: */
913 	/* disable GSM - Read Address Parity Check */
914 	regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
915 	pm8001_dbg(pm8001_ha, INIT,
916 		   "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
917 		   regVal1);
918 	pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
919 	pm8001_dbg(pm8001_ha, INIT,
920 		   "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
921 		   pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
922 
923 	/* disable GSM - Write Address Parity Check */
924 	regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
925 	pm8001_dbg(pm8001_ha, INIT,
926 		   "GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n",
927 		   regVal2);
928 	pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
929 	pm8001_dbg(pm8001_ha, INIT,
930 		   "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
931 		   pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
932 
933 	/* disable GSM - Write Data Parity Check */
934 	regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
935 	pm8001_dbg(pm8001_ha, INIT, "GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n",
936 		   regVal3);
937 	pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
938 	pm8001_dbg(pm8001_ha, INIT,
939 		   "GSM 0x300048 - Write Data Parity Check Enable is set to = 0x%x\n",
940 		   pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
941 
942 	/* step 5: delay 10 usec */
943 	udelay(10);
944 	/* step 5-b: set GPIO-0 output control to tristate anyway */
945 	if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
946 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
947 		pm8001_dbg(pm8001_ha, INIT, "Shift Bar4 to 0x%x failed\n",
948 			   GPIO_ADDR_BASE);
949 		return -1;
950 	}
951 	regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
952 	pm8001_dbg(pm8001_ha, INIT, "GPIO Output Control Register: = 0x%x\n",
953 		   regVal);
954 	/* set GPIO-0 output control to tri-state */
955 	regVal &= 0xFFFFFFFC;
956 	pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
957 
958 	/* Step 6: Reset the IOP and AAP1 */
959 	/* map 0x00000 to BAR4(0x20), BAR2(win) */
960 	if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
961 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
962 		pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
963 			   SPC_TOP_LEVEL_ADDR_BASE);
964 		return -1;
965 	}
966 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
967 	pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting IOP/AAP1:= 0x%x\n",
968 		   regVal);
969 	regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
970 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
971 
972 	/* step 7: Reset the BDMA/OSSP */
973 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
974 	pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting BDMA/OSSP: = 0x%x\n",
975 		   regVal);
976 	regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
977 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
978 
979 	/* step 8: delay 10 usec */
980 	udelay(10);
981 
982 	/* step 9: bring the BDMA and OSSP out of reset */
983 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
984 	pm8001_dbg(pm8001_ha, INIT,
985 		   "Top Register before bringing up BDMA/OSSP:= 0x%x\n",
986 		   regVal);
987 	regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
988 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
989 
990 	/* step 10: delay 10 usec */
991 	udelay(10);
992 
993 	/* step 11: reads and sets the GSM Configuration and Reset Register */
994 	/* map 0x0700000 to BAR4(0x20), BAR2(win) */
995 	if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
996 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
997 		pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
998 			   GSM_ADDR_BASE);
999 		return -1;
1000 	}
1001 	pm8001_dbg(pm8001_ha, INIT,
1002 		   "GSM 0x0 (0x00007b88)-GSM Configuration and Reset = 0x%x\n",
1003 		   pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1004 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1005 	/* Put those bits to high */
1006 	/* GSM XCBI offset = 0x70 0000
1007 	0x00 Bit 13 COM_SLV_SW_RSTB 1
1008 	0x00 Bit 12 QSSP_SW_RSTB 1
1009 	0x00 Bit 11 RAAE_SW_RSTB 1
1010 	0x00 Bit 9   RB_1_SW_RSTB 1
1011 	0x00 Bit 8   SM_SW_RSTB 1
1012 	*/
1013 	regVal |= (GSM_CONFIG_RESET_VALUE);
1014 	pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1015 	pm8001_dbg(pm8001_ha, INIT, "GSM (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n",
1016 		   pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1017 
1018 	/* step 12: Restore GSM - Read Address Parity Check */
1019 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1020 	/* just for debugging */
1021 	pm8001_dbg(pm8001_ha, INIT,
1022 		   "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
1023 		   regVal);
1024 	pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1025 	pm8001_dbg(pm8001_ha, INIT, "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
1026 		   pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
1027 	/* Restore GSM - Write Address Parity Check */
1028 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1029 	pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1030 	pm8001_dbg(pm8001_ha, INIT,
1031 		   "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
1032 		   pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
1033 	/* Restore GSM - Write Data Parity Check */
1034 	regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1035 	pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1036 	pm8001_dbg(pm8001_ha, INIT,
1037 		   "GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n",
1038 		   pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
1039 
1040 	/* step 13: bring the IOP and AAP1 out of reset */
1041 	/* map 0x00000 to BAR4(0x20), BAR2(win) */
1042 	if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1043 		spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1044 		pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
1045 			   SPC_TOP_LEVEL_ADDR_BASE);
1046 		return -1;
1047 	}
1048 	regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1049 	regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1050 	pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1051 
1052 	/* step 14: delay 10 usec - Normal Mode */
1053 	udelay(10);
1054 	/* check Soft Reset Normal mode or Soft Reset HDA mode */
1055 	if (signature == SPC_SOFT_RESET_SIGNATURE) {
1056 		/* step 15 (Normal Mode): wait until scratch pad1 register
1057 		bit 2 toggled */
1058 		max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1059 		do {
1060 			udelay(1);
1061 			regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1062 				SCRATCH_PAD1_RST;
1063 		} while ((regVal != toggleVal) && (--max_wait_count));
1064 
1065 		if (!max_wait_count) {
1066 			regVal = pm8001_cr32(pm8001_ha, 0,
1067 				MSGU_SCRATCH_PAD_1);
1068 			pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT : ToggleVal 0x%x,MSGU_SCRATCH_PAD1 = 0x%x\n",
1069 				   toggleVal, regVal);
1070 			pm8001_dbg(pm8001_ha, FAIL,
1071 				   "SCRATCH_PAD0 value = 0x%x\n",
1072 				   pm8001_cr32(pm8001_ha, 0,
1073 					       MSGU_SCRATCH_PAD_0));
1074 			pm8001_dbg(pm8001_ha, FAIL,
1075 				   "SCRATCH_PAD2 value = 0x%x\n",
1076 				   pm8001_cr32(pm8001_ha, 0,
1077 					       MSGU_SCRATCH_PAD_2));
1078 			pm8001_dbg(pm8001_ha, FAIL,
1079 				   "SCRATCH_PAD3 value = 0x%x\n",
1080 				   pm8001_cr32(pm8001_ha, 0,
1081 					       MSGU_SCRATCH_PAD_3));
1082 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1083 			return -1;
1084 		}
1085 
1086 		/* step 16 (Normal) - Clear ODMR and ODCR */
1087 		pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1088 		pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1089 
1090 		/* step 17 (Normal Mode): wait for the FW and IOP to get
1091 		ready - 1 sec timeout */
1092 		/* Wait for the SPC Configuration Table to be ready */
1093 		if (check_fw_ready(pm8001_ha) == -1) {
1094 			regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1095 			/* return error if MPI Configuration Table not ready */
1096 			pm8001_dbg(pm8001_ha, INIT,
1097 				   "FW not ready SCRATCH_PAD1 = 0x%x\n",
1098 				   regVal);
1099 			regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1100 			/* return error if MPI Configuration Table not ready */
1101 			pm8001_dbg(pm8001_ha, INIT,
1102 				   "FW not ready SCRATCH_PAD2 = 0x%x\n",
1103 				   regVal);
1104 			pm8001_dbg(pm8001_ha, INIT,
1105 				   "SCRATCH_PAD0 value = 0x%x\n",
1106 				   pm8001_cr32(pm8001_ha, 0,
1107 					       MSGU_SCRATCH_PAD_0));
1108 			pm8001_dbg(pm8001_ha, INIT,
1109 				   "SCRATCH_PAD3 value = 0x%x\n",
1110 				   pm8001_cr32(pm8001_ha, 0,
1111 					       MSGU_SCRATCH_PAD_3));
1112 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1113 			return -1;
1114 		}
1115 	}
1116 	pm8001_bar4_shift(pm8001_ha, 0);
1117 	spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1118 
1119 	pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1120 	return 0;
1121 }
1122 
pm8001_hw_chip_rst(struct pm8001_hba_info * pm8001_ha)1123 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1124 {
1125 	u32 i;
1126 	u32 regVal;
1127 	pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1128 
1129 	/* do SPC chip reset. */
1130 	regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1131 	regVal &= ~(SPC_REG_RESET_DEVICE);
1132 	pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1133 
1134 	/* delay 10 usec */
1135 	udelay(10);
1136 
1137 	/* bring chip reset out of reset */
1138 	regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1139 	regVal |= SPC_REG_RESET_DEVICE;
1140 	pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1141 
1142 	/* delay 10 usec */
1143 	udelay(10);
1144 
1145 	/* wait for 20 msec until the firmware gets reloaded */
1146 	i = 20;
1147 	do {
1148 		mdelay(1);
1149 	} while ((--i) != 0);
1150 
1151 	pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1152 }
1153 
1154 /**
1155  * pm8001_chip_iounmap - which mapped when initialized.
1156  * @pm8001_ha: our hba card information
1157  */
pm8001_chip_iounmap(struct pm8001_hba_info * pm8001_ha)1158 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1159 {
1160 	s8 bar, logical = 0;
1161 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
1162 		/*
1163 		** logical BARs for SPC:
1164 		** bar 0 and 1 - logical BAR0
1165 		** bar 2 and 3 - logical BAR1
1166 		** bar4 - logical BAR2
1167 		** bar5 - logical BAR3
1168 		** Skip the appropriate assignments:
1169 		*/
1170 		if ((bar == 1) || (bar == 3))
1171 			continue;
1172 		if (pm8001_ha->io_mem[logical].memvirtaddr) {
1173 			iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1174 			logical++;
1175 		}
1176 	}
1177 }
1178 
1179 #ifndef PM8001_USE_MSIX
1180 /**
1181  * pm8001_chip_intx_interrupt_enable - enable PM8001 chip interrupt
1182  * @pm8001_ha: our hba card information
1183  */
1184 static void
pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info * pm8001_ha)1185 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1186 {
1187 	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1188 	pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1189 }
1190 
1191 /**
1192  * pm8001_chip_intx_interrupt_disable - disable PM8001 chip interrupt
1193  * @pm8001_ha: our hba card information
1194  */
1195 static void
pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info * pm8001_ha)1196 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1197 {
1198 	pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1199 }
1200 
1201 #else
1202 
1203 /**
1204  * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1205  * @pm8001_ha: our hba card information
1206  * @int_vec_idx: interrupt number to enable
1207  */
1208 static void
pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info * pm8001_ha,u32 int_vec_idx)1209 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1210 	u32 int_vec_idx)
1211 {
1212 	u32 msi_index;
1213 	u32 value;
1214 	msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1215 	msi_index += MSIX_TABLE_BASE;
1216 	pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1217 	value = (1 << int_vec_idx);
1218 	pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1219 
1220 }
1221 
1222 /**
1223  * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1224  * @pm8001_ha: our hba card information
1225  * @int_vec_idx: interrupt number to disable
1226  */
1227 static void
pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info * pm8001_ha,u32 int_vec_idx)1228 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1229 	u32 int_vec_idx)
1230 {
1231 	u32 msi_index;
1232 	msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1233 	msi_index += MSIX_TABLE_BASE;
1234 	pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1235 }
1236 #endif
1237 
1238 /**
1239  * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1240  * @pm8001_ha: our hba card information
1241  * @vec: unused
1242  */
1243 static void
pm8001_chip_interrupt_enable(struct pm8001_hba_info * pm8001_ha,u8 vec)1244 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1245 {
1246 #ifdef PM8001_USE_MSIX
1247 	pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1248 #else
1249 	pm8001_chip_intx_interrupt_enable(pm8001_ha);
1250 #endif
1251 }
1252 
1253 /**
1254  * pm8001_chip_interrupt_disable - disable PM8001 chip interrupt
1255  * @pm8001_ha: our hba card information
1256  * @vec: unused
1257  */
1258 static void
pm8001_chip_interrupt_disable(struct pm8001_hba_info * pm8001_ha,u8 vec)1259 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1260 {
1261 #ifdef PM8001_USE_MSIX
1262 	pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1263 #else
1264 	pm8001_chip_intx_interrupt_disable(pm8001_ha);
1265 #endif
1266 }
1267 
1268 /**
1269  * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1270  * inbound queue.
1271  * @circularQ: the inbound queue  we want to transfer to HBA.
1272  * @messageSize: the message size of this transfer, normally it is 64 bytes
1273  * @messagePtr: the pointer to message.
1274  */
pm8001_mpi_msg_free_get(struct inbound_queue_table * circularQ,u16 messageSize,void ** messagePtr)1275 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1276 			    u16 messageSize, void **messagePtr)
1277 {
1278 	u32 offset, consumer_index;
1279 	struct mpi_msg_hdr *msgHeader;
1280 	u8 bcCount = 1; /* only support single buffer */
1281 
1282 	/* Checks is the requested message size can be allocated in this queue*/
1283 	if (messageSize > IOMB_SIZE_SPCV) {
1284 		*messagePtr = NULL;
1285 		return -1;
1286 	}
1287 
1288 	/* Stores the new consumer index */
1289 	consumer_index = pm8001_read_32(circularQ->ci_virt);
1290 	circularQ->consumer_index = cpu_to_le32(consumer_index);
1291 	if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1292 		le32_to_cpu(circularQ->consumer_index)) {
1293 		*messagePtr = NULL;
1294 		return -1;
1295 	}
1296 	/* get memory IOMB buffer address */
1297 	offset = circularQ->producer_idx * messageSize;
1298 	/* increment to next bcCount element */
1299 	circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1300 				% PM8001_MPI_QUEUE;
1301 	/* Adds that distance to the base of the region virtual address plus
1302 	the message header size*/
1303 	msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt	+ offset);
1304 	*messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1305 	return 0;
1306 }
1307 
1308 /**
1309  * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1310  * FW to tell the fw to get this message from IOMB.
1311  * @pm8001_ha: our hba card information
1312  * @q_index: the index in the inbound queue we want to transfer to HBA.
1313  * @opCode: the operation code represents commands which LLDD and fw recognized.
1314  * @payload: the command payload of each operation command.
1315  * @nb: size in bytes of the command payload
1316  * @responseQueue: queue to interrupt on w/ command response (if any)
1317  */
pm8001_mpi_build_cmd(struct pm8001_hba_info * pm8001_ha,u32 q_index,u32 opCode,void * payload,size_t nb,u32 responseQueue)1318 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1319 			 u32 q_index, u32 opCode, void *payload, size_t nb,
1320 			 u32 responseQueue)
1321 {
1322 	u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1323 	void *pMessage;
1324 	unsigned long flags;
1325 	struct inbound_queue_table *circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
1326 	int rv;
1327 	u32 htag = le32_to_cpu(*(__le32 *)payload);
1328 
1329 	trace_pm80xx_mpi_build_cmd(pm8001_ha->id, opCode, htag, q_index,
1330 		circularQ->producer_idx, le32_to_cpu(circularQ->consumer_index));
1331 
1332 	if (WARN_ON(q_index >= pm8001_ha->max_q_num))
1333 		return -EINVAL;
1334 
1335 	spin_lock_irqsave(&circularQ->iq_lock, flags);
1336 	rv = pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1337 			&pMessage);
1338 	if (rv < 0) {
1339 		pm8001_dbg(pm8001_ha, IO, "No free mpi buffer\n");
1340 		rv = -ENOMEM;
1341 		goto done;
1342 	}
1343 
1344 	if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr)))
1345 		nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr);
1346 	memcpy(pMessage, payload, nb);
1347 	if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size)
1348 		memset(pMessage + nb, 0, pm8001_ha->iomb_size -
1349 				(nb + sizeof(struct mpi_msg_hdr)));
1350 
1351 	/*Build the header*/
1352 	Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1353 		| ((responseQueue & 0x3F) << 16)
1354 		| ((category & 0xF) << 12) | (opCode & 0xFFF));
1355 
1356 	pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1357 	/*Update the PI to the firmware*/
1358 	pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1359 		circularQ->pi_offset, circularQ->producer_idx);
1360 	pm8001_dbg(pm8001_ha, DEVIO,
1361 		   "INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1362 		   responseQueue, opCode, circularQ->producer_idx,
1363 		   circularQ->consumer_index);
1364 done:
1365 	spin_unlock_irqrestore(&circularQ->iq_lock, flags);
1366 	return rv;
1367 }
1368 
pm8001_mpi_msg_free_set(struct pm8001_hba_info * pm8001_ha,void * pMsg,struct outbound_queue_table * circularQ,u8 bc)1369 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1370 			    struct outbound_queue_table *circularQ, u8 bc)
1371 {
1372 	u32 producer_index;
1373 	struct mpi_msg_hdr *msgHeader;
1374 	struct mpi_msg_hdr *pOutBoundMsgHeader;
1375 
1376 	msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1377 	pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1378 				circularQ->consumer_idx * pm8001_ha->iomb_size);
1379 	if (pOutBoundMsgHeader != msgHeader) {
1380 		pm8001_dbg(pm8001_ha, FAIL,
1381 			   "consumer_idx = %d msgHeader = %p\n",
1382 			   circularQ->consumer_idx, msgHeader);
1383 
1384 		/* Update the producer index from SPC */
1385 		producer_index = pm8001_read_32(circularQ->pi_virt);
1386 		circularQ->producer_index = cpu_to_le32(producer_index);
1387 		pm8001_dbg(pm8001_ha, FAIL,
1388 			   "consumer_idx = %d producer_index = %dmsgHeader = %p\n",
1389 			   circularQ->consumer_idx,
1390 			   circularQ->producer_index, msgHeader);
1391 		return 0;
1392 	}
1393 	/* free the circular queue buffer elements associated with the message*/
1394 	circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1395 				% PM8001_MPI_QUEUE;
1396 	/* update the CI of outbound queue */
1397 	pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1398 		circularQ->consumer_idx);
1399 	/* Update the producer index from SPC*/
1400 	producer_index = pm8001_read_32(circularQ->pi_virt);
1401 	circularQ->producer_index = cpu_to_le32(producer_index);
1402 	pm8001_dbg(pm8001_ha, IO, " CI=%d PI=%d\n",
1403 		   circularQ->consumer_idx, circularQ->producer_index);
1404 	return 0;
1405 }
1406 
1407 /**
1408  * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1409  * message table.
1410  * @pm8001_ha: our hba card information
1411  * @circularQ: the outbound queue  table.
1412  * @messagePtr1: the message contents of this outbound message.
1413  * @pBC: the message size.
1414  */
pm8001_mpi_msg_consume(struct pm8001_hba_info * pm8001_ha,struct outbound_queue_table * circularQ,void ** messagePtr1,u8 * pBC)1415 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1416 			   struct outbound_queue_table *circularQ,
1417 			   void **messagePtr1, u8 *pBC)
1418 {
1419 	struct mpi_msg_hdr	*msgHeader;
1420 	__le32	msgHeader_tmp;
1421 	u32 header_tmp;
1422 	do {
1423 		/* If there are not-yet-delivered messages ... */
1424 		if (le32_to_cpu(circularQ->producer_index)
1425 			!= circularQ->consumer_idx) {
1426 			/*Get the pointer to the circular queue buffer element*/
1427 			msgHeader = (struct mpi_msg_hdr *)
1428 				(circularQ->base_virt +
1429 				circularQ->consumer_idx * pm8001_ha->iomb_size);
1430 			/* read header */
1431 			header_tmp = pm8001_read_32(msgHeader);
1432 			msgHeader_tmp = cpu_to_le32(header_tmp);
1433 			pm8001_dbg(pm8001_ha, DEVIO,
1434 				   "outbound opcode msgheader:%x ci=%d pi=%d\n",
1435 				   msgHeader_tmp, circularQ->consumer_idx,
1436 				   circularQ->producer_index);
1437 			if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1438 				if (OPC_OUB_SKIP_ENTRY !=
1439 					(le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1440 					*messagePtr1 =
1441 						((u8 *)msgHeader) +
1442 						sizeof(struct mpi_msg_hdr);
1443 					*pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1444 						>> 24) & 0x1f);
1445 					pm8001_dbg(pm8001_ha, IO,
1446 						   ": CI=%d PI=%d msgHeader=%x\n",
1447 						   circularQ->consumer_idx,
1448 						   circularQ->producer_index,
1449 						   msgHeader_tmp);
1450 					return MPI_IO_STATUS_SUCCESS;
1451 				} else {
1452 					circularQ->consumer_idx =
1453 						(circularQ->consumer_idx +
1454 						((le32_to_cpu(msgHeader_tmp)
1455 						 >> 24) & 0x1f))
1456 							% PM8001_MPI_QUEUE;
1457 					msgHeader_tmp = 0;
1458 					pm8001_write_32(msgHeader, 0, 0);
1459 					/* update the CI of outbound queue */
1460 					pm8001_cw32(pm8001_ha,
1461 						circularQ->ci_pci_bar,
1462 						circularQ->ci_offset,
1463 						circularQ->consumer_idx);
1464 				}
1465 			} else {
1466 				circularQ->consumer_idx =
1467 					(circularQ->consumer_idx +
1468 					((le32_to_cpu(msgHeader_tmp) >> 24) &
1469 					0x1f)) % PM8001_MPI_QUEUE;
1470 				msgHeader_tmp = 0;
1471 				pm8001_write_32(msgHeader, 0, 0);
1472 				/* update the CI of outbound queue */
1473 				pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1474 					circularQ->ci_offset,
1475 					circularQ->consumer_idx);
1476 				return MPI_IO_STATUS_FAIL;
1477 			}
1478 		} else {
1479 			u32 producer_index;
1480 			void *pi_virt = circularQ->pi_virt;
1481 			/* spurious interrupt during setup if
1482 			 * kexec-ing and driver doing a doorbell access
1483 			 * with the pre-kexec oq interrupt setup
1484 			 */
1485 			if (!pi_virt)
1486 				break;
1487 			/* Update the producer index from SPC */
1488 			producer_index = pm8001_read_32(pi_virt);
1489 			circularQ->producer_index = cpu_to_le32(producer_index);
1490 		}
1491 	} while (le32_to_cpu(circularQ->producer_index) !=
1492 		circularQ->consumer_idx);
1493 	/* while we don't have any more not-yet-delivered message */
1494 	/* report empty */
1495 	return MPI_IO_STATUS_BUSY;
1496 }
1497 
pm8001_work_fn(struct work_struct * work)1498 void pm8001_work_fn(struct work_struct *work)
1499 {
1500 	struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1501 	struct pm8001_device *pm8001_dev;
1502 	struct domain_device *dev;
1503 
1504 	/*
1505 	 * So far, all users of this stash an associated structure here.
1506 	 * If we get here, and this pointer is null, then the action
1507 	 * was cancelled. This nullification happens when the device
1508 	 * goes away.
1509 	 */
1510 	if (pw->handler != IO_FATAL_ERROR) {
1511 		pm8001_dev = pw->data; /* Most stash device structure */
1512 		if ((pm8001_dev == NULL)
1513 		 || ((pw->handler != IO_XFER_ERROR_BREAK)
1514 			 && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
1515 			kfree(pw);
1516 			return;
1517 		}
1518 	}
1519 
1520 	switch (pw->handler) {
1521 	case IO_XFER_ERROR_BREAK:
1522 	{	/* This one stashes the sas_task instead */
1523 		struct sas_task *t = (struct sas_task *)pm8001_dev;
1524 		struct pm8001_ccb_info *ccb;
1525 		struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1526 		unsigned long flags, flags1;
1527 		struct task_status_struct *ts;
1528 		int i;
1529 
1530 		if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1531 			break; /* Task still on lu */
1532 		spin_lock_irqsave(&pm8001_ha->lock, flags);
1533 
1534 		spin_lock_irqsave(&t->task_state_lock, flags1);
1535 		if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1536 			spin_unlock_irqrestore(&t->task_state_lock, flags1);
1537 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1538 			break; /* Task got completed by another */
1539 		}
1540 		spin_unlock_irqrestore(&t->task_state_lock, flags1);
1541 
1542 		/* Search for a possible ccb that matches the task */
1543 		for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1544 			ccb = &pm8001_ha->ccb_info[i];
1545 			if ((ccb->ccb_tag != PM8001_INVALID_TAG) &&
1546 			    (ccb->task == t))
1547 				break;
1548 		}
1549 		if (!ccb) {
1550 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1551 			break; /* Task got freed by another */
1552 		}
1553 		ts = &t->task_status;
1554 		ts->resp = SAS_TASK_COMPLETE;
1555 		/* Force the midlayer to retry */
1556 		ts->stat = SAS_QUEUE_FULL;
1557 		pm8001_dev = ccb->device;
1558 		if (pm8001_dev)
1559 			atomic_dec(&pm8001_dev->running_req);
1560 		spin_lock_irqsave(&t->task_state_lock, flags1);
1561 		t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1562 		t->task_state_flags |= SAS_TASK_STATE_DONE;
1563 		if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1564 			spin_unlock_irqrestore(&t->task_state_lock, flags1);
1565 			pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
1566 				   t, pw->handler, ts->resp, ts->stat);
1567 			pm8001_ccb_task_free(pm8001_ha, ccb);
1568 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1569 		} else {
1570 			spin_unlock_irqrestore(&t->task_state_lock, flags1);
1571 			pm8001_ccb_task_free(pm8001_ha, ccb);
1572 			mb();/* in order to force CPU ordering */
1573 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1574 			t->task_done(t);
1575 		}
1576 	}	break;
1577 	case IO_XFER_OPEN_RETRY_TIMEOUT:
1578 	{	/* This one stashes the sas_task instead */
1579 		struct sas_task *t = (struct sas_task *)pm8001_dev;
1580 		struct pm8001_ccb_info *ccb;
1581 		struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1582 		unsigned long flags, flags1;
1583 		int i, ret = 0;
1584 
1585 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
1586 
1587 		ret = pm8001_query_task(t);
1588 
1589 		if (ret == TMF_RESP_FUNC_SUCC)
1590 			pm8001_dbg(pm8001_ha, IO, "...Task on lu\n");
1591 		else if (ret == TMF_RESP_FUNC_COMPLETE)
1592 			pm8001_dbg(pm8001_ha, IO, "...Task NOT on lu\n");
1593 		else
1594 			pm8001_dbg(pm8001_ha, DEVIO, "...query task failed!!!\n");
1595 
1596 		spin_lock_irqsave(&pm8001_ha->lock, flags);
1597 
1598 		spin_lock_irqsave(&t->task_state_lock, flags1);
1599 
1600 		if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1601 			spin_unlock_irqrestore(&t->task_state_lock, flags1);
1602 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1603 			if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1604 				(void)pm8001_abort_task(t);
1605 			break; /* Task got completed by another */
1606 		}
1607 
1608 		spin_unlock_irqrestore(&t->task_state_lock, flags1);
1609 
1610 		/* Search for a possible ccb that matches the task */
1611 		for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1612 			ccb = &pm8001_ha->ccb_info[i];
1613 			if ((ccb->ccb_tag != PM8001_INVALID_TAG) &&
1614 			    (ccb->task == t))
1615 				break;
1616 		}
1617 		if (!ccb) {
1618 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1619 			if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1620 				(void)pm8001_abort_task(t);
1621 			break; /* Task got freed by another */
1622 		}
1623 
1624 		pm8001_dev = ccb->device;
1625 		dev = pm8001_dev->sas_device;
1626 
1627 		switch (ret) {
1628 		case TMF_RESP_FUNC_SUCC: /* task on lu */
1629 			ccb->open_retry = 1; /* Snub completion */
1630 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1631 			ret = pm8001_abort_task(t);
1632 			ccb->open_retry = 0;
1633 			switch (ret) {
1634 			case TMF_RESP_FUNC_SUCC:
1635 			case TMF_RESP_FUNC_COMPLETE:
1636 				break;
1637 			default: /* device misbehavior */
1638 				ret = TMF_RESP_FUNC_FAILED;
1639 				pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1640 				pm8001_I_T_nexus_reset(dev);
1641 				break;
1642 			}
1643 			break;
1644 
1645 		case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1646 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1647 			/* Do we need to abort the task locally? */
1648 			break;
1649 
1650 		default: /* device misbehavior */
1651 			spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1652 			ret = TMF_RESP_FUNC_FAILED;
1653 			pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1654 			pm8001_I_T_nexus_reset(dev);
1655 		}
1656 
1657 		if (ret == TMF_RESP_FUNC_FAILED)
1658 			t = NULL;
1659 		pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1660 		pm8001_dbg(pm8001_ha, IO, "...Complete\n");
1661 	}	break;
1662 	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1663 		dev = pm8001_dev->sas_device;
1664 		pm8001_I_T_nexus_event_handler(dev);
1665 		break;
1666 	case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1667 		dev = pm8001_dev->sas_device;
1668 		pm8001_I_T_nexus_reset(dev);
1669 		break;
1670 	case IO_DS_IN_ERROR:
1671 		dev = pm8001_dev->sas_device;
1672 		pm8001_I_T_nexus_reset(dev);
1673 		break;
1674 	case IO_DS_NON_OPERATIONAL:
1675 		dev = pm8001_dev->sas_device;
1676 		pm8001_I_T_nexus_reset(dev);
1677 		break;
1678 	case IO_FATAL_ERROR:
1679 	{
1680 		struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1681 		struct pm8001_ccb_info *ccb;
1682 		struct task_status_struct *ts;
1683 		struct sas_task *task;
1684 		int i;
1685 		u32 device_id;
1686 
1687 		for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1688 			ccb = &pm8001_ha->ccb_info[i];
1689 			task = ccb->task;
1690 			ts = &task->task_status;
1691 
1692 			if (task != NULL) {
1693 				dev = task->dev;
1694 				if (!dev) {
1695 					pm8001_dbg(pm8001_ha, FAIL,
1696 						"dev is NULL\n");
1697 					continue;
1698 				}
1699 				/*complete sas task and update to top layer */
1700 				pm8001_ccb_task_free(pm8001_ha, ccb);
1701 				ts->resp = SAS_TASK_COMPLETE;
1702 				task->task_done(task);
1703 			} else if (ccb->ccb_tag != PM8001_INVALID_TAG) {
1704 				/* complete the internal commands/non-sas task */
1705 				pm8001_dev = ccb->device;
1706 				if (pm8001_dev->dcompletion) {
1707 					complete(pm8001_dev->dcompletion);
1708 					pm8001_dev->dcompletion = NULL;
1709 				}
1710 				complete(pm8001_ha->nvmd_completion);
1711 				pm8001_ccb_free(pm8001_ha, ccb);
1712 			}
1713 		}
1714 		/* Deregister all the device ids  */
1715 		for (i = 0; i < PM8001_MAX_DEVICES; i++) {
1716 			pm8001_dev = &pm8001_ha->devices[i];
1717 			device_id = pm8001_dev->device_id;
1718 			if (device_id) {
1719 				PM8001_CHIP_DISP->dereg_dev_req(pm8001_ha, device_id);
1720 				pm8001_free_dev(pm8001_dev);
1721 			}
1722 		}
1723 	}	break;
1724 	}
1725 	kfree(pw);
1726 }
1727 
pm8001_handle_event(struct pm8001_hba_info * pm8001_ha,void * data,int handler)1728 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1729 			       int handler)
1730 {
1731 	struct pm8001_work *pw;
1732 	int ret = 0;
1733 
1734 	pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1735 	if (pw) {
1736 		pw->pm8001_ha = pm8001_ha;
1737 		pw->data = data;
1738 		pw->handler = handler;
1739 		INIT_WORK(&pw->work, pm8001_work_fn);
1740 		queue_work(pm8001_wq, &pw->work);
1741 	} else
1742 		ret = -ENOMEM;
1743 
1744 	return ret;
1745 }
1746 
pm8001_send_abort_all(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_ha_dev)1747 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1748 		struct pm8001_device *pm8001_ha_dev)
1749 {
1750 	struct pm8001_ccb_info *ccb;
1751 	struct sas_task *task;
1752 	struct task_abort_req task_abort;
1753 	u32 opc = OPC_INB_SATA_ABORT;
1754 	int ret;
1755 
1756 	pm8001_ha_dev->id |= NCQ_ABORT_ALL_FLAG;
1757 	pm8001_ha_dev->id &= ~NCQ_READ_LOG_FLAG;
1758 
1759 	task = sas_alloc_slow_task(GFP_ATOMIC);
1760 	if (!task) {
1761 		pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1762 		return;
1763 	}
1764 
1765 	task->task_done = pm8001_task_done;
1766 
1767 	ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_ha_dev, task);
1768 	if (!ccb) {
1769 		sas_free_task(task);
1770 		return;
1771 	}
1772 
1773 	memset(&task_abort, 0, sizeof(task_abort));
1774 	task_abort.abort_all = cpu_to_le32(1);
1775 	task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1776 	task_abort.tag = cpu_to_le32(ccb->ccb_tag);
1777 
1778 	ret = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &task_abort,
1779 				   sizeof(task_abort), 0);
1780 	if (ret) {
1781 		sas_free_task(task);
1782 		pm8001_ccb_free(pm8001_ha, ccb);
1783 	}
1784 }
1785 
pm8001_send_read_log(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_ha_dev)1786 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
1787 		struct pm8001_device *pm8001_ha_dev)
1788 {
1789 	struct sata_start_req sata_cmd;
1790 	int res;
1791 	struct pm8001_ccb_info *ccb;
1792 	struct sas_task *task = NULL;
1793 	struct host_to_dev_fis fis;
1794 	struct domain_device *dev;
1795 	u32 opc = OPC_INB_SATA_HOST_OPSTART;
1796 
1797 	task = sas_alloc_slow_task(GFP_ATOMIC);
1798 	if (!task) {
1799 		pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1800 		return;
1801 	}
1802 	task->task_done = pm8001_task_done;
1803 
1804 	/*
1805 	 * Allocate domain device by ourselves as libsas is not going to
1806 	 * provide any.
1807 	 */
1808 	dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1809 	if (!dev) {
1810 		sas_free_task(task);
1811 		pm8001_dbg(pm8001_ha, FAIL,
1812 			   "Domain device cannot be allocated\n");
1813 		return;
1814 	}
1815 	task->dev = dev;
1816 	task->dev->lldd_dev = pm8001_ha_dev;
1817 
1818 	ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_ha_dev, task);
1819 	if (!ccb) {
1820 		sas_free_task(task);
1821 		kfree(dev);
1822 		return;
1823 	}
1824 
1825 	pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1826 	pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1827 
1828 	/* construct read log FIS */
1829 	memset(&fis, 0, sizeof(struct host_to_dev_fis));
1830 	fis.fis_type = 0x27;
1831 	fis.flags = 0x80;
1832 	fis.command = ATA_CMD_READ_LOG_EXT;
1833 	fis.lbal = 0x10;
1834 	fis.sector_count = 0x1;
1835 
1836 	memset(&sata_cmd, 0, sizeof(sata_cmd));
1837 	sata_cmd.tag = cpu_to_le32(ccb->ccb_tag);
1838 	sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1839 	sata_cmd.ncqtag_atap_dir_m = cpu_to_le32((0x1 << 7) | (0x5 << 9));
1840 	memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1841 
1842 	res = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sata_cmd,
1843 				   sizeof(sata_cmd), 0);
1844 	if (res) {
1845 		sas_free_task(task);
1846 		pm8001_ccb_free(pm8001_ha, ccb);
1847 		kfree(dev);
1848 	}
1849 }
1850 
1851 /**
1852  * mpi_ssp_completion- process the event that FW response to the SSP request.
1853  * @pm8001_ha: our hba card information
1854  * @piomb: the message contents of this outbound message.
1855  *
1856  * When FW has completed a ssp request for example a IO request, after it has
1857  * filled the SG data with the data, it will trigger this event representing
1858  * that he has finished the job; please check the corresponding buffer.
1859  * So we will tell the caller who maybe waiting the result to tell upper layer
1860  * that the task has been finished.
1861  */
1862 static void
mpi_ssp_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)1863 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1864 {
1865 	struct sas_task *t;
1866 	struct pm8001_ccb_info *ccb;
1867 	unsigned long flags;
1868 	u32 status;
1869 	u32 param;
1870 	u32 tag;
1871 	struct ssp_completion_resp *psspPayload;
1872 	struct task_status_struct *ts;
1873 	struct ssp_response_iu *iu;
1874 	struct pm8001_device *pm8001_dev;
1875 	psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1876 	status = le32_to_cpu(psspPayload->status);
1877 	tag = le32_to_cpu(psspPayload->tag);
1878 	ccb = &pm8001_ha->ccb_info[tag];
1879 	if ((status == IO_ABORTED) && ccb->open_retry) {
1880 		/* Being completed by another */
1881 		ccb->open_retry = 0;
1882 		return;
1883 	}
1884 	pm8001_dev = ccb->device;
1885 	param = le32_to_cpu(psspPayload->param);
1886 
1887 	t = ccb->task;
1888 
1889 	if (status && status != IO_UNDERFLOW)
1890 		pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1891 	if (unlikely(!t || !t->lldd_task || !t->dev))
1892 		return;
1893 	ts = &t->task_status;
1894 	/* Print sas address of IO failed device */
1895 	if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1896 		(status != IO_UNDERFLOW))
1897 		pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1898 			   SAS_ADDR(t->dev->sas_addr));
1899 
1900 	if (status)
1901 		pm8001_dbg(pm8001_ha, IOERR,
1902 			   "status:0x%x, tag:0x%x, task:0x%p\n",
1903 			   status, tag, t);
1904 
1905 	switch (status) {
1906 	case IO_SUCCESS:
1907 		pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS,param = %d\n",
1908 			   param);
1909 		if (param == 0) {
1910 			ts->resp = SAS_TASK_COMPLETE;
1911 			ts->stat = SAS_SAM_STAT_GOOD;
1912 		} else {
1913 			ts->resp = SAS_TASK_COMPLETE;
1914 			ts->stat = SAS_PROTO_RESPONSE;
1915 			ts->residual = param;
1916 			iu = &psspPayload->ssp_resp_iu;
1917 			sas_ssp_task_response(pm8001_ha->dev, t, iu);
1918 		}
1919 		if (pm8001_dev)
1920 			atomic_dec(&pm8001_dev->running_req);
1921 		break;
1922 	case IO_ABORTED:
1923 		pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1924 		ts->resp = SAS_TASK_COMPLETE;
1925 		ts->stat = SAS_ABORTED_TASK;
1926 		break;
1927 	case IO_UNDERFLOW:
1928 		/* SSP Completion with error */
1929 		pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW,param = %d\n",
1930 			   param);
1931 		ts->resp = SAS_TASK_COMPLETE;
1932 		ts->stat = SAS_DATA_UNDERRUN;
1933 		ts->residual = param;
1934 		if (pm8001_dev)
1935 			atomic_dec(&pm8001_dev->running_req);
1936 		break;
1937 	case IO_NO_DEVICE:
1938 		pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1939 		ts->resp = SAS_TASK_UNDELIVERED;
1940 		ts->stat = SAS_PHY_DOWN;
1941 		break;
1942 	case IO_XFER_ERROR_BREAK:
1943 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1944 		ts->resp = SAS_TASK_COMPLETE;
1945 		ts->stat = SAS_OPEN_REJECT;
1946 		/* Force the midlayer to retry */
1947 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1948 		break;
1949 	case IO_XFER_ERROR_PHY_NOT_READY:
1950 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1951 		ts->resp = SAS_TASK_COMPLETE;
1952 		ts->stat = SAS_OPEN_REJECT;
1953 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1954 		break;
1955 	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1956 		pm8001_dbg(pm8001_ha, IO,
1957 			   "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
1958 		ts->resp = SAS_TASK_COMPLETE;
1959 		ts->stat = SAS_OPEN_REJECT;
1960 		ts->open_rej_reason = SAS_OREJ_EPROTO;
1961 		break;
1962 	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1963 		pm8001_dbg(pm8001_ha, IO,
1964 			   "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
1965 		ts->resp = SAS_TASK_COMPLETE;
1966 		ts->stat = SAS_OPEN_REJECT;
1967 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1968 		break;
1969 	case IO_OPEN_CNX_ERROR_BREAK:
1970 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
1971 		ts->resp = SAS_TASK_COMPLETE;
1972 		ts->stat = SAS_OPEN_REJECT;
1973 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1974 		break;
1975 	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1976 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
1977 		ts->resp = SAS_TASK_COMPLETE;
1978 		ts->stat = SAS_OPEN_REJECT;
1979 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1980 		if (!t->uldd_task)
1981 			pm8001_handle_event(pm8001_ha,
1982 				pm8001_dev,
1983 				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1984 		break;
1985 	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1986 		pm8001_dbg(pm8001_ha, IO,
1987 			   "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
1988 		ts->resp = SAS_TASK_COMPLETE;
1989 		ts->stat = SAS_OPEN_REJECT;
1990 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1991 		break;
1992 	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1993 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
1994 		ts->resp = SAS_TASK_COMPLETE;
1995 		ts->stat = SAS_OPEN_REJECT;
1996 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1997 		break;
1998 	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1999 		pm8001_dbg(pm8001_ha, IO,
2000 			   "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2001 		ts->resp = SAS_TASK_UNDELIVERED;
2002 		ts->stat = SAS_OPEN_REJECT;
2003 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2004 		break;
2005 	case IO_XFER_ERROR_NAK_RECEIVED:
2006 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2007 		ts->resp = SAS_TASK_COMPLETE;
2008 		ts->stat = SAS_OPEN_REJECT;
2009 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2010 		break;
2011 	case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2012 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2013 		ts->resp = SAS_TASK_COMPLETE;
2014 		ts->stat = SAS_NAK_R_ERR;
2015 		break;
2016 	case IO_XFER_ERROR_DMA:
2017 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2018 		ts->resp = SAS_TASK_COMPLETE;
2019 		ts->stat = SAS_OPEN_REJECT;
2020 		break;
2021 	case IO_XFER_OPEN_RETRY_TIMEOUT:
2022 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2023 		ts->resp = SAS_TASK_COMPLETE;
2024 		ts->stat = SAS_OPEN_REJECT;
2025 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2026 		break;
2027 	case IO_XFER_ERROR_OFFSET_MISMATCH:
2028 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2029 		ts->resp = SAS_TASK_COMPLETE;
2030 		ts->stat = SAS_OPEN_REJECT;
2031 		break;
2032 	case IO_PORT_IN_RESET:
2033 		pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2034 		ts->resp = SAS_TASK_COMPLETE;
2035 		ts->stat = SAS_OPEN_REJECT;
2036 		break;
2037 	case IO_DS_NON_OPERATIONAL:
2038 		pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2039 		ts->resp = SAS_TASK_COMPLETE;
2040 		ts->stat = SAS_OPEN_REJECT;
2041 		if (!t->uldd_task)
2042 			pm8001_handle_event(pm8001_ha,
2043 				pm8001_dev,
2044 				IO_DS_NON_OPERATIONAL);
2045 		break;
2046 	case IO_DS_IN_RECOVERY:
2047 		pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2048 		ts->resp = SAS_TASK_COMPLETE;
2049 		ts->stat = SAS_OPEN_REJECT;
2050 		break;
2051 	case IO_TM_TAG_NOT_FOUND:
2052 		pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2053 		ts->resp = SAS_TASK_COMPLETE;
2054 		ts->stat = SAS_OPEN_REJECT;
2055 		break;
2056 	case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2057 		pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2058 		ts->resp = SAS_TASK_COMPLETE;
2059 		ts->stat = SAS_OPEN_REJECT;
2060 		break;
2061 	case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2062 		pm8001_dbg(pm8001_ha, IO,
2063 			   "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2064 		ts->resp = SAS_TASK_COMPLETE;
2065 		ts->stat = SAS_OPEN_REJECT;
2066 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2067 		break;
2068 	default:
2069 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2070 		/* not allowed case. Therefore, return failed status */
2071 		ts->resp = SAS_TASK_COMPLETE;
2072 		ts->stat = SAS_OPEN_REJECT;
2073 		break;
2074 	}
2075 	pm8001_dbg(pm8001_ha, IO, "scsi_status = %x\n",
2076 		   psspPayload->ssp_resp_iu.status);
2077 	spin_lock_irqsave(&t->task_state_lock, flags);
2078 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2079 	t->task_state_flags |= SAS_TASK_STATE_DONE;
2080 	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2081 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2082 		pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2083 			   t, status, ts->resp, ts->stat);
2084 		pm8001_ccb_task_free(pm8001_ha, ccb);
2085 	} else {
2086 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2087 		pm8001_ccb_task_free(pm8001_ha, ccb);
2088 		mb();/* in order to force CPU ordering */
2089 		t->task_done(t);
2090 	}
2091 }
2092 
2093 /*See the comments for mpi_ssp_completion */
mpi_ssp_event(struct pm8001_hba_info * pm8001_ha,void * piomb)2094 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2095 {
2096 	struct sas_task *t;
2097 	unsigned long flags;
2098 	struct task_status_struct *ts;
2099 	struct pm8001_ccb_info *ccb;
2100 	struct pm8001_device *pm8001_dev;
2101 	struct ssp_event_resp *psspPayload =
2102 		(struct ssp_event_resp *)(piomb + 4);
2103 	u32 event = le32_to_cpu(psspPayload->event);
2104 	u32 tag = le32_to_cpu(psspPayload->tag);
2105 	u32 port_id = le32_to_cpu(psspPayload->port_id);
2106 	u32 dev_id = le32_to_cpu(psspPayload->device_id);
2107 
2108 	ccb = &pm8001_ha->ccb_info[tag];
2109 	t = ccb->task;
2110 	pm8001_dev = ccb->device;
2111 	if (event)
2112 		pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2113 	if (unlikely(!t || !t->lldd_task || !t->dev))
2114 		return;
2115 	ts = &t->task_status;
2116 	pm8001_dbg(pm8001_ha, DEVIO, "port_id = %x,device_id = %x\n",
2117 		   port_id, dev_id);
2118 	switch (event) {
2119 	case IO_OVERFLOW:
2120 		pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2121 		ts->resp = SAS_TASK_COMPLETE;
2122 		ts->stat = SAS_DATA_OVERRUN;
2123 		ts->residual = 0;
2124 		if (pm8001_dev)
2125 			atomic_dec(&pm8001_dev->running_req);
2126 		break;
2127 	case IO_XFER_ERROR_BREAK:
2128 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2129 		pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2130 		return;
2131 	case IO_XFER_ERROR_PHY_NOT_READY:
2132 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2133 		ts->resp = SAS_TASK_COMPLETE;
2134 		ts->stat = SAS_OPEN_REJECT;
2135 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2136 		break;
2137 	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2138 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2139 		ts->resp = SAS_TASK_COMPLETE;
2140 		ts->stat = SAS_OPEN_REJECT;
2141 		ts->open_rej_reason = SAS_OREJ_EPROTO;
2142 		break;
2143 	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2144 		pm8001_dbg(pm8001_ha, IO,
2145 			   "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2146 		ts->resp = SAS_TASK_COMPLETE;
2147 		ts->stat = SAS_OPEN_REJECT;
2148 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2149 		break;
2150 	case IO_OPEN_CNX_ERROR_BREAK:
2151 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2152 		ts->resp = SAS_TASK_COMPLETE;
2153 		ts->stat = SAS_OPEN_REJECT;
2154 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2155 		break;
2156 	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2157 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2158 		ts->resp = SAS_TASK_COMPLETE;
2159 		ts->stat = SAS_OPEN_REJECT;
2160 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2161 		if (!t->uldd_task)
2162 			pm8001_handle_event(pm8001_ha,
2163 				pm8001_dev,
2164 				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2165 		break;
2166 	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2167 		pm8001_dbg(pm8001_ha, IO,
2168 			   "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2169 		ts->resp = SAS_TASK_COMPLETE;
2170 		ts->stat = SAS_OPEN_REJECT;
2171 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2172 		break;
2173 	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2174 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2175 		ts->resp = SAS_TASK_COMPLETE;
2176 		ts->stat = SAS_OPEN_REJECT;
2177 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2178 		break;
2179 	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2180 		pm8001_dbg(pm8001_ha, IO,
2181 			   "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2182 		ts->resp = SAS_TASK_COMPLETE;
2183 		ts->stat = SAS_OPEN_REJECT;
2184 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2185 		break;
2186 	case IO_XFER_ERROR_NAK_RECEIVED:
2187 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2188 		ts->resp = SAS_TASK_COMPLETE;
2189 		ts->stat = SAS_OPEN_REJECT;
2190 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2191 		break;
2192 	case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2193 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2194 		ts->resp = SAS_TASK_COMPLETE;
2195 		ts->stat = SAS_NAK_R_ERR;
2196 		break;
2197 	case IO_XFER_OPEN_RETRY_TIMEOUT:
2198 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2199 		pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2200 		return;
2201 	case IO_XFER_ERROR_UNEXPECTED_PHASE:
2202 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2203 		ts->resp = SAS_TASK_COMPLETE;
2204 		ts->stat = SAS_DATA_OVERRUN;
2205 		break;
2206 	case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2207 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2208 		ts->resp = SAS_TASK_COMPLETE;
2209 		ts->stat = SAS_DATA_OVERRUN;
2210 		break;
2211 	case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2212 		pm8001_dbg(pm8001_ha, IO,
2213 			   "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2214 		ts->resp = SAS_TASK_COMPLETE;
2215 		ts->stat = SAS_DATA_OVERRUN;
2216 		break;
2217 	case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2218 		pm8001_dbg(pm8001_ha, IO,
2219 			   "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2220 		ts->resp = SAS_TASK_COMPLETE;
2221 		ts->stat = SAS_DATA_OVERRUN;
2222 		break;
2223 	case IO_XFER_ERROR_OFFSET_MISMATCH:
2224 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2225 		ts->resp = SAS_TASK_COMPLETE;
2226 		ts->stat = SAS_DATA_OVERRUN;
2227 		break;
2228 	case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2229 		pm8001_dbg(pm8001_ha, IO,
2230 			   "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2231 		ts->resp = SAS_TASK_COMPLETE;
2232 		ts->stat = SAS_DATA_OVERRUN;
2233 		break;
2234 	case IO_XFER_CMD_FRAME_ISSUED:
2235 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2236 		return;
2237 	default:
2238 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2239 		/* not allowed case. Therefore, return failed status */
2240 		ts->resp = SAS_TASK_COMPLETE;
2241 		ts->stat = SAS_DATA_OVERRUN;
2242 		break;
2243 	}
2244 	spin_lock_irqsave(&t->task_state_lock, flags);
2245 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2246 	t->task_state_flags |= SAS_TASK_STATE_DONE;
2247 	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2248 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2249 		pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2250 			   t, event, ts->resp, ts->stat);
2251 		pm8001_ccb_task_free(pm8001_ha, ccb);
2252 	} else {
2253 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2254 		pm8001_ccb_task_free(pm8001_ha, ccb);
2255 		mb();/* in order to force CPU ordering */
2256 		t->task_done(t);
2257 	}
2258 }
2259 
2260 /*See the comments for mpi_ssp_completion */
2261 static void
mpi_sata_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)2262 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2263 {
2264 	struct sas_task *t;
2265 	struct pm8001_ccb_info *ccb;
2266 	u32 param;
2267 	u32 status;
2268 	u32 tag;
2269 	int i, j;
2270 	u8 sata_addr_low[4];
2271 	u32 temp_sata_addr_low;
2272 	u8 sata_addr_hi[4];
2273 	u32 temp_sata_addr_hi;
2274 	struct sata_completion_resp *psataPayload;
2275 	struct task_status_struct *ts;
2276 	struct ata_task_resp *resp ;
2277 	u32 *sata_resp;
2278 	struct pm8001_device *pm8001_dev;
2279 	unsigned long flags;
2280 
2281 	psataPayload = (struct sata_completion_resp *)(piomb + 4);
2282 	status = le32_to_cpu(psataPayload->status);
2283 	param = le32_to_cpu(psataPayload->param);
2284 	tag = le32_to_cpu(psataPayload->tag);
2285 
2286 	ccb = &pm8001_ha->ccb_info[tag];
2287 	t = ccb->task;
2288 	pm8001_dev = ccb->device;
2289 
2290 	if (t) {
2291 		if (t->dev && (t->dev->lldd_dev))
2292 			pm8001_dev = t->dev->lldd_dev;
2293 	} else {
2294 		pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2295 		return;
2296 	}
2297 
2298 	if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2299 		&& unlikely(!t || !t->lldd_task || !t->dev)) {
2300 		pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2301 		return;
2302 	}
2303 
2304 	ts = &t->task_status;
2305 
2306 	if (status)
2307 		pm8001_dbg(pm8001_ha, IOERR,
2308 			   "status:0x%x, tag:0x%x, task::0x%p\n",
2309 			   status, tag, t);
2310 
2311 	/* Print sas address of IO failed device */
2312 	if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2313 		(status != IO_UNDERFLOW)) {
2314 		if (!((t->dev->parent) &&
2315 			(dev_is_expander(t->dev->parent->dev_type)))) {
2316 			for (i = 0, j = 4; j <= 7 && i <= 3; i++, j++)
2317 				sata_addr_low[i] = pm8001_ha->sas_addr[j];
2318 			for (i = 0, j = 0; j <= 3 && i <= 3; i++, j++)
2319 				sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2320 			memcpy(&temp_sata_addr_low, sata_addr_low,
2321 				sizeof(sata_addr_low));
2322 			memcpy(&temp_sata_addr_hi, sata_addr_hi,
2323 				sizeof(sata_addr_hi));
2324 			temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2325 						|((temp_sata_addr_hi << 8) &
2326 						0xff0000) |
2327 						((temp_sata_addr_hi >> 8)
2328 						& 0xff00) |
2329 						((temp_sata_addr_hi << 24) &
2330 						0xff000000));
2331 			temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2332 						& 0xff) |
2333 						((temp_sata_addr_low << 8)
2334 						& 0xff0000) |
2335 						((temp_sata_addr_low >> 8)
2336 						& 0xff00) |
2337 						((temp_sata_addr_low << 24)
2338 						& 0xff000000)) +
2339 						pm8001_dev->attached_phy +
2340 						0x10);
2341 			pm8001_dbg(pm8001_ha, FAIL,
2342 				   "SAS Address of IO Failure Drive:%08x%08x\n",
2343 				   temp_sata_addr_hi,
2344 				   temp_sata_addr_low);
2345 		} else {
2346 			pm8001_dbg(pm8001_ha, FAIL,
2347 				   "SAS Address of IO Failure Drive:%016llx\n",
2348 				   SAS_ADDR(t->dev->sas_addr));
2349 		}
2350 	}
2351 	switch (status) {
2352 	case IO_SUCCESS:
2353 		pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2354 		if (param == 0) {
2355 			ts->resp = SAS_TASK_COMPLETE;
2356 			ts->stat = SAS_SAM_STAT_GOOD;
2357 			/* check if response is for SEND READ LOG */
2358 			if (pm8001_dev &&
2359 			    (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2360 				pm8001_send_abort_all(pm8001_ha, pm8001_dev);
2361 				/* Free the tag */
2362 				pm8001_tag_free(pm8001_ha, tag);
2363 				sas_free_task(t);
2364 				return;
2365 			}
2366 		} else {
2367 			u8 len;
2368 			ts->resp = SAS_TASK_COMPLETE;
2369 			ts->stat = SAS_PROTO_RESPONSE;
2370 			ts->residual = param;
2371 			pm8001_dbg(pm8001_ha, IO,
2372 				   "SAS_PROTO_RESPONSE len = %d\n",
2373 				   param);
2374 			sata_resp = &psataPayload->sata_resp[0];
2375 			resp = (struct ata_task_resp *)ts->buf;
2376 			if (t->ata_task.dma_xfer == 0 &&
2377 			    t->data_dir == DMA_FROM_DEVICE) {
2378 				len = sizeof(struct pio_setup_fis);
2379 				pm8001_dbg(pm8001_ha, IO,
2380 					   "PIO read len = %d\n", len);
2381 			} else if (t->ata_task.use_ncq &&
2382 				   t->data_dir != DMA_NONE) {
2383 				len = sizeof(struct set_dev_bits_fis);
2384 				pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2385 					   len);
2386 			} else {
2387 				len = sizeof(struct dev_to_host_fis);
2388 				pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2389 					   len);
2390 			}
2391 			if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2392 				resp->frame_len = len;
2393 				memcpy(&resp->ending_fis[0], sata_resp, len);
2394 				ts->buf_valid_size = sizeof(*resp);
2395 			} else
2396 				pm8001_dbg(pm8001_ha, IO,
2397 					   "response too large\n");
2398 		}
2399 		if (pm8001_dev)
2400 			atomic_dec(&pm8001_dev->running_req);
2401 		break;
2402 	case IO_ABORTED:
2403 		pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2404 		ts->resp = SAS_TASK_COMPLETE;
2405 		ts->stat = SAS_ABORTED_TASK;
2406 		if (pm8001_dev)
2407 			atomic_dec(&pm8001_dev->running_req);
2408 		break;
2409 		/* following cases are to do cases */
2410 	case IO_UNDERFLOW:
2411 		/* SATA Completion with error */
2412 		pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2413 		ts->resp = SAS_TASK_COMPLETE;
2414 		ts->stat = SAS_DATA_UNDERRUN;
2415 		ts->residual =  param;
2416 		if (pm8001_dev)
2417 			atomic_dec(&pm8001_dev->running_req);
2418 		break;
2419 	case IO_NO_DEVICE:
2420 		pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2421 		ts->resp = SAS_TASK_UNDELIVERED;
2422 		ts->stat = SAS_PHY_DOWN;
2423 		if (pm8001_dev)
2424 			atomic_dec(&pm8001_dev->running_req);
2425 		break;
2426 	case IO_XFER_ERROR_BREAK:
2427 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2428 		ts->resp = SAS_TASK_COMPLETE;
2429 		ts->stat = SAS_INTERRUPTED;
2430 		if (pm8001_dev)
2431 			atomic_dec(&pm8001_dev->running_req);
2432 		break;
2433 	case IO_XFER_ERROR_PHY_NOT_READY:
2434 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2435 		ts->resp = SAS_TASK_COMPLETE;
2436 		ts->stat = SAS_OPEN_REJECT;
2437 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2438 		if (pm8001_dev)
2439 			atomic_dec(&pm8001_dev->running_req);
2440 		break;
2441 	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2442 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2443 		ts->resp = SAS_TASK_COMPLETE;
2444 		ts->stat = SAS_OPEN_REJECT;
2445 		ts->open_rej_reason = SAS_OREJ_EPROTO;
2446 		if (pm8001_dev)
2447 			atomic_dec(&pm8001_dev->running_req);
2448 		break;
2449 	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2450 		pm8001_dbg(pm8001_ha, IO,
2451 			   "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2452 		ts->resp = SAS_TASK_COMPLETE;
2453 		ts->stat = SAS_OPEN_REJECT;
2454 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2455 		if (pm8001_dev)
2456 			atomic_dec(&pm8001_dev->running_req);
2457 		break;
2458 	case IO_OPEN_CNX_ERROR_BREAK:
2459 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2460 		ts->resp = SAS_TASK_COMPLETE;
2461 		ts->stat = SAS_OPEN_REJECT;
2462 		ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2463 		if (pm8001_dev)
2464 			atomic_dec(&pm8001_dev->running_req);
2465 		break;
2466 	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2467 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2468 		ts->resp = SAS_TASK_COMPLETE;
2469 		ts->stat = SAS_DEV_NO_RESPONSE;
2470 		if (!t->uldd_task) {
2471 			pm8001_handle_event(pm8001_ha,
2472 				pm8001_dev,
2473 				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2474 			ts->resp = SAS_TASK_UNDELIVERED;
2475 			ts->stat = SAS_QUEUE_FULL;
2476 			pm8001_ccb_task_free_done(pm8001_ha, ccb);
2477 			return;
2478 		}
2479 		break;
2480 	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2481 		pm8001_dbg(pm8001_ha, IO,
2482 			   "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2483 		ts->resp = SAS_TASK_UNDELIVERED;
2484 		ts->stat = SAS_OPEN_REJECT;
2485 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2486 		if (!t->uldd_task) {
2487 			pm8001_handle_event(pm8001_ha,
2488 				pm8001_dev,
2489 				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2490 			ts->resp = SAS_TASK_UNDELIVERED;
2491 			ts->stat = SAS_QUEUE_FULL;
2492 			pm8001_ccb_task_free_done(pm8001_ha, ccb);
2493 			return;
2494 		}
2495 		break;
2496 	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2497 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2498 		ts->resp = SAS_TASK_COMPLETE;
2499 		ts->stat = SAS_OPEN_REJECT;
2500 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2501 		if (pm8001_dev)
2502 			atomic_dec(&pm8001_dev->running_req);
2503 		break;
2504 	case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2505 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2506 		ts->resp = SAS_TASK_COMPLETE;
2507 		ts->stat = SAS_DEV_NO_RESPONSE;
2508 		if (!t->uldd_task) {
2509 			pm8001_handle_event(pm8001_ha,
2510 				pm8001_dev,
2511 				IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2512 			ts->resp = SAS_TASK_UNDELIVERED;
2513 			ts->stat = SAS_QUEUE_FULL;
2514 			pm8001_ccb_task_free_done(pm8001_ha, ccb);
2515 			return;
2516 		}
2517 		break;
2518 	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2519 		pm8001_dbg(pm8001_ha, IO,
2520 			   "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2521 		ts->resp = SAS_TASK_COMPLETE;
2522 		ts->stat = SAS_OPEN_REJECT;
2523 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2524 		if (pm8001_dev)
2525 			atomic_dec(&pm8001_dev->running_req);
2526 		break;
2527 	case IO_XFER_ERROR_NAK_RECEIVED:
2528 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2529 		ts->resp = SAS_TASK_COMPLETE;
2530 		ts->stat = SAS_NAK_R_ERR;
2531 		if (pm8001_dev)
2532 			atomic_dec(&pm8001_dev->running_req);
2533 		break;
2534 	case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2535 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2536 		ts->resp = SAS_TASK_COMPLETE;
2537 		ts->stat = SAS_NAK_R_ERR;
2538 		if (pm8001_dev)
2539 			atomic_dec(&pm8001_dev->running_req);
2540 		break;
2541 	case IO_XFER_ERROR_DMA:
2542 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2543 		ts->resp = SAS_TASK_COMPLETE;
2544 		ts->stat = SAS_ABORTED_TASK;
2545 		if (pm8001_dev)
2546 			atomic_dec(&pm8001_dev->running_req);
2547 		break;
2548 	case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2549 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2550 		ts->resp = SAS_TASK_UNDELIVERED;
2551 		ts->stat = SAS_DEV_NO_RESPONSE;
2552 		if (pm8001_dev)
2553 			atomic_dec(&pm8001_dev->running_req);
2554 		break;
2555 	case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2556 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2557 		ts->resp = SAS_TASK_COMPLETE;
2558 		ts->stat = SAS_DATA_UNDERRUN;
2559 		if (pm8001_dev)
2560 			atomic_dec(&pm8001_dev->running_req);
2561 		break;
2562 	case IO_XFER_OPEN_RETRY_TIMEOUT:
2563 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2564 		ts->resp = SAS_TASK_COMPLETE;
2565 		ts->stat = SAS_OPEN_TO;
2566 		if (pm8001_dev)
2567 			atomic_dec(&pm8001_dev->running_req);
2568 		break;
2569 	case IO_PORT_IN_RESET:
2570 		pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2571 		ts->resp = SAS_TASK_COMPLETE;
2572 		ts->stat = SAS_DEV_NO_RESPONSE;
2573 		if (pm8001_dev)
2574 			atomic_dec(&pm8001_dev->running_req);
2575 		break;
2576 	case IO_DS_NON_OPERATIONAL:
2577 		pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2578 		ts->resp = SAS_TASK_COMPLETE;
2579 		ts->stat = SAS_DEV_NO_RESPONSE;
2580 		if (!t->uldd_task) {
2581 			pm8001_handle_event(pm8001_ha, pm8001_dev,
2582 				    IO_DS_NON_OPERATIONAL);
2583 			ts->resp = SAS_TASK_UNDELIVERED;
2584 			ts->stat = SAS_QUEUE_FULL;
2585 			pm8001_ccb_task_free_done(pm8001_ha, ccb);
2586 			return;
2587 		}
2588 		break;
2589 	case IO_DS_IN_RECOVERY:
2590 		pm8001_dbg(pm8001_ha, IO, "  IO_DS_IN_RECOVERY\n");
2591 		ts->resp = SAS_TASK_COMPLETE;
2592 		ts->stat = SAS_DEV_NO_RESPONSE;
2593 		if (pm8001_dev)
2594 			atomic_dec(&pm8001_dev->running_req);
2595 		break;
2596 	case IO_DS_IN_ERROR:
2597 		pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2598 		ts->resp = SAS_TASK_COMPLETE;
2599 		ts->stat = SAS_DEV_NO_RESPONSE;
2600 		if (!t->uldd_task) {
2601 			pm8001_handle_event(pm8001_ha, pm8001_dev,
2602 				    IO_DS_IN_ERROR);
2603 			ts->resp = SAS_TASK_UNDELIVERED;
2604 			ts->stat = SAS_QUEUE_FULL;
2605 			pm8001_ccb_task_free_done(pm8001_ha, ccb);
2606 			return;
2607 		}
2608 		break;
2609 	case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2610 		pm8001_dbg(pm8001_ha, IO,
2611 			   "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2612 		ts->resp = SAS_TASK_COMPLETE;
2613 		ts->stat = SAS_OPEN_REJECT;
2614 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2615 		if (pm8001_dev)
2616 			atomic_dec(&pm8001_dev->running_req);
2617 		break;
2618 	default:
2619 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2620 		/* not allowed case. Therefore, return failed status */
2621 		ts->resp = SAS_TASK_COMPLETE;
2622 		ts->stat = SAS_DEV_NO_RESPONSE;
2623 		if (pm8001_dev)
2624 			atomic_dec(&pm8001_dev->running_req);
2625 		break;
2626 	}
2627 	spin_lock_irqsave(&t->task_state_lock, flags);
2628 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2629 	t->task_state_flags |= SAS_TASK_STATE_DONE;
2630 	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2631 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2632 		pm8001_dbg(pm8001_ha, FAIL,
2633 			   "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2634 			   t, status, ts->resp, ts->stat);
2635 		pm8001_ccb_task_free(pm8001_ha, ccb);
2636 	} else {
2637 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2638 		pm8001_ccb_task_free_done(pm8001_ha, ccb);
2639 	}
2640 }
2641 
2642 /*See the comments for mpi_ssp_completion */
mpi_sata_event(struct pm8001_hba_info * pm8001_ha,void * piomb)2643 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2644 {
2645 	struct sas_task *t;
2646 	struct task_status_struct *ts;
2647 	struct pm8001_ccb_info *ccb;
2648 	struct pm8001_device *pm8001_dev;
2649 	struct sata_event_resp *psataPayload =
2650 		(struct sata_event_resp *)(piomb + 4);
2651 	u32 event = le32_to_cpu(psataPayload->event);
2652 	u32 tag = le32_to_cpu(psataPayload->tag);
2653 	u32 port_id = le32_to_cpu(psataPayload->port_id);
2654 	u32 dev_id = le32_to_cpu(psataPayload->device_id);
2655 
2656 	if (event)
2657 		pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2658 
2659 	/* Check if this is NCQ error */
2660 	if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2661 		/* find device using device id */
2662 		pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2663 		/* send read log extension */
2664 		if (pm8001_dev)
2665 			pm8001_send_read_log(pm8001_ha, pm8001_dev);
2666 		return;
2667 	}
2668 
2669 	ccb = &pm8001_ha->ccb_info[tag];
2670 	t = ccb->task;
2671 	pm8001_dev = ccb->device;
2672 	if (event)
2673 		pm8001_dbg(pm8001_ha, FAIL, "sata IO status 0x%x\n", event);
2674 	if (unlikely(!t || !t->lldd_task || !t->dev))
2675 		return;
2676 	ts = &t->task_status;
2677 	pm8001_dbg(pm8001_ha, DEVIO,
2678 		   "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2679 		   port_id, dev_id, tag, event);
2680 	switch (event) {
2681 	case IO_OVERFLOW:
2682 		pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2683 		ts->resp = SAS_TASK_COMPLETE;
2684 		ts->stat = SAS_DATA_OVERRUN;
2685 		ts->residual = 0;
2686 		break;
2687 	case IO_XFER_ERROR_BREAK:
2688 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2689 		ts->resp = SAS_TASK_COMPLETE;
2690 		ts->stat = SAS_INTERRUPTED;
2691 		break;
2692 	case IO_XFER_ERROR_PHY_NOT_READY:
2693 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2694 		ts->resp = SAS_TASK_COMPLETE;
2695 		ts->stat = SAS_OPEN_REJECT;
2696 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2697 		break;
2698 	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2699 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2700 		ts->resp = SAS_TASK_COMPLETE;
2701 		ts->stat = SAS_OPEN_REJECT;
2702 		ts->open_rej_reason = SAS_OREJ_EPROTO;
2703 		break;
2704 	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2705 		pm8001_dbg(pm8001_ha, IO,
2706 			   "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2707 		ts->resp = SAS_TASK_COMPLETE;
2708 		ts->stat = SAS_OPEN_REJECT;
2709 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2710 		break;
2711 	case IO_OPEN_CNX_ERROR_BREAK:
2712 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2713 		ts->resp = SAS_TASK_COMPLETE;
2714 		ts->stat = SAS_OPEN_REJECT;
2715 		ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2716 		break;
2717 	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2718 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2719 		ts->resp = SAS_TASK_UNDELIVERED;
2720 		ts->stat = SAS_DEV_NO_RESPONSE;
2721 		if (!t->uldd_task) {
2722 			pm8001_handle_event(pm8001_ha,
2723 				pm8001_dev,
2724 				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2725 			ts->resp = SAS_TASK_COMPLETE;
2726 			ts->stat = SAS_QUEUE_FULL;
2727 			return;
2728 		}
2729 		break;
2730 	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2731 		pm8001_dbg(pm8001_ha, IO,
2732 			   "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2733 		ts->resp = SAS_TASK_UNDELIVERED;
2734 		ts->stat = SAS_OPEN_REJECT;
2735 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2736 		break;
2737 	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2738 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2739 		ts->resp = SAS_TASK_COMPLETE;
2740 		ts->stat = SAS_OPEN_REJECT;
2741 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2742 		break;
2743 	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2744 		pm8001_dbg(pm8001_ha, IO,
2745 			   "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2746 		ts->resp = SAS_TASK_COMPLETE;
2747 		ts->stat = SAS_OPEN_REJECT;
2748 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2749 		break;
2750 	case IO_XFER_ERROR_NAK_RECEIVED:
2751 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2752 		ts->resp = SAS_TASK_COMPLETE;
2753 		ts->stat = SAS_NAK_R_ERR;
2754 		break;
2755 	case IO_XFER_ERROR_PEER_ABORTED:
2756 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2757 		ts->resp = SAS_TASK_COMPLETE;
2758 		ts->stat = SAS_NAK_R_ERR;
2759 		break;
2760 	case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2761 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2762 		ts->resp = SAS_TASK_COMPLETE;
2763 		ts->stat = SAS_DATA_UNDERRUN;
2764 		break;
2765 	case IO_XFER_OPEN_RETRY_TIMEOUT:
2766 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2767 		ts->resp = SAS_TASK_COMPLETE;
2768 		ts->stat = SAS_OPEN_TO;
2769 		break;
2770 	case IO_XFER_ERROR_UNEXPECTED_PHASE:
2771 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2772 		ts->resp = SAS_TASK_COMPLETE;
2773 		ts->stat = SAS_OPEN_TO;
2774 		break;
2775 	case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2776 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2777 		ts->resp = SAS_TASK_COMPLETE;
2778 		ts->stat = SAS_OPEN_TO;
2779 		break;
2780 	case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2781 		pm8001_dbg(pm8001_ha, IO,
2782 			   "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2783 		ts->resp = SAS_TASK_COMPLETE;
2784 		ts->stat = SAS_OPEN_TO;
2785 		break;
2786 	case IO_XFER_ERROR_OFFSET_MISMATCH:
2787 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2788 		ts->resp = SAS_TASK_COMPLETE;
2789 		ts->stat = SAS_OPEN_TO;
2790 		break;
2791 	case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2792 		pm8001_dbg(pm8001_ha, IO,
2793 			   "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2794 		ts->resp = SAS_TASK_COMPLETE;
2795 		ts->stat = SAS_OPEN_TO;
2796 		break;
2797 	case IO_XFER_CMD_FRAME_ISSUED:
2798 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2799 		break;
2800 	case IO_XFER_PIO_SETUP_ERROR:
2801 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2802 		ts->resp = SAS_TASK_COMPLETE;
2803 		ts->stat = SAS_OPEN_TO;
2804 		break;
2805 	default:
2806 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2807 		/* not allowed case. Therefore, return failed status */
2808 		ts->resp = SAS_TASK_COMPLETE;
2809 		ts->stat = SAS_OPEN_TO;
2810 		break;
2811 	}
2812 }
2813 
2814 /*See the comments for mpi_ssp_completion */
2815 static void
mpi_smp_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)2816 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2817 {
2818 	struct sas_task *t;
2819 	struct pm8001_ccb_info *ccb;
2820 	unsigned long flags;
2821 	u32 status;
2822 	u32 tag;
2823 	struct smp_completion_resp *psmpPayload;
2824 	struct task_status_struct *ts;
2825 	struct pm8001_device *pm8001_dev;
2826 
2827 	psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2828 	status = le32_to_cpu(psmpPayload->status);
2829 	tag = le32_to_cpu(psmpPayload->tag);
2830 
2831 	ccb = &pm8001_ha->ccb_info[tag];
2832 	t = ccb->task;
2833 	ts = &t->task_status;
2834 	pm8001_dev = ccb->device;
2835 	if (status) {
2836 		pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
2837 		pm8001_dbg(pm8001_ha, IOERR,
2838 			   "status:0x%x, tag:0x%x, task:0x%p\n",
2839 			   status, tag, t);
2840 	}
2841 	if (unlikely(!t || !t->lldd_task || !t->dev))
2842 		return;
2843 
2844 	switch (status) {
2845 	case IO_SUCCESS:
2846 		pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2847 		ts->resp = SAS_TASK_COMPLETE;
2848 		ts->stat = SAS_SAM_STAT_GOOD;
2849 		if (pm8001_dev)
2850 			atomic_dec(&pm8001_dev->running_req);
2851 		break;
2852 	case IO_ABORTED:
2853 		pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
2854 		ts->resp = SAS_TASK_COMPLETE;
2855 		ts->stat = SAS_ABORTED_TASK;
2856 		if (pm8001_dev)
2857 			atomic_dec(&pm8001_dev->running_req);
2858 		break;
2859 	case IO_OVERFLOW:
2860 		pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2861 		ts->resp = SAS_TASK_COMPLETE;
2862 		ts->stat = SAS_DATA_OVERRUN;
2863 		ts->residual = 0;
2864 		if (pm8001_dev)
2865 			atomic_dec(&pm8001_dev->running_req);
2866 		break;
2867 	case IO_NO_DEVICE:
2868 		pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2869 		ts->resp = SAS_TASK_COMPLETE;
2870 		ts->stat = SAS_PHY_DOWN;
2871 		break;
2872 	case IO_ERROR_HW_TIMEOUT:
2873 		pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
2874 		ts->resp = SAS_TASK_COMPLETE;
2875 		ts->stat = SAS_SAM_STAT_BUSY;
2876 		break;
2877 	case IO_XFER_ERROR_BREAK:
2878 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2879 		ts->resp = SAS_TASK_COMPLETE;
2880 		ts->stat = SAS_SAM_STAT_BUSY;
2881 		break;
2882 	case IO_XFER_ERROR_PHY_NOT_READY:
2883 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2884 		ts->resp = SAS_TASK_COMPLETE;
2885 		ts->stat = SAS_SAM_STAT_BUSY;
2886 		break;
2887 	case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2888 		pm8001_dbg(pm8001_ha, IO,
2889 			   "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2890 		ts->resp = SAS_TASK_COMPLETE;
2891 		ts->stat = SAS_OPEN_REJECT;
2892 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2893 		break;
2894 	case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2895 		pm8001_dbg(pm8001_ha, IO,
2896 			   "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2897 		ts->resp = SAS_TASK_COMPLETE;
2898 		ts->stat = SAS_OPEN_REJECT;
2899 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2900 		break;
2901 	case IO_OPEN_CNX_ERROR_BREAK:
2902 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2903 		ts->resp = SAS_TASK_COMPLETE;
2904 		ts->stat = SAS_OPEN_REJECT;
2905 		ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2906 		break;
2907 	case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2908 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2909 		ts->resp = SAS_TASK_COMPLETE;
2910 		ts->stat = SAS_OPEN_REJECT;
2911 		ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2912 		pm8001_handle_event(pm8001_ha,
2913 				pm8001_dev,
2914 				IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2915 		break;
2916 	case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2917 		pm8001_dbg(pm8001_ha, IO,
2918 			   "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2919 		ts->resp = SAS_TASK_COMPLETE;
2920 		ts->stat = SAS_OPEN_REJECT;
2921 		ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2922 		break;
2923 	case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2924 		pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2925 		ts->resp = SAS_TASK_COMPLETE;
2926 		ts->stat = SAS_OPEN_REJECT;
2927 		ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2928 		break;
2929 	case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2930 		pm8001_dbg(pm8001_ha, IO,
2931 			   "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2932 		ts->resp = SAS_TASK_COMPLETE;
2933 		ts->stat = SAS_OPEN_REJECT;
2934 		ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2935 		break;
2936 	case IO_XFER_ERROR_RX_FRAME:
2937 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
2938 		ts->resp = SAS_TASK_COMPLETE;
2939 		ts->stat = SAS_DEV_NO_RESPONSE;
2940 		break;
2941 	case IO_XFER_OPEN_RETRY_TIMEOUT:
2942 		pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2943 		ts->resp = SAS_TASK_COMPLETE;
2944 		ts->stat = SAS_OPEN_REJECT;
2945 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2946 		break;
2947 	case IO_ERROR_INTERNAL_SMP_RESOURCE:
2948 		pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
2949 		ts->resp = SAS_TASK_COMPLETE;
2950 		ts->stat = SAS_QUEUE_FULL;
2951 		break;
2952 	case IO_PORT_IN_RESET:
2953 		pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2954 		ts->resp = SAS_TASK_COMPLETE;
2955 		ts->stat = SAS_OPEN_REJECT;
2956 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2957 		break;
2958 	case IO_DS_NON_OPERATIONAL:
2959 		pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2960 		ts->resp = SAS_TASK_COMPLETE;
2961 		ts->stat = SAS_DEV_NO_RESPONSE;
2962 		break;
2963 	case IO_DS_IN_RECOVERY:
2964 		pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2965 		ts->resp = SAS_TASK_COMPLETE;
2966 		ts->stat = SAS_OPEN_REJECT;
2967 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2968 		break;
2969 	case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2970 		pm8001_dbg(pm8001_ha, IO,
2971 			   "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2972 		ts->resp = SAS_TASK_COMPLETE;
2973 		ts->stat = SAS_OPEN_REJECT;
2974 		ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2975 		break;
2976 	default:
2977 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2978 		ts->resp = SAS_TASK_COMPLETE;
2979 		ts->stat = SAS_DEV_NO_RESPONSE;
2980 		/* not allowed case. Therefore, return failed status */
2981 		break;
2982 	}
2983 	spin_lock_irqsave(&t->task_state_lock, flags);
2984 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2985 	t->task_state_flags |= SAS_TASK_STATE_DONE;
2986 	if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2987 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2988 		pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2989 			   t, status, ts->resp, ts->stat);
2990 		pm8001_ccb_task_free(pm8001_ha, ccb);
2991 	} else {
2992 		spin_unlock_irqrestore(&t->task_state_lock, flags);
2993 		pm8001_ccb_task_free_done(pm8001_ha, ccb);
2994 	}
2995 }
2996 
pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)2997 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
2998 		void *piomb)
2999 {
3000 	struct set_dev_state_resp *pPayload =
3001 		(struct set_dev_state_resp *)(piomb + 4);
3002 	u32 tag = le32_to_cpu(pPayload->tag);
3003 	struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3004 	struct pm8001_device *pm8001_dev = ccb->device;
3005 	u32 status = le32_to_cpu(pPayload->status);
3006 	u32 device_id = le32_to_cpu(pPayload->device_id);
3007 	u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
3008 	u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
3009 
3010 	pm8001_dbg(pm8001_ha, MSG,
3011 		   "Set device id = 0x%x state from 0x%x to 0x%x status = 0x%x!\n",
3012 		   device_id, pds, nds, status);
3013 	complete(pm8001_dev->setds_completion);
3014 	pm8001_ccb_free(pm8001_ha, ccb);
3015 }
3016 
pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3017 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3018 {
3019 	struct get_nvm_data_resp *pPayload =
3020 		(struct get_nvm_data_resp *)(piomb + 4);
3021 	u32 tag = le32_to_cpu(pPayload->tag);
3022 	struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3023 	u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3024 
3025 	complete(pm8001_ha->nvmd_completion);
3026 	pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n");
3027 	if ((dlen_status & NVMD_STAT) != 0) {
3028 		pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error %x\n",
3029 				dlen_status);
3030 	}
3031 	pm8001_ccb_free(pm8001_ha, ccb);
3032 }
3033 
3034 void
pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3035 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3036 {
3037 	struct fw_control_ex    *fw_control_context;
3038 	struct get_nvm_data_resp *pPayload =
3039 		(struct get_nvm_data_resp *)(piomb + 4);
3040 	u32 tag = le32_to_cpu(pPayload->tag);
3041 	struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3042 	u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3043 	u32 ir_tds_bn_dps_das_nvm =
3044 		le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
3045 	void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
3046 	fw_control_context = ccb->fw_control_context;
3047 
3048 	pm8001_dbg(pm8001_ha, MSG, "Get nvm data complete!\n");
3049 	if ((dlen_status & NVMD_STAT) != 0) {
3050 		pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error %x\n",
3051 				dlen_status);
3052 		complete(pm8001_ha->nvmd_completion);
3053 		/* We should free tag during failure also, the tag is not being
3054 		 * freed by requesting path anywhere.
3055 		 */
3056 		pm8001_ccb_free(pm8001_ha, ccb);
3057 		return;
3058 	}
3059 	if (ir_tds_bn_dps_das_nvm & IPMode) {
3060 		/* indirect mode - IR bit set */
3061 		pm8001_dbg(pm8001_ha, MSG, "Get NVMD success, IR=1\n");
3062 		if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
3063 			if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
3064 				memcpy(pm8001_ha->sas_addr,
3065 				      ((u8 *)virt_addr + 4),
3066 				       SAS_ADDR_SIZE);
3067 				pm8001_dbg(pm8001_ha, MSG, "Get SAS address from VPD successfully!\n");
3068 			}
3069 		} else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
3070 			|| ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
3071 			((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
3072 				;
3073 		} else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
3074 			|| ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
3075 			;
3076 		} else {
3077 			/* Should not be happened*/
3078 			pm8001_dbg(pm8001_ha, MSG,
3079 				   "(IR=1)Wrong Device type 0x%x\n",
3080 				   ir_tds_bn_dps_das_nvm);
3081 		}
3082 	} else /* direct mode */{
3083 		pm8001_dbg(pm8001_ha, MSG,
3084 			   "Get NVMD success, IR=0, dataLen=%d\n",
3085 			   (dlen_status & NVMD_LEN) >> 24);
3086 	}
3087 	/* Though fw_control_context is freed below, usrAddr still needs
3088 	 * to be updated as this holds the response to the request function
3089 	 */
3090 	memcpy(fw_control_context->usrAddr,
3091 		pm8001_ha->memoryMap.region[NVMD].virt_ptr,
3092 		fw_control_context->len);
3093 	kfree(ccb->fw_control_context);
3094 	/* To avoid race condition, complete should be
3095 	 * called after the message is copied to
3096 	 * fw_control_context->usrAddr
3097 	 */
3098 	complete(pm8001_ha->nvmd_completion);
3099 	pm8001_dbg(pm8001_ha, MSG, "Get nvmd data complete!\n");
3100 	pm8001_ccb_free(pm8001_ha, ccb);
3101 }
3102 
pm8001_mpi_local_phy_ctl(struct pm8001_hba_info * pm8001_ha,void * piomb)3103 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
3104 {
3105 	u32 tag;
3106 	struct local_phy_ctl_resp *pPayload =
3107 		(struct local_phy_ctl_resp *)(piomb + 4);
3108 	u32 status = le32_to_cpu(pPayload->status);
3109 	u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3110 	u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3111 	tag = le32_to_cpu(pPayload->tag);
3112 	if (status != 0) {
3113 		pm8001_dbg(pm8001_ha, MSG,
3114 			   "%x phy execute %x phy op failed!\n",
3115 			   phy_id, phy_op);
3116 	} else {
3117 		pm8001_dbg(pm8001_ha, MSG,
3118 			   "%x phy execute %x phy op success!\n",
3119 			   phy_id, phy_op);
3120 		pm8001_ha->phy[phy_id].reset_success = true;
3121 	}
3122 	if (pm8001_ha->phy[phy_id].enable_completion) {
3123 		complete(pm8001_ha->phy[phy_id].enable_completion);
3124 		pm8001_ha->phy[phy_id].enable_completion = NULL;
3125 	}
3126 	pm8001_tag_free(pm8001_ha, tag);
3127 	return 0;
3128 }
3129 
3130 /**
3131  * pm8001_bytes_dmaed - one of the interface function communication with libsas
3132  * @pm8001_ha: our hba card information
3133  * @i: which phy that received the event.
3134  *
3135  * when HBA driver received the identify done event or initiate FIS received
3136  * event(for SATA), it will invoke this function to notify the sas layer that
3137  * the sas toplogy has formed, please discover the the whole sas domain,
3138  * while receive a broadcast(change) primitive just tell the sas
3139  * layer to discover the changed domain rather than the whole domain.
3140  */
pm8001_bytes_dmaed(struct pm8001_hba_info * pm8001_ha,int i)3141 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3142 {
3143 	struct pm8001_phy *phy = &pm8001_ha->phy[i];
3144 	struct asd_sas_phy *sas_phy = &phy->sas_phy;
3145 	if (!phy->phy_attached)
3146 		return;
3147 
3148 	if (phy->phy_type & PORT_TYPE_SAS) {
3149 		struct sas_identify_frame *id;
3150 		id = (struct sas_identify_frame *)phy->frame_rcvd;
3151 		id->dev_type = phy->identify.device_type;
3152 		id->initiator_bits = SAS_PROTOCOL_ALL;
3153 		id->target_bits = phy->identify.target_port_protocols;
3154 	} else if (phy->phy_type & PORT_TYPE_SATA) {
3155 		/*Nothing*/
3156 	}
3157 	pm8001_dbg(pm8001_ha, MSG, "phy %d byte dmaded.\n", i);
3158 
3159 	sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3160 	sas_notify_port_event(sas_phy, PORTE_BYTES_DMAED, GFP_ATOMIC);
3161 }
3162 
3163 /* Get the link rate speed  */
pm8001_get_lrate_mode(struct pm8001_phy * phy,u8 link_rate)3164 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3165 {
3166 	struct sas_phy *sas_phy = phy->sas_phy.phy;
3167 
3168 	switch (link_rate) {
3169 	case PHY_SPEED_120:
3170 		phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS;
3171 		break;
3172 	case PHY_SPEED_60:
3173 		phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3174 		break;
3175 	case PHY_SPEED_30:
3176 		phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3177 		break;
3178 	case PHY_SPEED_15:
3179 		phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3180 		break;
3181 	}
3182 	sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3183 	sas_phy->maximum_linkrate_hw = phy->maximum_linkrate;
3184 	sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3185 	sas_phy->maximum_linkrate = phy->maximum_linkrate;
3186 	sas_phy->minimum_linkrate = phy->minimum_linkrate;
3187 }
3188 
3189 /**
3190  * pm8001_get_attached_sas_addr - extract/generate attached SAS address
3191  * @phy: pointer to asd_phy
3192  * @sas_addr: pointer to buffer where the SAS address is to be written
3193  *
3194  * This function extracts the SAS address from an IDENTIFY frame
3195  * received.  If OOB is SATA, then a SAS address is generated from the
3196  * HA tables.
3197  *
3198  * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3199  * buffer.
3200  */
pm8001_get_attached_sas_addr(struct pm8001_phy * phy,u8 * sas_addr)3201 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3202 	u8 *sas_addr)
3203 {
3204 	if (phy->sas_phy.frame_rcvd[0] == 0x34
3205 		&& phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3206 		struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3207 		/* FIS device-to-host */
3208 		u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3209 		addr += phy->sas_phy.id;
3210 		*(__be64 *)sas_addr = cpu_to_be64(addr);
3211 	} else {
3212 		struct sas_identify_frame *idframe =
3213 			(void *) phy->sas_phy.frame_rcvd;
3214 		memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3215 	}
3216 }
3217 
3218 /**
3219  * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3220  * @pm8001_ha: our hba card information
3221  * @Qnum: the outbound queue message number.
3222  * @SEA: source of event to ack
3223  * @port_id: port id.
3224  * @phyId: phy id.
3225  * @param0: parameter 0.
3226  * @param1: parameter 1.
3227  */
pm8001_hw_event_ack_req(struct pm8001_hba_info * pm8001_ha,u32 Qnum,u32 SEA,u32 port_id,u32 phyId,u32 param0,u32 param1)3228 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3229 	u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3230 {
3231 	struct hw_event_ack_req	 payload;
3232 	u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3233 
3234 	memset((u8 *)&payload, 0, sizeof(payload));
3235 	payload.tag = cpu_to_le32(1);
3236 	payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3237 		((phyId & 0x0F) << 4) | (port_id & 0x0F));
3238 	payload.param0 = cpu_to_le32(param0);
3239 	payload.param1 = cpu_to_le32(param1);
3240 
3241 	pm8001_mpi_build_cmd(pm8001_ha, Qnum, opc, &payload, sizeof(payload), 0);
3242 }
3243 
3244 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3245 	u32 phyId, u32 phy_op);
3246 
3247 /**
3248  * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3249  * @pm8001_ha: our hba card information
3250  * @piomb: IO message buffer
3251  */
3252 static void
hw_event_sas_phy_up(struct pm8001_hba_info * pm8001_ha,void * piomb)3253 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3254 {
3255 	struct hw_event_resp *pPayload =
3256 		(struct hw_event_resp *)(piomb + 4);
3257 	u32 lr_evt_status_phyid_portid =
3258 		le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3259 	u8 link_rate =
3260 		(u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3261 	u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3262 	u8 phy_id =
3263 		(u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3264 	u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3265 	u8 portstate = (u8)(npip_portstate & 0x0000000F);
3266 	struct pm8001_port *port = &pm8001_ha->port[port_id];
3267 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3268 	unsigned long flags;
3269 	u8 deviceType = pPayload->sas_identify.dev_type;
3270 	phy->port = port;
3271 	port->port_id = port_id;
3272 	port->port_state =  portstate;
3273 	phy->phy_state = PHY_STATE_LINK_UP_SPC;
3274 	pm8001_dbg(pm8001_ha, MSG,
3275 		   "HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3276 		   port_id, phy_id);
3277 
3278 	switch (deviceType) {
3279 	case SAS_PHY_UNUSED:
3280 		pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3281 		break;
3282 	case SAS_END_DEVICE:
3283 		pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3284 		pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3285 			PHY_NOTIFY_ENABLE_SPINUP);
3286 		port->port_attached = 1;
3287 		pm8001_get_lrate_mode(phy, link_rate);
3288 		break;
3289 	case SAS_EDGE_EXPANDER_DEVICE:
3290 		pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3291 		port->port_attached = 1;
3292 		pm8001_get_lrate_mode(phy, link_rate);
3293 		break;
3294 	case SAS_FANOUT_EXPANDER_DEVICE:
3295 		pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3296 		port->port_attached = 1;
3297 		pm8001_get_lrate_mode(phy, link_rate);
3298 		break;
3299 	default:
3300 		pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3301 			   deviceType);
3302 		break;
3303 	}
3304 	phy->phy_type |= PORT_TYPE_SAS;
3305 	phy->identify.device_type = deviceType;
3306 	phy->phy_attached = 1;
3307 	if (phy->identify.device_type == SAS_END_DEVICE)
3308 		phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3309 	else if (phy->identify.device_type != SAS_PHY_UNUSED)
3310 		phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3311 	phy->sas_phy.oob_mode = SAS_OOB_MODE;
3312 	sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3313 	spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3314 	memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3315 		sizeof(struct sas_identify_frame)-4);
3316 	phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3317 	pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3318 	spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3319 	if (pm8001_ha->flags == PM8001F_RUN_TIME)
3320 		mdelay(200);/*delay a moment to wait disk to spinup*/
3321 	pm8001_bytes_dmaed(pm8001_ha, phy_id);
3322 }
3323 
3324 /**
3325  * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3326  * @pm8001_ha: our hba card information
3327  * @piomb: IO message buffer
3328  */
3329 static void
hw_event_sata_phy_up(struct pm8001_hba_info * pm8001_ha,void * piomb)3330 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3331 {
3332 	struct hw_event_resp *pPayload =
3333 		(struct hw_event_resp *)(piomb + 4);
3334 	u32 lr_evt_status_phyid_portid =
3335 		le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3336 	u8 link_rate =
3337 		(u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3338 	u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3339 	u8 phy_id =
3340 		(u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3341 	u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3342 	u8 portstate = (u8)(npip_portstate & 0x0000000F);
3343 	struct pm8001_port *port = &pm8001_ha->port[port_id];
3344 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3345 	unsigned long flags;
3346 	pm8001_dbg(pm8001_ha, DEVIO, "HW_EVENT_SATA_PHY_UP port id = %d, phy id = %d\n",
3347 		   port_id, phy_id);
3348 	phy->port = port;
3349 	port->port_id = port_id;
3350 	port->port_state =  portstate;
3351 	phy->phy_state = PHY_STATE_LINK_UP_SPC;
3352 	port->port_attached = 1;
3353 	pm8001_get_lrate_mode(phy, link_rate);
3354 	phy->phy_type |= PORT_TYPE_SATA;
3355 	phy->phy_attached = 1;
3356 	phy->sas_phy.oob_mode = SATA_OOB_MODE;
3357 	sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3358 	spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3359 	memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3360 		sizeof(struct dev_to_host_fis));
3361 	phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3362 	phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3363 	phy->identify.device_type = SAS_SATA_DEV;
3364 	pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3365 	spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3366 	pm8001_bytes_dmaed(pm8001_ha, phy_id);
3367 }
3368 
3369 /**
3370  * hw_event_phy_down -we should notify the libsas the phy is down.
3371  * @pm8001_ha: our hba card information
3372  * @piomb: IO message buffer
3373  */
3374 static void
hw_event_phy_down(struct pm8001_hba_info * pm8001_ha,void * piomb)3375 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3376 {
3377 	struct hw_event_resp *pPayload =
3378 		(struct hw_event_resp *)(piomb + 4);
3379 	u32 lr_evt_status_phyid_portid =
3380 		le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3381 	u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3382 	u8 phy_id =
3383 		(u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3384 	u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3385 	u8 portstate = (u8)(npip_portstate & 0x0000000F);
3386 	struct pm8001_port *port = &pm8001_ha->port[port_id];
3387 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3388 	port->port_state =  portstate;
3389 	phy->phy_type = 0;
3390 	phy->identify.device_type = 0;
3391 	phy->phy_attached = 0;
3392 	memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3393 	switch (portstate) {
3394 	case PORT_VALID:
3395 		break;
3396 	case PORT_INVALID:
3397 		pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3398 			   port_id);
3399 		pm8001_dbg(pm8001_ha, MSG,
3400 			   " Last phy Down and port invalid\n");
3401 		port->port_attached = 0;
3402 		pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3403 			port_id, phy_id, 0, 0);
3404 		break;
3405 	case PORT_IN_RESET:
3406 		pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3407 			   port_id);
3408 		break;
3409 	case PORT_NOT_ESTABLISHED:
3410 		pm8001_dbg(pm8001_ha, MSG,
3411 			   " phy Down and PORT_NOT_ESTABLISHED\n");
3412 		port->port_attached = 0;
3413 		break;
3414 	case PORT_LOSTCOMM:
3415 		pm8001_dbg(pm8001_ha, MSG, " phy Down and PORT_LOSTCOMM\n");
3416 		pm8001_dbg(pm8001_ha, MSG,
3417 			   " Last phy Down and port invalid\n");
3418 		port->port_attached = 0;
3419 		pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3420 			port_id, phy_id, 0, 0);
3421 		break;
3422 	default:
3423 		port->port_attached = 0;
3424 		pm8001_dbg(pm8001_ha, DEVIO, " phy Down and(default) = %x\n",
3425 			   portstate);
3426 		break;
3427 
3428 	}
3429 }
3430 
3431 /**
3432  * pm8001_mpi_reg_resp -process register device ID response.
3433  * @pm8001_ha: our hba card information
3434  * @piomb: IO message buffer
3435  *
3436  * when sas layer find a device it will notify LLDD, then the driver register
3437  * the domain device to FW, this event is the return device ID which the FW
3438  * has assigned, from now, inter-communication with FW is no longer using the
3439  * SAS address, use device ID which FW assigned.
3440  */
pm8001_mpi_reg_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3441 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3442 {
3443 	u32 status;
3444 	u32 device_id;
3445 	u32 htag;
3446 	struct pm8001_ccb_info *ccb;
3447 	struct pm8001_device *pm8001_dev;
3448 	struct dev_reg_resp *registerRespPayload =
3449 		(struct dev_reg_resp *)(piomb + 4);
3450 
3451 	htag = le32_to_cpu(registerRespPayload->tag);
3452 	ccb = &pm8001_ha->ccb_info[htag];
3453 	pm8001_dev = ccb->device;
3454 	status = le32_to_cpu(registerRespPayload->status);
3455 	device_id = le32_to_cpu(registerRespPayload->device_id);
3456 	pm8001_dbg(pm8001_ha, MSG, " register device is status = %d\n",
3457 		   status);
3458 	switch (status) {
3459 	case DEVREG_SUCCESS:
3460 		pm8001_dbg(pm8001_ha, MSG, "DEVREG_SUCCESS\n");
3461 		pm8001_dev->device_id = device_id;
3462 		break;
3463 	case DEVREG_FAILURE_OUT_OF_RESOURCE:
3464 		pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_OUT_OF_RESOURCE\n");
3465 		break;
3466 	case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3467 		pm8001_dbg(pm8001_ha, MSG,
3468 			   "DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n");
3469 		break;
3470 	case DEVREG_FAILURE_INVALID_PHY_ID:
3471 		pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_INVALID_PHY_ID\n");
3472 		break;
3473 	case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3474 		pm8001_dbg(pm8001_ha, MSG,
3475 			   "DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n");
3476 		break;
3477 	case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3478 		pm8001_dbg(pm8001_ha, MSG,
3479 			   "DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n");
3480 		break;
3481 	case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3482 		pm8001_dbg(pm8001_ha, MSG,
3483 			   "DEVREG_FAILURE_PORT_NOT_VALID_STATE\n");
3484 		break;
3485 	case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3486 		pm8001_dbg(pm8001_ha, MSG,
3487 			   "DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n");
3488 		break;
3489 	default:
3490 		pm8001_dbg(pm8001_ha, MSG,
3491 			   "DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n");
3492 		break;
3493 	}
3494 	complete(pm8001_dev->dcompletion);
3495 	pm8001_ccb_free(pm8001_ha, ccb);
3496 	return 0;
3497 }
3498 
pm8001_mpi_dereg_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3499 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3500 {
3501 	u32 status;
3502 	u32 device_id;
3503 	struct dev_reg_resp *registerRespPayload =
3504 		(struct dev_reg_resp *)(piomb + 4);
3505 
3506 	status = le32_to_cpu(registerRespPayload->status);
3507 	device_id = le32_to_cpu(registerRespPayload->device_id);
3508 	if (status != 0)
3509 		pm8001_dbg(pm8001_ha, MSG,
3510 			   " deregister device failed ,status = %x, device_id = %x\n",
3511 			   status, device_id);
3512 	return 0;
3513 }
3514 
3515 /**
3516  * pm8001_mpi_fw_flash_update_resp - Response from FW for flash update command.
3517  * @pm8001_ha: our hba card information
3518  * @piomb: IO message buffer
3519  */
pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3520 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3521 		void *piomb)
3522 {
3523 	u32 status;
3524 	struct fw_flash_Update_resp *ppayload =
3525 		(struct fw_flash_Update_resp *)(piomb + 4);
3526 	u32 tag = le32_to_cpu(ppayload->tag);
3527 	struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3528 
3529 	status = le32_to_cpu(ppayload->status);
3530 	switch (status) {
3531 	case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3532 		pm8001_dbg(pm8001_ha, MSG,
3533 			   ": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n");
3534 		break;
3535 	case FLASH_UPDATE_IN_PROGRESS:
3536 		pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_IN_PROGRESS\n");
3537 		break;
3538 	case FLASH_UPDATE_HDR_ERR:
3539 		pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HDR_ERR\n");
3540 		break;
3541 	case FLASH_UPDATE_OFFSET_ERR:
3542 		pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_OFFSET_ERR\n");
3543 		break;
3544 	case FLASH_UPDATE_CRC_ERR:
3545 		pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_CRC_ERR\n");
3546 		break;
3547 	case FLASH_UPDATE_LENGTH_ERR:
3548 		pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_LENGTH_ERR\n");
3549 		break;
3550 	case FLASH_UPDATE_HW_ERR:
3551 		pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HW_ERR\n");
3552 		break;
3553 	case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3554 		pm8001_dbg(pm8001_ha, MSG,
3555 			   ": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n");
3556 		break;
3557 	case FLASH_UPDATE_DISABLED:
3558 		pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_DISABLED\n");
3559 		break;
3560 	default:
3561 		pm8001_dbg(pm8001_ha, DEVIO, "No matched status = %d\n",
3562 			   status);
3563 		break;
3564 	}
3565 	kfree(ccb->fw_control_context);
3566 	pm8001_ccb_free(pm8001_ha, ccb);
3567 	complete(pm8001_ha->nvmd_completion);
3568 	return 0;
3569 }
3570 
pm8001_mpi_general_event(struct pm8001_hba_info * pm8001_ha,void * piomb)3571 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3572 {
3573 	u32 status;
3574 	int i;
3575 	struct general_event_resp *pPayload =
3576 		(struct general_event_resp *)(piomb + 4);
3577 	status = le32_to_cpu(pPayload->status);
3578 	pm8001_dbg(pm8001_ha, MSG, " status = 0x%x\n", status);
3579 	for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3580 		pm8001_dbg(pm8001_ha, MSG, "inb_IOMB_payload[0x%x] 0x%x,\n",
3581 			   i,
3582 			   pPayload->inb_IOMB_payload[i]);
3583 	return 0;
3584 }
3585 
pm8001_mpi_task_abort_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3586 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3587 {
3588 	struct sas_task *t;
3589 	struct pm8001_ccb_info *ccb;
3590 	unsigned long flags;
3591 	u32 status ;
3592 	u32 tag, scp;
3593 	struct task_status_struct *ts;
3594 	struct pm8001_device *pm8001_dev;
3595 
3596 	struct task_abort_resp *pPayload =
3597 		(struct task_abort_resp *)(piomb + 4);
3598 
3599 	status = le32_to_cpu(pPayload->status);
3600 	tag = le32_to_cpu(pPayload->tag);
3601 
3602 	scp = le32_to_cpu(pPayload->scp);
3603 	ccb = &pm8001_ha->ccb_info[tag];
3604 	t = ccb->task;
3605 	pm8001_dev = ccb->device; /* retrieve device */
3606 
3607 	if (!t)	{
3608 		pm8001_dbg(pm8001_ha, FAIL, " TASK NULL. RETURNING !!!\n");
3609 		return -1;
3610 	}
3611 	ts = &t->task_status;
3612 	if (status != 0)
3613 		pm8001_dbg(pm8001_ha, FAIL, "task abort failed status 0x%x ,tag = 0x%x, scp= 0x%x\n",
3614 			   status, tag, scp);
3615 	switch (status) {
3616 	case IO_SUCCESS:
3617 		pm8001_dbg(pm8001_ha, EH, "IO_SUCCESS\n");
3618 		ts->resp = SAS_TASK_COMPLETE;
3619 		ts->stat = SAS_SAM_STAT_GOOD;
3620 		break;
3621 	case IO_NOT_VALID:
3622 		pm8001_dbg(pm8001_ha, EH, "IO_NOT_VALID\n");
3623 		ts->resp = TMF_RESP_FUNC_FAILED;
3624 		break;
3625 	}
3626 	spin_lock_irqsave(&t->task_state_lock, flags);
3627 	t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3628 	t->task_state_flags |= SAS_TASK_STATE_DONE;
3629 	spin_unlock_irqrestore(&t->task_state_lock, flags);
3630 	pm8001_ccb_task_free(pm8001_ha, ccb);
3631 	mb();
3632 
3633 	if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
3634 		sas_free_task(t);
3635 		pm8001_dev->id &= ~NCQ_ABORT_ALL_FLAG;
3636 	} else {
3637 		t->task_done(t);
3638 	}
3639 
3640 	return 0;
3641 }
3642 
3643 /**
3644  * mpi_hw_event -The hw event has come.
3645  * @pm8001_ha: our hba card information
3646  * @piomb: IO message buffer
3647  */
mpi_hw_event(struct pm8001_hba_info * pm8001_ha,void * piomb)3648 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3649 {
3650 	unsigned long flags;
3651 	struct hw_event_resp *pPayload =
3652 		(struct hw_event_resp *)(piomb + 4);
3653 	u32 lr_evt_status_phyid_portid =
3654 		le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3655 	u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3656 	u8 phy_id =
3657 		(u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3658 	u16 eventType =
3659 		(u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3660 	u8 status =
3661 		(u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3662 	struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3663 	struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3664 	struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3665 	pm8001_dbg(pm8001_ha, DEVIO,
3666 		   "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n",
3667 		   port_id, phy_id, eventType, status);
3668 	switch (eventType) {
3669 	case HW_EVENT_PHY_START_STATUS:
3670 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS status = %x\n",
3671 			   status);
3672 		if (status == 0)
3673 			phy->phy_state = 1;
3674 
3675 		if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3676 				phy->enable_completion != NULL) {
3677 			complete(phy->enable_completion);
3678 			phy->enable_completion = NULL;
3679 		}
3680 		break;
3681 	case HW_EVENT_SAS_PHY_UP:
3682 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3683 		hw_event_sas_phy_up(pm8001_ha, piomb);
3684 		break;
3685 	case HW_EVENT_SATA_PHY_UP:
3686 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3687 		hw_event_sata_phy_up(pm8001_ha, piomb);
3688 		break;
3689 	case HW_EVENT_PHY_STOP_STATUS:
3690 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_STOP_STATUS status = %x\n",
3691 			   status);
3692 		if (status == 0)
3693 			phy->phy_state = 0;
3694 		break;
3695 	case HW_EVENT_SATA_SPINUP_HOLD:
3696 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3697 		sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD,
3698 			GFP_ATOMIC);
3699 		break;
3700 	case HW_EVENT_PHY_DOWN:
3701 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3702 		sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL,
3703 			GFP_ATOMIC);
3704 		phy->phy_attached = 0;
3705 		phy->phy_state = 0;
3706 		hw_event_phy_down(pm8001_ha, piomb);
3707 		break;
3708 	case HW_EVENT_PORT_INVALID:
3709 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
3710 		sas_phy_disconnected(sas_phy);
3711 		phy->phy_attached = 0;
3712 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3713 			GFP_ATOMIC);
3714 		break;
3715 	/* the broadcast change primitive received, tell the LIBSAS this event
3716 	to revalidate the sas domain*/
3717 	case HW_EVENT_BROADCAST_CHANGE:
3718 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3719 		pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3720 			port_id, phy_id, 1, 0);
3721 		spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3722 		sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3723 		spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3724 		sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3725 			GFP_ATOMIC);
3726 		break;
3727 	case HW_EVENT_PHY_ERROR:
3728 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
3729 		sas_phy_disconnected(&phy->sas_phy);
3730 		phy->phy_attached = 0;
3731 		sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC);
3732 		break;
3733 	case HW_EVENT_BROADCAST_EXP:
3734 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3735 		spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3736 		sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3737 		spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3738 		sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3739 			GFP_ATOMIC);
3740 		break;
3741 	case HW_EVENT_LINK_ERR_INVALID_DWORD:
3742 		pm8001_dbg(pm8001_ha, MSG,
3743 			   "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
3744 		pm8001_hw_event_ack_req(pm8001_ha, 0,
3745 			HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3746 		sas_phy_disconnected(sas_phy);
3747 		phy->phy_attached = 0;
3748 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3749 			GFP_ATOMIC);
3750 		break;
3751 	case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3752 		pm8001_dbg(pm8001_ha, MSG,
3753 			   "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
3754 		pm8001_hw_event_ack_req(pm8001_ha, 0,
3755 			HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3756 			port_id, phy_id, 0, 0);
3757 		sas_phy_disconnected(sas_phy);
3758 		phy->phy_attached = 0;
3759 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3760 			GFP_ATOMIC);
3761 		break;
3762 	case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3763 		pm8001_dbg(pm8001_ha, MSG,
3764 			   "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
3765 		pm8001_hw_event_ack_req(pm8001_ha, 0,
3766 			HW_EVENT_LINK_ERR_CODE_VIOLATION,
3767 			port_id, phy_id, 0, 0);
3768 		sas_phy_disconnected(sas_phy);
3769 		phy->phy_attached = 0;
3770 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3771 			GFP_ATOMIC);
3772 		break;
3773 	case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3774 		pm8001_dbg(pm8001_ha, MSG,
3775 			   "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
3776 		pm8001_hw_event_ack_req(pm8001_ha, 0,
3777 			HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3778 			port_id, phy_id, 0, 0);
3779 		sas_phy_disconnected(sas_phy);
3780 		phy->phy_attached = 0;
3781 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3782 			GFP_ATOMIC);
3783 		break;
3784 	case HW_EVENT_MALFUNCTION:
3785 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
3786 		break;
3787 	case HW_EVENT_BROADCAST_SES:
3788 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3789 		spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3790 		sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3791 		spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3792 		sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3793 			GFP_ATOMIC);
3794 		break;
3795 	case HW_EVENT_INBOUND_CRC_ERROR:
3796 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
3797 		pm8001_hw_event_ack_req(pm8001_ha, 0,
3798 			HW_EVENT_INBOUND_CRC_ERROR,
3799 			port_id, phy_id, 0, 0);
3800 		break;
3801 	case HW_EVENT_HARD_RESET_RECEIVED:
3802 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
3803 		sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC);
3804 		break;
3805 	case HW_EVENT_ID_FRAME_TIMEOUT:
3806 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
3807 		sas_phy_disconnected(sas_phy);
3808 		phy->phy_attached = 0;
3809 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3810 			GFP_ATOMIC);
3811 		break;
3812 	case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3813 		pm8001_dbg(pm8001_ha, MSG,
3814 			   "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
3815 		pm8001_hw_event_ack_req(pm8001_ha, 0,
3816 			HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3817 			port_id, phy_id, 0, 0);
3818 		sas_phy_disconnected(sas_phy);
3819 		phy->phy_attached = 0;
3820 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3821 			GFP_ATOMIC);
3822 		break;
3823 	case HW_EVENT_PORT_RESET_TIMER_TMO:
3824 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
3825 		sas_phy_disconnected(sas_phy);
3826 		phy->phy_attached = 0;
3827 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3828 			GFP_ATOMIC);
3829 		break;
3830 	case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3831 		pm8001_dbg(pm8001_ha, MSG,
3832 			   "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
3833 		sas_phy_disconnected(sas_phy);
3834 		phy->phy_attached = 0;
3835 		sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3836 			GFP_ATOMIC);
3837 		break;
3838 	case HW_EVENT_PORT_RECOVER:
3839 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
3840 		break;
3841 	case HW_EVENT_PORT_RESET_COMPLETE:
3842 		pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
3843 		break;
3844 	case EVENT_BROADCAST_ASYNCH_EVENT:
3845 		pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3846 		break;
3847 	default:
3848 		pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type = %x\n",
3849 			   eventType);
3850 		break;
3851 	}
3852 	return 0;
3853 }
3854 
3855 /**
3856  * process_one_iomb - process one outbound Queue memory block
3857  * @pm8001_ha: our hba card information
3858  * @piomb: IO message buffer
3859  */
process_one_iomb(struct pm8001_hba_info * pm8001_ha,void * piomb)3860 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3861 {
3862 	__le32 pHeader = *(__le32 *)piomb;
3863 	u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3864 
3865 	pm8001_dbg(pm8001_ha, MSG, "process_one_iomb:\n");
3866 
3867 	switch (opc) {
3868 	case OPC_OUB_ECHO:
3869 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3870 		break;
3871 	case OPC_OUB_HW_EVENT:
3872 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3873 		mpi_hw_event(pm8001_ha, piomb);
3874 		break;
3875 	case OPC_OUB_SSP_COMP:
3876 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3877 		mpi_ssp_completion(pm8001_ha, piomb);
3878 		break;
3879 	case OPC_OUB_SMP_COMP:
3880 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3881 		mpi_smp_completion(pm8001_ha, piomb);
3882 		break;
3883 	case OPC_OUB_LOCAL_PHY_CNTRL:
3884 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3885 		pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3886 		break;
3887 	case OPC_OUB_DEV_REGIST:
3888 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3889 		pm8001_mpi_reg_resp(pm8001_ha, piomb);
3890 		break;
3891 	case OPC_OUB_DEREG_DEV:
3892 		pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3893 		pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3894 		break;
3895 	case OPC_OUB_GET_DEV_HANDLE:
3896 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3897 		break;
3898 	case OPC_OUB_SATA_COMP:
3899 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3900 		mpi_sata_completion(pm8001_ha, piomb);
3901 		break;
3902 	case OPC_OUB_SATA_EVENT:
3903 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3904 		mpi_sata_event(pm8001_ha, piomb);
3905 		break;
3906 	case OPC_OUB_SSP_EVENT:
3907 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3908 		mpi_ssp_event(pm8001_ha, piomb);
3909 		break;
3910 	case OPC_OUB_DEV_HANDLE_ARRIV:
3911 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3912 		/*This is for target*/
3913 		break;
3914 	case OPC_OUB_SSP_RECV_EVENT:
3915 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3916 		/*This is for target*/
3917 		break;
3918 	case OPC_OUB_DEV_INFO:
3919 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_INFO\n");
3920 		break;
3921 	case OPC_OUB_FW_FLASH_UPDATE:
3922 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3923 		pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3924 		break;
3925 	case OPC_OUB_GPIO_RESPONSE:
3926 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
3927 		break;
3928 	case OPC_OUB_GPIO_EVENT:
3929 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
3930 		break;
3931 	case OPC_OUB_GENERAL_EVENT:
3932 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
3933 		pm8001_mpi_general_event(pm8001_ha, piomb);
3934 		break;
3935 	case OPC_OUB_SSP_ABORT_RSP:
3936 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
3937 		pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3938 		break;
3939 	case OPC_OUB_SATA_ABORT_RSP:
3940 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
3941 		pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3942 		break;
3943 	case OPC_OUB_SAS_DIAG_MODE_START_END:
3944 		pm8001_dbg(pm8001_ha, MSG,
3945 			   "OPC_OUB_SAS_DIAG_MODE_START_END\n");
3946 		break;
3947 	case OPC_OUB_SAS_DIAG_EXECUTE:
3948 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
3949 		break;
3950 	case OPC_OUB_GET_TIME_STAMP:
3951 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
3952 		break;
3953 	case OPC_OUB_SAS_HW_EVENT_ACK:
3954 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
3955 		break;
3956 	case OPC_OUB_PORT_CONTROL:
3957 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
3958 		break;
3959 	case OPC_OUB_SMP_ABORT_RSP:
3960 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
3961 		pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3962 		break;
3963 	case OPC_OUB_GET_NVMD_DATA:
3964 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
3965 		pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3966 		break;
3967 	case OPC_OUB_SET_NVMD_DATA:
3968 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
3969 		pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3970 		break;
3971 	case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3972 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
3973 		break;
3974 	case OPC_OUB_SET_DEVICE_STATE:
3975 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
3976 		pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3977 		break;
3978 	case OPC_OUB_GET_DEVICE_STATE:
3979 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
3980 		break;
3981 	case OPC_OUB_SET_DEV_INFO:
3982 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
3983 		break;
3984 	case OPC_OUB_SAS_RE_INITIALIZE:
3985 		pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_RE_INITIALIZE\n");
3986 		break;
3987 	default:
3988 		pm8001_dbg(pm8001_ha, DEVIO,
3989 			   "Unknown outbound Queue IOMB OPC = %x\n",
3990 			   opc);
3991 		break;
3992 	}
3993 }
3994 
process_oq(struct pm8001_hba_info * pm8001_ha,u8 vec)3995 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3996 {
3997 	struct outbound_queue_table *circularQ;
3998 	void *pMsg1 = NULL;
3999 	u8 bc;
4000 	u32 ret = MPI_IO_STATUS_FAIL;
4001 	unsigned long flags;
4002 
4003 	spin_lock_irqsave(&pm8001_ha->lock, flags);
4004 	circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4005 	do {
4006 		ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4007 		if (MPI_IO_STATUS_SUCCESS == ret) {
4008 			/* process the outbound message */
4009 			process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4010 			/* free the message from the outbound circular buffer */
4011 			pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4012 							circularQ, bc);
4013 		}
4014 		if (MPI_IO_STATUS_BUSY == ret) {
4015 			/* Update the producer index from SPC */
4016 			circularQ->producer_index =
4017 				cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4018 			if (le32_to_cpu(circularQ->producer_index) ==
4019 				circularQ->consumer_idx)
4020 				/* OQ is empty */
4021 				break;
4022 		}
4023 	} while (1);
4024 	spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4025 	return ret;
4026 }
4027 
4028 /* DMA_... to our direction translation. */
4029 static const u8 data_dir_flags[] = {
4030 	[DMA_BIDIRECTIONAL]	= DATA_DIR_BYRECIPIENT,	/* UNSPECIFIED */
4031 	[DMA_TO_DEVICE]		= DATA_DIR_OUT,		/* OUTBOUND */
4032 	[DMA_FROM_DEVICE]	= DATA_DIR_IN,		/* INBOUND */
4033 	[DMA_NONE]		= DATA_DIR_NONE,	/* NO TRANSFER */
4034 };
4035 void
pm8001_chip_make_sg(struct scatterlist * scatter,int nr,void * prd)4036 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
4037 {
4038 	int i;
4039 	struct scatterlist *sg;
4040 	struct pm8001_prd *buf_prd = prd;
4041 
4042 	for_each_sg(scatter, sg, nr, i) {
4043 		buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
4044 		buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
4045 		buf_prd->im_len.e = 0;
4046 		buf_prd++;
4047 	}
4048 }
4049 
build_smp_cmd(u32 deviceID,__le32 hTag,struct smp_req * psmp_cmd)4050 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
4051 {
4052 	psmp_cmd->tag = hTag;
4053 	psmp_cmd->device_id = cpu_to_le32(deviceID);
4054 	psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4055 }
4056 
4057 /**
4058  * pm8001_chip_smp_req - send a SMP task to FW
4059  * @pm8001_ha: our hba card information.
4060  * @ccb: the ccb information this request used.
4061  */
pm8001_chip_smp_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4062 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4063 	struct pm8001_ccb_info *ccb)
4064 {
4065 	int elem, rc;
4066 	struct sas_task *task = ccb->task;
4067 	struct domain_device *dev = task->dev;
4068 	struct pm8001_device *pm8001_dev = dev->lldd_dev;
4069 	struct scatterlist *sg_req, *sg_resp;
4070 	u32 req_len, resp_len;
4071 	struct smp_req smp_cmd;
4072 	u32 opc;
4073 
4074 	memset(&smp_cmd, 0, sizeof(smp_cmd));
4075 	/*
4076 	 * DMA-map SMP request, response buffers
4077 	 */
4078 	sg_req = &task->smp_task.smp_req;
4079 	elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4080 	if (!elem)
4081 		return -ENOMEM;
4082 	req_len = sg_dma_len(sg_req);
4083 
4084 	sg_resp = &task->smp_task.smp_resp;
4085 	elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4086 	if (!elem) {
4087 		rc = -ENOMEM;
4088 		goto err_out;
4089 	}
4090 	resp_len = sg_dma_len(sg_resp);
4091 	/* must be in dwords */
4092 	if ((req_len & 0x3) || (resp_len & 0x3)) {
4093 		rc = -EINVAL;
4094 		goto err_out_2;
4095 	}
4096 
4097 	opc = OPC_INB_SMP_REQUEST;
4098 	smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4099 	smp_cmd.long_smp_req.long_req_addr =
4100 		cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4101 	smp_cmd.long_smp_req.long_req_size =
4102 		cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4103 	smp_cmd.long_smp_req.long_resp_addr =
4104 		cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4105 	smp_cmd.long_smp_req.long_resp_size =
4106 		cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4107 	build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4108 	rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc,
4109 				  &smp_cmd, sizeof(smp_cmd), 0);
4110 	if (rc)
4111 		goto err_out_2;
4112 
4113 	return 0;
4114 
4115 err_out_2:
4116 	dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4117 			DMA_FROM_DEVICE);
4118 err_out:
4119 	dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4120 			DMA_TO_DEVICE);
4121 	return rc;
4122 }
4123 
4124 /**
4125  * pm8001_chip_ssp_io_req - send a SSP task to FW
4126  * @pm8001_ha: our hba card information.
4127  * @ccb: the ccb information this request used.
4128  */
pm8001_chip_ssp_io_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4129 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4130 	struct pm8001_ccb_info *ccb)
4131 {
4132 	struct sas_task *task = ccb->task;
4133 	struct domain_device *dev = task->dev;
4134 	struct pm8001_device *pm8001_dev = dev->lldd_dev;
4135 	struct ssp_ini_io_start_req ssp_cmd;
4136 	u32 tag = ccb->ccb_tag;
4137 	u64 phys_addr;
4138 	u32 opc = OPC_INB_SSPINIIOSTART;
4139 	memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4140 	memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4141 	ssp_cmd.dir_m_tlr =
4142 		cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4143 	SAS 1.1 compatible TLR*/
4144 	ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4145 	ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4146 	ssp_cmd.tag = cpu_to_le32(tag);
4147 	if (task->ssp_task.enable_first_burst)
4148 		ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4149 	ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4150 	ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4151 	memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4152 	       task->ssp_task.cmd->cmd_len);
4153 
4154 	/* fill in PRD (scatter/gather) table, if any */
4155 	if (task->num_scatter > 1) {
4156 		pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4157 		phys_addr = ccb->ccb_dma_handle;
4158 		ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4159 		ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4160 		ssp_cmd.esgl = cpu_to_le32(1<<31);
4161 	} else if (task->num_scatter == 1) {
4162 		u64 dma_addr = sg_dma_address(task->scatter);
4163 		ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4164 		ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4165 		ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4166 		ssp_cmd.esgl = 0;
4167 	} else if (task->num_scatter == 0) {
4168 		ssp_cmd.addr_low = 0;
4169 		ssp_cmd.addr_high = 0;
4170 		ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4171 		ssp_cmd.esgl = 0;
4172 	}
4173 
4174 	return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &ssp_cmd,
4175 				    sizeof(ssp_cmd), 0);
4176 }
4177 
pm8001_chip_sata_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4178 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4179 	struct pm8001_ccb_info *ccb)
4180 {
4181 	struct sas_task *task = ccb->task;
4182 	struct domain_device *dev = task->dev;
4183 	struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4184 	u32 tag = ccb->ccb_tag;
4185 	struct sata_start_req sata_cmd;
4186 	u32 hdr_tag, ncg_tag = 0;
4187 	u64 phys_addr;
4188 	u32 ATAP = 0x0;
4189 	u32 dir;
4190 	unsigned long flags;
4191 	u32  opc = OPC_INB_SATA_HOST_OPSTART;
4192 
4193 	memset(&sata_cmd, 0, sizeof(sata_cmd));
4194 
4195 	if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {
4196 		ATAP = 0x04;  /* no data*/
4197 		pm8001_dbg(pm8001_ha, IO, "no data\n");
4198 	} else if (likely(!task->ata_task.device_control_reg_update)) {
4199 		if (task->ata_task.use_ncq &&
4200 		    dev->sata_dev.class != ATA_DEV_ATAPI) {
4201 			ATAP = 0x07; /* FPDMA */
4202 			pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4203 		} else if (task->ata_task.dma_xfer) {
4204 			ATAP = 0x06; /* DMA */
4205 			pm8001_dbg(pm8001_ha, IO, "DMA\n");
4206 		} else {
4207 			ATAP = 0x05; /* PIO*/
4208 			pm8001_dbg(pm8001_ha, IO, "PIO\n");
4209 		}
4210 	}
4211 	if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4212 		task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4213 		ncg_tag = hdr_tag;
4214 	}
4215 	dir = data_dir_flags[task->data_dir] << 8;
4216 	sata_cmd.tag = cpu_to_le32(tag);
4217 	sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4218 	sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4219 	sata_cmd.ncqtag_atap_dir_m =
4220 		cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4221 	sata_cmd.sata_fis = task->ata_task.fis;
4222 	if (likely(!task->ata_task.device_control_reg_update))
4223 		sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4224 	sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4225 	/* fill in PRD (scatter/gather) table, if any */
4226 	if (task->num_scatter > 1) {
4227 		pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4228 		phys_addr = ccb->ccb_dma_handle;
4229 		sata_cmd.addr_low = lower_32_bits(phys_addr);
4230 		sata_cmd.addr_high = upper_32_bits(phys_addr);
4231 		sata_cmd.esgl = cpu_to_le32(1 << 31);
4232 	} else if (task->num_scatter == 1) {
4233 		u64 dma_addr = sg_dma_address(task->scatter);
4234 		sata_cmd.addr_low = lower_32_bits(dma_addr);
4235 		sata_cmd.addr_high = upper_32_bits(dma_addr);
4236 		sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4237 		sata_cmd.esgl = 0;
4238 	} else if (task->num_scatter == 0) {
4239 		sata_cmd.addr_low = 0;
4240 		sata_cmd.addr_high = 0;
4241 		sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4242 		sata_cmd.esgl = 0;
4243 	}
4244 
4245 	/* Check for read log for failed drive and return */
4246 	if (sata_cmd.sata_fis.command == 0x2f) {
4247 		if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4248 			(pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4249 			(pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4250 			struct task_status_struct *ts;
4251 
4252 			pm8001_ha_dev->id &= 0xDFFFFFFF;
4253 			ts = &task->task_status;
4254 
4255 			spin_lock_irqsave(&task->task_state_lock, flags);
4256 			ts->resp = SAS_TASK_COMPLETE;
4257 			ts->stat = SAS_SAM_STAT_GOOD;
4258 			task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4259 			task->task_state_flags |= SAS_TASK_STATE_DONE;
4260 			if (unlikely((task->task_state_flags &
4261 					SAS_TASK_STATE_ABORTED))) {
4262 				spin_unlock_irqrestore(&task->task_state_lock,
4263 							flags);
4264 				pm8001_dbg(pm8001_ha, FAIL,
4265 					   "task 0x%p resp 0x%x  stat 0x%x but aborted by upper layer\n",
4266 					   task, ts->resp,
4267 					   ts->stat);
4268 				pm8001_ccb_task_free(pm8001_ha, ccb);
4269 			} else {
4270 				spin_unlock_irqrestore(&task->task_state_lock,
4271 							flags);
4272 				pm8001_ccb_task_free_done(pm8001_ha, ccb);
4273 				return 0;
4274 			}
4275 		}
4276 	}
4277 
4278 	return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sata_cmd,
4279 				    sizeof(sata_cmd), 0);
4280 }
4281 
4282 /**
4283  * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4284  * @pm8001_ha: our hba card information.
4285  * @phy_id: the phy id which we wanted to start up.
4286  */
4287 static int
pm8001_chip_phy_start_req(struct pm8001_hba_info * pm8001_ha,u8 phy_id)4288 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4289 {
4290 	struct phy_start_req payload;
4291 	u32 tag = 0x01;
4292 	u32 opcode = OPC_INB_PHYSTART;
4293 
4294 	memset(&payload, 0, sizeof(payload));
4295 	payload.tag = cpu_to_le32(tag);
4296 	/*
4297 	 ** [0:7]   PHY Identifier
4298 	 ** [8:11]  link rate 1.5G, 3G, 6G
4299 	 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4300 	 ** [14]    0b disable spin up hold; 1b enable spin up hold
4301 	 */
4302 	payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4303 		LINKMODE_AUTO |	LINKRATE_15 |
4304 		LINKRATE_30 | LINKRATE_60 | phy_id);
4305 	payload.sas_identify.dev_type = SAS_END_DEVICE;
4306 	payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4307 	memcpy(payload.sas_identify.sas_addr,
4308 		pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4309 	payload.sas_identify.phy_id = phy_id;
4310 
4311 	return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4312 				    sizeof(payload), 0);
4313 }
4314 
4315 /**
4316  * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4317  * @pm8001_ha: our hba card information.
4318  * @phy_id: the phy id which we wanted to start up.
4319  */
pm8001_chip_phy_stop_req(struct pm8001_hba_info * pm8001_ha,u8 phy_id)4320 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4321 				    u8 phy_id)
4322 {
4323 	struct phy_stop_req payload;
4324 	u32 tag = 0x01;
4325 	u32 opcode = OPC_INB_PHYSTOP;
4326 
4327 	memset(&payload, 0, sizeof(payload));
4328 	payload.tag = cpu_to_le32(tag);
4329 	payload.phy_id = cpu_to_le32(phy_id);
4330 
4331 	return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4332 				    sizeof(payload), 0);
4333 }
4334 
4335 /*
4336  * see comments on pm8001_mpi_reg_resp.
4337  */
pm8001_chip_reg_dev_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_dev,u32 flag)4338 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4339 	struct pm8001_device *pm8001_dev, u32 flag)
4340 {
4341 	struct reg_dev_req payload;
4342 	u32	opc;
4343 	u32 stp_sspsmp_sata = 0x4;
4344 	u32 linkrate, phy_id;
4345 	int rc;
4346 	struct pm8001_ccb_info *ccb;
4347 	u8 retryFlag = 0x1;
4348 	u16 firstBurstSize = 0;
4349 	u16 ITNT = 2000;
4350 	struct domain_device *dev = pm8001_dev->sas_device;
4351 	struct domain_device *parent_dev = dev->parent;
4352 	struct pm8001_port *port = dev->port->lldd_port;
4353 
4354 	memset(&payload, 0, sizeof(payload));
4355 	ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL);
4356 	if (!ccb)
4357 		return -SAS_QUEUE_FULL;
4358 
4359 	payload.tag = cpu_to_le32(ccb->ccb_tag);
4360 	if (flag == 1)
4361 		stp_sspsmp_sata = 0x02; /*direct attached sata */
4362 	else {
4363 		if (pm8001_dev->dev_type == SAS_SATA_DEV)
4364 			stp_sspsmp_sata = 0x00; /* stp*/
4365 		else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4366 			dev_is_expander(pm8001_dev->dev_type))
4367 			stp_sspsmp_sata = 0x01; /*ssp or smp*/
4368 	}
4369 	if (parent_dev && dev_is_expander(parent_dev->dev_type))
4370 		phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4371 	else
4372 		phy_id = pm8001_dev->attached_phy;
4373 	opc = OPC_INB_REG_DEV;
4374 	linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4375 			pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4376 	payload.phyid_portid =
4377 		cpu_to_le32(((port->port_id) & 0x0F) |
4378 		((phy_id & 0x0F) << 4));
4379 	payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4380 		((linkrate & 0x0F) * 0x1000000) |
4381 		((stp_sspsmp_sata & 0x03) * 0x10000000));
4382 	payload.firstburstsize_ITNexustimeout =
4383 		cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4384 	memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4385 		SAS_ADDR_SIZE);
4386 
4387 	rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4388 				  sizeof(payload), 0);
4389 	if (rc)
4390 		pm8001_ccb_free(pm8001_ha, ccb);
4391 
4392 	return rc;
4393 }
4394 
4395 /*
4396  * see comments on pm8001_mpi_reg_resp.
4397  */
pm8001_chip_dereg_dev_req(struct pm8001_hba_info * pm8001_ha,u32 device_id)4398 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4399 	u32 device_id)
4400 {
4401 	struct dereg_dev_req payload;
4402 	u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4403 
4404 	memset(&payload, 0, sizeof(payload));
4405 	payload.tag = cpu_to_le32(1);
4406 	payload.device_id = cpu_to_le32(device_id);
4407 	pm8001_dbg(pm8001_ha, MSG, "unregister device device_id = %d\n",
4408 		   device_id);
4409 
4410 	return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4411 				    sizeof(payload), 0);
4412 }
4413 
4414 /**
4415  * pm8001_chip_phy_ctl_req - support the local phy operation
4416  * @pm8001_ha: our hba card information.
4417  * @phyId: the phy id which we wanted to operate
4418  * @phy_op: the phy operation to request
4419  */
pm8001_chip_phy_ctl_req(struct pm8001_hba_info * pm8001_ha,u32 phyId,u32 phy_op)4420 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4421 	u32 phyId, u32 phy_op)
4422 {
4423 	struct local_phy_ctl_req payload;
4424 	u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4425 
4426 	memset(&payload, 0, sizeof(payload));
4427 	payload.tag = cpu_to_le32(1);
4428 	payload.phyop_phyid =
4429 		cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4430 
4431 	return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4432 				    sizeof(payload), 0);
4433 }
4434 
pm8001_chip_is_our_interrupt(struct pm8001_hba_info * pm8001_ha)4435 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4436 {
4437 #ifdef PM8001_USE_MSIX
4438 	return 1;
4439 #else
4440 	u32 value;
4441 
4442 	value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4443 	if (value)
4444 		return 1;
4445 	return 0;
4446 #endif
4447 }
4448 
4449 /**
4450  * pm8001_chip_isr - PM8001 isr handler.
4451  * @pm8001_ha: our hba card information.
4452  * @vec: IRQ number
4453  */
4454 static irqreturn_t
pm8001_chip_isr(struct pm8001_hba_info * pm8001_ha,u8 vec)4455 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4456 {
4457 	pm8001_chip_interrupt_disable(pm8001_ha, vec);
4458 	pm8001_dbg(pm8001_ha, DEVIO,
4459 		   "irq vec %d, ODMR:0x%x\n",
4460 		   vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4461 	process_oq(pm8001_ha, vec);
4462 	pm8001_chip_interrupt_enable(pm8001_ha, vec);
4463 	return IRQ_HANDLED;
4464 }
4465 
send_task_abort(struct pm8001_hba_info * pm8001_ha,u32 opc,u32 dev_id,enum sas_internal_abort type,u32 task_tag,u32 cmd_tag)4466 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4467 	u32 dev_id, enum sas_internal_abort type, u32 task_tag, u32 cmd_tag)
4468 {
4469 	struct task_abort_req task_abort;
4470 
4471 	memset(&task_abort, 0, sizeof(task_abort));
4472 	if (type == SAS_INTERNAL_ABORT_SINGLE) {
4473 		task_abort.abort_all = 0;
4474 		task_abort.device_id = cpu_to_le32(dev_id);
4475 		task_abort.tag_to_abort = cpu_to_le32(task_tag);
4476 	} else if (type == SAS_INTERNAL_ABORT_DEV) {
4477 		task_abort.abort_all = cpu_to_le32(1);
4478 		task_abort.device_id = cpu_to_le32(dev_id);
4479 	} else {
4480 		pm8001_dbg(pm8001_ha, EH, "unknown type (%d)\n", type);
4481 		return -EIO;
4482 	}
4483 
4484 	task_abort.tag = cpu_to_le32(cmd_tag);
4485 
4486 	return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &task_abort,
4487 				    sizeof(task_abort), 0);
4488 }
4489 
4490 /*
4491  * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4492  */
pm8001_chip_abort_task(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4493 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4494 	struct pm8001_ccb_info *ccb)
4495 {
4496 	struct sas_task *task = ccb->task;
4497 	struct sas_internal_abort_task *abort = &task->abort_task;
4498 	struct pm8001_device *pm8001_dev = ccb->device;
4499 	int rc = TMF_RESP_FUNC_FAILED;
4500 	u32 opc, device_id;
4501 
4502 	pm8001_dbg(pm8001_ha, EH, "cmd_tag = %x, abort task tag = 0x%x\n",
4503 		   ccb->ccb_tag, abort->tag);
4504 	if (pm8001_dev->dev_type == SAS_END_DEVICE)
4505 		opc = OPC_INB_SSP_ABORT;
4506 	else if (pm8001_dev->dev_type == SAS_SATA_DEV)
4507 		opc = OPC_INB_SATA_ABORT;
4508 	else
4509 		opc = OPC_INB_SMP_ABORT;/* SMP */
4510 	device_id = pm8001_dev->device_id;
4511 	rc = send_task_abort(pm8001_ha, opc, device_id, abort->type,
4512 			     abort->tag, ccb->ccb_tag);
4513 	if (rc != TMF_RESP_FUNC_COMPLETE)
4514 		pm8001_dbg(pm8001_ha, EH, "rc= %d\n", rc);
4515 	return rc;
4516 }
4517 
4518 /**
4519  * pm8001_chip_ssp_tm_req - built the task management command.
4520  * @pm8001_ha: our hba card information.
4521  * @ccb: the ccb information.
4522  * @tmf: task management function.
4523  */
pm8001_chip_ssp_tm_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb,struct sas_tmf_task * tmf)4524 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4525 	struct pm8001_ccb_info *ccb, struct sas_tmf_task *tmf)
4526 {
4527 	struct sas_task *task = ccb->task;
4528 	struct domain_device *dev = task->dev;
4529 	struct pm8001_device *pm8001_dev = dev->lldd_dev;
4530 	u32 opc = OPC_INB_SSPINITMSTART;
4531 	struct ssp_ini_tm_start_req sspTMCmd;
4532 
4533 	memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4534 	sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4535 	sspTMCmd.relate_tag = cpu_to_le32((u32)tmf->tag_of_task_to_be_managed);
4536 	sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4537 	memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4538 	sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4539 	if (pm8001_ha->chip_id != chip_8001)
4540 		sspTMCmd.ds_ads_m = cpu_to_le32(0x08);
4541 
4542 	return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sspTMCmd,
4543 				    sizeof(sspTMCmd), 0);
4544 }
4545 
pm8001_chip_get_nvmd_req(struct pm8001_hba_info * pm8001_ha,void * payload)4546 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4547 	void *payload)
4548 {
4549 	u32 opc = OPC_INB_GET_NVMD_DATA;
4550 	u32 nvmd_type;
4551 	int rc;
4552 	struct pm8001_ccb_info *ccb;
4553 	struct get_nvm_data_req nvmd_req;
4554 	struct fw_control_ex *fw_control_context;
4555 	struct pm8001_ioctl_payload *ioctl_payload = payload;
4556 
4557 	nvmd_type = ioctl_payload->minor_function;
4558 	fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4559 	if (!fw_control_context)
4560 		return -ENOMEM;
4561 	fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
4562 	fw_control_context->len = ioctl_payload->rd_length;
4563 	memset(&nvmd_req, 0, sizeof(nvmd_req));
4564 
4565 	ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL);
4566 	if (!ccb) {
4567 		kfree(fw_control_context);
4568 		return -SAS_QUEUE_FULL;
4569 	}
4570 	ccb->fw_control_context = fw_control_context;
4571 
4572 	nvmd_req.tag = cpu_to_le32(ccb->ccb_tag);
4573 
4574 	switch (nvmd_type) {
4575 	case TWI_DEVICE: {
4576 		u32 twi_addr, twi_page_size;
4577 		twi_addr = 0xa8;
4578 		twi_page_size = 2;
4579 
4580 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4581 			twi_page_size << 8 | TWI_DEVICE);
4582 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4583 		nvmd_req.resp_addr_hi =
4584 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4585 		nvmd_req.resp_addr_lo =
4586 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4587 		break;
4588 	}
4589 	case C_SEEPROM: {
4590 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4591 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4592 		nvmd_req.resp_addr_hi =
4593 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4594 		nvmd_req.resp_addr_lo =
4595 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4596 		break;
4597 	}
4598 	case VPD_FLASH: {
4599 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4600 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4601 		nvmd_req.resp_addr_hi =
4602 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4603 		nvmd_req.resp_addr_lo =
4604 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4605 		break;
4606 	}
4607 	case EXPAN_ROM: {
4608 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4609 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4610 		nvmd_req.resp_addr_hi =
4611 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4612 		nvmd_req.resp_addr_lo =
4613 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4614 		break;
4615 	}
4616 	case IOP_RDUMP: {
4617 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
4618 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4619 		nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
4620 		nvmd_req.resp_addr_hi =
4621 		cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4622 		nvmd_req.resp_addr_lo =
4623 		cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4624 		break;
4625 	}
4626 	default:
4627 		break;
4628 	}
4629 
4630 	rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &nvmd_req,
4631 				  sizeof(nvmd_req), 0);
4632 	if (rc) {
4633 		kfree(fw_control_context);
4634 		pm8001_ccb_free(pm8001_ha, ccb);
4635 	}
4636 	return rc;
4637 }
4638 
pm8001_chip_set_nvmd_req(struct pm8001_hba_info * pm8001_ha,void * payload)4639 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4640 	void *payload)
4641 {
4642 	u32 opc = OPC_INB_SET_NVMD_DATA;
4643 	u32 nvmd_type;
4644 	int rc;
4645 	struct pm8001_ccb_info *ccb;
4646 	struct set_nvm_data_req nvmd_req;
4647 	struct fw_control_ex *fw_control_context;
4648 	struct pm8001_ioctl_payload *ioctl_payload = payload;
4649 
4650 	nvmd_type = ioctl_payload->minor_function;
4651 	fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4652 	if (!fw_control_context)
4653 		return -ENOMEM;
4654 
4655 	memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4656 		&ioctl_payload->func_specific,
4657 		ioctl_payload->wr_length);
4658 	memset(&nvmd_req, 0, sizeof(nvmd_req));
4659 
4660 	ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL);
4661 	if (!ccb) {
4662 		kfree(fw_control_context);
4663 		return -SAS_QUEUE_FULL;
4664 	}
4665 	ccb->fw_control_context = fw_control_context;
4666 
4667 	nvmd_req.tag = cpu_to_le32(ccb->ccb_tag);
4668 	switch (nvmd_type) {
4669 	case TWI_DEVICE: {
4670 		u32 twi_addr, twi_page_size;
4671 		twi_addr = 0xa8;
4672 		twi_page_size = 2;
4673 		nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4674 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4675 			twi_page_size << 8 | TWI_DEVICE);
4676 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4677 		nvmd_req.resp_addr_hi =
4678 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4679 		nvmd_req.resp_addr_lo =
4680 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4681 		break;
4682 	}
4683 	case C_SEEPROM:
4684 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4685 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4686 		nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4687 		nvmd_req.resp_addr_hi =
4688 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4689 		nvmd_req.resp_addr_lo =
4690 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4691 		break;
4692 	case VPD_FLASH:
4693 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4694 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4695 		nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4696 		nvmd_req.resp_addr_hi =
4697 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4698 		nvmd_req.resp_addr_lo =
4699 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4700 		break;
4701 	case EXPAN_ROM:
4702 		nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4703 		nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4704 		nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4705 		nvmd_req.resp_addr_hi =
4706 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4707 		nvmd_req.resp_addr_lo =
4708 		    cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4709 		break;
4710 	default:
4711 		break;
4712 	}
4713 
4714 	rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &nvmd_req,
4715 			sizeof(nvmd_req), 0);
4716 	if (rc) {
4717 		kfree(fw_control_context);
4718 		pm8001_ccb_free(pm8001_ha, ccb);
4719 	}
4720 	return rc;
4721 }
4722 
4723 /**
4724  * pm8001_chip_fw_flash_update_build - support the firmware update operation
4725  * @pm8001_ha: our hba card information.
4726  * @fw_flash_updata_info: firmware flash update param
4727  * @tag: Tag to apply to the payload
4728  */
4729 int
pm8001_chip_fw_flash_update_build(struct pm8001_hba_info * pm8001_ha,void * fw_flash_updata_info,u32 tag)4730 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4731 	void *fw_flash_updata_info, u32 tag)
4732 {
4733 	struct fw_flash_Update_req payload;
4734 	struct fw_flash_updata_info *info;
4735 	u32 opc = OPC_INB_FW_FLASH_UPDATE;
4736 
4737 	memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4738 	info = fw_flash_updata_info;
4739 	payload.tag = cpu_to_le32(tag);
4740 	payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4741 	payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4742 	payload.total_image_len = cpu_to_le32(info->total_image_len);
4743 	payload.len = info->sgl.im_len.len ;
4744 	payload.sgl_addr_lo =
4745 		cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4746 	payload.sgl_addr_hi =
4747 		cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4748 
4749 	return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4750 				    sizeof(payload), 0);
4751 }
4752 
4753 int
pm8001_chip_fw_flash_update_req(struct pm8001_hba_info * pm8001_ha,void * payload)4754 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4755 	void *payload)
4756 {
4757 	struct fw_flash_updata_info flash_update_info;
4758 	struct fw_control_info *fw_control;
4759 	struct fw_control_ex *fw_control_context;
4760 	int rc;
4761 	struct pm8001_ccb_info *ccb;
4762 	void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
4763 	dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
4764 	struct pm8001_ioctl_payload *ioctl_payload = payload;
4765 
4766 	fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4767 	if (!fw_control_context)
4768 		return -ENOMEM;
4769 	fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
4770 	pm8001_dbg(pm8001_ha, DEVIO,
4771 		   "dma fw_control context input length :%x\n",
4772 		   fw_control->len);
4773 	memcpy(buffer, fw_control->buffer, fw_control->len);
4774 	flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4775 	flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4776 	flash_update_info.sgl.im_len.e = 0;
4777 	flash_update_info.cur_image_offset = fw_control->offset;
4778 	flash_update_info.cur_image_len = fw_control->len;
4779 	flash_update_info.total_image_len = fw_control->size;
4780 	fw_control_context->fw_control = fw_control;
4781 	fw_control_context->virtAddr = buffer;
4782 	fw_control_context->phys_addr = phys_addr;
4783 	fw_control_context->len = fw_control->len;
4784 
4785 	ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL);
4786 	if (!ccb) {
4787 		kfree(fw_control_context);
4788 		return -SAS_QUEUE_FULL;
4789 	}
4790 	ccb->fw_control_context = fw_control_context;
4791 
4792 	rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4793 					       ccb->ccb_tag);
4794 	if (rc) {
4795 		kfree(fw_control_context);
4796 		pm8001_ccb_free(pm8001_ha, ccb);
4797 	}
4798 
4799 	return rc;
4800 }
4801 
4802 ssize_t
pm8001_get_gsm_dump(struct device * cdev,u32 length,char * buf)4803 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
4804 {
4805 	u32 value, rem, offset = 0, bar = 0;
4806 	u32 index, work_offset, dw_length;
4807 	u32 shift_value, gsm_base, gsm_dump_offset;
4808 	char *direct_data;
4809 	struct Scsi_Host *shost = class_to_shost(cdev);
4810 	struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
4811 	struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
4812 
4813 	direct_data = buf;
4814 	gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
4815 
4816 	/* check max is 1 Mbytes */
4817 	if ((length > 0x100000) || (gsm_dump_offset & 3) ||
4818 		((gsm_dump_offset + length) > 0x1000000))
4819 			return -EINVAL;
4820 
4821 	if (pm8001_ha->chip_id == chip_8001)
4822 		bar = 2;
4823 	else
4824 		bar = 1;
4825 
4826 	work_offset = gsm_dump_offset & 0xFFFF0000;
4827 	offset = gsm_dump_offset & 0x0000FFFF;
4828 	gsm_dump_offset = work_offset;
4829 	/* adjust length to dword boundary */
4830 	rem = length & 3;
4831 	dw_length = length >> 2;
4832 
4833 	for (index = 0; index < dw_length; index++) {
4834 		if ((work_offset + offset) & 0xFFFF0000) {
4835 			if (pm8001_ha->chip_id == chip_8001)
4836 				shift_value = ((gsm_dump_offset + offset) &
4837 						SHIFT_REG_64K_MASK);
4838 			else
4839 				shift_value = (((gsm_dump_offset + offset) &
4840 						SHIFT_REG_64K_MASK) >>
4841 						SHIFT_REG_BIT_SHIFT);
4842 
4843 			if (pm8001_ha->chip_id == chip_8001) {
4844 				gsm_base = GSM_BASE;
4845 				if (-1 == pm8001_bar4_shift(pm8001_ha,
4846 						(gsm_base + shift_value)))
4847 					return -EIO;
4848 			} else {
4849 				gsm_base = 0;
4850 				if (-1 == pm80xx_bar4_shift(pm8001_ha,
4851 						(gsm_base + shift_value)))
4852 					return -EIO;
4853 			}
4854 			gsm_dump_offset = (gsm_dump_offset + offset) &
4855 						0xFFFF0000;
4856 			work_offset = 0;
4857 			offset = offset & 0x0000FFFF;
4858 		}
4859 		value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
4860 						0x0000FFFF);
4861 		direct_data += sprintf(direct_data, "%08x ", value);
4862 		offset += 4;
4863 	}
4864 	if (rem != 0) {
4865 		value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
4866 						0x0000FFFF);
4867 		/* xfr for non_dw */
4868 		direct_data += sprintf(direct_data, "%08x ", value);
4869 	}
4870 	/* Shift back to BAR4 original address */
4871 	if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
4872 			return -EIO;
4873 	pm8001_ha->fatal_forensic_shift_offset += 1024;
4874 
4875 	if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
4876 		pm8001_ha->fatal_forensic_shift_offset = 0;
4877 	return direct_data - buf;
4878 }
4879 
4880 int
pm8001_chip_set_dev_state_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_dev,u32 state)4881 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4882 	struct pm8001_device *pm8001_dev, u32 state)
4883 {
4884 	struct set_dev_state_req payload;
4885 	struct pm8001_ccb_info *ccb;
4886 	int rc;
4887 	u32 opc = OPC_INB_SET_DEVICE_STATE;
4888 
4889 	memset(&payload, 0, sizeof(payload));
4890 
4891 	ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL);
4892 	if (!ccb)
4893 		return -SAS_QUEUE_FULL;
4894 
4895 	payload.tag = cpu_to_le32(ccb->ccb_tag);
4896 	payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4897 	payload.nds = cpu_to_le32(state);
4898 
4899 	rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4900 				  sizeof(payload), 0);
4901 	if (rc)
4902 		pm8001_ccb_free(pm8001_ha, ccb);
4903 
4904 	return rc;
4905 }
4906 
4907 static int
pm8001_chip_sas_re_initialization(struct pm8001_hba_info * pm8001_ha)4908 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4909 {
4910 	struct sas_re_initialization_req payload;
4911 	struct pm8001_ccb_info *ccb;
4912 	int rc;
4913 	u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4914 
4915 	memset(&payload, 0, sizeof(payload));
4916 
4917 	ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL);
4918 	if (!ccb)
4919 		return -SAS_QUEUE_FULL;
4920 
4921 	payload.tag = cpu_to_le32(ccb->ccb_tag);
4922 	payload.SSAHOLT = cpu_to_le32(0xd << 25);
4923 	payload.sata_hol_tmo = cpu_to_le32(80);
4924 	payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4925 
4926 	rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4927 				  sizeof(payload), 0);
4928 	if (rc)
4929 		pm8001_ccb_free(pm8001_ha, ccb);
4930 
4931 	return rc;
4932 }
4933 
4934 const struct pm8001_dispatch pm8001_8001_dispatch = {
4935 	.name			= "pmc8001",
4936 	.chip_init		= pm8001_chip_init,
4937 	.chip_soft_rst		= pm8001_chip_soft_rst,
4938 	.chip_rst		= pm8001_hw_chip_rst,
4939 	.chip_iounmap		= pm8001_chip_iounmap,
4940 	.isr			= pm8001_chip_isr,
4941 	.is_our_interrupt	= pm8001_chip_is_our_interrupt,
4942 	.isr_process_oq		= process_oq,
4943 	.interrupt_enable 	= pm8001_chip_interrupt_enable,
4944 	.interrupt_disable	= pm8001_chip_interrupt_disable,
4945 	.make_prd		= pm8001_chip_make_sg,
4946 	.smp_req		= pm8001_chip_smp_req,
4947 	.ssp_io_req		= pm8001_chip_ssp_io_req,
4948 	.sata_req		= pm8001_chip_sata_req,
4949 	.phy_start_req		= pm8001_chip_phy_start_req,
4950 	.phy_stop_req		= pm8001_chip_phy_stop_req,
4951 	.reg_dev_req		= pm8001_chip_reg_dev_req,
4952 	.dereg_dev_req		= pm8001_chip_dereg_dev_req,
4953 	.phy_ctl_req		= pm8001_chip_phy_ctl_req,
4954 	.task_abort		= pm8001_chip_abort_task,
4955 	.ssp_tm_req		= pm8001_chip_ssp_tm_req,
4956 	.get_nvmd_req		= pm8001_chip_get_nvmd_req,
4957 	.set_nvmd_req		= pm8001_chip_set_nvmd_req,
4958 	.fw_flash_update_req	= pm8001_chip_fw_flash_update_req,
4959 	.set_dev_state_req	= pm8001_chip_set_dev_state_req,
4960 	.sas_re_init_req	= pm8001_chip_sas_re_initialization,
4961 	.fatal_errors		= pm80xx_fatal_errors,
4962 };
4963