1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29
30 #include "resource.h"
31 #include "include/irq_service_interface.h"
32 #include "link_encoder.h"
33 #include "stream_encoder.h"
34 #include "opp.h"
35 #include "timing_generator.h"
36 #include "transform.h"
37 #include "dccg.h"
38 #include "dchubbub.h"
39 #include "dpp.h"
40 #include "core_types.h"
41 #include "set_mode_types.h"
42 #include "virtual/virtual_stream_encoder.h"
43 #include "dpcd_defs.h"
44 #include "link_enc_cfg.h"
45 #include "dc_link_dp.h"
46 #include "virtual/virtual_link_hwss.h"
47 #include "link/link_hwss_dio.h"
48 #include "link/link_hwss_dpia.h"
49 #include "link/link_hwss_hpo_dp.h"
50
51 #if defined(CONFIG_DRM_AMD_DC_SI)
52 #include "dce60/dce60_resource.h"
53 #endif
54 #include "dce80/dce80_resource.h"
55 #include "dce100/dce100_resource.h"
56 #include "dce110/dce110_resource.h"
57 #include "dce112/dce112_resource.h"
58 #include "dce120/dce120_resource.h"
59 #include "dcn10/dcn10_resource.h"
60 #include "dcn20/dcn20_resource.h"
61 #include "dcn21/dcn21_resource.h"
62 #include "dcn201/dcn201_resource.h"
63 #include "dcn30/dcn30_resource.h"
64 #include "dcn301/dcn301_resource.h"
65 #include "dcn302/dcn302_resource.h"
66 #include "dcn303/dcn303_resource.h"
67 #include "dcn31/dcn31_resource.h"
68 #include "dcn315/dcn315_resource.h"
69 #include "dcn316/dcn316_resource.h"
70
71 #define DC_LOGGER_INIT(logger)
72
resource_parse_asic_id(struct hw_asic_id asic_id)73 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
74 {
75 enum dce_version dc_version = DCE_VERSION_UNKNOWN;
76 switch (asic_id.chip_family) {
77
78 #if defined(CONFIG_DRM_AMD_DC_SI)
79 case FAMILY_SI:
80 if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
81 ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
82 ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
83 dc_version = DCE_VERSION_6_0;
84 else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
85 dc_version = DCE_VERSION_6_4;
86 else
87 dc_version = DCE_VERSION_6_1;
88 break;
89 #endif
90 case FAMILY_CI:
91 dc_version = DCE_VERSION_8_0;
92 break;
93 case FAMILY_KV:
94 if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
95 ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
96 ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
97 dc_version = DCE_VERSION_8_3;
98 else
99 dc_version = DCE_VERSION_8_1;
100 break;
101 case FAMILY_CZ:
102 dc_version = DCE_VERSION_11_0;
103 break;
104
105 case FAMILY_VI:
106 if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
107 ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
108 dc_version = DCE_VERSION_10_0;
109 break;
110 }
111 if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
112 ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
113 ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
114 dc_version = DCE_VERSION_11_2;
115 }
116 if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
117 dc_version = DCE_VERSION_11_22;
118 break;
119 case FAMILY_AI:
120 if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
121 dc_version = DCE_VERSION_12_1;
122 else
123 dc_version = DCE_VERSION_12_0;
124 break;
125 case FAMILY_RV:
126 dc_version = DCN_VERSION_1_0;
127 if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
128 dc_version = DCN_VERSION_1_01;
129 if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
130 dc_version = DCN_VERSION_2_1;
131 if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
132 dc_version = DCN_VERSION_2_1;
133 break;
134
135 case FAMILY_NV:
136 dc_version = DCN_VERSION_2_0;
137 if (asic_id.chip_id == DEVICE_ID_NV_13FE || asic_id.chip_id == DEVICE_ID_NV_143F) {
138 dc_version = DCN_VERSION_2_01;
139 break;
140 }
141 if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
142 dc_version = DCN_VERSION_3_0;
143 if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))
144 dc_version = DCN_VERSION_3_02;
145 if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev))
146 dc_version = DCN_VERSION_3_03;
147 break;
148
149 case FAMILY_VGH:
150 dc_version = DCN_VERSION_3_01;
151 break;
152
153 case FAMILY_YELLOW_CARP:
154 if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev))
155 dc_version = DCN_VERSION_3_1;
156 break;
157 case AMDGPU_FAMILY_GC_10_3_6:
158 if (ASICREV_IS_GC_10_3_6(asic_id.hw_internal_rev))
159 dc_version = DCN_VERSION_3_15;
160 break;
161 case AMDGPU_FAMILY_GC_10_3_7:
162 if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
163 dc_version = DCN_VERSION_3_16;
164 break;
165
166 default:
167 dc_version = DCE_VERSION_UNKNOWN;
168 break;
169 }
170 return dc_version;
171 }
172
dc_create_resource_pool(struct dc * dc,const struct dc_init_data * init_data,enum dce_version dc_version)173 struct resource_pool *dc_create_resource_pool(struct dc *dc,
174 const struct dc_init_data *init_data,
175 enum dce_version dc_version)
176 {
177 struct resource_pool *res_pool = NULL;
178
179 switch (dc_version) {
180 #if defined(CONFIG_DRM_AMD_DC_SI)
181 case DCE_VERSION_6_0:
182 res_pool = dce60_create_resource_pool(
183 init_data->num_virtual_links, dc);
184 break;
185 case DCE_VERSION_6_1:
186 res_pool = dce61_create_resource_pool(
187 init_data->num_virtual_links, dc);
188 break;
189 case DCE_VERSION_6_4:
190 res_pool = dce64_create_resource_pool(
191 init_data->num_virtual_links, dc);
192 break;
193 #endif
194 case DCE_VERSION_8_0:
195 res_pool = dce80_create_resource_pool(
196 init_data->num_virtual_links, dc);
197 break;
198 case DCE_VERSION_8_1:
199 res_pool = dce81_create_resource_pool(
200 init_data->num_virtual_links, dc);
201 break;
202 case DCE_VERSION_8_3:
203 res_pool = dce83_create_resource_pool(
204 init_data->num_virtual_links, dc);
205 break;
206 case DCE_VERSION_10_0:
207 res_pool = dce100_create_resource_pool(
208 init_data->num_virtual_links, dc);
209 break;
210 case DCE_VERSION_11_0:
211 res_pool = dce110_create_resource_pool(
212 init_data->num_virtual_links, dc,
213 init_data->asic_id);
214 break;
215 case DCE_VERSION_11_2:
216 case DCE_VERSION_11_22:
217 res_pool = dce112_create_resource_pool(
218 init_data->num_virtual_links, dc);
219 break;
220 case DCE_VERSION_12_0:
221 case DCE_VERSION_12_1:
222 res_pool = dce120_create_resource_pool(
223 init_data->num_virtual_links, dc);
224 break;
225
226 #if defined(CONFIG_DRM_AMD_DC_DCN)
227 case DCN_VERSION_1_0:
228 case DCN_VERSION_1_01:
229 res_pool = dcn10_create_resource_pool(init_data, dc);
230 break;
231 case DCN_VERSION_2_0:
232 res_pool = dcn20_create_resource_pool(init_data, dc);
233 break;
234 case DCN_VERSION_2_1:
235 res_pool = dcn21_create_resource_pool(init_data, dc);
236 break;
237 case DCN_VERSION_2_01:
238 res_pool = dcn201_create_resource_pool(init_data, dc);
239 break;
240 case DCN_VERSION_3_0:
241 res_pool = dcn30_create_resource_pool(init_data, dc);
242 break;
243 case DCN_VERSION_3_01:
244 res_pool = dcn301_create_resource_pool(init_data, dc);
245 break;
246 case DCN_VERSION_3_02:
247 res_pool = dcn302_create_resource_pool(init_data, dc);
248 break;
249 case DCN_VERSION_3_03:
250 res_pool = dcn303_create_resource_pool(init_data, dc);
251 break;
252 case DCN_VERSION_3_1:
253 res_pool = dcn31_create_resource_pool(init_data, dc);
254 break;
255 case DCN_VERSION_3_15:
256 res_pool = dcn315_create_resource_pool(init_data, dc);
257 break;
258 case DCN_VERSION_3_16:
259 res_pool = dcn316_create_resource_pool(init_data, dc);
260 break;
261 #endif
262 default:
263 break;
264 }
265
266 if (res_pool != NULL) {
267 if (dc->ctx->dc_bios->fw_info_valid) {
268 res_pool->ref_clocks.xtalin_clock_inKhz =
269 dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
270 /* initialize with firmware data first, no all
271 * ASIC have DCCG SW component. FPGA or
272 * simulation need initialization of
273 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
274 * with xtalin_clock_inKhz
275 */
276 res_pool->ref_clocks.dccg_ref_clock_inKhz =
277 res_pool->ref_clocks.xtalin_clock_inKhz;
278 res_pool->ref_clocks.dchub_ref_clock_inKhz =
279 res_pool->ref_clocks.xtalin_clock_inKhz;
280 } else
281 ASSERT_CRITICAL(false);
282 }
283
284 return res_pool;
285 }
286
dc_destroy_resource_pool(struct dc * dc)287 void dc_destroy_resource_pool(struct dc *dc)
288 {
289 if (dc) {
290 if (dc->res_pool)
291 dc->res_pool->funcs->destroy(&dc->res_pool);
292
293 kfree(dc->hwseq);
294 }
295 }
296
update_num_audio(const struct resource_straps * straps,unsigned int * num_audio,struct audio_support * aud_support)297 static void update_num_audio(
298 const struct resource_straps *straps,
299 unsigned int *num_audio,
300 struct audio_support *aud_support)
301 {
302 aud_support->dp_audio = true;
303 aud_support->hdmi_audio_native = false;
304 aud_support->hdmi_audio_on_dongle = false;
305
306 if (straps->hdmi_disable == 0) {
307 if (straps->dc_pinstraps_audio & 0x2) {
308 aud_support->hdmi_audio_on_dongle = true;
309 aud_support->hdmi_audio_native = true;
310 }
311 }
312
313 switch (straps->audio_stream_number) {
314 case 0: /* multi streams supported */
315 break;
316 case 1: /* multi streams not supported */
317 *num_audio = 1;
318 break;
319 default:
320 DC_ERR("DC: unexpected audio fuse!\n");
321 }
322 }
323
resource_construct(unsigned int num_virtual_links,struct dc * dc,struct resource_pool * pool,const struct resource_create_funcs * create_funcs)324 bool resource_construct(
325 unsigned int num_virtual_links,
326 struct dc *dc,
327 struct resource_pool *pool,
328 const struct resource_create_funcs *create_funcs)
329 {
330 struct dc_context *ctx = dc->ctx;
331 const struct resource_caps *caps = pool->res_cap;
332 int i;
333 unsigned int num_audio = caps->num_audio;
334 struct resource_straps straps = {0};
335
336 if (create_funcs->read_dce_straps)
337 create_funcs->read_dce_straps(dc->ctx, &straps);
338
339 pool->audio_count = 0;
340 if (create_funcs->create_audio) {
341 /* find the total number of streams available via the
342 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
343 * registers (one for each pin) starting from pin 1
344 * up to the max number of audio pins.
345 * We stop on the first pin where
346 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
347 */
348 update_num_audio(&straps, &num_audio, &pool->audio_support);
349 for (i = 0; i < caps->num_audio; i++) {
350 struct audio *aud = create_funcs->create_audio(ctx, i);
351
352 if (aud == NULL) {
353 DC_ERR("DC: failed to create audio!\n");
354 return false;
355 }
356 if (!aud->funcs->endpoint_valid(aud)) {
357 aud->funcs->destroy(&aud);
358 break;
359 }
360 pool->audios[i] = aud;
361 pool->audio_count++;
362 }
363 }
364
365 pool->stream_enc_count = 0;
366 if (create_funcs->create_stream_encoder) {
367 for (i = 0; i < caps->num_stream_encoder; i++) {
368 pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
369 if (pool->stream_enc[i] == NULL)
370 DC_ERR("DC: failed to create stream_encoder!\n");
371 pool->stream_enc_count++;
372 }
373 }
374
375 pool->hpo_dp_stream_enc_count = 0;
376 if (create_funcs->create_hpo_dp_stream_encoder) {
377 for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) {
378 pool->hpo_dp_stream_enc[i] = create_funcs->create_hpo_dp_stream_encoder(i+ENGINE_ID_HPO_DP_0, ctx);
379 if (pool->hpo_dp_stream_enc[i] == NULL)
380 DC_ERR("DC: failed to create HPO DP stream encoder!\n");
381 pool->hpo_dp_stream_enc_count++;
382
383 }
384 }
385
386 pool->hpo_dp_link_enc_count = 0;
387 if (create_funcs->create_hpo_dp_link_encoder) {
388 for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) {
389 pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx);
390 if (pool->hpo_dp_link_enc[i] == NULL)
391 DC_ERR("DC: failed to create HPO DP link encoder!\n");
392 pool->hpo_dp_link_enc_count++;
393 }
394 }
395
396 for (i = 0; i < caps->num_mpc_3dlut; i++) {
397 pool->mpc_lut[i] = dc_create_3dlut_func();
398 if (pool->mpc_lut[i] == NULL)
399 DC_ERR("DC: failed to create MPC 3dlut!\n");
400 pool->mpc_shaper[i] = dc_create_transfer_func();
401 if (pool->mpc_shaper[i] == NULL)
402 DC_ERR("DC: failed to create MPC shaper!\n");
403 }
404
405 dc->caps.dynamic_audio = false;
406 if (pool->audio_count < pool->stream_enc_count) {
407 dc->caps.dynamic_audio = true;
408 }
409 for (i = 0; i < num_virtual_links; i++) {
410 pool->stream_enc[pool->stream_enc_count] =
411 virtual_stream_encoder_create(
412 ctx, ctx->dc_bios);
413 if (pool->stream_enc[pool->stream_enc_count] == NULL) {
414 DC_ERR("DC: failed to create stream_encoder!\n");
415 return false;
416 }
417 pool->stream_enc_count++;
418 }
419
420 dc->hwseq = create_funcs->create_hwseq(ctx);
421
422 return true;
423 }
find_matching_clock_source(const struct resource_pool * pool,struct clock_source * clock_source)424 static int find_matching_clock_source(
425 const struct resource_pool *pool,
426 struct clock_source *clock_source)
427 {
428
429 int i;
430
431 for (i = 0; i < pool->clk_src_count; i++) {
432 if (pool->clock_sources[i] == clock_source)
433 return i;
434 }
435 return -1;
436 }
437
resource_unreference_clock_source(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)438 void resource_unreference_clock_source(
439 struct resource_context *res_ctx,
440 const struct resource_pool *pool,
441 struct clock_source *clock_source)
442 {
443 int i = find_matching_clock_source(pool, clock_source);
444
445 if (i > -1)
446 res_ctx->clock_source_ref_count[i]--;
447
448 if (pool->dp_clock_source == clock_source)
449 res_ctx->dp_clock_source_ref_count--;
450 }
451
resource_reference_clock_source(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)452 void resource_reference_clock_source(
453 struct resource_context *res_ctx,
454 const struct resource_pool *pool,
455 struct clock_source *clock_source)
456 {
457 int i = find_matching_clock_source(pool, clock_source);
458
459 if (i > -1)
460 res_ctx->clock_source_ref_count[i]++;
461
462 if (pool->dp_clock_source == clock_source)
463 res_ctx->dp_clock_source_ref_count++;
464 }
465
resource_get_clock_source_reference(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)466 int resource_get_clock_source_reference(
467 struct resource_context *res_ctx,
468 const struct resource_pool *pool,
469 struct clock_source *clock_source)
470 {
471 int i = find_matching_clock_source(pool, clock_source);
472
473 if (i > -1)
474 return res_ctx->clock_source_ref_count[i];
475
476 if (pool->dp_clock_source == clock_source)
477 return res_ctx->dp_clock_source_ref_count;
478
479 return -1;
480 }
481
resource_are_vblanks_synchronizable(struct dc_stream_state * stream1,struct dc_stream_state * stream2)482 bool resource_are_vblanks_synchronizable(
483 struct dc_stream_state *stream1,
484 struct dc_stream_state *stream2)
485 {
486 uint32_t base60_refresh_rates[] = {10, 20, 5};
487 uint8_t i;
488 uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates);
489 uint64_t frame_time_diff;
490
491 if (stream1->ctx->dc->config.vblank_alignment_dto_params &&
492 stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 &&
493 dc_is_dp_signal(stream1->signal) &&
494 dc_is_dp_signal(stream2->signal) &&
495 false == stream1->has_non_synchronizable_pclk &&
496 false == stream2->has_non_synchronizable_pclk &&
497 stream1->timing.flags.VBLANK_SYNCHRONIZABLE &&
498 stream2->timing.flags.VBLANK_SYNCHRONIZABLE) {
499 /* disable refresh rates higher than 60Hz for now */
500 if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/
501 stream1->timing.v_total > 60)
502 return false;
503 if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/
504 stream2->timing.v_total > 60)
505 return false;
506 frame_time_diff = (uint64_t)10000 *
507 stream1->timing.h_total *
508 stream1->timing.v_total *
509 stream2->timing.pix_clk_100hz;
510 frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz);
511 frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total);
512 frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total);
513 for (i = 0; i < rr_count; i++) {
514 int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000;
515
516 if (diff < 0)
517 diff = -diff;
518 if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff)
519 return true;
520 }
521 }
522 return false;
523 }
524
resource_are_streams_timing_synchronizable(struct dc_stream_state * stream1,struct dc_stream_state * stream2)525 bool resource_are_streams_timing_synchronizable(
526 struct dc_stream_state *stream1,
527 struct dc_stream_state *stream2)
528 {
529 if (stream1->timing.h_total != stream2->timing.h_total)
530 return false;
531
532 if (stream1->timing.v_total != stream2->timing.v_total)
533 return false;
534
535 if (stream1->timing.h_addressable
536 != stream2->timing.h_addressable)
537 return false;
538
539 if (stream1->timing.v_addressable
540 != stream2->timing.v_addressable)
541 return false;
542
543 if (stream1->timing.v_front_porch
544 != stream2->timing.v_front_porch)
545 return false;
546
547 if (stream1->timing.pix_clk_100hz
548 != stream2->timing.pix_clk_100hz)
549 return false;
550
551 if (stream1->clamping.c_depth != stream2->clamping.c_depth)
552 return false;
553
554 if (stream1->phy_pix_clk != stream2->phy_pix_clk
555 && (!dc_is_dp_signal(stream1->signal)
556 || !dc_is_dp_signal(stream2->signal)))
557 return false;
558
559 if (stream1->view_format != stream2->view_format)
560 return false;
561
562 if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
563 return false;
564
565 return true;
566 }
is_dp_and_hdmi_sharable(struct dc_stream_state * stream1,struct dc_stream_state * stream2)567 static bool is_dp_and_hdmi_sharable(
568 struct dc_stream_state *stream1,
569 struct dc_stream_state *stream2)
570 {
571 if (stream1->ctx->dc->caps.disable_dp_clk_share)
572 return false;
573
574 if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
575 stream2->clamping.c_depth != COLOR_DEPTH_888)
576 return false;
577
578 return true;
579
580 }
581
is_sharable_clk_src(const struct pipe_ctx * pipe_with_clk_src,const struct pipe_ctx * pipe)582 static bool is_sharable_clk_src(
583 const struct pipe_ctx *pipe_with_clk_src,
584 const struct pipe_ctx *pipe)
585 {
586 if (pipe_with_clk_src->clock_source == NULL)
587 return false;
588
589 if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
590 return false;
591
592 if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
593 (dc_is_dp_signal(pipe->stream->signal) &&
594 !is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
595 pipe->stream)))
596 return false;
597
598 if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
599 && dc_is_dual_link_signal(pipe->stream->signal))
600 return false;
601
602 if (dc_is_hdmi_signal(pipe->stream->signal)
603 && dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
604 return false;
605
606 if (!resource_are_streams_timing_synchronizable(
607 pipe_with_clk_src->stream, pipe->stream))
608 return false;
609
610 return true;
611 }
612
resource_find_used_clk_src_for_sharing(struct resource_context * res_ctx,struct pipe_ctx * pipe_ctx)613 struct clock_source *resource_find_used_clk_src_for_sharing(
614 struct resource_context *res_ctx,
615 struct pipe_ctx *pipe_ctx)
616 {
617 int i;
618
619 for (i = 0; i < MAX_PIPES; i++) {
620 if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
621 return res_ctx->pipe_ctx[i].clock_source;
622 }
623
624 return NULL;
625 }
626
convert_pixel_format_to_dalsurface(enum surface_pixel_format surface_pixel_format)627 static enum pixel_format convert_pixel_format_to_dalsurface(
628 enum surface_pixel_format surface_pixel_format)
629 {
630 enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
631
632 switch (surface_pixel_format) {
633 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
634 dal_pixel_format = PIXEL_FORMAT_INDEX8;
635 break;
636 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
637 dal_pixel_format = PIXEL_FORMAT_RGB565;
638 break;
639 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
640 dal_pixel_format = PIXEL_FORMAT_RGB565;
641 break;
642 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
643 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
644 break;
645 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
646 dal_pixel_format = PIXEL_FORMAT_ARGB8888;
647 break;
648 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
649 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
650 break;
651 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
652 dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
653 break;
654 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
655 dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
656 break;
657 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
658 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
659 dal_pixel_format = PIXEL_FORMAT_FP16;
660 break;
661 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
662 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
663 dal_pixel_format = PIXEL_FORMAT_420BPP8;
664 break;
665 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
666 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
667 dal_pixel_format = PIXEL_FORMAT_420BPP10;
668 break;
669 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
670 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
671 default:
672 dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
673 break;
674 }
675 return dal_pixel_format;
676 }
677
get_vp_scan_direction(enum dc_rotation_angle rotation,bool horizontal_mirror,bool * orthogonal_rotation,bool * flip_vert_scan_dir,bool * flip_horz_scan_dir)678 static inline void get_vp_scan_direction(
679 enum dc_rotation_angle rotation,
680 bool horizontal_mirror,
681 bool *orthogonal_rotation,
682 bool *flip_vert_scan_dir,
683 bool *flip_horz_scan_dir)
684 {
685 *orthogonal_rotation = false;
686 *flip_vert_scan_dir = false;
687 *flip_horz_scan_dir = false;
688 if (rotation == ROTATION_ANGLE_180) {
689 *flip_vert_scan_dir = true;
690 *flip_horz_scan_dir = true;
691 } else if (rotation == ROTATION_ANGLE_90) {
692 *orthogonal_rotation = true;
693 *flip_horz_scan_dir = true;
694 } else if (rotation == ROTATION_ANGLE_270) {
695 *orthogonal_rotation = true;
696 *flip_vert_scan_dir = true;
697 }
698
699 if (horizontal_mirror)
700 *flip_horz_scan_dir = !*flip_horz_scan_dir;
701 }
702
get_num_mpc_splits(struct pipe_ctx * pipe)703 int get_num_mpc_splits(struct pipe_ctx *pipe)
704 {
705 int mpc_split_count = 0;
706 struct pipe_ctx *other_pipe = pipe->bottom_pipe;
707
708 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
709 mpc_split_count++;
710 other_pipe = other_pipe->bottom_pipe;
711 }
712 other_pipe = pipe->top_pipe;
713 while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
714 mpc_split_count++;
715 other_pipe = other_pipe->top_pipe;
716 }
717
718 return mpc_split_count;
719 }
720
get_num_odm_splits(struct pipe_ctx * pipe)721 int get_num_odm_splits(struct pipe_ctx *pipe)
722 {
723 int odm_split_count = 0;
724 struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
725 while (next_pipe) {
726 odm_split_count++;
727 next_pipe = next_pipe->next_odm_pipe;
728 }
729 pipe = pipe->prev_odm_pipe;
730 while (pipe) {
731 odm_split_count++;
732 pipe = pipe->prev_odm_pipe;
733 }
734 return odm_split_count;
735 }
736
calculate_split_count_and_index(struct pipe_ctx * pipe_ctx,int * split_count,int * split_idx)737 static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx)
738 {
739 *split_count = get_num_odm_splits(pipe_ctx);
740 *split_idx = 0;
741 if (*split_count == 0) {
742 /*Check for mpc split*/
743 struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
744
745 *split_count = get_num_mpc_splits(pipe_ctx);
746 while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
747 (*split_idx)++;
748 split_pipe = split_pipe->top_pipe;
749 }
750 } else {
751 /*Get odm split index*/
752 struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe;
753
754 while (split_pipe) {
755 (*split_idx)++;
756 split_pipe = split_pipe->prev_odm_pipe;
757 }
758 }
759 }
760
761 /*
762 * This is a preliminary vp size calculation to allow us to check taps support.
763 * The result is completely overridden afterwards.
764 */
calculate_viewport_size(struct pipe_ctx * pipe_ctx)765 static void calculate_viewport_size(struct pipe_ctx *pipe_ctx)
766 {
767 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
768
769 data->viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz, data->recout.width));
770 data->viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert, data->recout.height));
771 data->viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz_c, data->recout.width));
772 data->viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert_c, data->recout.height));
773 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
774 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
775 swap(data->viewport.width, data->viewport.height);
776 swap(data->viewport_c.width, data->viewport_c.height);
777 }
778 }
779
calculate_recout(struct pipe_ctx * pipe_ctx)780 static void calculate_recout(struct pipe_ctx *pipe_ctx)
781 {
782 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
783 const struct dc_stream_state *stream = pipe_ctx->stream;
784 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
785 struct rect surf_clip = plane_state->clip_rect;
786 bool split_tb = stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
787 int split_count, split_idx;
788
789 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
790 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
791 split_idx = 0;
792
793 /*
794 * Only the leftmost ODM pipe should be offset by a nonzero distance
795 */
796 if (!pipe_ctx->prev_odm_pipe || split_idx == split_count) {
797 data->recout.x = stream->dst.x;
798 if (stream->src.x < surf_clip.x)
799 data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
800 / stream->src.width;
801 } else
802 data->recout.x = 0;
803
804 if (stream->src.x > surf_clip.x)
805 surf_clip.width -= stream->src.x - surf_clip.x;
806 data->recout.width = surf_clip.width * stream->dst.width / stream->src.width;
807 if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width)
808 data->recout.width = stream->dst.x + stream->dst.width - data->recout.x;
809
810 data->recout.y = stream->dst.y;
811 if (stream->src.y < surf_clip.y)
812 data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height
813 / stream->src.height;
814 else if (stream->src.y > surf_clip.y)
815 surf_clip.height -= stream->src.y - surf_clip.y;
816
817 data->recout.height = surf_clip.height * stream->dst.height / stream->src.height;
818 if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height)
819 data->recout.height = stream->dst.y + stream->dst.height - data->recout.y;
820
821 /* Handle h & v split */
822 if (split_tb) {
823 ASSERT(data->recout.height % 2 == 0);
824 data->recout.height /= 2;
825 } else if (split_count) {
826 if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) {
827 /* extra pixels in the division remainder need to go to pipes after
828 * the extra pixel index minus one(epimo) defined here as:
829 */
830 int epimo = split_count - data->recout.width % (split_count + 1);
831
832 data->recout.x += (data->recout.width / (split_count + 1)) * split_idx;
833 if (split_idx > epimo)
834 data->recout.x += split_idx - epimo - 1;
835 ASSERT(stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE || data->recout.width % 2 == 0);
836 data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
837 } else {
838 /* odm */
839 if (split_idx == split_count) {
840 /* rightmost pipe is the remainder recout */
841 data->recout.width -= data->h_active * split_count - data->recout.x;
842
843 /* ODM combine cases with MPO we can get negative widths */
844 if (data->recout.width < 0)
845 data->recout.width = 0;
846
847 data->recout.x = 0;
848 } else
849 data->recout.width = data->h_active - data->recout.x;
850 }
851 }
852 }
853
calculate_scaling_ratios(struct pipe_ctx * pipe_ctx)854 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
855 {
856 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
857 const struct dc_stream_state *stream = pipe_ctx->stream;
858 struct rect surf_src = plane_state->src_rect;
859 const int in_w = stream->src.width;
860 const int in_h = stream->src.height;
861 const int out_w = stream->dst.width;
862 const int out_h = stream->dst.height;
863
864 /*Swap surf_src height and width since scaling ratios are in recout rotation*/
865 if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
866 pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
867 swap(surf_src.height, surf_src.width);
868
869 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
870 surf_src.width,
871 plane_state->dst_rect.width);
872 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
873 surf_src.height,
874 plane_state->dst_rect.height);
875
876 if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
877 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
878 else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
879 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
880
881 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
882 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
883 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
884 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
885
886 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
887 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
888
889 if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
890 || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
891 pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
892 pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
893 }
894 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
895 pipe_ctx->plane_res.scl_data.ratios.horz, 19);
896 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
897 pipe_ctx->plane_res.scl_data.ratios.vert, 19);
898 pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
899 pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
900 pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
901 pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
902 }
903
904
905 /*
906 * We completely calculate vp offset, size and inits here based entirely on scaling
907 * ratios and recout for pixel perfect pipe combine.
908 */
calculate_init_and_vp(bool flip_scan_dir,int recout_offset_within_recout_full,int recout_size,int src_size,int taps,struct fixed31_32 ratio,struct fixed31_32 * init,int * vp_offset,int * vp_size)909 static void calculate_init_and_vp(
910 bool flip_scan_dir,
911 int recout_offset_within_recout_full,
912 int recout_size,
913 int src_size,
914 int taps,
915 struct fixed31_32 ratio,
916 struct fixed31_32 *init,
917 int *vp_offset,
918 int *vp_size)
919 {
920 struct fixed31_32 temp;
921 int int_part;
922
923 /*
924 * First of the taps starts sampling pixel number <init_int_part> corresponding to recout
925 * pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on.
926 * All following calculations are based on this logic.
927 *
928 * Init calculated according to formula:
929 * init = (scaling_ratio + number_of_taps + 1) / 2
930 * init_bot = init + scaling_ratio
931 * to get pixel perfect combine add the fraction from calculating vp offset
932 */
933 temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full);
934 *vp_offset = dc_fixpt_floor(temp);
935 temp.value &= 0xffffffff;
936 *init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int(
937 dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19);
938 /*
939 * If viewport has non 0 offset and there are more taps than covered by init then
940 * we should decrease the offset and increase init so we are never sampling
941 * outside of viewport.
942 */
943 int_part = dc_fixpt_floor(*init);
944 if (int_part < taps) {
945 int_part = taps - int_part;
946 if (int_part > *vp_offset)
947 int_part = *vp_offset;
948 *vp_offset -= int_part;
949 *init = dc_fixpt_add_int(*init, int_part);
950 }
951 /*
952 * If taps are sampling outside of viewport at end of recout and there are more pixels
953 * available in the surface we should increase the viewport size, regardless set vp to
954 * only what is used.
955 */
956 temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1));
957 *vp_size = dc_fixpt_floor(temp);
958 if (*vp_size + *vp_offset > src_size)
959 *vp_size = src_size - *vp_offset;
960
961 /* We did all the math assuming we are scanning same direction as display does,
962 * however mirror/rotation changes how vp scans vs how it is offset. If scan direction
963 * is flipped we simply need to calculate offset from the other side of plane.
964 * Note that outside of viewport all scaling hardware works in recout space.
965 */
966 if (flip_scan_dir)
967 *vp_offset = src_size - *vp_offset - *vp_size;
968 }
969
calculate_inits_and_viewports(struct pipe_ctx * pipe_ctx)970 static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx)
971 {
972 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
973 const struct dc_stream_state *stream = pipe_ctx->stream;
974 struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
975 struct rect src = plane_state->src_rect;
976 int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
977 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
978 int split_count, split_idx, ro_lb, ro_tb, recout_full_x, recout_full_y;
979 bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
980
981 calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
982 /*
983 * recout full is what the recout would have been if we didnt clip
984 * the source plane at all. We only care about left(ro_lb) and top(ro_tb)
985 * offsets of recout within recout full because those are the directions
986 * we scan from and therefore the only ones that affect inits.
987 */
988 recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x)
989 * stream->dst.width / stream->src.width;
990 recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y)
991 * stream->dst.height / stream->src.height;
992 if (pipe_ctx->prev_odm_pipe && split_idx)
993 ro_lb = data->h_active * split_idx - recout_full_x;
994 else
995 ro_lb = data->recout.x - recout_full_x;
996 ro_tb = data->recout.y - recout_full_y;
997 ASSERT(ro_lb >= 0 && ro_tb >= 0);
998
999 /*
1000 * Work in recout rotation since that requires less transformations
1001 */
1002 get_vp_scan_direction(
1003 plane_state->rotation,
1004 plane_state->horizontal_mirror,
1005 &orthogonal_rotation,
1006 &flip_vert_scan_dir,
1007 &flip_horz_scan_dir);
1008
1009 if (orthogonal_rotation) {
1010 swap(src.width, src.height);
1011 swap(flip_vert_scan_dir, flip_horz_scan_dir);
1012 }
1013
1014 calculate_init_and_vp(
1015 flip_horz_scan_dir,
1016 ro_lb,
1017 data->recout.width,
1018 src.width,
1019 data->taps.h_taps,
1020 data->ratios.horz,
1021 &data->inits.h,
1022 &data->viewport.x,
1023 &data->viewport.width);
1024 calculate_init_and_vp(
1025 flip_horz_scan_dir,
1026 ro_lb,
1027 data->recout.width,
1028 src.width / vpc_div,
1029 data->taps.h_taps_c,
1030 data->ratios.horz_c,
1031 &data->inits.h_c,
1032 &data->viewport_c.x,
1033 &data->viewport_c.width);
1034 calculate_init_and_vp(
1035 flip_vert_scan_dir,
1036 ro_tb,
1037 data->recout.height,
1038 src.height,
1039 data->taps.v_taps,
1040 data->ratios.vert,
1041 &data->inits.v,
1042 &data->viewport.y,
1043 &data->viewport.height);
1044 calculate_init_and_vp(
1045 flip_vert_scan_dir,
1046 ro_tb,
1047 data->recout.height,
1048 src.height / vpc_div,
1049 data->taps.v_taps_c,
1050 data->ratios.vert_c,
1051 &data->inits.v_c,
1052 &data->viewport_c.y,
1053 &data->viewport_c.height);
1054 if (orthogonal_rotation) {
1055 swap(data->viewport.x, data->viewport.y);
1056 swap(data->viewport.width, data->viewport.height);
1057 swap(data->viewport_c.x, data->viewport_c.y);
1058 swap(data->viewport_c.width, data->viewport_c.height);
1059 }
1060 data->viewport.x += src.x;
1061 data->viewport.y += src.y;
1062 ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0);
1063 data->viewport_c.x += src.x / vpc_div;
1064 data->viewport_c.y += src.y / vpc_div;
1065 }
1066
resource_build_scaling_params(struct pipe_ctx * pipe_ctx)1067 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
1068 {
1069 const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1070 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
1071 bool res = false;
1072 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1073
1074 /* Invalid input */
1075 if (!plane_state->dst_rect.width ||
1076 !plane_state->dst_rect.height ||
1077 !plane_state->src_rect.width ||
1078 !plane_state->src_rect.height) {
1079 ASSERT(0);
1080 return false;
1081 }
1082
1083 pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
1084 pipe_ctx->plane_state->format);
1085
1086 /* Timing borders are part of vactive that we are also supposed to skip in addition
1087 * to any stream dst offset. Since dm logic assumes dst is in addressable
1088 * space we need to add the left and top borders to dst offsets temporarily.
1089 * TODO: fix in DM, stream dst is supposed to be in vactive
1090 */
1091 pipe_ctx->stream->dst.x += timing->h_border_left;
1092 pipe_ctx->stream->dst.y += timing->v_border_top;
1093
1094 /* Calculate H and V active size */
1095 pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable +
1096 timing->h_border_left + timing->h_border_right;
1097 pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable +
1098 timing->v_border_top + timing->v_border_bottom;
1099 if (pipe_ctx->next_odm_pipe || pipe_ctx->prev_odm_pipe)
1100 pipe_ctx->plane_res.scl_data.h_active /= get_num_odm_splits(pipe_ctx) + 1;
1101
1102 /* depends on h_active */
1103 calculate_recout(pipe_ctx);
1104 /* depends on pixel format */
1105 calculate_scaling_ratios(pipe_ctx);
1106 /* depends on scaling ratios and recout, does not calculate offset yet */
1107 calculate_viewport_size(pipe_ctx);
1108
1109 /* Stopgap for validation of ODM + MPO on one side of screen case */
1110 if (pipe_ctx->plane_res.scl_data.viewport.height < 1 ||
1111 pipe_ctx->plane_res.scl_data.viewport.width < 1)
1112 return false;
1113
1114 /*
1115 * LB calculations depend on vp size, h/v_active and scaling ratios
1116 * Setting line buffer pixel depth to 24bpp yields banding
1117 * on certain displays, such as the Sharp 4k. 36bpp is needed
1118 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and
1119 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc
1120 * precision on DCN display engines, but apparently not for DCE, as
1121 * far as testing on DCE-11.2 and DCE-8 showed. Various DCE parts have
1122 * problems: Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
1123 * neither do DCE-8 at 4k resolution, or DCE-11.2 (broken identify pixel
1124 * passthrough). Therefore only use 36 bpp on DCN where it is actually needed.
1125 */
1126 if (plane_state->ctx->dce_version > DCE_VERSION_MAX)
1127 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
1128 else
1129 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1130
1131 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
1132
1133 if (pipe_ctx->plane_res.xfm != NULL)
1134 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1135 pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1136
1137 if (pipe_ctx->plane_res.dpp != NULL)
1138 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1139 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1140
1141
1142 if (!res) {
1143 /* Try 24 bpp linebuffer */
1144 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
1145
1146 if (pipe_ctx->plane_res.xfm != NULL)
1147 res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1148 pipe_ctx->plane_res.xfm,
1149 &pipe_ctx->plane_res.scl_data,
1150 &plane_state->scaling_quality);
1151
1152 if (pipe_ctx->plane_res.dpp != NULL)
1153 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1154 pipe_ctx->plane_res.dpp,
1155 &pipe_ctx->plane_res.scl_data,
1156 &plane_state->scaling_quality);
1157 }
1158
1159 /*
1160 * Depends on recout, scaling ratios, h_active and taps
1161 * May need to re-check lb size after this in some obscure scenario
1162 */
1163 if (res)
1164 calculate_inits_and_viewports(pipe_ctx);
1165
1166 /*
1167 * Handle side by side and top bottom 3d recout offsets after vp calculation
1168 * since 3d is special and needs to calculate vp as if there is no recout offset
1169 * This may break with rotation, good thing we aren't mixing hw rotation and 3d
1170 */
1171 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) {
1172 ASSERT(plane_state->rotation == ROTATION_ANGLE_0 ||
1173 (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM &&
1174 pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE));
1175 if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
1176 pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;
1177 else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
1178 pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;
1179 }
1180
1181 if (!pipe_ctx->stream->ctx->dc->config.enable_windowed_mpo_odm) {
1182 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE ||
1183 pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
1184 res = false;
1185 } else {
1186 /* Clamp minimum viewport size */
1187 if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE)
1188 pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE;
1189 if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
1190 pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;
1191 }
1192
1193 DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d Recout: height:%d width:%d x:%d y:%d HACTIVE:%d VACTIVE:%d\n"
1194 "src_rect: height:%d width:%d x:%d y:%d dst_rect: height:%d width:%d x:%d y:%d clip_rect: height:%d width:%d x:%d y:%d\n",
1195 __func__,
1196 pipe_ctx->pipe_idx,
1197 pipe_ctx->plane_res.scl_data.viewport.height,
1198 pipe_ctx->plane_res.scl_data.viewport.width,
1199 pipe_ctx->plane_res.scl_data.viewport.x,
1200 pipe_ctx->plane_res.scl_data.viewport.y,
1201 pipe_ctx->plane_res.scl_data.recout.height,
1202 pipe_ctx->plane_res.scl_data.recout.width,
1203 pipe_ctx->plane_res.scl_data.recout.x,
1204 pipe_ctx->plane_res.scl_data.recout.y,
1205 pipe_ctx->plane_res.scl_data.h_active,
1206 pipe_ctx->plane_res.scl_data.v_active,
1207 plane_state->src_rect.height,
1208 plane_state->src_rect.width,
1209 plane_state->src_rect.x,
1210 plane_state->src_rect.y,
1211 plane_state->dst_rect.height,
1212 plane_state->dst_rect.width,
1213 plane_state->dst_rect.x,
1214 plane_state->dst_rect.y,
1215 plane_state->clip_rect.height,
1216 plane_state->clip_rect.width,
1217 plane_state->clip_rect.x,
1218 plane_state->clip_rect.y);
1219
1220 pipe_ctx->stream->dst.x -= timing->h_border_left;
1221 pipe_ctx->stream->dst.y -= timing->v_border_top;
1222
1223 return res;
1224 }
1225
1226
resource_build_scaling_params_for_context(const struct dc * dc,struct dc_state * context)1227 enum dc_status resource_build_scaling_params_for_context(
1228 const struct dc *dc,
1229 struct dc_state *context)
1230 {
1231 int i;
1232
1233 for (i = 0; i < MAX_PIPES; i++) {
1234 if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
1235 context->res_ctx.pipe_ctx[i].stream != NULL)
1236 if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
1237 return DC_FAIL_SCALING;
1238 }
1239
1240 return DC_OK;
1241 }
1242
find_idle_secondary_pipe(struct resource_context * res_ctx,const struct resource_pool * pool,const struct pipe_ctx * primary_pipe)1243 struct pipe_ctx *find_idle_secondary_pipe(
1244 struct resource_context *res_ctx,
1245 const struct resource_pool *pool,
1246 const struct pipe_ctx *primary_pipe)
1247 {
1248 int i;
1249 struct pipe_ctx *secondary_pipe = NULL;
1250
1251 /*
1252 * We add a preferred pipe mapping to avoid the chance that
1253 * MPCCs already in use will need to be reassigned to other trees.
1254 * For example, if we went with the strict, assign backwards logic:
1255 *
1256 * (State 1)
1257 * Display A on, no surface, top pipe = 0
1258 * Display B on, no surface, top pipe = 1
1259 *
1260 * (State 2)
1261 * Display A on, no surface, top pipe = 0
1262 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1263 *
1264 * (State 3)
1265 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1266 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1267 *
1268 * The state 2->3 transition requires remapping MPCC 5 from display B
1269 * to display A.
1270 *
1271 * However, with the preferred pipe logic, state 2 would look like:
1272 *
1273 * (State 2)
1274 * Display A on, no surface, top pipe = 0
1275 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1276 *
1277 * This would then cause 2->3 to not require remapping any MPCCs.
1278 */
1279 if (primary_pipe) {
1280 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1281 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1282 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1283 secondary_pipe->pipe_idx = preferred_pipe_idx;
1284 }
1285 }
1286
1287 /*
1288 * search backwards for the second pipe to keep pipe
1289 * assignment more consistent
1290 */
1291 if (!secondary_pipe)
1292 for (i = pool->pipe_count - 1; i >= 0; i--) {
1293 if (res_ctx->pipe_ctx[i].stream == NULL) {
1294 secondary_pipe = &res_ctx->pipe_ctx[i];
1295 secondary_pipe->pipe_idx = i;
1296 break;
1297 }
1298 }
1299
1300 return secondary_pipe;
1301 }
1302
resource_get_head_pipe_for_stream(struct resource_context * res_ctx,struct dc_stream_state * stream)1303 struct pipe_ctx *resource_get_head_pipe_for_stream(
1304 struct resource_context *res_ctx,
1305 struct dc_stream_state *stream)
1306 {
1307 int i;
1308
1309 for (i = 0; i < MAX_PIPES; i++) {
1310 if (res_ctx->pipe_ctx[i].stream == stream
1311 && !res_ctx->pipe_ctx[i].top_pipe
1312 && !res_ctx->pipe_ctx[i].prev_odm_pipe)
1313 return &res_ctx->pipe_ctx[i];
1314 }
1315 return NULL;
1316 }
1317
resource_get_tail_pipe(struct resource_context * res_ctx,struct pipe_ctx * head_pipe)1318 static struct pipe_ctx *resource_get_tail_pipe(
1319 struct resource_context *res_ctx,
1320 struct pipe_ctx *head_pipe)
1321 {
1322 struct pipe_ctx *tail_pipe;
1323
1324 tail_pipe = head_pipe->bottom_pipe;
1325
1326 while (tail_pipe) {
1327 head_pipe = tail_pipe;
1328 tail_pipe = tail_pipe->bottom_pipe;
1329 }
1330
1331 return head_pipe;
1332 }
1333
1334 /*
1335 * A free_pipe for a stream is defined here as a pipe
1336 * that has no surface attached yet
1337 */
acquire_free_pipe_for_head(struct dc_state * context,const struct resource_pool * pool,struct pipe_ctx * head_pipe)1338 static struct pipe_ctx *acquire_free_pipe_for_head(
1339 struct dc_state *context,
1340 const struct resource_pool *pool,
1341 struct pipe_ctx *head_pipe)
1342 {
1343 int i;
1344 struct resource_context *res_ctx = &context->res_ctx;
1345
1346 if (!head_pipe->plane_state)
1347 return head_pipe;
1348
1349 /* Re-use pipe already acquired for this stream if available*/
1350 for (i = pool->pipe_count - 1; i >= 0; i--) {
1351 if (res_ctx->pipe_ctx[i].stream == head_pipe->stream &&
1352 !res_ctx->pipe_ctx[i].plane_state) {
1353 return &res_ctx->pipe_ctx[i];
1354 }
1355 }
1356
1357 /*
1358 * At this point we have no re-useable pipe for this stream and we need
1359 * to acquire an idle one to satisfy the request
1360 */
1361
1362 if (!pool->funcs->acquire_idle_pipe_for_layer)
1363 return NULL;
1364
1365 return pool->funcs->acquire_idle_pipe_for_layer(context, pool, head_pipe->stream);
1366 }
1367
acquire_first_split_pipe(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)1368 static int acquire_first_split_pipe(
1369 struct resource_context *res_ctx,
1370 const struct resource_pool *pool,
1371 struct dc_stream_state *stream)
1372 {
1373 int i;
1374
1375 for (i = 0; i < pool->pipe_count; i++) {
1376 struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1377
1378 if (split_pipe->top_pipe &&
1379 split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1380 split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1381 if (split_pipe->bottom_pipe)
1382 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1383
1384 if (split_pipe->top_pipe->plane_state)
1385 resource_build_scaling_params(split_pipe->top_pipe);
1386
1387 memset(split_pipe, 0, sizeof(*split_pipe));
1388 split_pipe->stream_res.tg = pool->timing_generators[i];
1389 split_pipe->plane_res.hubp = pool->hubps[i];
1390 split_pipe->plane_res.ipp = pool->ipps[i];
1391 split_pipe->plane_res.dpp = pool->dpps[i];
1392 split_pipe->stream_res.opp = pool->opps[i];
1393 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1394 split_pipe->pipe_idx = i;
1395
1396 split_pipe->stream = stream;
1397 return i;
1398 }
1399 }
1400 return -1;
1401 }
1402
dc_add_plane_to_context(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * plane_state,struct dc_state * context)1403 bool dc_add_plane_to_context(
1404 const struct dc *dc,
1405 struct dc_stream_state *stream,
1406 struct dc_plane_state *plane_state,
1407 struct dc_state *context)
1408 {
1409 int i;
1410 struct resource_pool *pool = dc->res_pool;
1411 struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe;
1412 struct dc_stream_status *stream_status = NULL;
1413
1414 for (i = 0; i < context->stream_count; i++)
1415 if (context->streams[i] == stream) {
1416 stream_status = &context->stream_status[i];
1417 break;
1418 }
1419 if (stream_status == NULL) {
1420 dm_error("Existing stream not found; failed to attach surface!\n");
1421 return false;
1422 }
1423
1424
1425 if (stream_status->plane_count == MAX_SURFACE_NUM) {
1426 dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1427 plane_state, MAX_SURFACE_NUM);
1428 return false;
1429 }
1430
1431 head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1432
1433 if (!head_pipe) {
1434 dm_error("Head pipe not found for stream_state %p !\n", stream);
1435 return false;
1436 }
1437
1438 /* retain new surface, but only once per stream */
1439 dc_plane_state_retain(plane_state);
1440
1441 while (head_pipe) {
1442 free_pipe = acquire_free_pipe_for_head(context, pool, head_pipe);
1443
1444 if (!free_pipe) {
1445 int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
1446 if (pipe_idx >= 0)
1447 free_pipe = &context->res_ctx.pipe_ctx[pipe_idx];
1448 }
1449
1450 if (!free_pipe) {
1451 dc_plane_state_release(plane_state);
1452 return false;
1453 }
1454
1455 free_pipe->plane_state = plane_state;
1456
1457 if (head_pipe != free_pipe) {
1458 tail_pipe = resource_get_tail_pipe(&context->res_ctx, head_pipe);
1459 ASSERT(tail_pipe);
1460 free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
1461 free_pipe->stream_res.abm = tail_pipe->stream_res.abm;
1462 free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
1463 free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc;
1464 free_pipe->stream_res.audio = tail_pipe->stream_res.audio;
1465 free_pipe->clock_source = tail_pipe->clock_source;
1466 free_pipe->top_pipe = tail_pipe;
1467 tail_pipe->bottom_pipe = free_pipe;
1468 if (!free_pipe->next_odm_pipe && tail_pipe->next_odm_pipe && tail_pipe->next_odm_pipe->bottom_pipe) {
1469 free_pipe->next_odm_pipe = tail_pipe->next_odm_pipe->bottom_pipe;
1470 tail_pipe->next_odm_pipe->bottom_pipe->prev_odm_pipe = free_pipe;
1471 }
1472 if (!free_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe && tail_pipe->prev_odm_pipe->bottom_pipe) {
1473 free_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
1474 tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = free_pipe;
1475 }
1476 }
1477 head_pipe = head_pipe->next_odm_pipe;
1478 }
1479 /* assign new surfaces*/
1480 stream_status->plane_states[stream_status->plane_count] = plane_state;
1481
1482 stream_status->plane_count++;
1483
1484 return true;
1485 }
1486
dc_remove_plane_from_context(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * plane_state,struct dc_state * context)1487 bool dc_remove_plane_from_context(
1488 const struct dc *dc,
1489 struct dc_stream_state *stream,
1490 struct dc_plane_state *plane_state,
1491 struct dc_state *context)
1492 {
1493 int i;
1494 struct dc_stream_status *stream_status = NULL;
1495 struct resource_pool *pool = dc->res_pool;
1496
1497 for (i = 0; i < context->stream_count; i++)
1498 if (context->streams[i] == stream) {
1499 stream_status = &context->stream_status[i];
1500 break;
1501 }
1502
1503 if (stream_status == NULL) {
1504 dm_error("Existing stream not found; failed to remove plane.\n");
1505 return false;
1506 }
1507
1508 /* release pipe for plane*/
1509 for (i = pool->pipe_count - 1; i >= 0; i--) {
1510 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1511
1512 if (pipe_ctx->plane_state == plane_state) {
1513 if (pipe_ctx->top_pipe)
1514 pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1515
1516 /* Second condition is to avoid setting NULL to top pipe
1517 * of tail pipe making it look like head pipe in subsequent
1518 * deletes
1519 */
1520 if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1521 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1522
1523 /*
1524 * For head pipe detach surfaces from pipe for tail
1525 * pipe just zero it out
1526 */
1527 if (!pipe_ctx->top_pipe)
1528 pipe_ctx->plane_state = NULL;
1529 else
1530 memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1531 }
1532 }
1533
1534
1535 for (i = 0; i < stream_status->plane_count; i++) {
1536 if (stream_status->plane_states[i] == plane_state) {
1537
1538 dc_plane_state_release(stream_status->plane_states[i]);
1539 break;
1540 }
1541 }
1542
1543 if (i == stream_status->plane_count) {
1544 dm_error("Existing plane_state not found; failed to detach it!\n");
1545 return false;
1546 }
1547
1548 stream_status->plane_count--;
1549
1550 /* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
1551 for (; i < stream_status->plane_count; i++)
1552 stream_status->plane_states[i] = stream_status->plane_states[i + 1];
1553
1554 stream_status->plane_states[stream_status->plane_count] = NULL;
1555
1556 return true;
1557 }
1558
dc_rem_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,struct dc_state * context)1559 bool dc_rem_all_planes_for_stream(
1560 const struct dc *dc,
1561 struct dc_stream_state *stream,
1562 struct dc_state *context)
1563 {
1564 int i, old_plane_count;
1565 struct dc_stream_status *stream_status = NULL;
1566 struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
1567
1568 for (i = 0; i < context->stream_count; i++)
1569 if (context->streams[i] == stream) {
1570 stream_status = &context->stream_status[i];
1571 break;
1572 }
1573
1574 if (stream_status == NULL) {
1575 dm_error("Existing stream %p not found!\n", stream);
1576 return false;
1577 }
1578
1579 old_plane_count = stream_status->plane_count;
1580
1581 for (i = 0; i < old_plane_count; i++)
1582 del_planes[i] = stream_status->plane_states[i];
1583
1584 for (i = 0; i < old_plane_count; i++)
1585 if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
1586 return false;
1587
1588 return true;
1589 }
1590
add_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,const struct dc_validation_set set[],int set_count,struct dc_state * context)1591 static bool add_all_planes_for_stream(
1592 const struct dc *dc,
1593 struct dc_stream_state *stream,
1594 const struct dc_validation_set set[],
1595 int set_count,
1596 struct dc_state *context)
1597 {
1598 int i, j;
1599
1600 for (i = 0; i < set_count; i++)
1601 if (set[i].stream == stream)
1602 break;
1603
1604 if (i == set_count) {
1605 dm_error("Stream %p not found in set!\n", stream);
1606 return false;
1607 }
1608
1609 for (j = 0; j < set[i].plane_count; j++)
1610 if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
1611 return false;
1612
1613 return true;
1614 }
1615
dc_add_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * const * plane_states,int plane_count,struct dc_state * context)1616 bool dc_add_all_planes_for_stream(
1617 const struct dc *dc,
1618 struct dc_stream_state *stream,
1619 struct dc_plane_state * const *plane_states,
1620 int plane_count,
1621 struct dc_state *context)
1622 {
1623 struct dc_validation_set set;
1624 int i;
1625
1626 set.stream = stream;
1627 set.plane_count = plane_count;
1628
1629 for (i = 0; i < plane_count; i++)
1630 set.plane_states[i] = plane_states[i];
1631
1632 return add_all_planes_for_stream(dc, stream, &set, 1, context);
1633 }
1634
is_timing_changed(struct dc_stream_state * cur_stream,struct dc_stream_state * new_stream)1635 bool is_timing_changed(struct dc_stream_state *cur_stream,
1636 struct dc_stream_state *new_stream)
1637 {
1638 if (cur_stream == NULL)
1639 return true;
1640
1641 /* If output color space is changed, need to reprogram info frames */
1642 if (cur_stream->output_color_space != new_stream->output_color_space)
1643 return true;
1644
1645 return memcmp(
1646 &cur_stream->timing,
1647 &new_stream->timing,
1648 sizeof(struct dc_crtc_timing)) != 0;
1649 }
1650
are_stream_backends_same(struct dc_stream_state * stream_a,struct dc_stream_state * stream_b)1651 static bool are_stream_backends_same(
1652 struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
1653 {
1654 if (stream_a == stream_b)
1655 return true;
1656
1657 if (stream_a == NULL || stream_b == NULL)
1658 return false;
1659
1660 if (is_timing_changed(stream_a, stream_b))
1661 return false;
1662
1663 if (stream_a->signal != stream_b->signal)
1664 return false;
1665
1666 if (stream_a->dpms_off != stream_b->dpms_off)
1667 return false;
1668
1669 return true;
1670 }
1671
1672 /*
1673 * dc_is_stream_unchanged() - Compare two stream states for equivalence.
1674 *
1675 * Checks if there a difference between the two states
1676 * that would require a mode change.
1677 *
1678 * Does not compare cursor position or attributes.
1679 */
dc_is_stream_unchanged(struct dc_stream_state * old_stream,struct dc_stream_state * stream)1680 bool dc_is_stream_unchanged(
1681 struct dc_stream_state *old_stream, struct dc_stream_state *stream)
1682 {
1683
1684 if (!are_stream_backends_same(old_stream, stream))
1685 return false;
1686
1687 if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
1688 return false;
1689
1690 /*compare audio info*/
1691 if (memcmp(&old_stream->audio_info, &stream->audio_info, sizeof(stream->audio_info)) != 0)
1692 return false;
1693
1694 return true;
1695 }
1696
1697 /*
1698 * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
1699 */
dc_is_stream_scaling_unchanged(struct dc_stream_state * old_stream,struct dc_stream_state * stream)1700 bool dc_is_stream_scaling_unchanged(struct dc_stream_state *old_stream,
1701 struct dc_stream_state *stream)
1702 {
1703 if (old_stream == stream)
1704 return true;
1705
1706 if (old_stream == NULL || stream == NULL)
1707 return false;
1708
1709 if (memcmp(&old_stream->src,
1710 &stream->src,
1711 sizeof(struct rect)) != 0)
1712 return false;
1713
1714 if (memcmp(&old_stream->dst,
1715 &stream->dst,
1716 sizeof(struct rect)) != 0)
1717 return false;
1718
1719 return true;
1720 }
1721
update_stream_engine_usage(struct resource_context * res_ctx,const struct resource_pool * pool,struct stream_encoder * stream_enc,bool acquired)1722 static void update_stream_engine_usage(
1723 struct resource_context *res_ctx,
1724 const struct resource_pool *pool,
1725 struct stream_encoder *stream_enc,
1726 bool acquired)
1727 {
1728 int i;
1729
1730 for (i = 0; i < pool->stream_enc_count; i++) {
1731 if (pool->stream_enc[i] == stream_enc)
1732 res_ctx->is_stream_enc_acquired[i] = acquired;
1733 }
1734 }
1735
update_hpo_dp_stream_engine_usage(struct resource_context * res_ctx,const struct resource_pool * pool,struct hpo_dp_stream_encoder * hpo_dp_stream_enc,bool acquired)1736 static void update_hpo_dp_stream_engine_usage(
1737 struct resource_context *res_ctx,
1738 const struct resource_pool *pool,
1739 struct hpo_dp_stream_encoder *hpo_dp_stream_enc,
1740 bool acquired)
1741 {
1742 int i;
1743
1744 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
1745 if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc)
1746 res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired;
1747 }
1748 }
1749
find_acquired_hpo_dp_link_enc_for_link(const struct resource_context * res_ctx,const struct dc_link * link)1750 static inline int find_acquired_hpo_dp_link_enc_for_link(
1751 const struct resource_context *res_ctx,
1752 const struct dc_link *link)
1753 {
1754 int i;
1755
1756 for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++)
1757 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] > 0 &&
1758 res_ctx->hpo_dp_link_enc_to_link_idx[i] == link->link_index)
1759 return i;
1760
1761 return -1;
1762 }
1763
find_free_hpo_dp_link_enc(const struct resource_context * res_ctx,const struct resource_pool * pool)1764 static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx,
1765 const struct resource_pool *pool)
1766 {
1767 int i;
1768
1769 for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++)
1770 if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0)
1771 break;
1772
1773 return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) &&
1774 i < pool->hpo_dp_link_enc_count) ? i : -1;
1775 }
1776
acquire_hpo_dp_link_enc(struct resource_context * res_ctx,unsigned int link_index,int enc_index)1777 static inline void acquire_hpo_dp_link_enc(
1778 struct resource_context *res_ctx,
1779 unsigned int link_index,
1780 int enc_index)
1781 {
1782 res_ctx->hpo_dp_link_enc_to_link_idx[enc_index] = link_index;
1783 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] = 1;
1784 }
1785
retain_hpo_dp_link_enc(struct resource_context * res_ctx,int enc_index)1786 static inline void retain_hpo_dp_link_enc(
1787 struct resource_context *res_ctx,
1788 int enc_index)
1789 {
1790 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++;
1791 }
1792
release_hpo_dp_link_enc(struct resource_context * res_ctx,int enc_index)1793 static inline void release_hpo_dp_link_enc(
1794 struct resource_context *res_ctx,
1795 int enc_index)
1796 {
1797 ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0);
1798 res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--;
1799 }
1800
add_hpo_dp_link_enc_to_ctx(struct resource_context * res_ctx,const struct resource_pool * pool,struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream)1801 static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
1802 const struct resource_pool *pool,
1803 struct pipe_ctx *pipe_ctx,
1804 struct dc_stream_state *stream)
1805 {
1806 int enc_index;
1807
1808 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
1809
1810 if (enc_index >= 0) {
1811 retain_hpo_dp_link_enc(res_ctx, enc_index);
1812 } else {
1813 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
1814 if (enc_index >= 0)
1815 acquire_hpo_dp_link_enc(res_ctx, stream->link->link_index, enc_index);
1816 }
1817
1818 if (enc_index >= 0)
1819 pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
1820
1821 return pipe_ctx->link_res.hpo_dp_link_enc != NULL;
1822 }
1823
remove_hpo_dp_link_enc_from_ctx(struct resource_context * res_ctx,struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream)1824 static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
1825 struct pipe_ctx *pipe_ctx,
1826 struct dc_stream_state *stream)
1827 {
1828 int enc_index;
1829
1830 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
1831
1832 if (enc_index >= 0) {
1833 release_hpo_dp_link_enc(res_ctx, enc_index);
1834 pipe_ctx->link_res.hpo_dp_link_enc = NULL;
1835 }
1836 }
1837
1838 /* TODO: release audio object */
update_audio_usage(struct resource_context * res_ctx,const struct resource_pool * pool,struct audio * audio,bool acquired)1839 void update_audio_usage(
1840 struct resource_context *res_ctx,
1841 const struct resource_pool *pool,
1842 struct audio *audio,
1843 bool acquired)
1844 {
1845 int i;
1846 for (i = 0; i < pool->audio_count; i++) {
1847 if (pool->audios[i] == audio)
1848 res_ctx->is_audio_acquired[i] = acquired;
1849 }
1850 }
1851
acquire_first_free_pipe(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)1852 static int acquire_first_free_pipe(
1853 struct resource_context *res_ctx,
1854 const struct resource_pool *pool,
1855 struct dc_stream_state *stream)
1856 {
1857 int i;
1858
1859 for (i = 0; i < pool->pipe_count; i++) {
1860 if (!res_ctx->pipe_ctx[i].stream) {
1861 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
1862
1863 pipe_ctx->stream_res.tg = pool->timing_generators[i];
1864 pipe_ctx->plane_res.mi = pool->mis[i];
1865 pipe_ctx->plane_res.hubp = pool->hubps[i];
1866 pipe_ctx->plane_res.ipp = pool->ipps[i];
1867 pipe_ctx->plane_res.xfm = pool->transforms[i];
1868 pipe_ctx->plane_res.dpp = pool->dpps[i];
1869 pipe_ctx->stream_res.opp = pool->opps[i];
1870 if (pool->dpps[i])
1871 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
1872 pipe_ctx->pipe_idx = i;
1873
1874
1875 pipe_ctx->stream = stream;
1876 return i;
1877 }
1878 }
1879 return -1;
1880 }
1881
find_first_free_match_hpo_dp_stream_enc_for_link(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)1882 static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for_link(
1883 struct resource_context *res_ctx,
1884 const struct resource_pool *pool,
1885 struct dc_stream_state *stream)
1886 {
1887 int i;
1888
1889 for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
1890 if (!res_ctx->is_hpo_dp_stream_enc_acquired[i] &&
1891 pool->hpo_dp_stream_enc[i]) {
1892
1893 return pool->hpo_dp_stream_enc[i];
1894 }
1895 }
1896
1897 return NULL;
1898 }
1899
find_first_free_audio(struct resource_context * res_ctx,const struct resource_pool * pool,enum engine_id id,enum dce_version dc_version)1900 static struct audio *find_first_free_audio(
1901 struct resource_context *res_ctx,
1902 const struct resource_pool *pool,
1903 enum engine_id id,
1904 enum dce_version dc_version)
1905 {
1906 int i, available_audio_count;
1907
1908 available_audio_count = pool->audio_count;
1909
1910 for (i = 0; i < available_audio_count; i++) {
1911 if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
1912 /*we have enough audio endpoint, find the matching inst*/
1913 if (id != i)
1914 continue;
1915 return pool->audios[i];
1916 }
1917 }
1918
1919 /* use engine id to find free audio */
1920 if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
1921 return pool->audios[id];
1922 }
1923 /*not found the matching one, first come first serve*/
1924 for (i = 0; i < available_audio_count; i++) {
1925 if (res_ctx->is_audio_acquired[i] == false) {
1926 return pool->audios[i];
1927 }
1928 }
1929 return NULL;
1930 }
1931
1932 /*
1933 * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
1934 */
dc_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * stream)1935 enum dc_status dc_add_stream_to_ctx(
1936 struct dc *dc,
1937 struct dc_state *new_ctx,
1938 struct dc_stream_state *stream)
1939 {
1940 enum dc_status res;
1941 DC_LOGGER_INIT(dc->ctx->logger);
1942
1943 if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
1944 DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
1945 return DC_ERROR_UNEXPECTED;
1946 }
1947
1948 new_ctx->streams[new_ctx->stream_count] = stream;
1949 dc_stream_retain(stream);
1950 new_ctx->stream_count++;
1951
1952 res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
1953 if (res != DC_OK)
1954 DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
1955
1956 return res;
1957 }
1958
1959 /*
1960 * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
1961 */
dc_remove_stream_from_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * stream)1962 enum dc_status dc_remove_stream_from_ctx(
1963 struct dc *dc,
1964 struct dc_state *new_ctx,
1965 struct dc_stream_state *stream)
1966 {
1967 int i;
1968 struct dc_context *dc_ctx = dc->ctx;
1969 struct pipe_ctx *del_pipe = resource_get_head_pipe_for_stream(&new_ctx->res_ctx, stream);
1970 struct pipe_ctx *odm_pipe;
1971
1972 if (!del_pipe) {
1973 DC_ERROR("Pipe not found for stream %p !\n", stream);
1974 return DC_ERROR_UNEXPECTED;
1975 }
1976
1977 odm_pipe = del_pipe->next_odm_pipe;
1978
1979 /* Release primary pipe */
1980 ASSERT(del_pipe->stream_res.stream_enc);
1981 update_stream_engine_usage(
1982 &new_ctx->res_ctx,
1983 dc->res_pool,
1984 del_pipe->stream_res.stream_enc,
1985 false);
1986 if (is_dp_128b_132b_signal(del_pipe)) {
1987 update_hpo_dp_stream_engine_usage(
1988 &new_ctx->res_ctx, dc->res_pool,
1989 del_pipe->stream_res.hpo_dp_stream_enc,
1990 false);
1991 remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
1992 }
1993
1994 if (del_pipe->stream_res.audio)
1995 update_audio_usage(
1996 &new_ctx->res_ctx,
1997 dc->res_pool,
1998 del_pipe->stream_res.audio,
1999 false);
2000
2001 resource_unreference_clock_source(&new_ctx->res_ctx,
2002 dc->res_pool,
2003 del_pipe->clock_source);
2004
2005 if (dc->res_pool->funcs->remove_stream_from_ctx)
2006 dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
2007
2008 while (odm_pipe) {
2009 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2010
2011 memset(odm_pipe, 0, sizeof(*odm_pipe));
2012 odm_pipe = next_odm_pipe;
2013 }
2014 memset(del_pipe, 0, sizeof(*del_pipe));
2015
2016 for (i = 0; i < new_ctx->stream_count; i++)
2017 if (new_ctx->streams[i] == stream)
2018 break;
2019
2020 if (new_ctx->streams[i] != stream) {
2021 DC_ERROR("Context doesn't have stream %p !\n", stream);
2022 return DC_ERROR_UNEXPECTED;
2023 }
2024
2025 dc_stream_release(new_ctx->streams[i]);
2026 new_ctx->stream_count--;
2027
2028 /* Trim back arrays */
2029 for (; i < new_ctx->stream_count; i++) {
2030 new_ctx->streams[i] = new_ctx->streams[i + 1];
2031 new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
2032 }
2033
2034 new_ctx->streams[new_ctx->stream_count] = NULL;
2035 memset(
2036 &new_ctx->stream_status[new_ctx->stream_count],
2037 0,
2038 sizeof(new_ctx->stream_status[0]));
2039
2040 return DC_OK;
2041 }
2042
find_pll_sharable_stream(struct dc_stream_state * stream_needs_pll,struct dc_state * context)2043 static struct dc_stream_state *find_pll_sharable_stream(
2044 struct dc_stream_state *stream_needs_pll,
2045 struct dc_state *context)
2046 {
2047 int i;
2048
2049 for (i = 0; i < context->stream_count; i++) {
2050 struct dc_stream_state *stream_has_pll = context->streams[i];
2051
2052 /* We are looking for non dp, non virtual stream */
2053 if (resource_are_streams_timing_synchronizable(
2054 stream_needs_pll, stream_has_pll)
2055 && !dc_is_dp_signal(stream_has_pll->signal)
2056 && stream_has_pll->link->connector_signal
2057 != SIGNAL_TYPE_VIRTUAL)
2058 return stream_has_pll;
2059
2060 }
2061
2062 return NULL;
2063 }
2064
get_norm_pix_clk(const struct dc_crtc_timing * timing)2065 static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
2066 {
2067 uint32_t pix_clk = timing->pix_clk_100hz;
2068 uint32_t normalized_pix_clk = pix_clk;
2069
2070 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2071 pix_clk /= 2;
2072 if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
2073 switch (timing->display_color_depth) {
2074 case COLOR_DEPTH_666:
2075 case COLOR_DEPTH_888:
2076 normalized_pix_clk = pix_clk;
2077 break;
2078 case COLOR_DEPTH_101010:
2079 normalized_pix_clk = (pix_clk * 30) / 24;
2080 break;
2081 case COLOR_DEPTH_121212:
2082 normalized_pix_clk = (pix_clk * 36) / 24;
2083 break;
2084 case COLOR_DEPTH_161616:
2085 normalized_pix_clk = (pix_clk * 48) / 24;
2086 break;
2087 default:
2088 ASSERT(0);
2089 break;
2090 }
2091 }
2092 return normalized_pix_clk;
2093 }
2094
calculate_phy_pix_clks(struct dc_stream_state * stream)2095 static void calculate_phy_pix_clks(struct dc_stream_state *stream)
2096 {
2097 /* update actual pixel clock on all streams */
2098 if (dc_is_hdmi_signal(stream->signal))
2099 stream->phy_pix_clk = get_norm_pix_clk(
2100 &stream->timing) / 10;
2101 else
2102 stream->phy_pix_clk =
2103 stream->timing.pix_clk_100hz / 10;
2104
2105 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2106 stream->phy_pix_clk *= 2;
2107 }
2108
acquire_resource_from_hw_enabled_state(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)2109 static int acquire_resource_from_hw_enabled_state(
2110 struct resource_context *res_ctx,
2111 const struct resource_pool *pool,
2112 struct dc_stream_state *stream)
2113 {
2114 struct dc_link *link = stream->link;
2115 unsigned int i, inst, tg_inst = 0;
2116 uint32_t numPipes = 1;
2117 uint32_t id_src[4] = {0};
2118
2119 /* Check for enabled DIG to identify enabled display */
2120 if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
2121 return -1;
2122
2123 inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
2124
2125 if (inst == ENGINE_ID_UNKNOWN)
2126 return -1;
2127
2128 for (i = 0; i < pool->stream_enc_count; i++) {
2129 if (pool->stream_enc[i]->id == inst) {
2130 tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
2131 pool->stream_enc[i]);
2132 break;
2133 }
2134 }
2135
2136 // tg_inst not found
2137 if (i == pool->stream_enc_count)
2138 return -1;
2139
2140 if (tg_inst >= pool->timing_generator_count)
2141 return -1;
2142
2143 if (!res_ctx->pipe_ctx[tg_inst].stream) {
2144 struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
2145
2146 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
2147 id_src[0] = tg_inst;
2148
2149 if (pipe_ctx->stream_res.tg->funcs->get_optc_source)
2150 pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,
2151 &numPipes, &id_src[0], &id_src[1]);
2152
2153 if (id_src[0] == 0xf && id_src[1] == 0xf) {
2154 id_src[0] = tg_inst;
2155 numPipes = 1;
2156 }
2157
2158 for (i = 0; i < numPipes; i++) {
2159 //Check if src id invalid
2160 if (id_src[i] == 0xf)
2161 return -1;
2162
2163 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
2164 pipe_ctx->plane_res.mi = pool->mis[id_src[i]];
2165 pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];
2166 pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]];
2167 pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]];
2168 pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];
2169 pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
2170
2171 if (pool->dpps[id_src[i]]) {
2172 pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;
2173
2174 if (pool->mpc->funcs->read_mpcc_state) {
2175 struct mpcc_state s = {0};
2176 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
2177 if (s.dpp_id < MAX_MPCC)
2178 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =
2179 s.dpp_id;
2180 if (s.bot_mpcc_id < MAX_MPCC)
2181 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
2182 &pool->mpc->mpcc_array[s.bot_mpcc_id];
2183 if (s.opp_id < MAX_OPP)
2184 pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
2185 }
2186 }
2187 pipe_ctx->pipe_idx = id_src[i];
2188
2189 if (id_src[i] >= pool->timing_generator_count) {
2190 id_src[i] = pool->timing_generator_count - 1;
2191 pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];
2192 pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
2193 }
2194
2195 pipe_ctx->stream = stream;
2196 }
2197
2198 if (numPipes == 2) {
2199 stream->apply_boot_odm_mode = dm_odm_combine_policy_2to1;
2200 res_ctx->pipe_ctx[id_src[0]].next_odm_pipe = &res_ctx->pipe_ctx[id_src[1]];
2201 res_ctx->pipe_ctx[id_src[0]].prev_odm_pipe = NULL;
2202 res_ctx->pipe_ctx[id_src[1]].next_odm_pipe = NULL;
2203 res_ctx->pipe_ctx[id_src[1]].prev_odm_pipe = &res_ctx->pipe_ctx[id_src[0]];
2204 } else
2205 stream->apply_boot_odm_mode = dm_odm_combine_mode_disabled;
2206
2207 return id_src[0];
2208 }
2209
2210 return -1;
2211 }
2212
mark_seamless_boot_stream(const struct dc * dc,struct dc_stream_state * stream)2213 static void mark_seamless_boot_stream(
2214 const struct dc *dc,
2215 struct dc_stream_state *stream)
2216 {
2217 struct dc_bios *dcb = dc->ctx->dc_bios;
2218
2219 if (dc->config.allow_seamless_boot_optimization &&
2220 !dcb->funcs->is_accelerated_mode(dcb)) {
2221 if (dc_validate_boot_timing(dc, stream->sink, &stream->timing))
2222 stream->apply_seamless_boot_optimization = true;
2223 }
2224 }
2225
resource_map_pool_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)2226 enum dc_status resource_map_pool_resources(
2227 const struct dc *dc,
2228 struct dc_state *context,
2229 struct dc_stream_state *stream)
2230 {
2231 const struct resource_pool *pool = dc->res_pool;
2232 int i;
2233 struct dc_context *dc_ctx = dc->ctx;
2234 struct pipe_ctx *pipe_ctx = NULL;
2235 int pipe_idx = -1;
2236
2237 calculate_phy_pix_clks(stream);
2238
2239 mark_seamless_boot_stream(dc, stream);
2240
2241 if (stream->apply_seamless_boot_optimization) {
2242 pipe_idx = acquire_resource_from_hw_enabled_state(
2243 &context->res_ctx,
2244 pool,
2245 stream);
2246 if (pipe_idx < 0)
2247 /* hw resource was assigned to other stream */
2248 stream->apply_seamless_boot_optimization = false;
2249 }
2250
2251 if (pipe_idx < 0)
2252 /* acquire new resources */
2253 pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
2254
2255 if (pipe_idx < 0)
2256 pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
2257
2258 if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
2259 return DC_NO_CONTROLLER_RESOURCE;
2260
2261 pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2262
2263 pipe_ctx->stream_res.stream_enc =
2264 dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
2265 &context->res_ctx, pool, stream);
2266
2267 if (!pipe_ctx->stream_res.stream_enc)
2268 return DC_NO_STREAM_ENC_RESOURCE;
2269
2270 update_stream_engine_usage(
2271 &context->res_ctx, pool,
2272 pipe_ctx->stream_res.stream_enc,
2273 true);
2274
2275 /* Allocate DP HPO Stream Encoder based on signal, hw capabilities
2276 * and link settings
2277 */
2278 if (dc_is_dp_signal(stream->signal) &&
2279 dc->caps.dp_hpo) {
2280 struct dc_link_settings link_settings = {0};
2281
2282 decide_link_settings(stream, &link_settings);
2283 if (dp_get_link_encoding_format(&link_settings) == DP_128b_132b_ENCODING) {
2284 pipe_ctx->stream_res.hpo_dp_stream_enc =
2285 find_first_free_match_hpo_dp_stream_enc_for_link(
2286 &context->res_ctx, pool, stream);
2287
2288 if (!pipe_ctx->stream_res.hpo_dp_stream_enc)
2289 return DC_NO_STREAM_ENC_RESOURCE;
2290
2291 update_hpo_dp_stream_engine_usage(
2292 &context->res_ctx, pool,
2293 pipe_ctx->stream_res.hpo_dp_stream_enc,
2294 true);
2295 if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream))
2296 return DC_NO_LINK_ENC_RESOURCE;
2297 }
2298 }
2299
2300 /* TODO: Add check if ASIC support and EDID audio */
2301 if (!stream->converter_disable_audio &&
2302 dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
2303 stream->audio_info.mode_count && stream->audio_info.flags.all) {
2304 pipe_ctx->stream_res.audio = find_first_free_audio(
2305 &context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
2306
2307 /*
2308 * Audio assigned in order first come first get.
2309 * There are asics which has number of audio
2310 * resources less then number of pipes
2311 */
2312 if (pipe_ctx->stream_res.audio)
2313 update_audio_usage(&context->res_ctx, pool,
2314 pipe_ctx->stream_res.audio, true);
2315 }
2316
2317 /* Add ABM to the resource if on EDP */
2318 if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {
2319 if (pool->abm)
2320 pipe_ctx->stream_res.abm = pool->abm;
2321 else
2322 pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];
2323 }
2324
2325 for (i = 0; i < context->stream_count; i++)
2326 if (context->streams[i] == stream) {
2327 context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
2328 context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;
2329 context->stream_status[i].audio_inst =
2330 pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2331
2332 return DC_OK;
2333 }
2334
2335 DC_ERROR("Stream %p not found in new ctx!\n", stream);
2336 return DC_ERROR_UNEXPECTED;
2337 }
2338
2339 /**
2340 * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2341 * Is a shallow copy. Increments refcounts on existing streams and planes.
2342 * @dc: copy out of dc->current_state
2343 * @dst_ctx: copy into this
2344 */
dc_resource_state_copy_construct_current(const struct dc * dc,struct dc_state * dst_ctx)2345 void dc_resource_state_copy_construct_current(
2346 const struct dc *dc,
2347 struct dc_state *dst_ctx)
2348 {
2349 dc_resource_state_copy_construct(dc->current_state, dst_ctx);
2350 }
2351
2352
dc_resource_state_construct(const struct dc * dc,struct dc_state * dst_ctx)2353 void dc_resource_state_construct(
2354 const struct dc *dc,
2355 struct dc_state *dst_ctx)
2356 {
2357 dst_ctx->clk_mgr = dc->clk_mgr;
2358
2359 /* Initialise DIG link encoder resource tracking variables. */
2360 link_enc_cfg_init(dc, dst_ctx);
2361 }
2362
2363
dc_resource_is_dsc_encoding_supported(const struct dc * dc)2364 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
2365 {
2366 if (dc->res_pool == NULL)
2367 return false;
2368
2369 return dc->res_pool->res_cap->num_dsc > 0;
2370 }
2371
2372
2373 /**
2374 * dc_validate_global_state() - Determine if HW can support a given state
2375 * Checks HW resource availability and bandwidth requirement.
2376 * @dc: dc struct for this driver
2377 * @new_ctx: state to be validated
2378 * @fast_validate: set to true if only yes/no to support matters
2379 *
2380 * Return: DC_OK if the result can be programmed. Otherwise, an error code.
2381 */
dc_validate_global_state(struct dc * dc,struct dc_state * new_ctx,bool fast_validate)2382 enum dc_status dc_validate_global_state(
2383 struct dc *dc,
2384 struct dc_state *new_ctx,
2385 bool fast_validate)
2386 {
2387 enum dc_status result = DC_ERROR_UNEXPECTED;
2388 int i, j;
2389
2390 if (!new_ctx)
2391 return DC_ERROR_UNEXPECTED;
2392
2393 if (dc->res_pool->funcs->validate_global) {
2394 result = dc->res_pool->funcs->validate_global(dc, new_ctx);
2395 if (result != DC_OK)
2396 return result;
2397 }
2398
2399 for (i = 0; i < new_ctx->stream_count; i++) {
2400 struct dc_stream_state *stream = new_ctx->streams[i];
2401
2402 for (j = 0; j < dc->res_pool->pipe_count; j++) {
2403 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
2404
2405 if (pipe_ctx->stream != stream)
2406 continue;
2407
2408 if (dc->res_pool->funcs->patch_unknown_plane_state &&
2409 pipe_ctx->plane_state &&
2410 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
2411 result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);
2412 if (result != DC_OK)
2413 return result;
2414 }
2415
2416 /* Switch to dp clock source only if there is
2417 * no non dp stream that shares the same timing
2418 * with the dp stream.
2419 */
2420 if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
2421 !find_pll_sharable_stream(stream, new_ctx)) {
2422
2423 resource_unreference_clock_source(
2424 &new_ctx->res_ctx,
2425 dc->res_pool,
2426 pipe_ctx->clock_source);
2427
2428 pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
2429 resource_reference_clock_source(
2430 &new_ctx->res_ctx,
2431 dc->res_pool,
2432 pipe_ctx->clock_source);
2433 }
2434 }
2435 }
2436
2437 result = resource_build_scaling_params_for_context(dc, new_ctx);
2438
2439 if (result == DC_OK)
2440 if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
2441 result = DC_FAIL_BANDWIDTH_VALIDATE;
2442
2443 /*
2444 * Only update link encoder to stream assignment after bandwidth validation passed.
2445 * TODO: Split out assignment and validation.
2446 */
2447 if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false)
2448 dc->res_pool->funcs->link_encs_assign(
2449 dc, new_ctx, new_ctx->streams, new_ctx->stream_count);
2450
2451 return result;
2452 }
2453
patch_gamut_packet_checksum(struct dc_info_packet * gamut_packet)2454 static void patch_gamut_packet_checksum(
2455 struct dc_info_packet *gamut_packet)
2456 {
2457 /* For gamut we recalc checksum */
2458 if (gamut_packet->valid) {
2459 uint8_t chk_sum = 0;
2460 uint8_t *ptr;
2461 uint8_t i;
2462
2463 /*start of the Gamut data. */
2464 ptr = &gamut_packet->sb[3];
2465
2466 for (i = 0; i <= gamut_packet->sb[1]; i++)
2467 chk_sum += ptr[i];
2468
2469 gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
2470 }
2471 }
2472
set_avi_info_frame(struct dc_info_packet * info_packet,struct pipe_ctx * pipe_ctx)2473 static void set_avi_info_frame(
2474 struct dc_info_packet *info_packet,
2475 struct pipe_ctx *pipe_ctx)
2476 {
2477 struct dc_stream_state *stream = pipe_ctx->stream;
2478 enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
2479 uint32_t pixel_encoding = 0;
2480 enum scanning_type scan_type = SCANNING_TYPE_NODATA;
2481 enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
2482 bool itc = false;
2483 uint8_t itc_value = 0;
2484 uint8_t cn0_cn1 = 0;
2485 unsigned int cn0_cn1_value = 0;
2486 uint8_t *check_sum = NULL;
2487 uint8_t byte_index = 0;
2488 union hdmi_info_packet hdmi_info;
2489 union display_content_support support = {0};
2490 unsigned int vic = pipe_ctx->stream->timing.vic;
2491 enum dc_timing_3d_format format;
2492
2493 memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
2494
2495 color_space = pipe_ctx->stream->output_color_space;
2496 if (color_space == COLOR_SPACE_UNKNOWN)
2497 color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
2498 COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
2499
2500 /* Initialize header */
2501 hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
2502 /* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
2503 * not be used in HDMI 2.0 (Section 10.1) */
2504 hdmi_info.bits.header.version = 2;
2505 hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
2506
2507 /*
2508 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
2509 * according to HDMI 2.0 spec (Section 10.1)
2510 */
2511
2512 switch (stream->timing.pixel_encoding) {
2513 case PIXEL_ENCODING_YCBCR422:
2514 pixel_encoding = 1;
2515 break;
2516
2517 case PIXEL_ENCODING_YCBCR444:
2518 pixel_encoding = 2;
2519 break;
2520 case PIXEL_ENCODING_YCBCR420:
2521 pixel_encoding = 3;
2522 break;
2523
2524 case PIXEL_ENCODING_RGB:
2525 default:
2526 pixel_encoding = 0;
2527 }
2528
2529 /* Y0_Y1_Y2 : The pixel encoding */
2530 /* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
2531 hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
2532
2533 /* A0 = 1 Active Format Information valid */
2534 hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
2535
2536 /* B0, B1 = 3; Bar info data is valid */
2537 hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
2538
2539 hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
2540
2541 /* S0, S1 : Underscan / Overscan */
2542 /* TODO: un-hardcode scan type */
2543 scan_type = SCANNING_TYPE_UNDERSCAN;
2544 hdmi_info.bits.S0_S1 = scan_type;
2545
2546 /* C0, C1 : Colorimetry */
2547 if (color_space == COLOR_SPACE_YCBCR709 ||
2548 color_space == COLOR_SPACE_YCBCR709_LIMITED)
2549 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
2550 else if (color_space == COLOR_SPACE_YCBCR601 ||
2551 color_space == COLOR_SPACE_YCBCR601_LIMITED)
2552 hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
2553 else {
2554 hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
2555 }
2556 if (color_space == COLOR_SPACE_2020_RGB_FULLRANGE ||
2557 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE ||
2558 color_space == COLOR_SPACE_2020_YCBCR) {
2559 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
2560 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
2561 } else if (color_space == COLOR_SPACE_ADOBERGB) {
2562 hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
2563 hdmi_info.bits.C0_C1 = COLORIMETRY_EXTENDED;
2564 }
2565
2566 /* TODO: un-hardcode aspect ratio */
2567 aspect = stream->timing.aspect_ratio;
2568
2569 switch (aspect) {
2570 case ASPECT_RATIO_4_3:
2571 case ASPECT_RATIO_16_9:
2572 hdmi_info.bits.M0_M1 = aspect;
2573 break;
2574
2575 case ASPECT_RATIO_NO_DATA:
2576 case ASPECT_RATIO_64_27:
2577 case ASPECT_RATIO_256_135:
2578 default:
2579 hdmi_info.bits.M0_M1 = 0;
2580 }
2581
2582 /* Active Format Aspect ratio - same as Picture Aspect Ratio. */
2583 hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
2584
2585 /* TODO: un-hardcode cn0_cn1 and itc */
2586
2587 cn0_cn1 = 0;
2588 cn0_cn1_value = 0;
2589
2590 itc = true;
2591 itc_value = 1;
2592
2593 support = stream->content_support;
2594
2595 if (itc) {
2596 if (!support.bits.valid_content_type) {
2597 cn0_cn1_value = 0;
2598 } else {
2599 if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
2600 if (support.bits.graphics_content == 1) {
2601 cn0_cn1_value = 0;
2602 }
2603 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
2604 if (support.bits.photo_content == 1) {
2605 cn0_cn1_value = 1;
2606 } else {
2607 cn0_cn1_value = 0;
2608 itc_value = 0;
2609 }
2610 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
2611 if (support.bits.cinema_content == 1) {
2612 cn0_cn1_value = 2;
2613 } else {
2614 cn0_cn1_value = 0;
2615 itc_value = 0;
2616 }
2617 } else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
2618 if (support.bits.game_content == 1) {
2619 cn0_cn1_value = 3;
2620 } else {
2621 cn0_cn1_value = 0;
2622 itc_value = 0;
2623 }
2624 }
2625 }
2626 hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
2627 hdmi_info.bits.ITC = itc_value;
2628 }
2629
2630 if (stream->qs_bit == 1) {
2631 if (color_space == COLOR_SPACE_SRGB ||
2632 color_space == COLOR_SPACE_2020_RGB_FULLRANGE)
2633 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE;
2634 else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
2635 color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
2636 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_LIMITED_RANGE;
2637 else
2638 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2639 } else
2640 hdmi_info.bits.Q0_Q1 = RGB_QUANTIZATION_DEFAULT_RANGE;
2641
2642 /* TODO : We should handle YCC quantization */
2643 /* but we do not have matrix calculation */
2644 hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
2645
2646 ///VIC
2647 if (pipe_ctx->stream->timing.hdmi_vic != 0)
2648 vic = 0;
2649 format = stream->timing.timing_3d_format;
2650 /*todo, add 3DStereo support*/
2651 if (format != TIMING_3D_FORMAT_NONE) {
2652 // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
2653 switch (pipe_ctx->stream->timing.hdmi_vic) {
2654 case 1:
2655 vic = 95;
2656 break;
2657 case 2:
2658 vic = 94;
2659 break;
2660 case 3:
2661 vic = 93;
2662 break;
2663 case 4:
2664 vic = 98;
2665 break;
2666 default:
2667 break;
2668 }
2669 }
2670 /* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
2671 hdmi_info.bits.VIC0_VIC7 = vic;
2672 if (vic >= 128)
2673 hdmi_info.bits.header.version = 3;
2674 /* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
2675 * the Source shall use 20 AVI InfoFrame Version 4
2676 */
2677 if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
2678 hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
2679 hdmi_info.bits.header.version = 4;
2680 hdmi_info.bits.header.length = 14;
2681 }
2682
2683 /* pixel repetition
2684 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
2685 * repetition start from 1 */
2686 hdmi_info.bits.PR0_PR3 = 0;
2687
2688 /* Bar Info
2689 * barTop: Line Number of End of Top Bar.
2690 * barBottom: Line Number of Start of Bottom Bar.
2691 * barLeft: Pixel Number of End of Left Bar.
2692 * barRight: Pixel Number of Start of Right Bar. */
2693 hdmi_info.bits.bar_top = stream->timing.v_border_top;
2694 hdmi_info.bits.bar_bottom = (stream->timing.v_total
2695 - stream->timing.v_border_bottom + 1);
2696 hdmi_info.bits.bar_left = stream->timing.h_border_left;
2697 hdmi_info.bits.bar_right = (stream->timing.h_total
2698 - stream->timing.h_border_right + 1);
2699
2700 /* Additional Colorimetry Extension
2701 * Used in conduction with C0-C1 and EC0-EC2
2702 * 0 = DCI-P3 RGB (D65)
2703 * 1 = DCI-P3 RGB (theater)
2704 */
2705 hdmi_info.bits.ACE0_ACE3 = 0;
2706
2707 /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
2708 check_sum = &hdmi_info.packet_raw_data.sb[0];
2709
2710 *check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
2711
2712 for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
2713 *check_sum += hdmi_info.packet_raw_data.sb[byte_index];
2714
2715 /* one byte complement */
2716 *check_sum = (uint8_t) (0x100 - *check_sum);
2717
2718 /* Store in hw_path_mode */
2719 info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
2720 info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
2721 info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
2722
2723 for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
2724 info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
2725
2726 info_packet->valid = true;
2727 }
2728
set_vendor_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)2729 static void set_vendor_info_packet(
2730 struct dc_info_packet *info_packet,
2731 struct dc_stream_state *stream)
2732 {
2733 /* SPD info packet for FreeSync */
2734
2735 /* Check if Freesync is supported. Return if false. If true,
2736 * set the corresponding bit in the info packet
2737 */
2738 if (!stream->vsp_infopacket.valid)
2739 return;
2740
2741 *info_packet = stream->vsp_infopacket;
2742 }
2743
set_spd_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)2744 static void set_spd_info_packet(
2745 struct dc_info_packet *info_packet,
2746 struct dc_stream_state *stream)
2747 {
2748 /* SPD info packet for FreeSync */
2749
2750 /* Check if Freesync is supported. Return if false. If true,
2751 * set the corresponding bit in the info packet
2752 */
2753 if (!stream->vrr_infopacket.valid)
2754 return;
2755
2756 *info_packet = stream->vrr_infopacket;
2757 }
2758
set_hdr_static_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)2759 static void set_hdr_static_info_packet(
2760 struct dc_info_packet *info_packet,
2761 struct dc_stream_state *stream)
2762 {
2763 /* HDR Static Metadata info packet for HDR10 */
2764
2765 if (!stream->hdr_static_metadata.valid ||
2766 stream->use_dynamic_meta)
2767 return;
2768
2769 *info_packet = stream->hdr_static_metadata;
2770 }
2771
set_vsc_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)2772 static void set_vsc_info_packet(
2773 struct dc_info_packet *info_packet,
2774 struct dc_stream_state *stream)
2775 {
2776 if (!stream->vsc_infopacket.valid)
2777 return;
2778
2779 *info_packet = stream->vsc_infopacket;
2780 }
2781
dc_resource_state_destruct(struct dc_state * context)2782 void dc_resource_state_destruct(struct dc_state *context)
2783 {
2784 int i, j;
2785
2786 for (i = 0; i < context->stream_count; i++) {
2787 for (j = 0; j < context->stream_status[i].plane_count; j++)
2788 dc_plane_state_release(
2789 context->stream_status[i].plane_states[j]);
2790
2791 context->stream_status[i].plane_count = 0;
2792 dc_stream_release(context->streams[i]);
2793 context->streams[i] = NULL;
2794 }
2795 context->stream_count = 0;
2796 }
2797
dc_resource_state_copy_construct(const struct dc_state * src_ctx,struct dc_state * dst_ctx)2798 void dc_resource_state_copy_construct(
2799 const struct dc_state *src_ctx,
2800 struct dc_state *dst_ctx)
2801 {
2802 int i, j;
2803 struct kref refcount = dst_ctx->refcount;
2804
2805 *dst_ctx = *src_ctx;
2806
2807 for (i = 0; i < MAX_PIPES; i++) {
2808 struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
2809
2810 if (cur_pipe->top_pipe)
2811 cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
2812
2813 if (cur_pipe->bottom_pipe)
2814 cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
2815
2816 if (cur_pipe->next_odm_pipe)
2817 cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
2818
2819 if (cur_pipe->prev_odm_pipe)
2820 cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
2821 }
2822
2823 for (i = 0; i < dst_ctx->stream_count; i++) {
2824 dc_stream_retain(dst_ctx->streams[i]);
2825 for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
2826 dc_plane_state_retain(
2827 dst_ctx->stream_status[i].plane_states[j]);
2828 }
2829
2830 /* context refcount should not be overridden */
2831 dst_ctx->refcount = refcount;
2832
2833 }
2834
dc_resource_find_first_free_pll(struct resource_context * res_ctx,const struct resource_pool * pool)2835 struct clock_source *dc_resource_find_first_free_pll(
2836 struct resource_context *res_ctx,
2837 const struct resource_pool *pool)
2838 {
2839 int i;
2840
2841 for (i = 0; i < pool->clk_src_count; ++i) {
2842 if (res_ctx->clock_source_ref_count[i] == 0)
2843 return pool->clock_sources[i];
2844 }
2845
2846 return NULL;
2847 }
2848
resource_build_info_frame(struct pipe_ctx * pipe_ctx)2849 void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
2850 {
2851 enum signal_type signal = SIGNAL_TYPE_NONE;
2852 struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
2853
2854 /* default all packets to invalid */
2855 info->avi.valid = false;
2856 info->gamut.valid = false;
2857 info->vendor.valid = false;
2858 info->spd.valid = false;
2859 info->hdrsmd.valid = false;
2860 info->vsc.valid = false;
2861
2862 signal = pipe_ctx->stream->signal;
2863
2864 /* HDMi and DP have different info packets*/
2865 if (dc_is_hdmi_signal(signal)) {
2866 set_avi_info_frame(&info->avi, pipe_ctx);
2867
2868 set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
2869
2870 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2871
2872 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
2873
2874 } else if (dc_is_dp_signal(signal)) {
2875 set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
2876
2877 set_spd_info_packet(&info->spd, pipe_ctx->stream);
2878
2879 set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
2880 }
2881
2882 patch_gamut_packet_checksum(&info->gamut);
2883 }
2884
resource_map_clock_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)2885 enum dc_status resource_map_clock_resources(
2886 const struct dc *dc,
2887 struct dc_state *context,
2888 struct dc_stream_state *stream)
2889 {
2890 /* acquire new resources */
2891 const struct resource_pool *pool = dc->res_pool;
2892 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
2893 &context->res_ctx, stream);
2894
2895 if (!pipe_ctx)
2896 return DC_ERROR_UNEXPECTED;
2897
2898 if (dc_is_dp_signal(pipe_ctx->stream->signal)
2899 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
2900 pipe_ctx->clock_source = pool->dp_clock_source;
2901 else {
2902 pipe_ctx->clock_source = NULL;
2903
2904 if (!dc->config.disable_disp_pll_sharing)
2905 pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
2906 &context->res_ctx,
2907 pipe_ctx);
2908
2909 if (pipe_ctx->clock_source == NULL)
2910 pipe_ctx->clock_source =
2911 dc_resource_find_first_free_pll(
2912 &context->res_ctx,
2913 pool);
2914 }
2915
2916 if (pipe_ctx->clock_source == NULL)
2917 return DC_NO_CLOCK_SOURCE_RESOURCE;
2918
2919 resource_reference_clock_source(
2920 &context->res_ctx, pool,
2921 pipe_ctx->clock_source);
2922
2923 return DC_OK;
2924 }
2925
2926 /*
2927 * Note: We need to disable output if clock sources change,
2928 * since bios does optimization and doesn't apply if changing
2929 * PHY when not already disabled.
2930 */
pipe_need_reprogram(struct pipe_ctx * pipe_ctx_old,struct pipe_ctx * pipe_ctx)2931 bool pipe_need_reprogram(
2932 struct pipe_ctx *pipe_ctx_old,
2933 struct pipe_ctx *pipe_ctx)
2934 {
2935 if (!pipe_ctx_old->stream)
2936 return false;
2937
2938 if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
2939 return true;
2940
2941 if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
2942 return true;
2943
2944 if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
2945 return true;
2946
2947 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
2948 && pipe_ctx_old->stream != pipe_ctx->stream)
2949 return true;
2950
2951 if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
2952 return true;
2953
2954 if (is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
2955 return true;
2956
2957 if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
2958 return true;
2959
2960 if (false == pipe_ctx_old->stream->link->link_state_valid &&
2961 false == pipe_ctx_old->stream->dpms_off)
2962 return true;
2963
2964 if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)
2965 return true;
2966
2967 if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc)
2968 return true;
2969 if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc)
2970 return true;
2971
2972 /* DIG link encoder resource assignment for stream changed. */
2973 if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) {
2974 bool need_reprogram = false;
2975 struct dc *dc = pipe_ctx_old->stream->ctx->dc;
2976 enum link_enc_cfg_mode mode = dc->current_state->res_ctx.link_enc_cfg_ctx.mode;
2977
2978 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = LINK_ENC_CFG_STEADY;
2979 if (link_enc_cfg_get_link_enc_used_by_stream(dc, pipe_ctx_old->stream) != pipe_ctx->stream->link_enc)
2980 need_reprogram = true;
2981 dc->current_state->res_ctx.link_enc_cfg_ctx.mode = mode;
2982
2983 return need_reprogram;
2984 }
2985
2986 return false;
2987 }
2988
resource_build_bit_depth_reduction_params(struct dc_stream_state * stream,struct bit_depth_reduction_params * fmt_bit_depth)2989 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
2990 struct bit_depth_reduction_params *fmt_bit_depth)
2991 {
2992 enum dc_dither_option option = stream->dither_option;
2993 enum dc_pixel_encoding pixel_encoding =
2994 stream->timing.pixel_encoding;
2995
2996 memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
2997
2998 if (option == DITHER_OPTION_DEFAULT) {
2999 switch (stream->timing.display_color_depth) {
3000 case COLOR_DEPTH_666:
3001 option = DITHER_OPTION_SPATIAL6;
3002 break;
3003 case COLOR_DEPTH_888:
3004 option = DITHER_OPTION_SPATIAL8;
3005 break;
3006 case COLOR_DEPTH_101010:
3007 option = DITHER_OPTION_SPATIAL10;
3008 break;
3009 default:
3010 option = DITHER_OPTION_DISABLE;
3011 }
3012 }
3013
3014 if (option == DITHER_OPTION_DISABLE)
3015 return;
3016
3017 if (option == DITHER_OPTION_TRUN6) {
3018 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
3019 fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
3020 } else if (option == DITHER_OPTION_TRUN8 ||
3021 option == DITHER_OPTION_TRUN8_SPATIAL6 ||
3022 option == DITHER_OPTION_TRUN8_FM6) {
3023 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
3024 fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
3025 } else if (option == DITHER_OPTION_TRUN10 ||
3026 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
3027 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
3028 option == DITHER_OPTION_TRUN10_FM8 ||
3029 option == DITHER_OPTION_TRUN10_FM6 ||
3030 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
3031 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
3032 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
3033 }
3034
3035 /* special case - Formatter can only reduce by 4 bits at most.
3036 * When reducing from 12 to 6 bits,
3037 * HW recommends we use trunc with round mode
3038 * (if we did nothing, trunc to 10 bits would be used)
3039 * note that any 12->10 bit reduction is ignored prior to DCE8,
3040 * as the input was 10 bits.
3041 */
3042 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
3043 option == DITHER_OPTION_SPATIAL6 ||
3044 option == DITHER_OPTION_FM6) {
3045 fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
3046 fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
3047 fmt_bit_depth->flags.TRUNCATE_MODE = 1;
3048 }
3049
3050 /* spatial dither
3051 * note that spatial modes 1-3 are never used
3052 */
3053 if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
3054 option == DITHER_OPTION_SPATIAL6 ||
3055 option == DITHER_OPTION_TRUN10_SPATIAL6 ||
3056 option == DITHER_OPTION_TRUN8_SPATIAL6) {
3057 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
3058 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
3059 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
3060 fmt_bit_depth->flags.RGB_RANDOM =
3061 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
3062 } else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM ||
3063 option == DITHER_OPTION_SPATIAL8 ||
3064 option == DITHER_OPTION_SPATIAL8_FM6 ||
3065 option == DITHER_OPTION_TRUN10_SPATIAL8 ||
3066 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
3067 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
3068 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
3069 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
3070 fmt_bit_depth->flags.RGB_RANDOM =
3071 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
3072 } else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
3073 option == DITHER_OPTION_SPATIAL10 ||
3074 option == DITHER_OPTION_SPATIAL10_FM8 ||
3075 option == DITHER_OPTION_SPATIAL10_FM6) {
3076 fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
3077 fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
3078 fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
3079 fmt_bit_depth->flags.RGB_RANDOM =
3080 (pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
3081 }
3082
3083 if (option == DITHER_OPTION_SPATIAL6 ||
3084 option == DITHER_OPTION_SPATIAL8 ||
3085 option == DITHER_OPTION_SPATIAL10) {
3086 fmt_bit_depth->flags.FRAME_RANDOM = 0;
3087 } else {
3088 fmt_bit_depth->flags.FRAME_RANDOM = 1;
3089 }
3090
3091 //////////////////////
3092 //// temporal dither
3093 //////////////////////
3094 if (option == DITHER_OPTION_FM6 ||
3095 option == DITHER_OPTION_SPATIAL8_FM6 ||
3096 option == DITHER_OPTION_SPATIAL10_FM6 ||
3097 option == DITHER_OPTION_TRUN10_FM6 ||
3098 option == DITHER_OPTION_TRUN8_FM6 ||
3099 option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
3100 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
3101 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
3102 } else if (option == DITHER_OPTION_FM8 ||
3103 option == DITHER_OPTION_SPATIAL10_FM8 ||
3104 option == DITHER_OPTION_TRUN10_FM8) {
3105 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
3106 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
3107 } else if (option == DITHER_OPTION_FM10) {
3108 fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
3109 fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
3110 }
3111
3112 fmt_bit_depth->pixel_encoding = pixel_encoding;
3113 }
3114
dc_validate_stream(struct dc * dc,struct dc_stream_state * stream)3115 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
3116 {
3117 struct dc_link *link = stream->link;
3118 struct timing_generator *tg = dc->res_pool->timing_generators[0];
3119 enum dc_status res = DC_OK;
3120
3121 calculate_phy_pix_clks(stream);
3122
3123 if (!tg->funcs->validate_timing(tg, &stream->timing))
3124 res = DC_FAIL_CONTROLLER_VALIDATE;
3125
3126 if (res == DC_OK) {
3127 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
3128 !link->link_enc->funcs->validate_output_with_stream(
3129 link->link_enc, stream))
3130 res = DC_FAIL_ENC_VALIDATE;
3131 }
3132
3133 /* TODO: validate audio ASIC caps, encoder */
3134
3135 if (res == DC_OK)
3136 res = dc_link_validate_mode_timing(stream,
3137 link,
3138 &stream->timing);
3139
3140 return res;
3141 }
3142
dc_validate_plane(struct dc * dc,const struct dc_plane_state * plane_state)3143 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
3144 {
3145 enum dc_status res = DC_OK;
3146
3147 /* check if surface has invalid dimensions */
3148 if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 0 ||
3149 plane_state->dst_rect.width == 0 || plane_state->dst_rect.height == 0)
3150 return DC_FAIL_SURFACE_VALIDATE;
3151
3152 /* TODO For now validates pixel format only */
3153 if (dc->res_pool->funcs->validate_plane)
3154 return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
3155
3156 return res;
3157 }
3158
resource_pixel_format_to_bpp(enum surface_pixel_format format)3159 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
3160 {
3161 switch (format) {
3162 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
3163 return 8;
3164 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
3165 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
3166 return 12;
3167 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
3168 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
3169 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
3170 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
3171 return 16;
3172 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
3173 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
3174 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
3175 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
3176 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
3177 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
3178 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
3179 return 32;
3180 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
3181 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
3182 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
3183 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
3184 return 64;
3185 default:
3186 ASSERT_CRITICAL(false);
3187 return -1;
3188 }
3189 }
get_max_audio_sample_rate(struct audio_mode * modes)3190 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
3191 {
3192 if (modes) {
3193 if (modes->sample_rates.rate.RATE_192)
3194 return 192000;
3195 if (modes->sample_rates.rate.RATE_176_4)
3196 return 176400;
3197 if (modes->sample_rates.rate.RATE_96)
3198 return 96000;
3199 if (modes->sample_rates.rate.RATE_88_2)
3200 return 88200;
3201 if (modes->sample_rates.rate.RATE_48)
3202 return 48000;
3203 if (modes->sample_rates.rate.RATE_44_1)
3204 return 44100;
3205 if (modes->sample_rates.rate.RATE_32)
3206 return 32000;
3207 }
3208 /*original logic when no audio info*/
3209 return 441000;
3210 }
3211
get_audio_check(struct audio_info * aud_modes,struct audio_check * audio_chk)3212 void get_audio_check(struct audio_info *aud_modes,
3213 struct audio_check *audio_chk)
3214 {
3215 unsigned int i;
3216 unsigned int max_sample_rate = 0;
3217
3218 if (aud_modes) {
3219 audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
3220
3221 audio_chk->max_audiosample_rate = 0;
3222 for (i = 0; i < aud_modes->mode_count; i++) {
3223 max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]);
3224 if (audio_chk->max_audiosample_rate < max_sample_rate)
3225 audio_chk->max_audiosample_rate = max_sample_rate;
3226 /*dts takes the same as type 2: AP = 0.25*/
3227 }
3228 /*check which one take more bandwidth*/
3229 if (audio_chk->max_audiosample_rate > 192000)
3230 audio_chk->audio_packet_type = 0x9;/*AP =1*/
3231 audio_chk->acat = 0;/*not support*/
3232 }
3233 }
3234
get_temp_hpo_dp_link_enc(const struct resource_context * res_ctx,const struct resource_pool * const pool,const struct dc_link * link)3235 static struct hpo_dp_link_encoder *get_temp_hpo_dp_link_enc(
3236 const struct resource_context *res_ctx,
3237 const struct resource_pool *const pool,
3238 const struct dc_link *link)
3239 {
3240 struct hpo_dp_link_encoder *hpo_dp_link_enc = NULL;
3241 int enc_index;
3242
3243 enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, link);
3244
3245 if (enc_index < 0)
3246 enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
3247
3248 if (enc_index >= 0)
3249 hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
3250
3251 return hpo_dp_link_enc;
3252 }
3253
get_temp_dp_link_res(struct dc_link * link,struct link_resource * link_res,struct dc_link_settings * link_settings)3254 bool get_temp_dp_link_res(struct dc_link *link,
3255 struct link_resource *link_res,
3256 struct dc_link_settings *link_settings)
3257 {
3258 const struct dc *dc = link->dc;
3259 const struct resource_context *res_ctx = &dc->current_state->res_ctx;
3260
3261 memset(link_res, 0, sizeof(*link_res));
3262
3263 if (dp_get_link_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
3264 link_res->hpo_dp_link_enc = get_temp_hpo_dp_link_enc(res_ctx,
3265 dc->res_pool, link);
3266 if (!link_res->hpo_dp_link_enc)
3267 return false;
3268 }
3269 return true;
3270 }
3271
reset_syncd_pipes_from_disabled_pipes(struct dc * dc,struct dc_state * context)3272 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
3273 struct dc_state *context)
3274 {
3275 int i, j;
3276 struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd;
3277
3278 /* If pipe backend is reset, need to reset pipe syncd status */
3279 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3280 pipe_ctx_old = &dc->current_state->res_ctx.pipe_ctx[i];
3281 pipe_ctx = &context->res_ctx.pipe_ctx[i];
3282
3283 if (!pipe_ctx_old->stream)
3284 continue;
3285
3286 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
3287 continue;
3288
3289 if (!pipe_ctx->stream ||
3290 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
3291
3292 /* Reset all the syncd pipes from the disabled pipe */
3293 for (j = 0; j < dc->res_pool->pipe_count; j++) {
3294 pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j];
3295 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_syncd) == pipe_ctx_old->pipe_idx) ||
3296 !IS_PIPE_SYNCD_VALID(pipe_ctx_syncd))
3297 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_syncd, j);
3298 }
3299 }
3300 }
3301 }
3302
check_syncd_pipes_for_disabled_master_pipe(struct dc * dc,struct dc_state * context,uint8_t disabled_master_pipe_idx)3303 void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
3304 struct dc_state *context,
3305 uint8_t disabled_master_pipe_idx)
3306 {
3307 int i;
3308 struct pipe_ctx *pipe_ctx, *pipe_ctx_check;
3309
3310 pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];
3311 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) ||
3312 !IS_PIPE_SYNCD_VALID(pipe_ctx))
3313 SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx);
3314
3315 /* for the pipe disabled, check if any slave pipe exists and assert */
3316 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3317 pipe_ctx_check = &context->res_ctx.pipe_ctx[i];
3318
3319 if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) &&
3320 IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx))
3321 DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n",
3322 i, disabled_master_pipe_idx);
3323 }
3324 }
3325
resource_transmitter_to_phy_idx(const struct dc * dc,enum transmitter transmitter)3326 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter)
3327 {
3328 /* TODO - get transmitter to phy idx mapping from DMUB */
3329 uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
3330
3331 if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
3332 dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
3333 switch (transmitter) {
3334 case TRANSMITTER_UNIPHY_A:
3335 phy_idx = 0;
3336 break;
3337 case TRANSMITTER_UNIPHY_B:
3338 phy_idx = 1;
3339 break;
3340 case TRANSMITTER_UNIPHY_C:
3341 phy_idx = 5;
3342 break;
3343 case TRANSMITTER_UNIPHY_D:
3344 phy_idx = 6;
3345 break;
3346 case TRANSMITTER_UNIPHY_E:
3347 phy_idx = 4;
3348 break;
3349 default:
3350 phy_idx = 0;
3351 break;
3352 }
3353 }
3354
3355 return phy_idx;
3356 }
3357
get_link_hwss(const struct dc_link * link,const struct link_resource * link_res)3358 const struct link_hwss *get_link_hwss(const struct dc_link *link,
3359 const struct link_resource *link_res)
3360 {
3361 /* Link_hwss is only accessible by getter function instead of accessing
3362 * by pointers in dc with the intent to protect against breaking polymorphism.
3363 */
3364 if (can_use_hpo_dp_link_hwss(link, link_res))
3365 /* TODO: some assumes that if decided link settings is 128b/132b
3366 * channel coding format hpo_dp_link_enc should be used.
3367 * Others believe that if hpo_dp_link_enc is available in link
3368 * resource then hpo_dp_link_enc must be used. This bound between
3369 * hpo_dp_link_enc != NULL and decided link settings is loosely coupled
3370 * with a premise that both hpo_dp_link_enc pointer and decided link
3371 * settings are determined based on single policy function like
3372 * "decide_link_settings" from upper layer. This "convention"
3373 * cannot be maintained and enforced at current level.
3374 * Therefore a refactor is due so we can enforce a strong bound
3375 * between those two parameters at this level.
3376 *
3377 * To put it simple, we want to make enforcement at low level so that
3378 * we will not return link hwss if caller plans to do 8b/10b
3379 * with an hpo encoder. Or we can return a very dummy one that doesn't
3380 * do work for all functions
3381 */
3382 return get_hpo_dp_link_hwss();
3383 else if (can_use_dpia_link_hwss(link, link_res))
3384 return get_dpia_link_hwss();
3385 else if (can_use_dio_link_hwss(link, link_res))
3386 return get_dio_link_hwss();
3387 else
3388 return get_virtual_link_hwss();
3389 }
3390