1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef ATH_H
18 #define ATH_H
19
20 #include <linux/skbuff.h>
21 #include <linux/if_ether.h>
22 #include <linux/spinlock.h>
23 #include <net/mac80211.h>
24
25 /*
26 * The key cache is used for h/w cipher state and also for
27 * tracking station state such as the current tx antenna.
28 * We also setup a mapping table between key cache slot indices
29 * and station state to short-circuit node lookups on rx.
30 * Different parts have different size key caches. We handle
31 * up to ATH_KEYMAX entries (could dynamically allocate state).
32 */
33 #define ATH_KEYMAX 128 /* max key cache size we handle */
34
35 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
36
37 struct ath_ani {
38 bool caldone;
39 unsigned int longcal_timer;
40 unsigned int shortcal_timer;
41 unsigned int resetcal_timer;
42 unsigned int checkani_timer;
43 struct timer_list timer;
44 };
45
46 struct ath_cycle_counters {
47 u32 cycles;
48 u32 rx_busy;
49 u32 rx_frame;
50 u32 tx_frame;
51 };
52
53 enum ath_device_state {
54 ATH_HW_UNAVAILABLE,
55 ATH_HW_INITIALIZED,
56 };
57
58 enum ath_bus_type {
59 ATH_PCI,
60 ATH_AHB,
61 ATH_USB,
62 };
63
64 struct reg_dmn_pair_mapping {
65 u16 regDmnEnum;
66 u16 reg_5ghz_ctl;
67 u16 reg_2ghz_ctl;
68 };
69
70 struct ath_regulatory {
71 char alpha2[2];
72 u16 country_code;
73 u16 max_power_level;
74 u16 current_rd;
75 int16_t power_limit;
76 struct reg_dmn_pair_mapping *regpair;
77 };
78
79 enum ath_crypt_caps {
80 ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
81 ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
82 };
83
84 struct ath_keyval {
85 u8 kv_type;
86 u8 kv_pad;
87 u16 kv_len;
88 u8 kv_val[16]; /* TK */
89 u8 kv_mic[8]; /* Michael MIC key */
90 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
91 * supports both MIC keys in the same key cache entry;
92 * in that case, kv_mic is the RX key) */
93 };
94
95 enum ath_cipher {
96 ATH_CIPHER_WEP = 0,
97 ATH_CIPHER_AES_OCB = 1,
98 ATH_CIPHER_AES_CCM = 2,
99 ATH_CIPHER_CKIP = 3,
100 ATH_CIPHER_TKIP = 4,
101 ATH_CIPHER_CLR = 5,
102 ATH_CIPHER_MIC = 127
103 };
104
105 /**
106 * struct ath_ops - Register read/write operations
107 *
108 * @read: Register read
109 * @multi_read: Multiple register read
110 * @write: Register write
111 * @enable_write_buffer: Enable multiple register writes
112 * @write_flush: flush buffered register writes and disable buffering
113 */
114 struct ath_ops {
115 unsigned int (*read)(void *, u32 reg_offset);
116 void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
117 void (*write)(void *, u32 val, u32 reg_offset);
118 void (*enable_write_buffer)(void *);
119 void (*write_flush) (void *);
120 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
121 };
122
123 struct ath_common;
124 struct ath_bus_ops;
125
126 struct ath_common {
127 void *ah;
128 void *priv;
129 struct ieee80211_hw *hw;
130 int debug_mask;
131 enum ath_device_state state;
132
133 struct ath_ani ani;
134
135 u16 cachelsz;
136 u16 curaid;
137 u8 macaddr[ETH_ALEN];
138 u8 curbssid[ETH_ALEN];
139 u8 bssidmask[ETH_ALEN];
140
141 u32 rx_bufsize;
142
143 u32 keymax;
144 DECLARE_BITMAP(keymap, ATH_KEYMAX);
145 DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
146 DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX);
147 enum ath_crypt_caps crypt_caps;
148
149 unsigned int clockrate;
150
151 spinlock_t cc_lock;
152 struct ath_cycle_counters cc_ani;
153 struct ath_cycle_counters cc_survey;
154
155 struct ath_regulatory regulatory;
156 struct ath_regulatory reg_world_copy;
157 const struct ath_ops *ops;
158 const struct ath_bus_ops *bus_ops;
159
160 bool btcoex_enabled;
161 bool disable_ani;
162 };
163
164 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
165 u32 len,
166 gfp_t gfp_mask);
167
168 void ath_hw_setbssidmask(struct ath_common *common);
169 void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
170 int ath_key_config(struct ath_common *common,
171 struct ieee80211_vif *vif,
172 struct ieee80211_sta *sta,
173 struct ieee80211_key_conf *key);
174 bool ath_hw_keyreset(struct ath_common *common, u16 entry);
175 void ath_hw_cycle_counters_update(struct ath_common *common);
176 int32_t ath_hw_get_listen_time(struct ath_common *common);
177
178 __printf(3, 4)
179 void ath_printk(const char *level, const struct ath_common *common,
180 const char *fmt, ...);
181
182 #define ath_emerg(common, fmt, ...) \
183 ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
184 #define ath_alert(common, fmt, ...) \
185 ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
186 #define ath_crit(common, fmt, ...) \
187 ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
188 #define ath_err(common, fmt, ...) \
189 ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
190 #define ath_warn(common, fmt, ...) \
191 ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
192 #define ath_notice(common, fmt, ...) \
193 ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
194 #define ath_info(common, fmt, ...) \
195 ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
196
197 /**
198 * enum ath_debug_level - atheros wireless debug level
199 *
200 * @ATH_DBG_RESET: reset processing
201 * @ATH_DBG_QUEUE: hardware queue management
202 * @ATH_DBG_EEPROM: eeprom processing
203 * @ATH_DBG_CALIBRATE: periodic calibration
204 * @ATH_DBG_INTERRUPT: interrupt processing
205 * @ATH_DBG_REGULATORY: regulatory processing
206 * @ATH_DBG_ANI: adaptive noise immunitive processing
207 * @ATH_DBG_XMIT: basic xmit operation
208 * @ATH_DBG_BEACON: beacon handling
209 * @ATH_DBG_CONFIG: configuration of the hardware
210 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
211 * @ATH_DBG_PS: power save processing
212 * @ATH_DBG_HWTIMER: hardware timer handling
213 * @ATH_DBG_BTCOEX: bluetooth coexistance
214 * @ATH_DBG_BSTUCK: stuck beacons
215 * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol
216 * used exclusively for WLAN-BT coexistence starting from
217 * AR9462.
218 * @ATH_DBG_DFS: radar datection
219 * @ATH_DBG_ANY: enable all debugging
220 *
221 * The debug level is used to control the amount and type of debugging output
222 * we want to see. Each driver has its own method for enabling debugging and
223 * modifying debug level states -- but this is typically done through a
224 * module parameter 'debug' along with a respective 'debug' debugfs file
225 * entry.
226 */
227 enum ATH_DEBUG {
228 ATH_DBG_RESET = 0x00000001,
229 ATH_DBG_QUEUE = 0x00000002,
230 ATH_DBG_EEPROM = 0x00000004,
231 ATH_DBG_CALIBRATE = 0x00000008,
232 ATH_DBG_INTERRUPT = 0x00000010,
233 ATH_DBG_REGULATORY = 0x00000020,
234 ATH_DBG_ANI = 0x00000040,
235 ATH_DBG_XMIT = 0x00000080,
236 ATH_DBG_BEACON = 0x00000100,
237 ATH_DBG_CONFIG = 0x00000200,
238 ATH_DBG_FATAL = 0x00000400,
239 ATH_DBG_PS = 0x00000800,
240 ATH_DBG_HWTIMER = 0x00001000,
241 ATH_DBG_BTCOEX = 0x00002000,
242 ATH_DBG_WMI = 0x00004000,
243 ATH_DBG_BSTUCK = 0x00008000,
244 ATH_DBG_MCI = 0x00010000,
245 ATH_DBG_DFS = 0x00020000,
246 ATH_DBG_ANY = 0xffffffff
247 };
248
249 #define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
250
251 #ifdef CONFIG_ATH_DEBUG
252
253 #define ath_dbg(common, dbg_mask, fmt, ...) \
254 do { \
255 if ((common)->debug_mask & ATH_DBG_##dbg_mask) \
256 ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \
257 } while (0)
258
259 #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
260 #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
261
262 #else
263
264 static inline __attribute__ ((format (printf, 3, 4)))
_ath_dbg(struct ath_common * common,enum ATH_DEBUG dbg_mask,const char * fmt,...)265 void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
266 const char *fmt, ...)
267 {
268 }
269 #define ath_dbg(common, dbg_mask, fmt, ...) \
270 _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__)
271
272 #define ATH_DBG_WARN(foo, arg...) do {} while (0)
273 #define ATH_DBG_WARN_ON_ONCE(foo) ({ \
274 int __ret_warn_once = !!(foo); \
275 unlikely(__ret_warn_once); \
276 })
277
278 #endif /* CONFIG_ATH_DEBUG */
279
280 /** Returns string describing opmode, or NULL if unknown mode. */
281 #ifdef CONFIG_ATH_DEBUG
282 const char *ath_opmode_to_string(enum nl80211_iftype opmode);
283 #else
ath_opmode_to_string(enum nl80211_iftype opmode)284 static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
285 {
286 return "UNKNOWN";
287 }
288 #endif
289
290 #endif /* ATH_H */
291