1 /****************************************************************************** 2 * QLOGIC LINUX SOFTWARE 3 * 4 * QLogic ISP1280 (Ultra2) /12160 (Ultra3) SCSI driver 5 * Copyright (C) 2000 Qlogic Corporation 6 * (www.qlogic.com) 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2, or (at your option) any 11 * later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 ******************************************************************************/ 19 20 #ifndef _IO_HBA_QLA1280_H /* wrapper symbol for kernel use */ 21 #define _IO_HBA_QLA1280_H /* subject to change without notice */ 22 23 #ifndef HOSTS_C /* included in hosts.c */ 24 25 /* 26 * Data bit definitions. 27 */ 28 #define BIT_0 0x1 29 #define BIT_1 0x2 30 #define BIT_2 0x4 31 #define BIT_3 0x8 32 #define BIT_4 0x10 33 #define BIT_5 0x20 34 #define BIT_6 0x40 35 #define BIT_7 0x80 36 #define BIT_8 0x100 37 #define BIT_9 0x200 38 #define BIT_10 0x400 39 #define BIT_11 0x800 40 #define BIT_12 0x1000 41 #define BIT_13 0x2000 42 #define BIT_14 0x4000 43 #define BIT_15 0x8000 44 #define BIT_16 0x10000 45 #define BIT_17 0x20000 46 #define BIT_18 0x40000 47 #define BIT_19 0x80000 48 #define BIT_20 0x100000 49 #define BIT_21 0x200000 50 #define BIT_22 0x400000 51 #define BIT_23 0x800000 52 #define BIT_24 0x1000000 53 #define BIT_25 0x2000000 54 #define BIT_26 0x4000000 55 #define BIT_27 0x8000000 56 #define BIT_28 0x10000000 57 #define BIT_29 0x20000000 58 #define BIT_30 0x40000000 59 #define BIT_31 0x80000000 60 61 #if MEMORY_MAPPED_IO 62 #define RD_REG_WORD(addr) readw(addr) 63 #define WRT_REG_WORD(addr, data) writew(data, addr) 64 #else /* MEMORY_MAPPED_IO */ 65 #define RD_REG_WORD(addr) inw((unsigned long)addr) 66 #define WRT_REG_WORD(addr, data) outw(data, (unsigned long)addr) 67 #endif /* MEMORY_MAPPED_IO */ 68 69 /* 70 * Host adapter default definitions. 71 */ 72 #define MAX_BUSES 2 /* 2 */ 73 #define MAX_B_BITS 1 74 75 #define MAX_TARGETS 16 /* 16 */ 76 #define MAX_T_BITS 4 /* 4 */ 77 78 #define MAX_LUNS 8 /* 32 */ 79 #define MAX_L_BITS 3 /* 5 */ 80 81 /* 82 * Watchdog time quantum 83 */ 84 #define QLA1280_WDG_TIME_QUANTUM 5 /* In seconds */ 85 86 /* Command retry count (0-65535) */ 87 #define COMMAND_RETRY_COUNT 255 88 89 /* Maximum outstanding commands in ISP queues */ 90 #define MAX_OUTSTANDING_COMMANDS 512 91 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS + 2) 92 93 /* ISP request and response entry counts (37-65535) */ 94 #define REQUEST_ENTRY_CNT 256 /* Number of request entries. */ 95 #define RESPONSE_ENTRY_CNT 16 /* Number of response entries. */ 96 97 /* Number of segments 1 - 65535 */ 98 #define SG_SEGMENTS 32 /* Cmd entry + 6 continuations */ 99 100 /* 101 * SCSI Request Block structure (sp) that is placed 102 * on cmd->SCp location of every I/O 103 */ 104 struct srb { 105 Scsi_Cmnd *cmd; /* (4/8) SCSI command block */ 106 struct srb *s_next; /* (4/8) Next block on LU queue */ 107 struct srb *s_prev; /* (4/8) Previous block on LU queue */ 108 uint8_t flags; /* (1) Status flags. */ 109 uint8_t dir; /* direction of transfer */ 110 /* 111 * This should be moved around to save space. 112 */ 113 dma_addr_t saved_dma_handle; /* for unmap of single transfers */ 114 /* NOTE: the sp->cmd will be NULL when this completion is 115 * called, so you should know the scsi_cmnd when using this */ 116 struct completion *wait; 117 }; 118 119 /* 120 * SRB flag definitions 121 */ 122 #define SRB_TIMEOUT BIT_0 /* Command timed out */ 123 #define SRB_SENT BIT_1 /* Command sent to ISP */ 124 #define SRB_ABORT_PENDING BIT_2 /* Command abort sent to device */ 125 #define SRB_ABORTED BIT_3 /* Command aborted command already */ 126 127 /* 128 * Logical Unit Queue structure 129 */ 130 struct scsi_lu { 131 struct srb *q_first; /* First block on LU queue */ 132 struct srb *q_last; /* Last block on LU queue */ 133 uint8_t q_flag; /* LU queue state flags */ 134 uint8_t q_sense[16]; /* sense data */ 135 unsigned long io_cnt; /* total xfer count */ 136 unsigned long resp_time;/* total response time (start - finish) */ 137 unsigned long act_time; /* total actived time (minus queuing time) */ 138 unsigned long w_cnt; /* total writes */ 139 unsigned long r_cnt; /* total reads */ 140 uint16_t q_outcnt; /* Pending jobs for this LU */ 141 }; 142 143 /* 144 * Logical Unit flags 145 */ 146 #define QLA1280_QBUSY BIT_0 147 #define QLA1280_QWAIT BIT_1 148 #define QLA1280_QSUSP BIT_2 149 #define QLA1280_QSENSE BIT_3 /* Sense data cache valid */ 150 #define QLA1280_QRESET BIT_4 151 #define QLA1280_QHBA BIT_5 152 #define QLA1280_BSUSP BIT_6 /* controller is suspended */ 153 #define QLA1280_BREM BIT_7 /* controller is removed */ 154 155 /* 156 * ISP I/O Register Set structure definitions. 157 */ 158 struct device_reg { 159 uint16_t id_l; /* ID low */ 160 uint16_t id_h; /* ID high */ 161 uint16_t cfg_0; /* Configuration 0 */ 162 uint16_t cfg_1; /* Configuration 1 */ 163 uint16_t ictrl; /* Interface control */ 164 #define ISP_RESET BIT_0 /* ISP soft reset */ 165 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */ 166 #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */ 167 #define ISP_FLASH_ENABLE BIT_8 /* Flash BIOS Read/Write enable */ 168 #define ISP_FLASH_UPPER BIT_9 /* Flash upper bank select */ 169 uint16_t istatus; /* Interface status */ 170 #define PCI_64BIT_SLOT BIT_14 /* PCI 64-bit slot indicator. */ 171 #define RISC_INT BIT_2 /* RISC interrupt */ 172 #define PCI_INT BIT_1 /* PCI interrupt */ 173 uint16_t semaphore; /* Semaphore */ 174 uint16_t nvram; /* NVRAM register. */ 175 #define NV_DESELECT 0 176 #define NV_CLOCK BIT_0 177 #define NV_SELECT BIT_1 178 #define NV_DATA_OUT BIT_2 179 #define NV_DATA_IN BIT_3 180 uint16_t flash_data; /* Flash BIOS data */ 181 uint16_t flash_address; /* Flash BIOS address */ 182 183 uint16_t unused_1[0x2e]; /* 0x14-0x6f Gap */ 184 185 uint16_t mailbox0; /* Mailbox 0 */ 186 uint16_t mailbox1; /* Mailbox 1 */ 187 uint16_t mailbox2; /* Mailbox 2 */ 188 uint16_t mailbox3; /* Mailbox 3 */ 189 uint16_t mailbox4; /* Mailbox 4 */ 190 uint16_t mailbox5; /* Mailbox 5 */ 191 uint16_t mailbox6; /* Mailbox 6 */ 192 uint16_t mailbox7; /* Mailbox 7 */ 193 194 uint16_t unused_2[0x20];/* 0x80-0xbf Gap */ 195 196 uint16_t host_cmd; /* Host command and control */ 197 #define HOST_INT BIT_7 /* host interrupt bit */ 198 #define BIOS_ENABLE BIT_0 199 200 uint16_t unused_6[0x5]; /* 0xc2-0xcb Gap */ 201 202 uint16_t gpio_data; 203 uint16_t gpio_enable; 204 205 uint16_t unused_7[0x11]; /* d0-f0 */ 206 uint16_t scsiControlPins; /* f2 */ 207 }; 208 209 #define MAILBOX_REGISTER_COUNT 8 210 211 /* 212 * ISP product identification definitions in mailboxes after reset. 213 */ 214 #define PROD_ID_1 0x4953 215 #define PROD_ID_2 0x0000 216 #define PROD_ID_2a 0x5020 217 #define PROD_ID_3 0x2020 218 #define PROD_ID_4 0x1 219 220 /* 221 * ISP host command and control register command definitions 222 */ 223 #define HC_RESET_RISC 0x1000 /* Reset RISC */ 224 #define HC_PAUSE_RISC 0x2000 /* Pause RISC */ 225 #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 226 #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */ 227 #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 228 #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 229 #define HC_DISABLE_BIOS 0x9000 /* Disable BIOS. */ 230 231 /* 232 * ISP mailbox Self-Test status codes 233 */ 234 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 235 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 236 #define MBS_SHADOW_LD_ERR 2 /* Shadow Load Error. */ 237 #define MBS_BUSY 4 /* Busy. */ 238 239 /* 240 * ISP mailbox command complete status codes 241 */ 242 #define MBS_CMD_CMP 0x4000 /* Command Complete. */ 243 #define MBS_INV_CMD 0x4001 /* Invalid Command. */ 244 #define MBS_HOST_INF_ERR 0x4002 /* Host Interface Error. */ 245 #define MBS_TEST_FAILED 0x4003 /* Test Failed. */ 246 #define MBS_CMD_ERR 0x4005 /* Command Error. */ 247 #define MBS_CMD_PARAM_ERR 0x4006 /* Command Parameter Error. */ 248 249 /* 250 * ISP mailbox asynchronous event status codes 251 */ 252 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 253 #define MBA_BUS_RESET 0x8001 /* SCSI Bus Reset. */ 254 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 255 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 256 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 257 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 258 #define MBA_TIMEOUT_RESET 0x8006 /* Execution Timeout Reset. */ 259 #define MBA_DEVICE_RESET 0x8007 /* Bus Device Reset. */ 260 #define MBA_BUS_MODE_CHANGE 0x800E /* SCSI bus mode transition. */ 261 #define MBA_SCSI_COMPLETION 0x8020 /* Completion response. */ 262 263 /* 264 * ISP mailbox commands 265 */ 266 #define MBC_NOP 0 /* No Operation */ 267 #define MBC_LOAD_RAM 1 /* Load RAM */ 268 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware */ 269 #define MBC_DUMP_RAM 3 /* Dump RAM contents */ 270 #define MBC_WRITE_RAM_WORD 4 /* Write ram word */ 271 #define MBC_READ_RAM_WORD 5 /* Read ram word */ 272 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 273 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum */ 274 #define MBC_ABOUT_FIRMWARE 8 /* Get firmware revision */ 275 #define MBC_INIT_REQUEST_QUEUE 0x10 /* Initialize request queue */ 276 #define MBC_INIT_RESPONSE_QUEUE 0x11 /* Initialize response queue */ 277 #define MBC_EXECUTE_IOCB 0x12 /* Execute IOCB command */ 278 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command */ 279 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN) */ 280 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID) */ 281 #define MBC_BUS_RESET 0x18 /* SCSI bus reset */ 282 #define MBC_GET_RETRY_COUNT 0x22 /* Get retry count and delay */ 283 #define MBC_GET_TARGET_PARAMETERS 0x28 /* Get target parameters */ 284 #define MBC_SET_INITIATOR_ID 0x30 /* Set initiator SCSI ID */ 285 #define MBC_SET_SELECTION_TIMEOUT 0x31 /* Set selection timeout */ 286 #define MBC_SET_RETRY_COUNT 0x32 /* Set retry count and delay */ 287 #define MBC_SET_TAG_AGE_LIMIT 0x33 /* Set tag age limit */ 288 #define MBC_SET_CLOCK_RATE 0x34 /* Set clock rate */ 289 #define MBC_SET_ACTIVE_NEGATION 0x35 /* Set active negation state */ 290 #define MBC_SET_ASYNC_DATA_SETUP 0x36 /* Set async data setup time */ 291 #define MBC_SET_PCI_CONTROL 0x37 /* Set BUS control parameters */ 292 #define MBC_SET_TARGET_PARAMETERS 0x38 /* Set target parameters */ 293 #define MBC_SET_DEVICE_QUEUE 0x39 /* Set device queue parameters */ 294 #define MBC_SET_RESET_DELAY_PARAMETERS 0x3A /* Set reset delay parameters */ 295 #define MBC_SET_SYSTEM_PARAMETER 0x45 /* Set system parameter word */ 296 #define MBC_SET_FIRMWARE_FEATURES 0x4A /* Set firmware feature word */ 297 #define MBC_INIT_REQUEST_QUEUE_A64 0x52 /* Initialize request queue A64 */ 298 #define MBC_INIT_RESPONSE_QUEUE_A64 0x53 /* Initialize response q A64 */ 299 #define MBC_ENABLE_TARGET_MODE 0x55 /* Enable target mode */ 300 #define MBC_SET_DATA_OVERRUN_RECOVERY 0x5A /* Set data overrun recovery mode */ 301 302 /* 303 * ISP Get/Set Target Parameters mailbox command control flags. 304 */ 305 #define TP_PPR BIT_5 /* PPR */ 306 #define TP_RENEGOTIATE BIT_8 /* Renegotiate on error. */ 307 #define TP_STOP_QUEUE BIT_9 /* Stop que on check condition */ 308 #define TP_AUTO_REQUEST_SENSE BIT_10 /* Automatic request sense. */ 309 #define TP_TAGGED_QUEUE BIT_11 /* Tagged queuing. */ 310 #define TP_SYNC BIT_12 /* Synchronous data transfers. */ 311 #define TP_WIDE BIT_13 /* Wide data transfers. */ 312 #define TP_PARITY BIT_14 /* Parity checking. */ 313 #define TP_DISCONNECT BIT_15 /* Disconnect privilege. */ 314 315 /* 316 * NVRAM Command values. 317 */ 318 #define NV_START_BIT BIT_2 319 #define NV_WRITE_OP (BIT_26 | BIT_24) 320 #define NV_READ_OP (BIT_26 | BIT_25) 321 #define NV_ERASE_OP (BIT_26 | BIT_25 | BIT_24) 322 #define NV_MASK_OP (BIT_26 | BIT_25 | BIT_24) 323 #define NV_DELAY_COUNT 10 324 325 /* 326 * QLogic ISP1280/ISP12160 NVRAM structure definition. 327 */ 328 struct nvram { 329 uint8_t id0; /* 0 */ 330 uint8_t id1; /* 1 */ 331 uint8_t id2; /* 2 */ 332 uint8_t id3; /* 3 */ 333 uint8_t version; /* 4 */ 334 335 struct { 336 uint8_t bios_configuration_mode:2; 337 uint8_t bios_disable:1; 338 uint8_t selectable_scsi_boot_enable:1; 339 uint8_t cd_rom_boot_enable:1; 340 uint8_t disable_loading_risc_code:1; 341 uint8_t enable_64bit_addressing:1; 342 uint8_t unused_7:1; 343 } cntr_flags_1; /* 5 */ 344 345 struct { 346 uint16_t boot_lun_number:5; 347 uint16_t scsi_bus_number:1; 348 uint16_t unused_6:1; 349 uint16_t unused_7:1; 350 uint16_t boot_target_number:4; 351 uint16_t unused_12:1; 352 uint16_t unused_13:1; 353 uint16_t unused_14:1; 354 uint16_t unused_15:1; 355 } cntr_flags_2; /* 6, 7 */ 356 357 uint16_t unused_8; /* 8, 9 */ 358 uint16_t unused_10; /* 10, 11 */ 359 uint16_t unused_12; /* 12, 13 */ 360 uint16_t unused_14; /* 14, 15 */ 361 362 union { 363 uint8_t c; 364 struct { 365 uint8_t reserved:2; 366 uint8_t burst_enable:1; 367 uint8_t reserved_1:1; 368 uint8_t fifo_threshold:4; 369 } f; 370 } isp_config; /* 16 */ 371 372 /* Termination 373 * 0 = Disable, 1 = high only, 3 = Auto term 374 */ 375 union { 376 uint8_t c; 377 struct { 378 uint8_t scsi_bus_1_control:2; 379 uint8_t scsi_bus_0_control:2; 380 uint8_t unused_0:1; 381 uint8_t unused_1:1; 382 uint8_t unused_2:1; 383 uint8_t auto_term_support:1; 384 } f; 385 } termination; /* 17 */ 386 387 uint16_t isp_parameter; /* 18, 19 */ 388 389 union { 390 uint16_t w; 391 struct { 392 uint16_t enable_fast_posting:1; 393 uint16_t report_lvd_bus_transition:1; 394 uint16_t unused_2:1; 395 uint16_t unused_3:1; 396 uint16_t disable_iosbs_with_bus_reset_status:1; 397 uint16_t disable_synchronous_backoff:1; 398 uint16_t unused_6:1; 399 uint16_t synchronous_backoff_reporting:1; 400 uint16_t disable_reselection_fairness:1; 401 uint16_t unused_9:1; 402 uint16_t unused_10:1; 403 uint16_t unused_11:1; 404 uint16_t unused_12:1; 405 uint16_t unused_13:1; 406 uint16_t unused_14:1; 407 uint16_t unused_15:1; 408 } f; 409 } firmware_feature; /* 20, 21 */ 410 411 uint16_t unused_22; /* 22, 23 */ 412 413 struct { 414 struct { 415 uint8_t initiator_id:4; 416 uint8_t scsi_reset_disable:1; 417 uint8_t scsi_bus_size:1; 418 uint8_t scsi_bus_type:1; 419 uint8_t unused_7:1; 420 } config_1; /* 24 */ 421 422 uint8_t bus_reset_delay; /* 25 */ 423 uint8_t retry_count; /* 26 */ 424 uint8_t retry_delay; /* 27 */ 425 426 struct { 427 uint8_t async_data_setup_time:4; 428 uint8_t req_ack_active_negation:1; 429 uint8_t data_line_active_negation:1; 430 uint8_t unused_6:1; 431 uint8_t unused_7:1; 432 } config_2; /* 28 */ 433 434 uint8_t unused_29; /* 29 */ 435 436 uint16_t selection_timeout; /* 30, 31 */ 437 uint16_t max_queue_depth; /* 32, 33 */ 438 439 uint16_t unused_34; /* 34, 35 */ 440 uint16_t unused_36; /* 36, 37 */ 441 uint16_t unused_38; /* 38, 39 */ 442 443 struct { 444 union { 445 uint8_t c; 446 struct { 447 uint8_t renegotiate_on_error:1; 448 uint8_t stop_queue_on_check:1; 449 uint8_t auto_request_sense:1; 450 uint8_t tag_queuing:1; 451 uint8_t enable_sync:1; 452 uint8_t enable_wide:1; 453 uint8_t parity_checking:1; 454 uint8_t disconnect_allowed:1; 455 } f; 456 } parameter; /* 40 */ 457 458 uint8_t execution_throttle; /* 41 */ 459 uint8_t sync_period; /* 42 */ 460 461 union { /* 43 */ 462 uint8_t flags_43; 463 struct { 464 uint8_t sync_offset:4; 465 uint8_t device_enable:1; 466 uint8_t lun_disable:1; 467 uint8_t unused_6:1; 468 uint8_t unused_7:1; 469 } flags1x80; 470 struct { 471 uint8_t sync_offset:5; 472 uint8_t device_enable:1; 473 uint8_t unused_6:1; 474 uint8_t unused_7:1; 475 } flags1x160; 476 } flags; 477 union { /* PPR flags for the 1x160 controllers */ 478 uint8_t unused_44; 479 struct { 480 uint8_t ppr_options:4; 481 uint8_t ppr_bus_width:2; 482 uint8_t unused_8:1; 483 uint8_t enable_ppr:1; 484 } flags; /* 44 */ 485 } ppr_1x160; 486 uint8_t unused_45; /* 45 */ 487 } target[MAX_TARGETS]; 488 } bus[MAX_BUSES]; 489 490 uint16_t unused_248; /* 248, 249 */ 491 492 uint16_t subsystem_id[2]; /* 250, 251, 252, 253 */ 493 494 union { /* 254 */ 495 uint8_t unused_254; 496 uint8_t system_id_pointer; 497 } sysid_1x160; 498 499 uint8_t chksum; /* 255 */ 500 }; 501 502 /* 503 * ISP queue - command entry structure definition. 504 */ 505 #define MAX_CMDSZ 12 /* SCSI maximum CDB size. */ 506 struct cmd_entry { 507 uint8_t entry_type; /* Entry type. */ 508 #define COMMAND_TYPE 1 /* Command entry */ 509 uint8_t entry_count; /* Entry count. */ 510 uint8_t sys_define; /* System defined. */ 511 uint8_t entry_status; /* Entry Status. */ 512 uint32_t handle; /* System handle. */ 513 uint8_t lun; /* SCSI LUN */ 514 uint8_t target; /* SCSI ID */ 515 uint16_t cdb_len; /* SCSI command length. */ 516 uint16_t control_flags; /* Control flags. */ 517 uint16_t reserved; 518 uint16_t timeout; /* Command timeout. */ 519 uint16_t dseg_count; /* Data segment count. */ 520 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 521 uint32_t dseg_0_address; /* Data segment 0 address. */ 522 uint32_t dseg_0_length; /* Data segment 0 length. */ 523 uint32_t dseg_1_address; /* Data segment 1 address. */ 524 uint32_t dseg_1_length; /* Data segment 1 length. */ 525 uint32_t dseg_2_address; /* Data segment 2 address. */ 526 uint32_t dseg_2_length; /* Data segment 2 length. */ 527 uint32_t dseg_3_address; /* Data segment 3 address. */ 528 uint32_t dseg_3_length; /* Data segment 3 length. */ 529 }; 530 531 /* 532 * ISP queue - continuation entry structure definition. 533 */ 534 struct cont_entry { 535 uint8_t entry_type; /* Entry type. */ 536 #define CONTINUE_TYPE 2 /* Continuation entry. */ 537 uint8_t entry_count; /* Entry count. */ 538 uint8_t sys_define; /* System defined. */ 539 uint8_t entry_status; /* Entry Status. */ 540 uint32_t reserved; /* Reserved */ 541 uint32_t dseg_0_address; /* Data segment 0 address. */ 542 uint32_t dseg_0_length; /* Data segment 0 length. */ 543 uint32_t dseg_1_address; /* Data segment 1 address. */ 544 uint32_t dseg_1_length; /* Data segment 1 length. */ 545 uint32_t dseg_2_address; /* Data segment 2 address. */ 546 uint32_t dseg_2_length; /* Data segment 2 length. */ 547 uint32_t dseg_3_address; /* Data segment 3 address. */ 548 uint32_t dseg_3_length; /* Data segment 3 length. */ 549 uint32_t dseg_4_address; /* Data segment 4 address. */ 550 uint32_t dseg_4_length; /* Data segment 4 length. */ 551 uint32_t dseg_5_address; /* Data segment 5 address. */ 552 uint32_t dseg_5_length; /* Data segment 5 length. */ 553 uint32_t dseg_6_address; /* Data segment 6 address. */ 554 uint32_t dseg_6_length; /* Data segment 6 length. */ 555 }; 556 557 /* 558 * ISP queue - status entry structure definition. 559 */ 560 struct response { 561 uint8_t entry_type; /* Entry type. */ 562 #define STATUS_TYPE 3 /* Status entry. */ 563 uint8_t entry_count; /* Entry count. */ 564 uint8_t sys_define; /* System defined. */ 565 uint8_t entry_status; /* Entry Status. */ 566 #define RF_CONT BIT_0 /* Continuation. */ 567 #define RF_FULL BIT_1 /* Full */ 568 #define RF_BAD_HEADER BIT_2 /* Bad header. */ 569 #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */ 570 uint32_t handle; /* System handle. */ 571 uint16_t scsi_status; /* SCSI status. */ 572 uint16_t comp_status; /* Completion status. */ 573 uint16_t state_flags; /* State flags. */ 574 #define SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */ 575 #define SF_GOT_SENSE BIT_13 /* Got Sense */ 576 #define SF_GOT_STATUS BIT_12 /* Got Status */ 577 #define SF_TRANSFERRED_DATA BIT_11 /* Transferred data */ 578 #define SF_SENT_CDB BIT_10 /* Send CDB */ 579 #define SF_GOT_TARGET BIT_9 /* */ 580 #define SF_GOT_BUS BIT_8 /* */ 581 uint16_t status_flags; /* Status flags. */ 582 uint16_t time; /* Time. */ 583 uint16_t req_sense_length; /* Request sense data length. */ 584 uint32_t residual_length; /* Residual transfer length. */ 585 uint16_t reserved[4]; 586 uint8_t req_sense_data[32]; /* Request sense data. */ 587 }; 588 589 /* 590 * ISP queue - marker entry structure definition. 591 */ 592 struct mrk_entry { 593 uint8_t entry_type; /* Entry type. */ 594 #define MARKER_TYPE 4 /* Marker entry. */ 595 uint8_t entry_count; /* Entry count. */ 596 uint8_t sys_define; /* System defined. */ 597 uint8_t entry_status; /* Entry Status. */ 598 uint32_t reserved; 599 uint8_t lun; /* SCSI LUN */ 600 uint8_t target; /* SCSI ID */ 601 uint8_t modifier; /* Modifier (7-0). */ 602 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 603 #define MK_SYNC_ID 1 /* Synchronize ID */ 604 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 605 uint8_t reserved_1[53]; 606 }; 607 608 /* 609 * ISP queue - extended command entry structure definition. 610 * 611 * Unused by the driver! 612 */ 613 struct ecmd_entry { 614 uint8_t entry_type; /* Entry type. */ 615 #define EXTENDED_CMD_TYPE 5 /* Extended command entry. */ 616 uint8_t entry_count; /* Entry count. */ 617 uint8_t sys_define; /* System defined. */ 618 uint8_t entry_status; /* Entry Status. */ 619 uint32_t handle; /* System handle. */ 620 uint8_t lun; /* SCSI LUN */ 621 uint8_t target; /* SCSI ID */ 622 uint16_t cdb_len; /* SCSI command length. */ 623 uint16_t control_flags; /* Control flags. */ 624 uint16_t reserved; 625 uint16_t timeout; /* Command timeout. */ 626 uint16_t dseg_count; /* Data segment count. */ 627 uint8_t scsi_cdb[88]; /* SCSI command words. */ 628 }; 629 630 /* 631 * ISP queue - 64-Bit addressing, command entry structure definition. 632 */ 633 typedef struct { 634 uint8_t entry_type; /* Entry type. */ 635 #define COMMAND_A64_TYPE 9 /* Command A64 entry */ 636 uint8_t entry_count; /* Entry count. */ 637 uint8_t sys_define; /* System defined. */ 638 uint8_t entry_status; /* Entry Status. */ 639 uint32_t handle; /* System handle. */ 640 uint8_t lun; /* SCSI LUN */ 641 uint8_t target; /* SCSI ID */ 642 uint16_t cdb_len; /* SCSI command length. */ 643 uint16_t control_flags; /* Control flags. */ 644 uint16_t reserved; 645 uint16_t timeout; /* Command timeout. */ 646 uint16_t dseg_count; /* Data segment count. */ 647 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 648 uint32_t reserved_1[2]; /* unused */ 649 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 650 uint32_t dseg_0_length; /* Data segment 0 length. */ 651 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 652 uint32_t dseg_1_length; /* Data segment 1 length. */ 653 } cmd_a64_entry_t, request_t; 654 655 /* 656 * ISP queue - 64-Bit addressing, continuation entry structure definition. 657 */ 658 struct cont_a64_entry { 659 uint8_t entry_type; /* Entry type. */ 660 #define CONTINUE_A64_TYPE 0xA /* Continuation A64 entry. */ 661 uint8_t entry_count; /* Entry count. */ 662 uint8_t sys_define; /* System defined. */ 663 uint8_t entry_status; /* Entry Status. */ 664 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 665 uint32_t dseg_0_length; /* Data segment 0 length. */ 666 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 667 uint32_t dseg_1_length; /* Data segment 1 length. */ 668 uint32_t dseg_2_address[2]; /* Data segment 2 address. */ 669 uint32_t dseg_2_length; /* Data segment 2 length. */ 670 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 671 uint32_t dseg_3_length; /* Data segment 3 length. */ 672 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 673 uint32_t dseg_4_length; /* Data segment 4 length. */ 674 }; 675 676 /* 677 * ISP queue - enable LUN entry structure definition. 678 */ 679 struct elun_entry { 680 uint8_t entry_type; /* Entry type. */ 681 #define ENABLE_LUN_TYPE 0xB /* Enable LUN entry. */ 682 uint8_t entry_count; /* Entry count. */ 683 uint8_t reserved_1; 684 uint8_t entry_status; /* Entry Status not used. */ 685 uint32_t reserved_2; 686 uint16_t lun; /* Bit 15 is bus number. */ 687 uint16_t reserved_4; 688 uint32_t option_flags; 689 uint8_t status; 690 uint8_t reserved_5; 691 uint8_t command_count; /* Number of ATIOs allocated. */ 692 uint8_t immed_notify_count; /* Number of Immediate Notify */ 693 /* entries allocated. */ 694 uint8_t group_6_length; /* SCSI CDB length for group 6 */ 695 /* commands (2-26). */ 696 uint8_t group_7_length; /* SCSI CDB length for group 7 */ 697 /* commands (2-26). */ 698 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 699 uint16_t reserved_6[20]; 700 }; 701 702 /* 703 * ISP queue - modify LUN entry structure definition. 704 * 705 * Unused by the driver! 706 */ 707 struct modify_lun_entry { 708 uint8_t entry_type; /* Entry type. */ 709 #define MODIFY_LUN_TYPE 0xC /* Modify LUN entry. */ 710 uint8_t entry_count; /* Entry count. */ 711 uint8_t reserved_1; 712 uint8_t entry_status; /* Entry Status. */ 713 uint32_t reserved_2; 714 uint8_t lun; /* SCSI LUN */ 715 uint8_t reserved_3; 716 uint8_t operators; 717 uint8_t reserved_4; 718 uint32_t option_flags; 719 uint8_t status; 720 uint8_t reserved_5; 721 uint8_t command_count; /* Number of ATIOs allocated. */ 722 uint8_t immed_notify_count; /* Number of Immediate Notify */ 723 /* entries allocated. */ 724 uint16_t reserved_6; 725 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 726 uint16_t reserved_7[20]; 727 }; 728 729 /* 730 * ISP queue - immediate notify entry structure definition. 731 */ 732 struct notify_entry { 733 uint8_t entry_type; /* Entry type. */ 734 #define IMMED_NOTIFY_TYPE 0xD /* Immediate notify entry. */ 735 uint8_t entry_count; /* Entry count. */ 736 uint8_t reserved_1; 737 uint8_t entry_status; /* Entry Status. */ 738 uint32_t reserved_2; 739 uint8_t lun; 740 uint8_t initiator_id; 741 uint8_t reserved_3; 742 uint8_t target_id; 743 uint32_t option_flags; 744 uint8_t status; 745 uint8_t reserved_4; 746 uint8_t tag_value; /* Received queue tag message value */ 747 uint8_t tag_type; /* Received queue tag message type */ 748 /* entries allocated. */ 749 uint16_t seq_id; 750 uint8_t scsi_msg[8]; /* SCSI message not handled by ISP */ 751 uint16_t reserved_5[8]; 752 uint8_t sense_data[18]; 753 }; 754 755 /* 756 * ISP queue - notify acknowledge entry structure definition. 757 */ 758 struct nack_entry { 759 uint8_t entry_type; /* Entry type. */ 760 #define NOTIFY_ACK_TYPE 0xE /* Notify acknowledge entry. */ 761 uint8_t entry_count; /* Entry count. */ 762 uint8_t reserved_1; 763 uint8_t entry_status; /* Entry Status. */ 764 uint32_t reserved_2; 765 uint8_t lun; 766 uint8_t initiator_id; 767 uint8_t reserved_3; 768 uint8_t target_id; 769 uint32_t option_flags; 770 uint8_t status; 771 uint8_t event; 772 uint16_t seq_id; 773 uint16_t reserved_4[22]; 774 }; 775 776 /* 777 * ISP queue - Accept Target I/O (ATIO) entry structure definition. 778 */ 779 struct atio_entry { 780 uint8_t entry_type; /* Entry type. */ 781 #define ACCEPT_TGT_IO_TYPE 6 /* Accept target I/O entry. */ 782 uint8_t entry_count; /* Entry count. */ 783 uint8_t reserved_1; 784 uint8_t entry_status; /* Entry Status. */ 785 uint32_t reserved_2; 786 uint8_t lun; 787 uint8_t initiator_id; 788 uint8_t cdb_len; 789 uint8_t target_id; 790 uint32_t option_flags; 791 uint8_t status; 792 uint8_t scsi_status; 793 uint8_t tag_value; /* Received queue tag message value */ 794 uint8_t tag_type; /* Received queue tag message type */ 795 uint8_t cdb[26]; 796 uint8_t sense_data[18]; 797 }; 798 799 /* 800 * ISP queue - Continue Target I/O (CTIO) entry structure definition. 801 */ 802 struct ctio_entry { 803 uint8_t entry_type; /* Entry type. */ 804 #define CONTINUE_TGT_IO_TYPE 7 /* CTIO entry */ 805 uint8_t entry_count; /* Entry count. */ 806 uint8_t reserved_1; 807 uint8_t entry_status; /* Entry Status. */ 808 uint32_t reserved_2; 809 uint8_t lun; /* SCSI LUN */ 810 uint8_t initiator_id; 811 uint8_t reserved_3; 812 uint8_t target_id; 813 uint32_t option_flags; 814 uint8_t status; 815 uint8_t scsi_status; 816 uint8_t tag_value; /* Received queue tag message value */ 817 uint8_t tag_type; /* Received queue tag message type */ 818 uint32_t transfer_length; 819 uint32_t residual; 820 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 821 uint16_t dseg_count; /* Data segment count. */ 822 uint32_t dseg_0_address; /* Data segment 0 address. */ 823 uint32_t dseg_0_length; /* Data segment 0 length. */ 824 uint32_t dseg_1_address; /* Data segment 1 address. */ 825 uint32_t dseg_1_length; /* Data segment 1 length. */ 826 uint32_t dseg_2_address; /* Data segment 2 address. */ 827 uint32_t dseg_2_length; /* Data segment 2 length. */ 828 uint32_t dseg_3_address; /* Data segment 3 address. */ 829 uint32_t dseg_3_length; /* Data segment 3 length. */ 830 }; 831 832 /* 833 * ISP queue - CTIO returned entry structure definition. 834 */ 835 struct ctio_ret_entry { 836 uint8_t entry_type; /* Entry type. */ 837 #define CTIO_RET_TYPE 7 /* CTIO return entry */ 838 uint8_t entry_count; /* Entry count. */ 839 uint8_t reserved_1; 840 uint8_t entry_status; /* Entry Status. */ 841 uint32_t reserved_2; 842 uint8_t lun; /* SCSI LUN */ 843 uint8_t initiator_id; 844 uint8_t reserved_3; 845 uint8_t target_id; 846 uint32_t option_flags; 847 uint8_t status; 848 uint8_t scsi_status; 849 uint8_t tag_value; /* Received queue tag message value */ 850 uint8_t tag_type; /* Received queue tag message type */ 851 uint32_t transfer_length; 852 uint32_t residual; 853 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 854 uint16_t dseg_count; /* Data segment count. */ 855 uint32_t dseg_0_address; /* Data segment 0 address. */ 856 uint32_t dseg_0_length; /* Data segment 0 length. */ 857 uint32_t dseg_1_address; /* Data segment 1 address. */ 858 uint16_t dseg_1_length; /* Data segment 1 length. */ 859 uint8_t sense_data[18]; 860 }; 861 862 /* 863 * ISP queue - CTIO A64 entry structure definition. 864 */ 865 struct ctio_a64_entry { 866 uint8_t entry_type; /* Entry type. */ 867 #define CTIO_A64_TYPE 0xF /* CTIO A64 entry */ 868 uint8_t entry_count; /* Entry count. */ 869 uint8_t reserved_1; 870 uint8_t entry_status; /* Entry Status. */ 871 uint32_t reserved_2; 872 uint8_t lun; /* SCSI LUN */ 873 uint8_t initiator_id; 874 uint8_t reserved_3; 875 uint8_t target_id; 876 uint32_t option_flags; 877 uint8_t status; 878 uint8_t scsi_status; 879 uint8_t tag_value; /* Received queue tag message value */ 880 uint8_t tag_type; /* Received queue tag message type */ 881 uint32_t transfer_length; 882 uint32_t residual; 883 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 884 uint16_t dseg_count; /* Data segment count. */ 885 uint32_t reserved_4[2]; 886 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 887 uint32_t dseg_0_length; /* Data segment 0 length. */ 888 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 889 uint32_t dseg_1_length; /* Data segment 1 length. */ 890 }; 891 892 /* 893 * ISP queue - CTIO returned entry structure definition. 894 */ 895 struct ctio_a64_ret_entry { 896 uint8_t entry_type; /* Entry type. */ 897 #define CTIO_A64_RET_TYPE 0xF /* CTIO A64 returned entry */ 898 uint8_t entry_count; /* Entry count. */ 899 uint8_t reserved_1; 900 uint8_t entry_status; /* Entry Status. */ 901 uint32_t reserved_2; 902 uint8_t lun; /* SCSI LUN */ 903 uint8_t initiator_id; 904 uint8_t reserved_3; 905 uint8_t target_id; 906 uint32_t option_flags; 907 uint8_t status; 908 uint8_t scsi_status; 909 uint8_t tag_value; /* Received queue tag message value */ 910 uint8_t tag_type; /* Received queue tag message type */ 911 uint32_t transfer_length; 912 uint32_t residual; 913 uint16_t timeout; /* 0 = 30 seconds, 0xFFFF = disable */ 914 uint16_t dseg_count; /* Data segment count. */ 915 uint16_t reserved_4[7]; 916 uint8_t sense_data[18]; 917 }; 918 919 /* 920 * ISP request and response queue entry sizes 921 */ 922 #define RESPONSE_ENTRY_SIZE (sizeof(struct response)) 923 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 924 925 /* 926 * ISP status entry - completion status definitions. 927 */ 928 #define CS_COMPLETE 0x0 /* No errors */ 929 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 930 #define CS_DMA 0x2 /* A DMA direction error. */ 931 #define CS_TRANSPORT 0x3 /* Transport error. */ 932 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 933 #define CS_ABORTED 0x5 /* System aborted command. */ 934 #define CS_TIMEOUT 0x6 /* Timeout error. */ 935 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 936 #define CS_COMMAND_OVERRUN 0x8 /* Command Overrun. */ 937 #define CS_STATUS_OVERRUN 0x9 /* Status Overrun. */ 938 #define CS_BAD_MSG 0xA /* Bad msg after status phase. */ 939 #define CS_NO_MSG_OUT 0xB /* No msg out after selection. */ 940 #define CS_EXTENDED_ID 0xC /* Extended ID failed. */ 941 #define CS_IDE_MSG 0xD /* Target rejected IDE msg. */ 942 #define CS_ABORT_MSG 0xE /* Target rejected abort msg. */ 943 #define CS_REJECT_MSG 0xF /* Target rejected reject msg. */ 944 #define CS_NOP_MSG 0x10 /* Target rejected NOP msg. */ 945 #define CS_PARITY_MSG 0x11 /* Target rejected parity msg. */ 946 #define CS_DEV_RESET_MSG 0x12 /* Target rejected dev rst msg. */ 947 #define CS_ID_MSG 0x13 /* Target rejected ID msg. */ 948 #define CS_FREE 0x14 /* Unexpected bus free. */ 949 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 950 #define CS_TRANACTION_1 0x18 /* Transaction error 1 */ 951 #define CS_TRANACTION_2 0x19 /* Transaction error 2 */ 952 #define CS_TRANACTION_3 0x1a /* Transaction error 3 */ 953 #define CS_INV_ENTRY_TYPE 0x1b /* Invalid entry type */ 954 #define CS_DEV_QUEUE_FULL 0x1c /* Device queue full */ 955 #define CS_PHASED_SKIPPED 0x1d /* SCSI phase skipped */ 956 #define CS_ARS_FAILED 0x1e /* ARS failed */ 957 #define CS_LVD_BUS_ERROR 0x21 /* LVD bus error */ 958 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 959 #define CS_UNKNOWN 0x81 /* Driver defined */ 960 #define CS_RETRY 0x82 /* Driver defined */ 961 962 /* 963 * ISP status entry - SCSI status byte bit definitions. 964 */ 965 #define SS_CHECK_CONDITION BIT_1 966 #define SS_CONDITION_MET BIT_2 967 #define SS_BUSY_CONDITION BIT_3 968 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 969 970 /* 971 * ISP target entries - Option flags bit definitions. 972 */ 973 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */ 974 #define OF_DATA_IN BIT_6 /* Data in to initiator */ 975 /* (data from target to initiator) */ 976 #define OF_DATA_OUT BIT_7 /* Data out from initiator */ 977 /* (data from initiator to target) */ 978 #define OF_NO_DATA (BIT_7 | BIT_6) 979 #define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */ 980 #define OF_DISABLE_SDP BIT_24 /* Disable sending save data ptr */ 981 #define OF_SEND_RDP BIT_26 /* Send restore data pointers msg */ 982 #define OF_FORCE_DISC BIT_30 /* Disconnects mandatory */ 983 #define OF_SSTS BIT_31 /* Send SCSI status */ 984 985 986 /* 987 * BUS parameters/settings structure - UNUSED 988 */ 989 struct bus_param { 990 uint8_t id; /* Host adapter SCSI id */ 991 uint8_t bus_reset_delay; /* SCSI bus reset delay. */ 992 uint8_t failed_reset_count; /* number of time reset failed */ 993 uint8_t unused; 994 uint16_t device_enables; /* Device enable bits. */ 995 uint16_t lun_disables; /* LUN disable bits. */ 996 uint16_t qtag_enables; /* Tag queue enables. */ 997 uint16_t hiwat; /* High water mark per device. */ 998 uint8_t reset_marker:1; 999 uint8_t disable_scsi_reset:1; 1000 uint8_t scsi_bus_dead:1; /* SCSI Bus is Dead, when 5 back to back resets failed */ 1001 }; 1002 1003 1004 struct qla_driver_setup { 1005 uint32_t no_sync:1; 1006 uint32_t no_wide:1; 1007 uint32_t no_ppr:1; 1008 uint32_t no_nvram:1; 1009 uint16_t sync_mask; 1010 uint16_t wide_mask; 1011 uint16_t ppr_mask; 1012 }; 1013 1014 1015 /* 1016 * Linux Host Adapter structure 1017 */ 1018 struct scsi_qla_host { 1019 /* Linux adapter configuration data */ 1020 struct Scsi_Host *host; /* pointer to host data */ 1021 struct scsi_qla_host *next; 1022 struct device_reg *iobase; /* Base Memory-mapped I/O address */ 1023 1024 unsigned char *mmpbase; /* memory mapped address */ 1025 unsigned long host_no; 1026 unsigned long instance; 1027 struct pci_dev *pdev; 1028 uint32_t device_id; 1029 uint8_t pci_bus; 1030 uint8_t pci_device_fn; 1031 uint8_t devnum; 1032 uint8_t revision; 1033 uint8_t ports; 1034 1035 unsigned long actthreads; 1036 unsigned long isr_count; /* Interrupt count */ 1037 unsigned long spurious_int; 1038 1039 /* Outstandings ISP commands. */ 1040 struct srb *outstanding_cmds[MAX_OUTSTANDING_COMMANDS]; 1041 1042 /* BUS configuration data */ 1043 struct bus_param bus_settings[MAX_BUSES]; 1044 1045 #if 0 1046 /* bottom half run queue */ 1047 struct tq_struct run_qla_bh; 1048 #endif 1049 1050 /* Received ISP mailbox data. */ 1051 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 1052 1053 #ifdef UNUSED 1054 struct timer_list dev_timer[MAX_TARGETS]; 1055 #endif 1056 1057 dma_addr_t request_dma; /* Physical Address */ 1058 request_t *request_ring; /* Base virtual address */ 1059 request_t *request_ring_ptr; /* Current address. */ 1060 uint16_t req_ring_index; /* Current index. */ 1061 uint16_t req_q_cnt; /* Number of available entries. */ 1062 1063 dma_addr_t response_dma; /* Physical address. */ 1064 struct response *response_ring; /* Base virtual address */ 1065 struct response *response_ring_ptr; /* Current address. */ 1066 uint16_t rsp_ring_index; /* Current index. */ 1067 1068 #if WATCHDOGTIMER 1069 /* Watchdog queue, lock and total timer */ 1070 uint8_t watchdog_q_lock; /* Lock for watchdog queue */ 1071 struct srb *wdg_q_first; /* First job on watchdog queue */ 1072 struct srb *wdg_q_last; /* Last job on watchdog queue */ 1073 uint32_t total_timeout; /* Total timeout (quantum count) */ 1074 uint32_t watchdogactive; 1075 #endif 1076 1077 struct srb *done_q_first; /* First job on done queue */ 1078 struct srb *done_q_last; /* Last job on done queue */ 1079 1080 struct completion *mailbox_wait; 1081 1082 volatile struct { 1083 uint32_t mbox_busy:1; /* 0 */ 1084 uint32_t online:1; /* 1 */ 1085 uint32_t reset_marker:1; /* 2 */ 1086 uint32_t disable_host_adapter:1; /* 4 */ 1087 uint32_t reset_active:1; /* 5 */ 1088 uint32_t abort_isp_active:1; /* 6 */ 1089 uint32_t disable_risc_code_load:1; /* 7 */ 1090 uint32_t enable_64bit_addressing:1; /* 8 */ 1091 uint32_t in_reset:1; /* 9 */ 1092 uint32_t ints_enabled:1; 1093 uint32_t ignore_nvram:1; 1094 #ifdef __ia64__ 1095 uint32_t use_pci_vchannel:1; 1096 #endif 1097 } flags; 1098 1099 struct nvram nvram; 1100 int nvram_valid; 1101 }; 1102 1103 /* 1104 * Macros to help code, maintain, etc. 1105 */ 1106 #define SUBDEV(b, t, l) ((b << (MAX_T_BITS + MAX_L_BITS)) | (t << MAX_L_BITS) | l) 1107 #define LU_Q(ha, b, t, l) (ha->dev[SUBDEV(b, t, l)]) 1108 1109 #endif /* HOSTS_C */ 1110 1111 1112 #endif /* _IO_HBA_QLA1280_H */ 1113