1 /*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
18 * Copyright (C) Shaohua Li <shaohua.li@intel.com>
19 */
20
21 #ifndef __DMAR_H__
22 #define __DMAR_H__
23
24 #include <linux/acpi.h>
25 #include <linux/types.h>
26 #include <linux/msi.h>
27 #include <linux/irqreturn.h>
28
29 struct acpi_dmar_header;
30
31 /* DMAR Flags */
32 #define DMAR_INTR_REMAP 0x1
33 #define DMAR_X2APIC_OPT_OUT 0x2
34
35 struct intel_iommu;
36 #ifdef CONFIG_DMAR_TABLE
37 extern struct acpi_table_header *dmar_tbl;
38 struct dmar_drhd_unit {
39 struct list_head list; /* list of drhd units */
40 struct acpi_dmar_header *hdr; /* ACPI header */
41 u64 reg_base_addr; /* register base address*/
42 struct pci_dev **devices; /* target device array */
43 int devices_cnt; /* target device count */
44 u16 segment; /* PCI domain */
45 u8 ignored:1; /* ignore drhd */
46 u8 include_all:1;
47 struct intel_iommu *iommu;
48 };
49
50 extern struct list_head dmar_drhd_units;
51
52 #define for_each_drhd_unit(drhd) \
53 list_for_each_entry(drhd, &dmar_drhd_units, list)
54
55 #define for_each_active_iommu(i, drhd) \
56 list_for_each_entry(drhd, &dmar_drhd_units, list) \
57 if (i=drhd->iommu, drhd->ignored) {} else
58
59 #define for_each_iommu(i, drhd) \
60 list_for_each_entry(drhd, &dmar_drhd_units, list) \
61 if (i=drhd->iommu, 0) {} else
62
63 extern int dmar_table_init(void);
64 extern int dmar_dev_scope_init(void);
65
66 /* Intel IOMMU detection */
67 extern int detect_intel_iommu(void);
68 extern int enable_drhd_fault_handling(void);
69
70 extern int parse_ioapics_under_ir(void);
71 extern int alloc_iommu(struct dmar_drhd_unit *);
72 #else
detect_intel_iommu(void)73 static inline int detect_intel_iommu(void)
74 {
75 return -ENODEV;
76 }
77
dmar_table_init(void)78 static inline int dmar_table_init(void)
79 {
80 return -ENODEV;
81 }
enable_drhd_fault_handling(void)82 static inline int enable_drhd_fault_handling(void)
83 {
84 return -1;
85 }
86 #endif /* !CONFIG_DMAR_TABLE */
87
88 struct irte {
89 union {
90 struct {
91 __u64 present : 1,
92 fpd : 1,
93 dst_mode : 1,
94 redir_hint : 1,
95 trigger_mode : 1,
96 dlvry_mode : 3,
97 avail : 4,
98 __reserved_1 : 4,
99 vector : 8,
100 __reserved_2 : 8,
101 dest_id : 32;
102 };
103 __u64 low;
104 };
105
106 union {
107 struct {
108 __u64 sid : 16,
109 sq : 2,
110 svt : 2,
111 __reserved_3 : 44;
112 };
113 __u64 high;
114 };
115 };
116
117 #ifdef CONFIG_IRQ_REMAP
118 extern int intr_remapping_enabled;
119 extern int intr_remapping_supported(void);
120 extern int enable_intr_remapping(void);
121 extern void disable_intr_remapping(void);
122 extern int reenable_intr_remapping(int);
123
124 extern int get_irte(int irq, struct irte *entry);
125 extern int modify_irte(int irq, struct irte *irte_modified);
126 extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
127 extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
128 u16 sub_handle);
129 extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
130 extern int free_irte(int irq);
131
132 extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
133 extern struct intel_iommu *map_ioapic_to_ir(int apic);
134 extern struct intel_iommu *map_hpet_to_ir(u8 id);
135 extern int set_ioapic_sid(struct irte *irte, int apic);
136 extern int set_hpet_sid(struct irte *irte, u8 id);
137 extern int set_msi_sid(struct irte *irte, struct pci_dev *dev);
138 #else
alloc_irte(struct intel_iommu * iommu,int irq,u16 count)139 static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
140 {
141 return -1;
142 }
modify_irte(int irq,struct irte * irte_modified)143 static inline int modify_irte(int irq, struct irte *irte_modified)
144 {
145 return -1;
146 }
free_irte(int irq)147 static inline int free_irte(int irq)
148 {
149 return -1;
150 }
map_irq_to_irte_handle(int irq,u16 * sub_handle)151 static inline int map_irq_to_irte_handle(int irq, u16 *sub_handle)
152 {
153 return -1;
154 }
set_irte_irq(int irq,struct intel_iommu * iommu,u16 index,u16 sub_handle)155 static inline int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
156 u16 sub_handle)
157 {
158 return -1;
159 }
map_dev_to_ir(struct pci_dev * dev)160 static inline struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
161 {
162 return NULL;
163 }
map_ioapic_to_ir(int apic)164 static inline struct intel_iommu *map_ioapic_to_ir(int apic)
165 {
166 return NULL;
167 }
map_hpet_to_ir(unsigned int hpet_id)168 static inline struct intel_iommu *map_hpet_to_ir(unsigned int hpet_id)
169 {
170 return NULL;
171 }
set_ioapic_sid(struct irte * irte,int apic)172 static inline int set_ioapic_sid(struct irte *irte, int apic)
173 {
174 return 0;
175 }
set_hpet_sid(struct irte * irte,u8 id)176 static inline int set_hpet_sid(struct irte *irte, u8 id)
177 {
178 return -1;
179 }
set_msi_sid(struct irte * irte,struct pci_dev * dev)180 static inline int set_msi_sid(struct irte *irte, struct pci_dev *dev)
181 {
182 return 0;
183 }
184
185 #define intr_remapping_enabled (0)
186
enable_intr_remapping(void)187 static inline int enable_intr_remapping(void)
188 {
189 return -1;
190 }
191
disable_intr_remapping(void)192 static inline void disable_intr_remapping(void)
193 {
194 }
195
reenable_intr_remapping(int eim)196 static inline int reenable_intr_remapping(int eim)
197 {
198 return 0;
199 }
200 #endif
201
202 enum {
203 IRQ_REMAP_XAPIC_MODE,
204 IRQ_REMAP_X2APIC_MODE,
205 };
206
207 /* Can't use the common MSI interrupt functions
208 * since DMAR is not a pci device
209 */
210 struct irq_data;
211 extern void dmar_msi_unmask(struct irq_data *data);
212 extern void dmar_msi_mask(struct irq_data *data);
213 extern void dmar_msi_read(int irq, struct msi_msg *msg);
214 extern void dmar_msi_write(int irq, struct msi_msg *msg);
215 extern int dmar_set_interrupt(struct intel_iommu *iommu);
216 extern irqreturn_t dmar_fault(int irq, void *dev_id);
217 extern int arch_setup_dmar_msi(unsigned int irq);
218
219 #ifdef CONFIG_INTEL_IOMMU
220 extern int iommu_detected, no_iommu;
221 extern struct list_head dmar_rmrr_units;
222 struct dmar_rmrr_unit {
223 struct list_head list; /* list of rmrr units */
224 struct acpi_dmar_header *hdr; /* ACPI header */
225 u64 base_address; /* reserved base address*/
226 u64 end_address; /* reserved end address */
227 struct pci_dev **devices; /* target devices */
228 int devices_cnt; /* target device count */
229 };
230
231 #define for_each_rmrr_units(rmrr) \
232 list_for_each_entry(rmrr, &dmar_rmrr_units, list)
233
234 struct dmar_atsr_unit {
235 struct list_head list; /* list of ATSR units */
236 struct acpi_dmar_header *hdr; /* ACPI header */
237 struct pci_dev **devices; /* target devices */
238 int devices_cnt; /* target device count */
239 u8 include_all:1; /* include all ports */
240 };
241
242 int dmar_parse_rmrr_atsr_dev(void);
243 extern int dmar_parse_one_rmrr(struct acpi_dmar_header *header);
244 extern int dmar_parse_one_atsr(struct acpi_dmar_header *header);
245 extern int dmar_parse_dev_scope(void *start, void *end, int *cnt,
246 struct pci_dev ***devices, u16 segment);
247 extern int intel_iommu_init(void);
248 #else /* !CONFIG_INTEL_IOMMU: */
intel_iommu_init(void)249 static inline int intel_iommu_init(void) { return -ENODEV; }
dmar_parse_one_rmrr(struct acpi_dmar_header * header)250 static inline int dmar_parse_one_rmrr(struct acpi_dmar_header *header)
251 {
252 return 0;
253 }
dmar_parse_one_atsr(struct acpi_dmar_header * header)254 static inline int dmar_parse_one_atsr(struct acpi_dmar_header *header)
255 {
256 return 0;
257 }
dmar_parse_rmrr_atsr_dev(void)258 static inline int dmar_parse_rmrr_atsr_dev(void)
259 {
260 return 0;
261 }
262 #endif /* CONFIG_INTEL_IOMMU */
263
264 #endif /* __DMAR_H__ */
265