1 /*
2 * linux/arch/arm/mach-realview/core.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/amba/bus.h>
27 #include <linux/amba/clcd.h>
28 #include <linux/io.h>
29 #include <linux/smsc911x.h>
30 #include <linux/ata_platform.h>
31 #include <linux/amba/mmci.h>
32 #include <linux/gfp.h>
33 #include <linux/clkdev.h>
34
35 #include <asm/system.h>
36 #include <mach/hardware.h>
37 #include <asm/irq.h>
38 #include <asm/leds.h>
39 #include <asm/mach-types.h>
40 #include <asm/hardware/arm_timer.h>
41 #include <asm/hardware/icst.h>
42
43 #include <asm/mach/arch.h>
44 #include <asm/mach/flash.h>
45 #include <asm/mach/irq.h>
46 #include <asm/mach/map.h>
47
48 #include <asm/hardware/gic.h>
49
50 #include <mach/platform.h>
51 #include <mach/irqs.h>
52 #include <asm/hardware/timer-sp.h>
53
54 #include <plat/clcd.h>
55 #include <plat/sched_clock.h>
56
57 #include "core.h"
58
59 #ifdef CONFIG_ZONE_DMA
60 /*
61 * Adjust the zones if there are restrictions for DMA access.
62 */
realview_adjust_zones(unsigned long * size,unsigned long * hole)63 void __init realview_adjust_zones(unsigned long *size, unsigned long *hole)
64 {
65 unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
66
67 if (!machine_is_realview_pbx() || size[0] <= dma_size)
68 return;
69
70 size[ZONE_NORMAL] = size[0] - dma_size;
71 size[ZONE_DMA] = dma_size;
72 hole[ZONE_NORMAL] = hole[0];
73 hole[ZONE_DMA] = 0;
74 }
75 #endif
76
77
78 #define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
79
realview_flash_init(void)80 static int realview_flash_init(void)
81 {
82 u32 val;
83
84 val = __raw_readl(REALVIEW_FLASHCTRL);
85 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
86 __raw_writel(val, REALVIEW_FLASHCTRL);
87
88 return 0;
89 }
90
realview_flash_exit(void)91 static void realview_flash_exit(void)
92 {
93 u32 val;
94
95 val = __raw_readl(REALVIEW_FLASHCTRL);
96 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
97 __raw_writel(val, REALVIEW_FLASHCTRL);
98 }
99
realview_flash_set_vpp(int on)100 static void realview_flash_set_vpp(int on)
101 {
102 u32 val;
103
104 val = __raw_readl(REALVIEW_FLASHCTRL);
105 if (on)
106 val |= REALVIEW_FLASHPROG_FLVPPEN;
107 else
108 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
109 __raw_writel(val, REALVIEW_FLASHCTRL);
110 }
111
112 static struct flash_platform_data realview_flash_data = {
113 .map_name = "cfi_probe",
114 .width = 4,
115 .init = realview_flash_init,
116 .exit = realview_flash_exit,
117 .set_vpp = realview_flash_set_vpp,
118 };
119
120 struct platform_device realview_flash_device = {
121 .name = "armflash",
122 .id = 0,
123 .dev = {
124 .platform_data = &realview_flash_data,
125 },
126 };
127
realview_flash_register(struct resource * res,u32 num)128 int realview_flash_register(struct resource *res, u32 num)
129 {
130 realview_flash_device.resource = res;
131 realview_flash_device.num_resources = num;
132 return platform_device_register(&realview_flash_device);
133 }
134
135 static struct smsc911x_platform_config smsc911x_config = {
136 .flags = SMSC911X_USE_32BIT,
137 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
138 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
139 .phy_interface = PHY_INTERFACE_MODE_MII,
140 };
141
142 static struct platform_device realview_eth_device = {
143 .name = "smsc911x",
144 .id = 0,
145 .num_resources = 2,
146 };
147
realview_eth_register(const char * name,struct resource * res)148 int realview_eth_register(const char *name, struct resource *res)
149 {
150 if (name)
151 realview_eth_device.name = name;
152 realview_eth_device.resource = res;
153 if (strcmp(realview_eth_device.name, "smsc911x") == 0)
154 realview_eth_device.dev.platform_data = &smsc911x_config;
155
156 return platform_device_register(&realview_eth_device);
157 }
158
159 struct platform_device realview_usb_device = {
160 .name = "isp1760",
161 .num_resources = 2,
162 };
163
realview_usb_register(struct resource * res)164 int realview_usb_register(struct resource *res)
165 {
166 realview_usb_device.resource = res;
167 return platform_device_register(&realview_usb_device);
168 }
169
170 static struct pata_platform_info pata_platform_data = {
171 .ioport_shift = 1,
172 };
173
174 static struct resource pata_resources[] = {
175 [0] = {
176 .start = REALVIEW_CF_BASE,
177 .end = REALVIEW_CF_BASE + 0xff,
178 .flags = IORESOURCE_MEM,
179 },
180 [1] = {
181 .start = REALVIEW_CF_BASE + 0x100,
182 .end = REALVIEW_CF_BASE + SZ_4K - 1,
183 .flags = IORESOURCE_MEM,
184 },
185 };
186
187 struct platform_device realview_cf_device = {
188 .name = "pata_platform",
189 .id = -1,
190 .num_resources = ARRAY_SIZE(pata_resources),
191 .resource = pata_resources,
192 .dev = {
193 .platform_data = &pata_platform_data,
194 },
195 };
196
197 static struct resource realview_i2c_resource = {
198 .start = REALVIEW_I2C_BASE,
199 .end = REALVIEW_I2C_BASE + SZ_4K - 1,
200 .flags = IORESOURCE_MEM,
201 };
202
203 struct platform_device realview_i2c_device = {
204 .name = "versatile-i2c",
205 .id = 0,
206 .num_resources = 1,
207 .resource = &realview_i2c_resource,
208 };
209
210 static struct i2c_board_info realview_i2c_board_info[] = {
211 {
212 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
213 },
214 };
215
realview_i2c_init(void)216 static int __init realview_i2c_init(void)
217 {
218 return i2c_register_board_info(0, realview_i2c_board_info,
219 ARRAY_SIZE(realview_i2c_board_info));
220 }
221 arch_initcall(realview_i2c_init);
222
223 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
224
225 /*
226 * This is only used if GPIOLIB support is disabled
227 */
realview_mmc_status(struct device * dev)228 static unsigned int realview_mmc_status(struct device *dev)
229 {
230 struct amba_device *adev = container_of(dev, struct amba_device, dev);
231 u32 mask;
232
233 if (machine_is_realview_pb1176()) {
234 static bool inserted = false;
235
236 /*
237 * The PB1176 does not have the status register,
238 * assume it is inserted at startup, then invert
239 * for each call so card insertion/removal will
240 * be detected anyway. This will not be called if
241 * GPIO on PL061 is active, which is the proper
242 * way to do this on the PB1176.
243 */
244 inserted = !inserted;
245 return inserted ? 0 : 1;
246 }
247
248 if (adev->res.start == REALVIEW_MMCI0_BASE)
249 mask = 1;
250 else
251 mask = 2;
252
253 return readl(REALVIEW_SYSMCI) & mask;
254 }
255
256 struct mmci_platform_data realview_mmc0_plat_data = {
257 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
258 .status = realview_mmc_status,
259 .gpio_wp = 17,
260 .gpio_cd = 16,
261 .cd_invert = true,
262 };
263
264 struct mmci_platform_data realview_mmc1_plat_data = {
265 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
266 .status = realview_mmc_status,
267 .gpio_wp = 19,
268 .gpio_cd = 18,
269 .cd_invert = true,
270 };
271
272 /*
273 * Clock handling
274 */
275 static const struct icst_params realview_oscvco_params = {
276 .ref = 24000000,
277 .vco_max = ICST307_VCO_MAX,
278 .vco_min = ICST307_VCO_MIN,
279 .vd_min = 4 + 8,
280 .vd_max = 511 + 8,
281 .rd_min = 1 + 2,
282 .rd_max = 127 + 2,
283 .s2div = icst307_s2div,
284 .idx2s = icst307_idx2s,
285 };
286
realview_oscvco_set(struct clk * clk,struct icst_vco vco)287 static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
288 {
289 void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
290 u32 val;
291
292 val = readl(clk->vcoreg) & ~0x7ffff;
293 val |= vco.v | (vco.r << 9) | (vco.s << 16);
294
295 writel(0xa05f, sys_lock);
296 writel(val, clk->vcoreg);
297 writel(0, sys_lock);
298 }
299
300 static const struct clk_ops oscvco_clk_ops = {
301 .round = icst_clk_round,
302 .set = icst_clk_set,
303 .setvco = realview_oscvco_set,
304 };
305
306 static struct clk oscvco_clk = {
307 .ops = &oscvco_clk_ops,
308 .params = &realview_oscvco_params,
309 };
310
311 /*
312 * These are fixed clocks.
313 */
314 static struct clk ref24_clk = {
315 .rate = 24000000,
316 };
317
318 static struct clk dummy_apb_pclk;
319
320 static struct clk_lookup lookups[] = {
321 { /* Bus clock */
322 .con_id = "apb_pclk",
323 .clk = &dummy_apb_pclk,
324 }, { /* UART0 */
325 .dev_id = "dev:uart0",
326 .clk = &ref24_clk,
327 }, { /* UART1 */
328 .dev_id = "dev:uart1",
329 .clk = &ref24_clk,
330 }, { /* UART2 */
331 .dev_id = "dev:uart2",
332 .clk = &ref24_clk,
333 }, { /* UART3 */
334 .dev_id = "fpga:uart3",
335 .clk = &ref24_clk,
336 }, { /* UART3 is on the dev chip in PB1176 */
337 .dev_id = "dev:uart3",
338 .clk = &ref24_clk,
339 }, { /* UART4 only exists in PB1176 */
340 .dev_id = "fpga:uart4",
341 .clk = &ref24_clk,
342 }, { /* KMI0 */
343 .dev_id = "fpga:kmi0",
344 .clk = &ref24_clk,
345 }, { /* KMI1 */
346 .dev_id = "fpga:kmi1",
347 .clk = &ref24_clk,
348 }, { /* MMC0 */
349 .dev_id = "fpga:mmc0",
350 .clk = &ref24_clk,
351 }, { /* CLCD is in the PB1176 and EB DevChip */
352 .dev_id = "dev:clcd",
353 .clk = &oscvco_clk,
354 }, { /* PB:CLCD */
355 .dev_id = "issp:clcd",
356 .clk = &oscvco_clk,
357 }, { /* SSP */
358 .dev_id = "dev:ssp0",
359 .clk = &ref24_clk,
360 }
361 };
362
realview_init_early(void)363 void __init realview_init_early(void)
364 {
365 void __iomem *sys = __io_address(REALVIEW_SYS_BASE);
366
367 if (machine_is_realview_pb1176())
368 oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC0_OFFSET;
369 else
370 oscvco_clk.vcoreg = sys + REALVIEW_SYS_OSC4_OFFSET;
371
372 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
373
374 versatile_sched_clock_init(sys + REALVIEW_SYS_24MHz_OFFSET, 24000000);
375 }
376
377 /*
378 * CLCD support.
379 */
380 #define SYS_CLCD_NLCDIOON (1 << 2)
381 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
382 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
383 #define SYS_CLCD_ID_MASK (0x1f << 8)
384 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
385 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
386 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
387 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
388 #define SYS_CLCD_ID_VGA (0x1f << 8)
389
390 /*
391 * Disable all display connectors on the interface module.
392 */
realview_clcd_disable(struct clcd_fb * fb)393 static void realview_clcd_disable(struct clcd_fb *fb)
394 {
395 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
396 u32 val;
397
398 val = readl(sys_clcd);
399 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
400 writel(val, sys_clcd);
401 }
402
403 /*
404 * Enable the relevant connector on the interface module.
405 */
realview_clcd_enable(struct clcd_fb * fb)406 static void realview_clcd_enable(struct clcd_fb *fb)
407 {
408 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
409 u32 val;
410
411 /*
412 * Enable the PSUs
413 */
414 val = readl(sys_clcd);
415 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
416 writel(val, sys_clcd);
417 }
418
419 /*
420 * Detect which LCD panel is connected, and return the appropriate
421 * clcd_panel structure. Note: we do not have any information on
422 * the required timings for the 8.4in panel, so we presently assume
423 * VGA timings.
424 */
realview_clcd_setup(struct clcd_fb * fb)425 static int realview_clcd_setup(struct clcd_fb *fb)
426 {
427 void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
428 const char *panel_name, *vga_panel_name;
429 unsigned long framesize;
430 u32 val;
431
432 if (machine_is_realview_eb()) {
433 /* VGA, 16bpp */
434 framesize = 640 * 480 * 2;
435 vga_panel_name = "VGA";
436 } else {
437 /* XVGA, 16bpp */
438 framesize = 1024 * 768 * 2;
439 vga_panel_name = "XVGA";
440 }
441
442 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
443 if (val == SYS_CLCD_ID_SANYO_3_8)
444 panel_name = "Sanyo TM38QV67A02A";
445 else if (val == SYS_CLCD_ID_SANYO_2_5)
446 panel_name = "Sanyo QVGA Portrait";
447 else if (val == SYS_CLCD_ID_EPSON_2_2)
448 panel_name = "Epson L2F50113T00";
449 else if (val == SYS_CLCD_ID_VGA)
450 panel_name = vga_panel_name;
451 else {
452 pr_err("CLCD: unknown LCD panel ID 0x%08x, using VGA\n", val);
453 panel_name = vga_panel_name;
454 }
455
456 fb->panel = versatile_clcd_get_panel(panel_name);
457 if (!fb->panel)
458 return -EINVAL;
459
460 return versatile_clcd_setup_dma(fb, framesize);
461 }
462
463 struct clcd_board clcd_plat_data = {
464 .name = "RealView",
465 .caps = CLCD_CAP_ALL,
466 .check = clcdfb_check,
467 .decode = clcdfb_decode,
468 .disable = realview_clcd_disable,
469 .enable = realview_clcd_enable,
470 .setup = realview_clcd_setup,
471 .mmap = versatile_clcd_mmap_dma,
472 .remove = versatile_clcd_remove_dma,
473 };
474
475 #ifdef CONFIG_LEDS
476 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
477
realview_leds_event(led_event_t ledevt)478 void realview_leds_event(led_event_t ledevt)
479 {
480 unsigned long flags;
481 u32 val;
482 u32 led = 1 << smp_processor_id();
483
484 local_irq_save(flags);
485 val = readl(VA_LEDS_BASE);
486
487 switch (ledevt) {
488 case led_idle_start:
489 val = val & ~led;
490 break;
491
492 case led_idle_end:
493 val = val | led;
494 break;
495
496 case led_timer:
497 val = val ^ REALVIEW_SYS_LED7;
498 break;
499
500 case led_halted:
501 val = 0;
502 break;
503
504 default:
505 break;
506 }
507
508 writel(val, VA_LEDS_BASE);
509 local_irq_restore(flags);
510 }
511 #endif /* CONFIG_LEDS */
512
513 /*
514 * Where is the timer (VA)?
515 */
516 void __iomem *timer0_va_base;
517 void __iomem *timer1_va_base;
518 void __iomem *timer2_va_base;
519 void __iomem *timer3_va_base;
520
521 /*
522 * Set up the clock source and clock events devices
523 */
realview_timer_init(unsigned int timer_irq)524 void __init realview_timer_init(unsigned int timer_irq)
525 {
526 u32 val;
527
528 /*
529 * set clock frequency:
530 * REALVIEW_REFCLK is 32KHz
531 * REALVIEW_TIMCLK is 1MHz
532 */
533 val = readl(__io_address(REALVIEW_SCTL_BASE));
534 writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
535 (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
536 (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
537 (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
538 __io_address(REALVIEW_SCTL_BASE));
539
540 /*
541 * Initialise to a known state (all timers off)
542 */
543 writel(0, timer0_va_base + TIMER_CTRL);
544 writel(0, timer1_va_base + TIMER_CTRL);
545 writel(0, timer2_va_base + TIMER_CTRL);
546 writel(0, timer3_va_base + TIMER_CTRL);
547
548 sp804_clocksource_init(timer3_va_base);
549 sp804_clockevents_init(timer0_va_base, timer_irq);
550 }
551
552 /*
553 * Setup the memory banks.
554 */
realview_fixup(struct machine_desc * mdesc,struct tag * tags,char ** from,struct meminfo * meminfo)555 void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
556 struct meminfo *meminfo)
557 {
558 /*
559 * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
560 * Half of this is mirrored at 0.
561 */
562 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
563 meminfo->bank[0].start = 0x70000000;
564 meminfo->bank[0].size = SZ_512M;
565 meminfo->nr_banks = 1;
566 #else
567 meminfo->bank[0].start = 0;
568 meminfo->bank[0].size = SZ_256M;
569 meminfo->nr_banks = 1;
570 #endif
571 }
572