1 /* SPDX-License-Identifier: ISC */
2 /*
3  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4  */
5 
6 #ifndef __MT76_H
7 #define __MT76_H
8 
9 #include <linux/kernel.h>
10 #include <linux/io.h>
11 #include <linux/spinlock.h>
12 #include <linux/skbuff.h>
13 #include <linux/leds.h>
14 #include <linux/usb.h>
15 #include <linux/average.h>
16 #include <linux/soc/mediatek/mtk_wed.h>
17 #include <net/mac80211.h>
18 #include "util.h"
19 #include "testmode.h"
20 
21 #define MT_MCU_RING_SIZE	32
22 #define MT_RX_BUF_SIZE		2048
23 #define MT_SKB_HEAD_LEN		256
24 
25 #define MT_MAX_NON_AQL_PKT	16
26 #define MT_TXQ_FREE_THR		32
27 
28 #define MT76_TOKEN_FREE_THR	64
29 
30 #define MT_QFLAG_WED_RING	GENMASK(1, 0)
31 #define MT_QFLAG_WED_TYPE	GENMASK(3, 2)
32 #define MT_QFLAG_WED		BIT(4)
33 
34 #define __MT_WED_Q(_type, _n)	(MT_QFLAG_WED | \
35 				 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \
36 				 FIELD_PREP(MT_QFLAG_WED_RING, _n))
37 #define MT_WED_Q_TX(_n)		__MT_WED_Q(MT76_WED_Q_TX, _n)
38 #define MT_WED_Q_TXFREE		__MT_WED_Q(MT76_WED_Q_TXFREE, 0)
39 
40 struct mt76_dev;
41 struct mt76_phy;
42 struct mt76_wcid;
43 struct mt76s_intr;
44 
45 struct mt76_reg_pair {
46 	u32 reg;
47 	u32 value;
48 };
49 
50 enum mt76_bus_type {
51 	MT76_BUS_MMIO,
52 	MT76_BUS_USB,
53 	MT76_BUS_SDIO,
54 };
55 
56 enum mt76_wed_type {
57 	MT76_WED_Q_TX,
58 	MT76_WED_Q_TXFREE,
59 };
60 
61 struct mt76_bus_ops {
62 	u32 (*rr)(struct mt76_dev *dev, u32 offset);
63 	void (*wr)(struct mt76_dev *dev, u32 offset, u32 val);
64 	u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
65 	void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data,
66 			   int len);
67 	void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data,
68 			  int len);
69 	int (*wr_rp)(struct mt76_dev *dev, u32 base,
70 		     const struct mt76_reg_pair *rp, int len);
71 	int (*rd_rp)(struct mt76_dev *dev, u32 base,
72 		     struct mt76_reg_pair *rp, int len);
73 	enum mt76_bus_type type;
74 };
75 
76 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB)
77 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO)
78 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO)
79 
80 enum mt76_txq_id {
81 	MT_TXQ_VO = IEEE80211_AC_VO,
82 	MT_TXQ_VI = IEEE80211_AC_VI,
83 	MT_TXQ_BE = IEEE80211_AC_BE,
84 	MT_TXQ_BK = IEEE80211_AC_BK,
85 	MT_TXQ_PSD,
86 	MT_TXQ_BEACON,
87 	MT_TXQ_CAB,
88 	__MT_TXQ_MAX
89 };
90 
91 enum mt76_mcuq_id {
92 	MT_MCUQ_WM,
93 	MT_MCUQ_WA,
94 	MT_MCUQ_FWDL,
95 	__MT_MCUQ_MAX
96 };
97 
98 enum mt76_rxq_id {
99 	MT_RXQ_MAIN,
100 	MT_RXQ_MCU,
101 	MT_RXQ_MCU_WA,
102 	MT_RXQ_BAND1,
103 	MT_RXQ_BAND1_WA,
104 	MT_RXQ_MAIN_WA,
105 	MT_RXQ_BAND2,
106 	MT_RXQ_BAND2_WA,
107 	__MT_RXQ_MAX
108 };
109 
110 enum mt76_band_id {
111 	MT_BAND0,
112 	MT_BAND1,
113 	MT_BAND2,
114 	__MT_MAX_BAND
115 };
116 
117 enum mt76_cipher_type {
118 	MT_CIPHER_NONE,
119 	MT_CIPHER_WEP40,
120 	MT_CIPHER_TKIP,
121 	MT_CIPHER_TKIP_NO_MIC,
122 	MT_CIPHER_AES_CCMP,
123 	MT_CIPHER_WEP104,
124 	MT_CIPHER_BIP_CMAC_128,
125 	MT_CIPHER_WEP128,
126 	MT_CIPHER_WAPI,
127 	MT_CIPHER_CCMP_CCX,
128 	MT_CIPHER_CCMP_256,
129 	MT_CIPHER_GCMP,
130 	MT_CIPHER_GCMP_256,
131 };
132 
133 enum mt76_dfs_state {
134 	MT_DFS_STATE_UNKNOWN,
135 	MT_DFS_STATE_DISABLED,
136 	MT_DFS_STATE_CAC,
137 	MT_DFS_STATE_ACTIVE,
138 };
139 
140 struct mt76_queue_buf {
141 	dma_addr_t addr;
142 	u16 len;
143 	bool skip_unmap;
144 };
145 
146 struct mt76_tx_info {
147 	struct mt76_queue_buf buf[32];
148 	struct sk_buff *skb;
149 	int nbuf;
150 	u32 info;
151 };
152 
153 struct mt76_queue_entry {
154 	union {
155 		void *buf;
156 		struct sk_buff *skb;
157 	};
158 	union {
159 		struct mt76_txwi_cache *txwi;
160 		struct urb *urb;
161 		int buf_sz;
162 	};
163 	u32 dma_addr[2];
164 	u16 dma_len[2];
165 	u16 wcid;
166 	bool skip_buf0:1;
167 	bool skip_buf1:1;
168 	bool done:1;
169 };
170 
171 struct mt76_queue_regs {
172 	u32 desc_base;
173 	u32 ring_size;
174 	u32 cpu_idx;
175 	u32 dma_idx;
176 } __packed __aligned(4);
177 
178 struct mt76_queue {
179 	struct mt76_queue_regs __iomem *regs;
180 
181 	spinlock_t lock;
182 	spinlock_t cleanup_lock;
183 	struct mt76_queue_entry *entry;
184 	struct mt76_desc *desc;
185 
186 	u16 first;
187 	u16 head;
188 	u16 tail;
189 	int ndesc;
190 	int queued;
191 	int buf_size;
192 	bool stopped;
193 	bool blocked;
194 
195 	u8 buf_offset;
196 	u8 hw_idx;
197 	u8 flags;
198 
199 	u32 wed_regs;
200 
201 	dma_addr_t desc_dma;
202 	struct sk_buff *rx_head;
203 	struct page_frag_cache rx_page;
204 };
205 
206 struct mt76_mcu_ops {
207 	u32 headroom;
208 	u32 tailroom;
209 
210 	int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data,
211 			    int len, bool wait_resp);
212 	int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb,
213 				int cmd, int *seq);
214 	int (*mcu_parse_response)(struct mt76_dev *dev, int cmd,
215 				  struct sk_buff *skb, int seq);
216 	u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset);
217 	void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val);
218 	int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base,
219 			 const struct mt76_reg_pair *rp, int len);
220 	int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base,
221 			 struct mt76_reg_pair *rp, int len);
222 	int (*mcu_restart)(struct mt76_dev *dev);
223 };
224 
225 struct mt76_queue_ops {
226 	int (*init)(struct mt76_dev *dev,
227 		    int (*poll)(struct napi_struct *napi, int budget));
228 
229 	int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q,
230 		     int idx, int n_desc, int bufsize,
231 		     u32 ring_base);
232 
233 	int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q,
234 			    enum mt76_txq_id qid, struct sk_buff *skb,
235 			    struct mt76_wcid *wcid, struct ieee80211_sta *sta);
236 
237 	int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q,
238 				struct sk_buff *skb, u32 tx_info);
239 
240 	void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush,
241 			 int *len, u32 *info, bool *more);
242 
243 	void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid);
244 
245 	void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q,
246 			   bool flush);
247 
248 	void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q);
249 
250 	void (*kick)(struct mt76_dev *dev, struct mt76_queue *q);
251 
252 	void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q);
253 };
254 
255 enum mt76_phy_type {
256 	MT_PHY_TYPE_CCK,
257 	MT_PHY_TYPE_OFDM,
258 	MT_PHY_TYPE_HT,
259 	MT_PHY_TYPE_HT_GF,
260 	MT_PHY_TYPE_VHT,
261 	MT_PHY_TYPE_HE_SU = 8,
262 	MT_PHY_TYPE_HE_EXT_SU,
263 	MT_PHY_TYPE_HE_TB,
264 	MT_PHY_TYPE_HE_MU,
265 	__MT_PHY_TYPE_HE_MAX,
266 };
267 
268 struct mt76_sta_stats {
269 	u64 tx_mode[__MT_PHY_TYPE_HE_MAX];
270 	u64 tx_bw[4];		/* 20, 40, 80, 160 */
271 	u64 tx_nss[4];		/* 1, 2, 3, 4 */
272 	u64 tx_mcs[16];		/* mcs idx */
273 	u64 tx_bytes;
274 	u32 tx_packets;
275 	u32 tx_retries;
276 	u32 tx_failed;
277 };
278 
279 enum mt76_wcid_flags {
280 	MT_WCID_FLAG_CHECK_PS,
281 	MT_WCID_FLAG_PS,
282 	MT_WCID_FLAG_4ADDR,
283 	MT_WCID_FLAG_HDR_TRANS,
284 };
285 
286 #define MT76_N_WCIDS 544
287 
288 /* stored in ieee80211_tx_info::hw_queue */
289 #define MT_TX_HW_QUEUE_PHY		GENMASK(3, 2)
290 
291 DECLARE_EWMA(signal, 10, 8);
292 
293 #define MT_WCID_TX_INFO_RATE		GENMASK(15, 0)
294 #define MT_WCID_TX_INFO_NSS		GENMASK(17, 16)
295 #define MT_WCID_TX_INFO_TXPWR_ADJ	GENMASK(25, 18)
296 #define MT_WCID_TX_INFO_SET		BIT(31)
297 
298 struct mt76_wcid {
299 	struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS];
300 
301 	atomic_t non_aql_packets;
302 	unsigned long flags;
303 
304 	struct ewma_signal rssi;
305 	int inactive_count;
306 
307 	struct rate_info rate;
308 
309 	u16 idx;
310 	u8 hw_key_idx;
311 	u8 hw_key_idx2;
312 
313 	u8 sta:1;
314 	u8 amsdu:1;
315 	u8 phy_idx:2;
316 
317 	u8 rx_check_pn;
318 	u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6];
319 	u16 cipher;
320 
321 	u32 tx_info;
322 	bool sw_iv;
323 
324 	struct list_head list;
325 	struct idr pktid;
326 
327 	struct mt76_sta_stats stats;
328 };
329 
330 struct mt76_txq {
331 	u16 wcid;
332 
333 	u16 agg_ssn;
334 	bool send_bar;
335 	bool aggr;
336 };
337 
338 struct mt76_txwi_cache {
339 	struct list_head list;
340 	dma_addr_t dma_addr;
341 
342 	struct sk_buff *skb;
343 };
344 
345 struct mt76_rx_tid {
346 	struct rcu_head rcu_head;
347 
348 	struct mt76_dev *dev;
349 
350 	spinlock_t lock;
351 	struct delayed_work reorder_work;
352 
353 	u16 head;
354 	u16 size;
355 	u16 nframes;
356 
357 	u8 num;
358 
359 	u8 started:1, stopped:1, timer_pending:1;
360 
361 	struct sk_buff *reorder_buf[];
362 };
363 
364 #define MT_TX_CB_DMA_DONE		BIT(0)
365 #define MT_TX_CB_TXS_DONE		BIT(1)
366 #define MT_TX_CB_TXS_FAILED		BIT(2)
367 
368 #define MT_PACKET_ID_MASK		GENMASK(6, 0)
369 #define MT_PACKET_ID_NO_ACK		0
370 #define MT_PACKET_ID_NO_SKB		1
371 #define MT_PACKET_ID_WED		2
372 #define MT_PACKET_ID_FIRST		3
373 #define MT_PACKET_ID_HAS_RATE		BIT(7)
374 /* This is timer for when to give up when waiting for TXS callback,
375  * with starting time being the time at which the DMA_DONE callback
376  * was seen (so, we know packet was processed then, it should not take
377  * long after that for firmware to send the TXS callback if it is going
378  * to do so.)
379  */
380 #define MT_TX_STATUS_SKB_TIMEOUT	(HZ / 4)
381 
382 struct mt76_tx_cb {
383 	unsigned long jiffies;
384 	u16 wcid;
385 	u8 pktid;
386 	u8 flags;
387 };
388 
389 enum {
390 	MT76_STATE_INITIALIZED,
391 	MT76_STATE_RUNNING,
392 	MT76_STATE_MCU_RUNNING,
393 	MT76_SCANNING,
394 	MT76_HW_SCANNING,
395 	MT76_HW_SCHED_SCANNING,
396 	MT76_RESTART,
397 	MT76_RESET,
398 	MT76_MCU_RESET,
399 	MT76_REMOVED,
400 	MT76_READING_STATS,
401 	MT76_STATE_POWER_OFF,
402 	MT76_STATE_SUSPEND,
403 	MT76_STATE_ROC,
404 	MT76_STATE_PM,
405 };
406 
407 struct mt76_hw_cap {
408 	bool has_2ghz;
409 	bool has_5ghz;
410 	bool has_6ghz;
411 };
412 
413 #define MT_DRV_TXWI_NO_FREE		BIT(0)
414 #define MT_DRV_TX_ALIGNED4_SKBS		BIT(1)
415 #define MT_DRV_SW_RX_AIRTIME		BIT(2)
416 #define MT_DRV_RX_DMA_HDR		BIT(3)
417 #define MT_DRV_HW_MGMT_TXQ		BIT(4)
418 
419 struct mt76_driver_ops {
420 	u32 drv_flags;
421 	u32 survey_flags;
422 	u16 txwi_size;
423 	u16 token_size;
424 	u8 mcs_rates;
425 
426 	void (*update_survey)(struct mt76_phy *phy);
427 
428 	int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr,
429 			      enum mt76_txq_id qid, struct mt76_wcid *wcid,
430 			      struct ieee80211_sta *sta,
431 			      struct mt76_tx_info *tx_info);
432 
433 	void (*tx_complete_skb)(struct mt76_dev *dev,
434 				struct mt76_queue_entry *e);
435 
436 	bool (*tx_status_data)(struct mt76_dev *dev, u8 *update);
437 
438 	bool (*rx_check)(struct mt76_dev *dev, void *data, int len);
439 
440 	void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q,
441 		       struct sk_buff *skb);
442 
443 	void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q);
444 
445 	void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta,
446 		       bool ps);
447 
448 	int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif,
449 		       struct ieee80211_sta *sta);
450 
451 	void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif,
452 			  struct ieee80211_sta *sta);
453 
454 	void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif,
455 			   struct ieee80211_sta *sta);
456 };
457 
458 struct mt76_channel_state {
459 	u64 cc_active;
460 	u64 cc_busy;
461 	u64 cc_rx;
462 	u64 cc_bss_rx;
463 	u64 cc_tx;
464 
465 	s8 noise;
466 };
467 
468 struct mt76_sband {
469 	struct ieee80211_supported_band sband;
470 	struct mt76_channel_state *chan;
471 };
472 
473 struct mt76_rate_power {
474 	union {
475 		struct {
476 			s8 cck[4];
477 			s8 ofdm[8];
478 			s8 stbc[10];
479 			s8 ht[16];
480 			s8 vht[10];
481 		};
482 		s8 all[48];
483 	};
484 };
485 
486 /* addr req mask */
487 #define MT_VEND_TYPE_EEPROM	BIT(31)
488 #define MT_VEND_TYPE_CFG	BIT(30)
489 #define MT_VEND_TYPE_MASK	(MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG)
490 
491 #define MT_VEND_ADDR(type, n)	(MT_VEND_TYPE_##type | (n))
492 enum mt_vendor_req {
493 	MT_VEND_DEV_MODE =	0x1,
494 	MT_VEND_WRITE =		0x2,
495 	MT_VEND_POWER_ON =	0x4,
496 	MT_VEND_MULTI_WRITE =	0x6,
497 	MT_VEND_MULTI_READ =	0x7,
498 	MT_VEND_READ_EEPROM =	0x9,
499 	MT_VEND_WRITE_FCE =	0x42,
500 	MT_VEND_WRITE_CFG =	0x46,
501 	MT_VEND_READ_CFG =	0x47,
502 	MT_VEND_READ_EXT =	0x63,
503 	MT_VEND_WRITE_EXT =	0x66,
504 	MT_VEND_FEATURE_SET =	0x91,
505 };
506 
507 enum mt76u_in_ep {
508 	MT_EP_IN_PKT_RX,
509 	MT_EP_IN_CMD_RESP,
510 	__MT_EP_IN_MAX,
511 };
512 
513 enum mt76u_out_ep {
514 	MT_EP_OUT_INBAND_CMD,
515 	MT_EP_OUT_AC_BE,
516 	MT_EP_OUT_AC_BK,
517 	MT_EP_OUT_AC_VI,
518 	MT_EP_OUT_AC_VO,
519 	MT_EP_OUT_HCCA,
520 	__MT_EP_OUT_MAX,
521 };
522 
523 struct mt76_mcu {
524 	struct mutex mutex;
525 	u32 msg_seq;
526 	int timeout;
527 
528 	struct sk_buff_head res_q;
529 	wait_queue_head_t wait;
530 };
531 
532 #define MT_TX_SG_MAX_SIZE	8
533 #define MT_RX_SG_MAX_SIZE	4
534 #define MT_NUM_TX_ENTRIES	256
535 #define MT_NUM_RX_ENTRIES	128
536 #define MCU_RESP_URB_SIZE	1024
537 struct mt76_usb {
538 	struct mutex usb_ctrl_mtx;
539 	u8 *data;
540 	u16 data_len;
541 
542 	struct mt76_worker status_worker;
543 	struct mt76_worker rx_worker;
544 
545 	struct work_struct stat_work;
546 
547 	u8 out_ep[__MT_EP_OUT_MAX];
548 	u8 in_ep[__MT_EP_IN_MAX];
549 	bool sg_en;
550 
551 	struct mt76u_mcu {
552 		u8 *data;
553 		/* multiple reads */
554 		struct mt76_reg_pair *rp;
555 		int rp_len;
556 		u32 base;
557 	} mcu;
558 };
559 
560 #define MT76S_XMIT_BUF_SZ	0x3fe00
561 #define MT76S_NUM_TX_ENTRIES	256
562 #define MT76S_NUM_RX_ENTRIES	512
563 struct mt76_sdio {
564 	struct mt76_worker txrx_worker;
565 	struct mt76_worker status_worker;
566 	struct mt76_worker net_worker;
567 
568 	struct work_struct stat_work;
569 
570 	u8 *xmit_buf;
571 	u32 xmit_buf_sz;
572 
573 	struct sdio_func *func;
574 	void *intr_data;
575 	u8 hw_ver;
576 	wait_queue_head_t wait;
577 
578 	struct {
579 		int pse_data_quota;
580 		int ple_data_quota;
581 		int pse_mcu_quota;
582 		int pse_page_size;
583 		int deficit;
584 	} sched;
585 
586 	int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr);
587 };
588 
589 struct mt76_mmio {
590 	void __iomem *regs;
591 	spinlock_t irq_lock;
592 	u32 irqmask;
593 
594 	struct mtk_wed_device wed;
595 };
596 
597 struct mt76_rx_status {
598 	union {
599 		struct mt76_wcid *wcid;
600 		u16 wcid_idx;
601 	};
602 
603 	u32 reorder_time;
604 
605 	u32 ampdu_ref;
606 	u32 timestamp;
607 
608 	u8 iv[6];
609 
610 	u8 phy_idx:2;
611 	u8 aggr:1;
612 	u8 qos_ctl;
613 	u16 seqno;
614 
615 	u16 freq;
616 	u32 flag;
617 	u8 enc_flags;
618 	u8 encoding:2, bw:3, he_ru:3;
619 	u8 he_gi:2, he_dcm:1;
620 	u8 amsdu:1, first_amsdu:1, last_amsdu:1;
621 	u8 rate_idx;
622 	u8 nss;
623 	u8 band;
624 	s8 signal;
625 	u8 chains;
626 	s8 chain_signal[IEEE80211_MAX_CHAINS];
627 };
628 
629 struct mt76_freq_range_power {
630 	const struct cfg80211_sar_freq_ranges *range;
631 	s8 power;
632 };
633 
634 struct mt76_testmode_ops {
635 	int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state);
636 	int (*set_params)(struct mt76_phy *phy, struct nlattr **tb,
637 			  enum mt76_testmode_state new_state);
638 	int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg);
639 };
640 
641 struct mt76_testmode_data {
642 	enum mt76_testmode_state state;
643 
644 	u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)];
645 	struct sk_buff *tx_skb;
646 
647 	u32 tx_count;
648 	u16 tx_mpdu_len;
649 
650 	u8 tx_rate_mode;
651 	u8 tx_rate_idx;
652 	u8 tx_rate_nss;
653 	u8 tx_rate_sgi;
654 	u8 tx_rate_ldpc;
655 	u8 tx_rate_stbc;
656 	u8 tx_ltf;
657 
658 	u8 tx_antenna_mask;
659 	u8 tx_spe_idx;
660 
661 	u8 tx_duty_cycle;
662 	u32 tx_time;
663 	u32 tx_ipg;
664 
665 	u32 freq_offset;
666 
667 	u8 tx_power[4];
668 	u8 tx_power_control;
669 
670 	u8 addr[3][ETH_ALEN];
671 
672 	u32 tx_pending;
673 	u32 tx_queued;
674 	u16 tx_queued_limit;
675 	u32 tx_done;
676 	struct {
677 		u64 packets[__MT_RXQ_MAX];
678 		u64 fcs_error[__MT_RXQ_MAX];
679 	} rx_stats;
680 };
681 
682 struct mt76_vif {
683 	u8 idx;
684 	u8 omac_idx;
685 	u8 band_idx;
686 	u8 wmm_idx;
687 	u8 scan_seq_num;
688 	u8 cipher;
689 };
690 
691 struct mt76_phy {
692 	struct ieee80211_hw *hw;
693 	struct mt76_dev *dev;
694 	void *priv;
695 
696 	unsigned long state;
697 	u8 band_idx;
698 
699 	struct mt76_queue *q_tx[__MT_TXQ_MAX];
700 
701 	struct cfg80211_chan_def chandef;
702 	struct ieee80211_channel *main_chan;
703 
704 	struct mt76_channel_state *chan_state;
705 	enum mt76_dfs_state dfs_state;
706 	ktime_t survey_time;
707 
708 	struct mt76_hw_cap cap;
709 	struct mt76_sband sband_2g;
710 	struct mt76_sband sband_5g;
711 	struct mt76_sband sband_6g;
712 
713 	u8 macaddr[ETH_ALEN];
714 
715 	int txpower_cur;
716 	u8 antenna_mask;
717 	u16 chainmask;
718 
719 #ifdef CONFIG_NL80211_TESTMODE
720 	struct mt76_testmode_data test;
721 #endif
722 
723 	struct delayed_work mac_work;
724 	u8 mac_work_count;
725 
726 	struct {
727 		struct sk_buff *head;
728 		struct sk_buff **tail;
729 		u16 seqno;
730 	} rx_amsdu[__MT_RXQ_MAX];
731 
732 	struct mt76_freq_range_power *frp;
733 };
734 
735 struct mt76_dev {
736 	struct mt76_phy phy; /* must be first */
737 	struct mt76_phy *phys[__MT_MAX_BAND];
738 
739 	struct ieee80211_hw *hw;
740 
741 	spinlock_t lock;
742 	spinlock_t cc_lock;
743 
744 	u32 cur_cc_bss_rx;
745 
746 	struct mt76_rx_status rx_ampdu_status;
747 	u32 rx_ampdu_len;
748 	u32 rx_ampdu_ref;
749 
750 	struct mutex mutex;
751 
752 	const struct mt76_bus_ops *bus;
753 	const struct mt76_driver_ops *drv;
754 	const struct mt76_mcu_ops *mcu_ops;
755 	struct device *dev;
756 	struct device *dma_dev;
757 
758 	struct mt76_mcu mcu;
759 
760 	struct net_device napi_dev;
761 	struct net_device tx_napi_dev;
762 	spinlock_t rx_lock;
763 	struct napi_struct napi[__MT_RXQ_MAX];
764 	struct sk_buff_head rx_skb[__MT_RXQ_MAX];
765 
766 	struct list_head txwi_cache;
767 	struct mt76_queue *q_mcu[__MT_MCUQ_MAX];
768 	struct mt76_queue q_rx[__MT_RXQ_MAX];
769 	const struct mt76_queue_ops *queue_ops;
770 	int tx_dma_idx[4];
771 
772 	struct mt76_worker tx_worker;
773 	struct napi_struct tx_napi;
774 
775 	spinlock_t token_lock;
776 	struct idr token;
777 	u16 wed_token_count;
778 	u16 token_count;
779 	u16 token_size;
780 
781 	wait_queue_head_t tx_wait;
782 	/* spinclock used to protect wcid pktid linked list */
783 	spinlock_t status_lock;
784 
785 	u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];
786 	u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)];
787 
788 	u64 vif_mask;
789 
790 	struct mt76_wcid global_wcid;
791 	struct mt76_wcid __rcu *wcid[MT76_N_WCIDS];
792 	struct list_head wcid_list;
793 
794 	u32 rev;
795 
796 	u32 aggr_stats[32];
797 
798 	struct tasklet_struct pre_tbtt_tasklet;
799 	int beacon_int;
800 	u8 beacon_mask;
801 
802 	struct debugfs_blob_wrapper eeprom;
803 	struct debugfs_blob_wrapper otp;
804 
805 	struct mt76_rate_power rate_power;
806 
807 	char alpha2[3];
808 	enum nl80211_dfs_regions region;
809 
810 	u32 debugfs_reg;
811 
812 	struct led_classdev led_cdev;
813 	char led_name[32];
814 	bool led_al;
815 	u8 led_pin;
816 
817 	u8 csa_complete;
818 
819 	u32 rxfilter;
820 
821 #ifdef CONFIG_NL80211_TESTMODE
822 	const struct mt76_testmode_ops *test_ops;
823 	struct {
824 		const char *name;
825 		u32 offset;
826 	} test_mtd;
827 #endif
828 	struct workqueue_struct *wq;
829 
830 	union {
831 		struct mt76_mmio mmio;
832 		struct mt76_usb usb;
833 		struct mt76_sdio sdio;
834 	};
835 };
836 
837 struct mt76_power_limits {
838 	s8 cck[4];
839 	s8 ofdm[8];
840 	s8 mcs[4][10];
841 	s8 ru[7][12];
842 };
843 
844 struct mt76_ethtool_worker_info {
845 	u64 *data;
846 	int idx;
847 	int initial_stat_idx;
848 	int worker_stat_count;
849 	int sta_count;
850 };
851 
852 #define CCK_RATE(_idx, _rate) {					\
853 	.bitrate = _rate,					\
854 	.flags = IEEE80211_RATE_SHORT_PREAMBLE,			\
855 	.hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx),		\
856 	.hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx),	\
857 }
858 
859 #define OFDM_RATE(_idx, _rate) {				\
860 	.bitrate = _rate,					\
861 	.hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx),		\
862 	.hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx),	\
863 }
864 
865 extern struct ieee80211_rate mt76_rates[12];
866 
867 #define __mt76_rr(dev, ...)	(dev)->bus->rr((dev), __VA_ARGS__)
868 #define __mt76_wr(dev, ...)	(dev)->bus->wr((dev), __VA_ARGS__)
869 #define __mt76_rmw(dev, ...)	(dev)->bus->rmw((dev), __VA_ARGS__)
870 #define __mt76_wr_copy(dev, ...)	(dev)->bus->write_copy((dev), __VA_ARGS__)
871 #define __mt76_rr_copy(dev, ...)	(dev)->bus->read_copy((dev), __VA_ARGS__)
872 
873 #define __mt76_set(dev, offset, val)	__mt76_rmw(dev, offset, 0, val)
874 #define __mt76_clear(dev, offset, val)	__mt76_rmw(dev, offset, val, 0)
875 
876 #define mt76_rr(dev, ...)	(dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__)
877 #define mt76_wr(dev, ...)	(dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__)
878 #define mt76_rmw(dev, ...)	(dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__)
879 #define mt76_wr_copy(dev, ...)	(dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__)
880 #define mt76_rr_copy(dev, ...)	(dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__)
881 #define mt76_wr_rp(dev, ...)	(dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__)
882 #define mt76_rd_rp(dev, ...)	(dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__)
883 
884 
885 #define mt76_mcu_restart(dev, ...)	(dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76))
886 #define __mt76_mcu_restart(dev, ...)	(dev)->mcu_ops->mcu_restart((dev))
887 
888 #define mt76_set(dev, offset, val)	mt76_rmw(dev, offset, 0, val)
889 #define mt76_clear(dev, offset, val)	mt76_rmw(dev, offset, val, 0)
890 
891 #define mt76_get_field(_dev, _reg, _field)		\
892 	FIELD_GET(_field, mt76_rr(dev, _reg))
893 
894 #define mt76_rmw_field(_dev, _reg, _field, _val)	\
895 	mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
896 
897 #define __mt76_rmw_field(_dev, _reg, _field, _val)	\
898 	__mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
899 
900 #define mt76_hw(dev) (dev)->mphy.hw
901 
902 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
903 		 int timeout);
904 
905 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__)
906 
907 bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val,
908 		      int timeout);
909 
910 #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__)
911 
912 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs);
913 void mt76_pci_disable_aspm(struct pci_dev *pdev);
914 
mt76_chip(struct mt76_dev * dev)915 static inline u16 mt76_chip(struct mt76_dev *dev)
916 {
917 	return dev->rev >> 16;
918 }
919 
mt76_rev(struct mt76_dev * dev)920 static inline u16 mt76_rev(struct mt76_dev *dev)
921 {
922 	return dev->rev & 0xffff;
923 }
924 
925 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76))
926 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76))
927 
928 #define mt76_init_queues(dev, ...)		(dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__)
929 #define mt76_queue_alloc(dev, ...)	(dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__)
930 #define mt76_tx_queue_skb_raw(dev, ...)	(dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__)
931 #define mt76_tx_queue_skb(dev, ...)	(dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__)
932 #define mt76_queue_rx_reset(dev, ...)	(dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__)
933 #define mt76_queue_tx_cleanup(dev, ...)	(dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__)
934 #define mt76_queue_rx_cleanup(dev, ...)	(dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__)
935 #define mt76_queue_kick(dev, ...)	(dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__)
936 #define mt76_queue_reset(dev, ...)	(dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__)
937 
938 #define mt76_for_each_q_rx(dev, i)	\
939 	for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++)	\
940 		if ((dev)->q_rx[i].ndesc)
941 
942 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size,
943 				   const struct ieee80211_ops *ops,
944 				   const struct mt76_driver_ops *drv_ops);
945 int mt76_register_device(struct mt76_dev *dev, bool vht,
946 			 struct ieee80211_rate *rates, int n_rates);
947 void mt76_unregister_device(struct mt76_dev *dev);
948 void mt76_free_device(struct mt76_dev *dev);
949 void mt76_unregister_phy(struct mt76_phy *phy);
950 
951 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size,
952 				const struct ieee80211_ops *ops,
953 				u8 band_idx);
954 int mt76_register_phy(struct mt76_phy *phy, bool vht,
955 		      struct ieee80211_rate *rates, int n_rates);
956 
957 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy,
958 					  const struct file_operations *ops);
mt76_register_debugfs(struct mt76_dev * dev)959 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev)
960 {
961 	return mt76_register_debugfs_fops(&dev->phy, NULL);
962 }
963 
964 int mt76_queues_read(struct seq_file *s, void *data);
965 void mt76_seq_puts_array(struct seq_file *file, const char *str,
966 			 s8 *val, int len);
967 
968 int mt76_eeprom_init(struct mt76_dev *dev, int len);
969 void mt76_eeprom_override(struct mt76_phy *phy);
970 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len);
971 
972 struct mt76_queue *
973 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc,
974 		int ring_base, u32 flags);
975 u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx);
mt76_init_tx_queue(struct mt76_phy * phy,int qid,int idx,int n_desc,int ring_base,u32 flags)976 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx,
977 				     int n_desc, int ring_base, u32 flags)
978 {
979 	struct mt76_queue *q;
980 
981 	q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags);
982 	if (IS_ERR(q))
983 		return PTR_ERR(q);
984 
985 	phy->q_tx[qid] = q;
986 
987 	return 0;
988 }
989 
mt76_init_mcu_queue(struct mt76_dev * dev,int qid,int idx,int n_desc,int ring_base)990 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx,
991 				      int n_desc, int ring_base)
992 {
993 	struct mt76_queue *q;
994 
995 	q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0);
996 	if (IS_ERR(q))
997 		return PTR_ERR(q);
998 
999 	dev->q_mcu[qid] = q;
1000 
1001 	return 0;
1002 }
1003 
1004 static inline struct mt76_phy *
mt76_dev_phy(struct mt76_dev * dev,u8 phy_idx)1005 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx)
1006 {
1007 	if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) ||
1008 	    (phy_idx == MT_BAND2 && dev->phys[phy_idx]))
1009 		return dev->phys[phy_idx];
1010 
1011 	return &dev->phy;
1012 }
1013 
1014 static inline struct ieee80211_hw *
mt76_phy_hw(struct mt76_dev * dev,u8 phy_idx)1015 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx)
1016 {
1017 	return mt76_dev_phy(dev, phy_idx)->hw;
1018 }
1019 
1020 static inline u8 *
mt76_get_txwi_ptr(struct mt76_dev * dev,struct mt76_txwi_cache * t)1021 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t)
1022 {
1023 	return (u8 *)t - dev->drv->txwi_size;
1024 }
1025 
1026 /* increment with wrap-around */
mt76_incr(int val,int size)1027 static inline int mt76_incr(int val, int size)
1028 {
1029 	return (val + 1) & (size - 1);
1030 }
1031 
1032 /* decrement with wrap-around */
mt76_decr(int val,int size)1033 static inline int mt76_decr(int val, int size)
1034 {
1035 	return (val - 1) & (size - 1);
1036 }
1037 
1038 u8 mt76_ac_to_hwq(u8 ac);
1039 
1040 static inline struct ieee80211_txq *
mtxq_to_txq(struct mt76_txq * mtxq)1041 mtxq_to_txq(struct mt76_txq *mtxq)
1042 {
1043 	void *ptr = mtxq;
1044 
1045 	return container_of(ptr, struct ieee80211_txq, drv_priv);
1046 }
1047 
1048 static inline struct ieee80211_sta *
wcid_to_sta(struct mt76_wcid * wcid)1049 wcid_to_sta(struct mt76_wcid *wcid)
1050 {
1051 	void *ptr = wcid;
1052 
1053 	if (!wcid || !wcid->sta)
1054 		return NULL;
1055 
1056 	return container_of(ptr, struct ieee80211_sta, drv_priv);
1057 }
1058 
mt76_tx_skb_cb(struct sk_buff * skb)1059 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb)
1060 {
1061 	BUILD_BUG_ON(sizeof(struct mt76_tx_cb) >
1062 		     sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data));
1063 	return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data);
1064 }
1065 
mt76_skb_get_hdr(struct sk_buff * skb)1066 static inline void *mt76_skb_get_hdr(struct sk_buff *skb)
1067 {
1068 	struct mt76_rx_status mstat;
1069 	u8 *data = skb->data;
1070 
1071 	/* Alignment concerns */
1072 	BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4);
1073 	BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4);
1074 
1075 	mstat = *((struct mt76_rx_status *)skb->cb);
1076 
1077 	if (mstat.flag & RX_FLAG_RADIOTAP_HE)
1078 		data += sizeof(struct ieee80211_radiotap_he);
1079 	if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU)
1080 		data += sizeof(struct ieee80211_radiotap_he_mu);
1081 
1082 	return data;
1083 }
1084 
mt76_insert_hdr_pad(struct sk_buff * skb)1085 static inline void mt76_insert_hdr_pad(struct sk_buff *skb)
1086 {
1087 	int len = ieee80211_get_hdrlen_from_skb(skb);
1088 
1089 	if (len % 4 == 0)
1090 		return;
1091 
1092 	skb_push(skb, 2);
1093 	memmove(skb->data, skb->data + 2, len);
1094 
1095 	skb->data[len] = 0;
1096 	skb->data[len + 1] = 0;
1097 }
1098 
mt76_is_skb_pktid(u8 pktid)1099 static inline bool mt76_is_skb_pktid(u8 pktid)
1100 {
1101 	if (pktid & MT_PACKET_ID_HAS_RATE)
1102 		return false;
1103 
1104 	return pktid >= MT_PACKET_ID_FIRST;
1105 }
1106 
mt76_tx_power_nss_delta(u8 nss)1107 static inline u8 mt76_tx_power_nss_delta(u8 nss)
1108 {
1109 	static const u8 nss_delta[4] = { 0, 6, 9, 12 };
1110 	u8 idx = nss - 1;
1111 
1112 	return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0;
1113 }
1114 
mt76_testmode_enabled(struct mt76_phy * phy)1115 static inline bool mt76_testmode_enabled(struct mt76_phy *phy)
1116 {
1117 #ifdef CONFIG_NL80211_TESTMODE
1118 	return phy->test.state != MT76_TM_STATE_OFF;
1119 #else
1120 	return false;
1121 #endif
1122 }
1123 
mt76_is_testmode_skb(struct mt76_dev * dev,struct sk_buff * skb,struct ieee80211_hw ** hw)1124 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev,
1125 					struct sk_buff *skb,
1126 					struct ieee80211_hw **hw)
1127 {
1128 #ifdef CONFIG_NL80211_TESTMODE
1129 	int i;
1130 
1131 	for (i = 0; i < ARRAY_SIZE(dev->phys); i++) {
1132 		struct mt76_phy *phy = dev->phys[i];
1133 
1134 		if (phy && skb == phy->test.tx_skb) {
1135 			*hw = dev->phys[i]->hw;
1136 			return true;
1137 		}
1138 	}
1139 	return false;
1140 #else
1141 	return false;
1142 #endif
1143 }
1144 
1145 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb);
1146 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta,
1147 	     struct mt76_wcid *wcid, struct sk_buff *skb);
1148 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq);
1149 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta,
1150 			 bool send_bar);
1151 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb);
1152 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid);
1153 void mt76_txq_schedule_all(struct mt76_phy *phy);
1154 void mt76_tx_worker_run(struct mt76_dev *dev);
1155 void mt76_tx_worker(struct mt76_worker *w);
1156 void mt76_release_buffered_frames(struct ieee80211_hw *hw,
1157 				  struct ieee80211_sta *sta,
1158 				  u16 tids, int nframes,
1159 				  enum ieee80211_frame_release_type reason,
1160 				  bool more_data);
1161 bool mt76_has_tx_pending(struct mt76_phy *phy);
1162 void mt76_set_channel(struct mt76_phy *phy);
1163 void mt76_update_survey(struct mt76_phy *phy);
1164 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time);
1165 int mt76_get_survey(struct ieee80211_hw *hw, int idx,
1166 		    struct survey_info *survey);
1167 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht);
1168 
1169 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid,
1170 		       u16 ssn, u16 size);
1171 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid);
1172 
1173 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid,
1174 			 struct ieee80211_key_conf *key);
1175 
1176 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list)
1177 			 __acquires(&dev->status_lock);
1178 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list)
1179 			   __releases(&dev->status_lock);
1180 
1181 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid,
1182 			   struct sk_buff *skb);
1183 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev,
1184 				       struct mt76_wcid *wcid, int pktid,
1185 				       struct sk_buff_head *list);
1186 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb,
1187 			     struct sk_buff_head *list);
1188 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb,
1189 			    struct list_head *free_list);
1190 static inline void
mt76_tx_complete_skb(struct mt76_dev * dev,u16 wcid,struct sk_buff * skb)1191 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb)
1192 {
1193     __mt76_tx_complete_skb(dev, wcid, skb, NULL);
1194 }
1195 
1196 void mt76_tx_status_check(struct mt76_dev *dev, bool flush);
1197 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1198 		   struct ieee80211_sta *sta,
1199 		   enum ieee80211_sta_state old_state,
1200 		   enum ieee80211_sta_state new_state);
1201 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif,
1202 		       struct ieee80211_sta *sta);
1203 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1204 			     struct ieee80211_sta *sta);
1205 
1206 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy);
1207 
1208 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1209 		     int *dbm);
1210 int mt76_init_sar_power(struct ieee80211_hw *hw,
1211 			const struct cfg80211_sar_specs *sar);
1212 int mt76_get_sar_power(struct mt76_phy *phy,
1213 		       struct ieee80211_channel *chan,
1214 		       int power);
1215 
1216 void mt76_csa_check(struct mt76_dev *dev);
1217 void mt76_csa_finish(struct mt76_dev *dev);
1218 
1219 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant);
1220 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set);
1221 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id);
1222 int mt76_get_rate(struct mt76_dev *dev,
1223 		  struct ieee80211_supported_band *sband,
1224 		  int idx, bool cck);
1225 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1226 		  const u8 *mac);
1227 void mt76_sw_scan_complete(struct ieee80211_hw *hw,
1228 			   struct ieee80211_vif *vif);
1229 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy);
1230 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1231 		      void *data, int len);
1232 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb,
1233 		       struct netlink_callback *cb, void *data, int len);
1234 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state);
1235 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len);
1236 
mt76_testmode_reset(struct mt76_phy * phy,bool disable)1237 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable)
1238 {
1239 #ifdef CONFIG_NL80211_TESTMODE
1240 	enum mt76_testmode_state state = MT76_TM_STATE_IDLE;
1241 
1242 	if (disable || phy->test.state == MT76_TM_STATE_OFF)
1243 		state = MT76_TM_STATE_OFF;
1244 
1245 	mt76_testmode_set_state(phy, state);
1246 #endif
1247 }
1248 
1249 
1250 /* internal */
1251 static inline struct ieee80211_hw *
mt76_tx_status_get_hw(struct mt76_dev * dev,struct sk_buff * skb)1252 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb)
1253 {
1254 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1255 	u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2;
1256 	struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx);
1257 
1258 	info->hw_queue &= ~MT_TX_HW_QUEUE_PHY;
1259 
1260 	return hw;
1261 }
1262 
1263 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t);
1264 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames,
1265 		      struct napi_struct *napi);
1266 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q,
1267 			   struct napi_struct *napi);
1268 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames);
1269 void mt76_testmode_tx_pending(struct mt76_phy *phy);
1270 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q,
1271 			    struct mt76_queue_entry *e);
1272 
1273 /* usb */
mt76u_urb_error(struct urb * urb)1274 static inline bool mt76u_urb_error(struct urb *urb)
1275 {
1276 	return urb->status &&
1277 	       urb->status != -ECONNRESET &&
1278 	       urb->status != -ESHUTDOWN &&
1279 	       urb->status != -ENOENT;
1280 }
1281 
1282 /* Map hardware queues to usb endpoints */
q2ep(u8 qid)1283 static inline u8 q2ep(u8 qid)
1284 {
1285 	/* TODO: take management packets to queue 5 */
1286 	return qid + 1;
1287 }
1288 
1289 static inline int
mt76u_bulk_msg(struct mt76_dev * dev,void * data,int len,int * actual_len,int timeout,int ep)1290 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len,
1291 	       int timeout, int ep)
1292 {
1293 	struct usb_interface *uintf = to_usb_interface(dev->dev);
1294 	struct usb_device *udev = interface_to_usbdev(uintf);
1295 	struct mt76_usb *usb = &dev->usb;
1296 	unsigned int pipe;
1297 
1298 	if (actual_len)
1299 		pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]);
1300 	else
1301 		pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]);
1302 
1303 	return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout);
1304 }
1305 
1306 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi,
1307 			 struct mt76_sta_stats *stats);
1308 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad);
1309 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type,
1310 			   u16 val, u16 offset, void *buf, size_t len);
1311 int mt76u_vendor_request(struct mt76_dev *dev, u8 req,
1312 			 u8 req_type, u16 val, u16 offset,
1313 			 void *buf, size_t len);
1314 void mt76u_single_wr(struct mt76_dev *dev, const u8 req,
1315 		     const u16 offset, const u32 val);
1316 void mt76u_read_copy(struct mt76_dev *dev, u32 offset,
1317 		     void *data, int len);
1318 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr);
1319 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type,
1320 		 u32 addr, u32 val);
1321 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf,
1322 		 struct mt76_bus_ops *ops);
1323 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf);
1324 int mt76u_alloc_mcu_queue(struct mt76_dev *dev);
1325 int mt76u_alloc_queues(struct mt76_dev *dev);
1326 void mt76u_stop_tx(struct mt76_dev *dev);
1327 void mt76u_stop_rx(struct mt76_dev *dev);
1328 int mt76u_resume_rx(struct mt76_dev *dev);
1329 void mt76u_queues_deinit(struct mt76_dev *dev);
1330 
1331 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func,
1332 	       const struct mt76_bus_ops *bus_ops);
1333 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid);
1334 int mt76s_alloc_tx(struct mt76_dev *dev);
1335 void mt76s_deinit(struct mt76_dev *dev);
1336 void mt76s_sdio_irq(struct sdio_func *func);
1337 void mt76s_txrx_worker(struct mt76_sdio *sdio);
1338 bool mt76s_txqs_empty(struct mt76_dev *dev);
1339 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func,
1340 		  int hw_ver);
1341 u32 mt76s_rr(struct mt76_dev *dev, u32 offset);
1342 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val);
1343 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val);
1344 u32 mt76s_read_pcr(struct mt76_dev *dev);
1345 void mt76s_write_copy(struct mt76_dev *dev, u32 offset,
1346 		      const void *data, int len);
1347 void mt76s_read_copy(struct mt76_dev *dev, u32 offset,
1348 		     void *data, int len);
1349 int mt76s_wr_rp(struct mt76_dev *dev, u32 base,
1350 		const struct mt76_reg_pair *data,
1351 		int len);
1352 int mt76s_rd_rp(struct mt76_dev *dev, u32 base,
1353 		struct mt76_reg_pair *data, int len);
1354 
1355 struct sk_buff *
1356 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,
1357 		     int len, int data_len, gfp_t gfp);
1358 static inline struct sk_buff *
mt76_mcu_msg_alloc(struct mt76_dev * dev,const void * data,int data_len)1359 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data,
1360 		   int data_len)
1361 {
1362 	return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL);
1363 }
1364 
1365 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb);
1366 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev,
1367 				      unsigned long expires);
1368 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data,
1369 			      int len, bool wait_resp, struct sk_buff **ret);
1370 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb,
1371 				  int cmd, bool wait_resp, struct sk_buff **ret);
1372 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,
1373 			     int len, int max_len);
1374 static inline int
mt76_mcu_send_firmware(struct mt76_dev * dev,int cmd,const void * data,int len)1375 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data,
1376 		       int len)
1377 {
1378 	int max_len = 4096 - dev->mcu_ops->headroom;
1379 
1380 	return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len);
1381 }
1382 
1383 static inline int
mt76_mcu_send_msg(struct mt76_dev * dev,int cmd,const void * data,int len,bool wait_resp)1384 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len,
1385 		  bool wait_resp)
1386 {
1387 	return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL);
1388 }
1389 
1390 static inline int
mt76_mcu_skb_send_msg(struct mt76_dev * dev,struct sk_buff * skb,int cmd,bool wait_resp)1391 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd,
1392 		      bool wait_resp)
1393 {
1394 	return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL);
1395 }
1396 
1397 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set);
1398 
1399 s8 mt76_get_rate_power_limits(struct mt76_phy *phy,
1400 			      struct ieee80211_channel *chan,
1401 			      struct mt76_power_limits *dest,
1402 			      s8 target_power);
1403 
1404 struct mt76_txwi_cache *
1405 mt76_token_release(struct mt76_dev *dev, int token, bool *wake);
1406 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi);
1407 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked);
1408 
mt76_set_tx_blocked(struct mt76_dev * dev,bool blocked)1409 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked)
1410 {
1411 	spin_lock_bh(&dev->token_lock);
1412 	__mt76_set_tx_blocked(dev, blocked);
1413 	spin_unlock_bh(&dev->token_lock);
1414 }
1415 
1416 static inline int
mt76_token_get(struct mt76_dev * dev,struct mt76_txwi_cache ** ptxwi)1417 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi)
1418 {
1419 	int token;
1420 
1421 	spin_lock_bh(&dev->token_lock);
1422 	token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC);
1423 	spin_unlock_bh(&dev->token_lock);
1424 
1425 	return token;
1426 }
1427 
1428 static inline struct mt76_txwi_cache *
mt76_token_put(struct mt76_dev * dev,int token)1429 mt76_token_put(struct mt76_dev *dev, int token)
1430 {
1431 	struct mt76_txwi_cache *txwi;
1432 
1433 	spin_lock_bh(&dev->token_lock);
1434 	txwi = idr_remove(&dev->token, token);
1435 	spin_unlock_bh(&dev->token_lock);
1436 
1437 	return txwi;
1438 }
1439 
mt76_packet_id_init(struct mt76_wcid * wcid)1440 static inline void mt76_packet_id_init(struct mt76_wcid *wcid)
1441 {
1442 	INIT_LIST_HEAD(&wcid->list);
1443 	idr_init(&wcid->pktid);
1444 }
1445 
1446 static inline void
mt76_packet_id_flush(struct mt76_dev * dev,struct mt76_wcid * wcid)1447 mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid)
1448 {
1449 	struct sk_buff_head list;
1450 
1451 	mt76_tx_status_lock(dev, &list);
1452 	mt76_tx_status_skb_get(dev, wcid, -1, &list);
1453 	mt76_tx_status_unlock(dev, &list);
1454 
1455 	idr_destroy(&wcid->pktid);
1456 }
1457 
1458 #endif
1459