1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, 2021 Intel Corporation
5 */
6
7 #ifndef SPI_PXA2XX_H
8 #define SPI_PXA2XX_H
9
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/types.h>
13 #include <linux/sizes.h>
14
15 #include <linux/pxa2xx_ssp.h>
16
17 struct gpio_desc;
18 struct pxa2xx_spi_controller;
19 struct spi_controller;
20 struct spi_device;
21 struct spi_transfer;
22
23 struct driver_data {
24 /* SSP Info */
25 struct ssp_device *ssp;
26
27 /* SPI framework hookup */
28 enum pxa_ssp_type ssp_type;
29 struct spi_controller *controller;
30
31 /* PXA hookup */
32 struct pxa2xx_spi_controller *controller_info;
33
34 /* SSP masks*/
35 u32 dma_cr1;
36 u32 int_cr1;
37 u32 clear_sr;
38 u32 mask_sr;
39
40 /* DMA engine support */
41 atomic_t dma_running;
42
43 /* Current transfer state info */
44 void *tx;
45 void *tx_end;
46 void *rx;
47 void *rx_end;
48 u8 n_bytes;
49 int (*write)(struct driver_data *drv_data);
50 int (*read)(struct driver_data *drv_data);
51 irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
52
53 void __iomem *lpss_base;
54
55 /* Optional slave FIFO ready signal */
56 struct gpio_desc *gpiod_ready;
57 };
58
59 struct chip_data {
60 u32 cr1;
61 u32 dds_rate;
62 u32 timeout;
63 u8 enable_dma;
64 u32 dma_burst_size;
65 u32 dma_threshold;
66 u32 threshold;
67 u16 lpss_rx_threshold;
68 u16 lpss_tx_threshold;
69 };
70
pxa2xx_spi_read(const struct driver_data * drv_data,u32 reg)71 static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, u32 reg)
72 {
73 return pxa_ssp_read_reg(drv_data->ssp, reg);
74 }
75
pxa2xx_spi_write(const struct driver_data * drv_data,u32 reg,u32 val)76 static inline void pxa2xx_spi_write(const struct driver_data *drv_data, u32 reg, u32 val)
77 {
78 pxa_ssp_write_reg(drv_data->ssp, reg, val);
79 }
80
81 #define DMA_ALIGNMENT 8
82
pxa25x_ssp_comp(const struct driver_data * drv_data)83 static inline int pxa25x_ssp_comp(const struct driver_data *drv_data)
84 {
85 switch (drv_data->ssp_type) {
86 case PXA25x_SSP:
87 case CE4100_SSP:
88 case QUARK_X1000_SSP:
89 return 1;
90 default:
91 return 0;
92 }
93 }
94
clear_SSCR1_bits(const struct driver_data * drv_data,u32 bits)95 static inline void clear_SSCR1_bits(const struct driver_data *drv_data, u32 bits)
96 {
97 pxa2xx_spi_write(drv_data, SSCR1, pxa2xx_spi_read(drv_data, SSCR1) & ~bits);
98 }
99
read_SSSR_bits(const struct driver_data * drv_data,u32 bits)100 static inline u32 read_SSSR_bits(const struct driver_data *drv_data, u32 bits)
101 {
102 return pxa2xx_spi_read(drv_data, SSSR) & bits;
103 }
104
write_SSSR_CS(const struct driver_data * drv_data,u32 val)105 static inline void write_SSSR_CS(const struct driver_data *drv_data, u32 val)
106 {
107 if (drv_data->ssp_type == CE4100_SSP ||
108 drv_data->ssp_type == QUARK_X1000_SSP)
109 val |= read_SSSR_bits(drv_data, SSSR_ALT_FRM_MASK);
110
111 pxa2xx_spi_write(drv_data, SSSR, val);
112 }
113
114 extern int pxa2xx_spi_flush(struct driver_data *drv_data);
115
116 #define MAX_DMA_LEN SZ_64K
117 #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
118
119 extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
120 extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
121 struct spi_transfer *xfer);
122 extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
123 extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
124 extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
125 extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
126 extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
127 struct spi_device *spi,
128 u8 bits_per_word,
129 u32 *burst_code,
130 u32 *threshold);
131
132 #endif /* SPI_PXA2XX_H */
133