1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include "drm_crtc_helper.h"
34 #include "drm_edid.h"
35
avivo_crtc_load_lut(struct drm_crtc * crtc)36 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
37 {
38 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
39 struct drm_device *dev = crtc->dev;
40 struct radeon_device *rdev = dev->dev_private;
41 int i;
42
43 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
44 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
45
46 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
47 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
49
50 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
51 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
53
54 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
55 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
56 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
57
58 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
59 for (i = 0; i < 256; i++) {
60 WREG32(AVIVO_DC_LUT_30_COLOR,
61 (radeon_crtc->lut_r[i] << 20) |
62 (radeon_crtc->lut_g[i] << 10) |
63 (radeon_crtc->lut_b[i] << 0));
64 }
65
66 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
67 }
68
dce4_crtc_load_lut(struct drm_crtc * crtc)69 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
70 {
71 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
72 struct drm_device *dev = crtc->dev;
73 struct radeon_device *rdev = dev->dev_private;
74 int i;
75
76 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
77 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
78
79 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
80 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
82
83 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
84 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
86
87 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
88 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
89
90 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
91 for (i = 0; i < 256; i++) {
92 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
93 (radeon_crtc->lut_r[i] << 20) |
94 (radeon_crtc->lut_g[i] << 10) |
95 (radeon_crtc->lut_b[i] << 0));
96 }
97 }
98
dce5_crtc_load_lut(struct drm_crtc * crtc)99 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
100 {
101 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
102 struct drm_device *dev = crtc->dev;
103 struct radeon_device *rdev = dev->dev_private;
104 int i;
105
106 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
107
108 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
109 (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
110 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
111 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
112 NI_GRPH_PRESCALE_BYPASS);
113 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
114 NI_OVL_PRESCALE_BYPASS);
115 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
116 (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
117 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
118
119 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
120
121 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
122 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
123 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
124
125 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
126 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
127 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
128
129 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
130 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
131
132 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
133 for (i = 0; i < 256; i++) {
134 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
135 (radeon_crtc->lut_r[i] << 20) |
136 (radeon_crtc->lut_g[i] << 10) |
137 (radeon_crtc->lut_b[i] << 0));
138 }
139
140 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
141 (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
142 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
143 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
144 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
145 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
146 (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
147 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
148 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
149 (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
150 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
151 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
152 (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
153 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
154 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
155 WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
156
157 }
158
legacy_crtc_load_lut(struct drm_crtc * crtc)159 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
160 {
161 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
162 struct drm_device *dev = crtc->dev;
163 struct radeon_device *rdev = dev->dev_private;
164 int i;
165 uint32_t dac2_cntl;
166
167 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
168 if (radeon_crtc->crtc_id == 0)
169 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
170 else
171 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
172 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
173
174 WREG8(RADEON_PALETTE_INDEX, 0);
175 for (i = 0; i < 256; i++) {
176 WREG32(RADEON_PALETTE_30_DATA,
177 (radeon_crtc->lut_r[i] << 20) |
178 (radeon_crtc->lut_g[i] << 10) |
179 (radeon_crtc->lut_b[i] << 0));
180 }
181 }
182
radeon_crtc_load_lut(struct drm_crtc * crtc)183 void radeon_crtc_load_lut(struct drm_crtc *crtc)
184 {
185 struct drm_device *dev = crtc->dev;
186 struct radeon_device *rdev = dev->dev_private;
187
188 if (!crtc->enabled)
189 return;
190
191 if (ASIC_IS_DCE5(rdev))
192 dce5_crtc_load_lut(crtc);
193 else if (ASIC_IS_DCE4(rdev))
194 dce4_crtc_load_lut(crtc);
195 else if (ASIC_IS_AVIVO(rdev))
196 avivo_crtc_load_lut(crtc);
197 else
198 legacy_crtc_load_lut(crtc);
199 }
200
201 /** Sets the color ramps on behalf of fbcon */
radeon_crtc_fb_gamma_set(struct drm_crtc * crtc,u16 red,u16 green,u16 blue,int regno)202 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
203 u16 blue, int regno)
204 {
205 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
206
207 radeon_crtc->lut_r[regno] = red >> 6;
208 radeon_crtc->lut_g[regno] = green >> 6;
209 radeon_crtc->lut_b[regno] = blue >> 6;
210 }
211
212 /** Gets the color ramps on behalf of fbcon */
radeon_crtc_fb_gamma_get(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,int regno)213 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
214 u16 *blue, int regno)
215 {
216 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
217
218 *red = radeon_crtc->lut_r[regno] << 6;
219 *green = radeon_crtc->lut_g[regno] << 6;
220 *blue = radeon_crtc->lut_b[regno] << 6;
221 }
222
radeon_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t start,uint32_t size)223 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
224 u16 *blue, uint32_t start, uint32_t size)
225 {
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 int end = (start + size > 256) ? 256 : start + size, i;
228
229 /* userspace palettes are always correct as is */
230 for (i = start; i < end; i++) {
231 radeon_crtc->lut_r[i] = red[i] >> 6;
232 radeon_crtc->lut_g[i] = green[i] >> 6;
233 radeon_crtc->lut_b[i] = blue[i] >> 6;
234 }
235 radeon_crtc_load_lut(crtc);
236 }
237
radeon_crtc_destroy(struct drm_crtc * crtc)238 static void radeon_crtc_destroy(struct drm_crtc *crtc)
239 {
240 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
241
242 drm_crtc_cleanup(crtc);
243 kfree(radeon_crtc);
244 }
245
246 /*
247 * Handle unpin events outside the interrupt handler proper.
248 */
radeon_unpin_work_func(struct work_struct * __work)249 static void radeon_unpin_work_func(struct work_struct *__work)
250 {
251 struct radeon_unpin_work *work =
252 container_of(__work, struct radeon_unpin_work, work);
253 int r;
254
255 /* unpin of the old buffer */
256 r = radeon_bo_reserve(work->old_rbo, false);
257 if (likely(r == 0)) {
258 r = radeon_bo_unpin(work->old_rbo);
259 if (unlikely(r != 0)) {
260 DRM_ERROR("failed to unpin buffer after flip\n");
261 }
262 radeon_bo_unreserve(work->old_rbo);
263 } else
264 DRM_ERROR("failed to reserve buffer after flip\n");
265
266 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
267 kfree(work);
268 }
269
radeon_crtc_handle_flip(struct radeon_device * rdev,int crtc_id)270 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
271 {
272 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
273 struct radeon_unpin_work *work;
274 struct drm_pending_vblank_event *e;
275 struct timeval now;
276 unsigned long flags;
277 u32 update_pending;
278 int vpos, hpos;
279
280 spin_lock_irqsave(&rdev->ddev->event_lock, flags);
281 work = radeon_crtc->unpin_work;
282 if (work == NULL ||
283 (work->fence && !radeon_fence_signaled(work->fence))) {
284 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
285 return;
286 }
287 /* New pageflip, or just completion of a previous one? */
288 if (!radeon_crtc->deferred_flip_completion) {
289 /* do the flip (mmio) */
290 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
291 } else {
292 /* This is just a completion of a flip queued in crtc
293 * at last invocation. Make sure we go directly to
294 * completion routine.
295 */
296 update_pending = 0;
297 radeon_crtc->deferred_flip_completion = 0;
298 }
299
300 /* Has the pageflip already completed in crtc, or is it certain
301 * to complete in this vblank?
302 */
303 if (update_pending &&
304 (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
305 &vpos, &hpos)) &&
306 ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
307 (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
308 /* crtc didn't flip in this target vblank interval,
309 * but flip is pending in crtc. Based on the current
310 * scanout position we know that the current frame is
311 * (nearly) complete and the flip will (likely)
312 * complete before the start of the next frame.
313 */
314 update_pending = 0;
315 }
316 if (update_pending) {
317 /* crtc didn't flip in this target vblank interval,
318 * but flip is pending in crtc. It will complete it
319 * in next vblank interval, so complete the flip at
320 * next vblank irq.
321 */
322 radeon_crtc->deferred_flip_completion = 1;
323 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
324 return;
325 }
326
327 /* Pageflip (will be) certainly completed in this vblank. Clean up. */
328 radeon_crtc->unpin_work = NULL;
329
330 /* wakeup userspace */
331 if (work->event) {
332 e = work->event;
333 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
334 e->event.tv_sec = now.tv_sec;
335 e->event.tv_usec = now.tv_usec;
336 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
337 wake_up_interruptible(&e->base.file_priv->event_wait);
338 }
339 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
340
341 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
342 radeon_fence_unref(&work->fence);
343 radeon_post_page_flip(work->rdev, work->crtc_id);
344 schedule_work(&work->work);
345 }
346
radeon_crtc_page_flip(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event)347 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
348 struct drm_framebuffer *fb,
349 struct drm_pending_vblank_event *event)
350 {
351 struct drm_device *dev = crtc->dev;
352 struct radeon_device *rdev = dev->dev_private;
353 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
354 struct radeon_framebuffer *old_radeon_fb;
355 struct radeon_framebuffer *new_radeon_fb;
356 struct drm_gem_object *obj;
357 struct radeon_bo *rbo;
358 struct radeon_unpin_work *work;
359 unsigned long flags;
360 u32 tiling_flags, pitch_pixels;
361 u64 base;
362 int r;
363
364 work = kzalloc(sizeof *work, GFP_KERNEL);
365 if (work == NULL)
366 return -ENOMEM;
367
368 work->event = event;
369 work->rdev = rdev;
370 work->crtc_id = radeon_crtc->crtc_id;
371 old_radeon_fb = to_radeon_framebuffer(crtc->fb);
372 new_radeon_fb = to_radeon_framebuffer(fb);
373 /* schedule unpin of the old buffer */
374 obj = old_radeon_fb->obj;
375 /* take a reference to the old object */
376 drm_gem_object_reference(obj);
377 rbo = gem_to_radeon_bo(obj);
378 work->old_rbo = rbo;
379 obj = new_radeon_fb->obj;
380 rbo = gem_to_radeon_bo(obj);
381 if (rbo->tbo.sync_obj)
382 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
383 INIT_WORK(&work->work, radeon_unpin_work_func);
384
385 /* We borrow the event spin lock for protecting unpin_work */
386 spin_lock_irqsave(&dev->event_lock, flags);
387 if (radeon_crtc->unpin_work) {
388 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
389 r = -EBUSY;
390 goto unlock_free;
391 }
392 radeon_crtc->unpin_work = work;
393 radeon_crtc->deferred_flip_completion = 0;
394 spin_unlock_irqrestore(&dev->event_lock, flags);
395
396 /* pin the new buffer */
397 DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
398 work->old_rbo, rbo);
399
400 r = radeon_bo_reserve(rbo, false);
401 if (unlikely(r != 0)) {
402 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
403 goto pflip_cleanup;
404 }
405 /* Only 27 bit offset for legacy CRTC */
406 r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
407 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
408 if (unlikely(r != 0)) {
409 radeon_bo_unreserve(rbo);
410 r = -EINVAL;
411 DRM_ERROR("failed to pin new rbo buffer before flip\n");
412 goto pflip_cleanup;
413 }
414 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
415 radeon_bo_unreserve(rbo);
416
417 if (!ASIC_IS_AVIVO(rdev)) {
418 /* crtc offset is from display base addr not FB location */
419 base -= radeon_crtc->legacy_display_base_addr;
420 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
421
422 if (tiling_flags & RADEON_TILING_MACRO) {
423 if (ASIC_IS_R300(rdev)) {
424 base &= ~0x7ff;
425 } else {
426 int byteshift = fb->bits_per_pixel >> 4;
427 int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
428 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
429 }
430 } else {
431 int offset = crtc->y * pitch_pixels + crtc->x;
432 switch (fb->bits_per_pixel) {
433 case 8:
434 default:
435 offset *= 1;
436 break;
437 case 15:
438 case 16:
439 offset *= 2;
440 break;
441 case 24:
442 offset *= 3;
443 break;
444 case 32:
445 offset *= 4;
446 break;
447 }
448 base += offset;
449 }
450 base &= ~7;
451 }
452
453 spin_lock_irqsave(&dev->event_lock, flags);
454 work->new_crtc_base = base;
455 spin_unlock_irqrestore(&dev->event_lock, flags);
456
457 /* update crtc fb */
458 crtc->fb = fb;
459
460 r = drm_vblank_get(dev, radeon_crtc->crtc_id);
461 if (r) {
462 DRM_ERROR("failed to get vblank before flip\n");
463 goto pflip_cleanup1;
464 }
465
466 /* set the proper interrupt */
467 radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
468
469 return 0;
470
471 pflip_cleanup1:
472 if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
473 DRM_ERROR("failed to reserve new rbo in error path\n");
474 goto pflip_cleanup;
475 }
476 if (unlikely(radeon_bo_unpin(rbo) != 0)) {
477 DRM_ERROR("failed to unpin new rbo in error path\n");
478 }
479 radeon_bo_unreserve(rbo);
480
481 pflip_cleanup:
482 spin_lock_irqsave(&dev->event_lock, flags);
483 radeon_crtc->unpin_work = NULL;
484 unlock_free:
485 spin_unlock_irqrestore(&dev->event_lock, flags);
486 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
487 radeon_fence_unref(&work->fence);
488 kfree(work);
489
490 return r;
491 }
492
493 static const struct drm_crtc_funcs radeon_crtc_funcs = {
494 .cursor_set = radeon_crtc_cursor_set,
495 .cursor_move = radeon_crtc_cursor_move,
496 .gamma_set = radeon_crtc_gamma_set,
497 .set_config = drm_crtc_helper_set_config,
498 .destroy = radeon_crtc_destroy,
499 .page_flip = radeon_crtc_page_flip,
500 };
501
radeon_crtc_init(struct drm_device * dev,int index)502 static void radeon_crtc_init(struct drm_device *dev, int index)
503 {
504 struct radeon_device *rdev = dev->dev_private;
505 struct radeon_crtc *radeon_crtc;
506 int i;
507
508 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
509 if (radeon_crtc == NULL)
510 return;
511
512 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
513
514 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
515 radeon_crtc->crtc_id = index;
516 rdev->mode_info.crtcs[index] = radeon_crtc;
517
518 #if 0
519 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
520 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
521 radeon_crtc->mode_set.num_connectors = 0;
522 #endif
523
524 for (i = 0; i < 256; i++) {
525 radeon_crtc->lut_r[i] = i << 2;
526 radeon_crtc->lut_g[i] = i << 2;
527 radeon_crtc->lut_b[i] = i << 2;
528 }
529
530 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
531 radeon_atombios_init_crtc(dev, radeon_crtc);
532 else
533 radeon_legacy_init_crtc(dev, radeon_crtc);
534 }
535
536 static const char *encoder_names[37] = {
537 "NONE",
538 "INTERNAL_LVDS",
539 "INTERNAL_TMDS1",
540 "INTERNAL_TMDS2",
541 "INTERNAL_DAC1",
542 "INTERNAL_DAC2",
543 "INTERNAL_SDVOA",
544 "INTERNAL_SDVOB",
545 "SI170B",
546 "CH7303",
547 "CH7301",
548 "INTERNAL_DVO1",
549 "EXTERNAL_SDVOA",
550 "EXTERNAL_SDVOB",
551 "TITFP513",
552 "INTERNAL_LVTM1",
553 "VT1623",
554 "HDMI_SI1930",
555 "HDMI_INTERNAL",
556 "INTERNAL_KLDSCP_TMDS1",
557 "INTERNAL_KLDSCP_DVO1",
558 "INTERNAL_KLDSCP_DAC1",
559 "INTERNAL_KLDSCP_DAC2",
560 "SI178",
561 "MVPU_FPGA",
562 "INTERNAL_DDI",
563 "VT1625",
564 "HDMI_SI1932",
565 "DP_AN9801",
566 "DP_DP501",
567 "INTERNAL_UNIPHY",
568 "INTERNAL_KLDSCP_LVTMA",
569 "INTERNAL_UNIPHY1",
570 "INTERNAL_UNIPHY2",
571 "NUTMEG",
572 "TRAVIS",
573 "INTERNAL_VCE"
574 };
575
576 static const char *connector_names[15] = {
577 "Unknown",
578 "VGA",
579 "DVI-I",
580 "DVI-D",
581 "DVI-A",
582 "Composite",
583 "S-video",
584 "LVDS",
585 "Component",
586 "DIN",
587 "DisplayPort",
588 "HDMI-A",
589 "HDMI-B",
590 "TV",
591 "eDP",
592 };
593
594 static const char *hpd_names[6] = {
595 "HPD1",
596 "HPD2",
597 "HPD3",
598 "HPD4",
599 "HPD5",
600 "HPD6",
601 };
602
radeon_print_display_setup(struct drm_device * dev)603 static void radeon_print_display_setup(struct drm_device *dev)
604 {
605 struct drm_connector *connector;
606 struct radeon_connector *radeon_connector;
607 struct drm_encoder *encoder;
608 struct radeon_encoder *radeon_encoder;
609 uint32_t devices;
610 int i = 0;
611
612 DRM_INFO("Radeon Display Connectors\n");
613 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
614 radeon_connector = to_radeon_connector(connector);
615 DRM_INFO("Connector %d:\n", i);
616 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
617 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
618 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
619 if (radeon_connector->ddc_bus) {
620 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
621 radeon_connector->ddc_bus->rec.mask_clk_reg,
622 radeon_connector->ddc_bus->rec.mask_data_reg,
623 radeon_connector->ddc_bus->rec.a_clk_reg,
624 radeon_connector->ddc_bus->rec.a_data_reg,
625 radeon_connector->ddc_bus->rec.en_clk_reg,
626 radeon_connector->ddc_bus->rec.en_data_reg,
627 radeon_connector->ddc_bus->rec.y_clk_reg,
628 radeon_connector->ddc_bus->rec.y_data_reg);
629 if (radeon_connector->router.ddc_valid)
630 DRM_INFO(" DDC Router 0x%x/0x%x\n",
631 radeon_connector->router.ddc_mux_control_pin,
632 radeon_connector->router.ddc_mux_state);
633 if (radeon_connector->router.cd_valid)
634 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
635 radeon_connector->router.cd_mux_control_pin,
636 radeon_connector->router.cd_mux_state);
637 } else {
638 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
639 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
640 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
641 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
642 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
643 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
644 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
645 }
646 DRM_INFO(" Encoders:\n");
647 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
648 radeon_encoder = to_radeon_encoder(encoder);
649 devices = radeon_encoder->devices & radeon_connector->devices;
650 if (devices) {
651 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
652 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
653 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
654 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
655 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
656 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
657 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
658 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
659 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
660 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
661 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
662 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
663 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
664 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
665 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
666 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
667 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
668 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
669 if (devices & ATOM_DEVICE_TV1_SUPPORT)
670 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
671 if (devices & ATOM_DEVICE_CV_SUPPORT)
672 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
673 }
674 }
675 i++;
676 }
677 }
678
radeon_setup_enc_conn(struct drm_device * dev)679 static bool radeon_setup_enc_conn(struct drm_device *dev)
680 {
681 struct radeon_device *rdev = dev->dev_private;
682 bool ret = false;
683
684 if (rdev->bios) {
685 if (rdev->is_atom_bios) {
686 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
687 if (ret == false)
688 ret = radeon_get_atom_connector_info_from_object_table(dev);
689 } else {
690 ret = radeon_get_legacy_connector_info_from_bios(dev);
691 if (ret == false)
692 ret = radeon_get_legacy_connector_info_from_table(dev);
693 }
694 } else {
695 if (!ASIC_IS_AVIVO(rdev))
696 ret = radeon_get_legacy_connector_info_from_table(dev);
697 }
698 if (ret) {
699 radeon_setup_encoder_clones(dev);
700 radeon_print_display_setup(dev);
701 }
702
703 return ret;
704 }
705
radeon_ddc_get_modes(struct radeon_connector * radeon_connector)706 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
707 {
708 struct drm_device *dev = radeon_connector->base.dev;
709 struct radeon_device *rdev = dev->dev_private;
710 int ret = 0;
711
712 /* on hw with routers, select right port */
713 if (radeon_connector->router.ddc_valid)
714 radeon_router_select_ddc_port(radeon_connector);
715
716 if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
717 ENCODER_OBJECT_ID_NONE) {
718 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
719
720 if (dig->dp_i2c_bus)
721 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
722 &dig->dp_i2c_bus->adapter);
723 } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
724 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
725 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
726
727 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
728 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
729 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
730 &dig->dp_i2c_bus->adapter);
731 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
732 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
733 &radeon_connector->ddc_bus->adapter);
734 } else {
735 if (radeon_connector->ddc_bus && !radeon_connector->edid)
736 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
737 &radeon_connector->ddc_bus->adapter);
738 }
739
740 if (!radeon_connector->edid) {
741 if (rdev->is_atom_bios) {
742 /* some laptops provide a hardcoded edid in rom for LCDs */
743 if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
744 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
745 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
746 } else
747 /* some servers provide a hardcoded edid in rom for KVMs */
748 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
749 }
750 if (radeon_connector->edid) {
751 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
752 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
753 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
754 return ret;
755 }
756 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
757 return 0;
758 }
759
760 /* avivo */
avivo_get_fb_div(struct radeon_pll * pll,u32 target_clock,u32 post_div,u32 ref_div,u32 * fb_div,u32 * frac_fb_div)761 static void avivo_get_fb_div(struct radeon_pll *pll,
762 u32 target_clock,
763 u32 post_div,
764 u32 ref_div,
765 u32 *fb_div,
766 u32 *frac_fb_div)
767 {
768 u32 tmp = post_div * ref_div;
769
770 tmp *= target_clock;
771 *fb_div = tmp / pll->reference_freq;
772 *frac_fb_div = tmp % pll->reference_freq;
773
774 if (*fb_div > pll->max_feedback_div)
775 *fb_div = pll->max_feedback_div;
776 else if (*fb_div < pll->min_feedback_div)
777 *fb_div = pll->min_feedback_div;
778 }
779
avivo_get_post_div(struct radeon_pll * pll,u32 target_clock)780 static u32 avivo_get_post_div(struct radeon_pll *pll,
781 u32 target_clock)
782 {
783 u32 vco, post_div, tmp;
784
785 if (pll->flags & RADEON_PLL_USE_POST_DIV)
786 return pll->post_div;
787
788 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
789 if (pll->flags & RADEON_PLL_IS_LCD)
790 vco = pll->lcd_pll_out_min;
791 else
792 vco = pll->pll_out_min;
793 } else {
794 if (pll->flags & RADEON_PLL_IS_LCD)
795 vco = pll->lcd_pll_out_max;
796 else
797 vco = pll->pll_out_max;
798 }
799
800 post_div = vco / target_clock;
801 tmp = vco % target_clock;
802
803 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
804 if (tmp)
805 post_div++;
806 } else {
807 if (!tmp)
808 post_div--;
809 }
810
811 if (post_div > pll->max_post_div)
812 post_div = pll->max_post_div;
813 else if (post_div < pll->min_post_div)
814 post_div = pll->min_post_div;
815
816 return post_div;
817 }
818
819 #define MAX_TOLERANCE 10
820
radeon_compute_pll_avivo(struct radeon_pll * pll,u32 freq,u32 * dot_clock_p,u32 * fb_div_p,u32 * frac_fb_div_p,u32 * ref_div_p,u32 * post_div_p)821 void radeon_compute_pll_avivo(struct radeon_pll *pll,
822 u32 freq,
823 u32 *dot_clock_p,
824 u32 *fb_div_p,
825 u32 *frac_fb_div_p,
826 u32 *ref_div_p,
827 u32 *post_div_p)
828 {
829 u32 target_clock = freq / 10;
830 u32 post_div = avivo_get_post_div(pll, target_clock);
831 u32 ref_div = pll->min_ref_div;
832 u32 fb_div = 0, frac_fb_div = 0, tmp;
833
834 if (pll->flags & RADEON_PLL_USE_REF_DIV)
835 ref_div = pll->reference_div;
836
837 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
838 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
839 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
840 if (frac_fb_div >= 5) {
841 frac_fb_div -= 5;
842 frac_fb_div = frac_fb_div / 10;
843 frac_fb_div++;
844 }
845 if (frac_fb_div >= 10) {
846 fb_div++;
847 frac_fb_div = 0;
848 }
849 } else {
850 while (ref_div <= pll->max_ref_div) {
851 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
852 &fb_div, &frac_fb_div);
853 if (frac_fb_div >= (pll->reference_freq / 2))
854 fb_div++;
855 frac_fb_div = 0;
856 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
857 tmp = (tmp * 10000) / target_clock;
858
859 if (tmp > (10000 + MAX_TOLERANCE))
860 ref_div++;
861 else if (tmp >= (10000 - MAX_TOLERANCE))
862 break;
863 else
864 ref_div++;
865 }
866 }
867
868 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
869 (ref_div * post_div * 10);
870 *fb_div_p = fb_div;
871 *frac_fb_div_p = frac_fb_div;
872 *ref_div_p = ref_div;
873 *post_div_p = post_div;
874 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
875 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
876 }
877
878 /* pre-avivo */
radeon_div(uint64_t n,uint32_t d)879 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
880 {
881 uint64_t mod;
882
883 n += d / 2;
884
885 mod = do_div(n, d);
886 return n;
887 }
888
radeon_compute_pll_legacy(struct radeon_pll * pll,uint64_t freq,uint32_t * dot_clock_p,uint32_t * fb_div_p,uint32_t * frac_fb_div_p,uint32_t * ref_div_p,uint32_t * post_div_p)889 void radeon_compute_pll_legacy(struct radeon_pll *pll,
890 uint64_t freq,
891 uint32_t *dot_clock_p,
892 uint32_t *fb_div_p,
893 uint32_t *frac_fb_div_p,
894 uint32_t *ref_div_p,
895 uint32_t *post_div_p)
896 {
897 uint32_t min_ref_div = pll->min_ref_div;
898 uint32_t max_ref_div = pll->max_ref_div;
899 uint32_t min_post_div = pll->min_post_div;
900 uint32_t max_post_div = pll->max_post_div;
901 uint32_t min_fractional_feed_div = 0;
902 uint32_t max_fractional_feed_div = 0;
903 uint32_t best_vco = pll->best_vco;
904 uint32_t best_post_div = 1;
905 uint32_t best_ref_div = 1;
906 uint32_t best_feedback_div = 1;
907 uint32_t best_frac_feedback_div = 0;
908 uint32_t best_freq = -1;
909 uint32_t best_error = 0xffffffff;
910 uint32_t best_vco_diff = 1;
911 uint32_t post_div;
912 u32 pll_out_min, pll_out_max;
913
914 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
915 freq = freq * 1000;
916
917 if (pll->flags & RADEON_PLL_IS_LCD) {
918 pll_out_min = pll->lcd_pll_out_min;
919 pll_out_max = pll->lcd_pll_out_max;
920 } else {
921 pll_out_min = pll->pll_out_min;
922 pll_out_max = pll->pll_out_max;
923 }
924
925 if (pll_out_min > 64800)
926 pll_out_min = 64800;
927
928 if (pll->flags & RADEON_PLL_USE_REF_DIV)
929 min_ref_div = max_ref_div = pll->reference_div;
930 else {
931 while (min_ref_div < max_ref_div-1) {
932 uint32_t mid = (min_ref_div + max_ref_div) / 2;
933 uint32_t pll_in = pll->reference_freq / mid;
934 if (pll_in < pll->pll_in_min)
935 max_ref_div = mid;
936 else if (pll_in > pll->pll_in_max)
937 min_ref_div = mid;
938 else
939 break;
940 }
941 }
942
943 if (pll->flags & RADEON_PLL_USE_POST_DIV)
944 min_post_div = max_post_div = pll->post_div;
945
946 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
947 min_fractional_feed_div = pll->min_frac_feedback_div;
948 max_fractional_feed_div = pll->max_frac_feedback_div;
949 }
950
951 for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
952 uint32_t ref_div;
953
954 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
955 continue;
956
957 /* legacy radeons only have a few post_divs */
958 if (pll->flags & RADEON_PLL_LEGACY) {
959 if ((post_div == 5) ||
960 (post_div == 7) ||
961 (post_div == 9) ||
962 (post_div == 10) ||
963 (post_div == 11) ||
964 (post_div == 13) ||
965 (post_div == 14) ||
966 (post_div == 15))
967 continue;
968 }
969
970 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
971 uint32_t feedback_div, current_freq = 0, error, vco_diff;
972 uint32_t pll_in = pll->reference_freq / ref_div;
973 uint32_t min_feed_div = pll->min_feedback_div;
974 uint32_t max_feed_div = pll->max_feedback_div + 1;
975
976 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
977 continue;
978
979 while (min_feed_div < max_feed_div) {
980 uint32_t vco;
981 uint32_t min_frac_feed_div = min_fractional_feed_div;
982 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
983 uint32_t frac_feedback_div;
984 uint64_t tmp;
985
986 feedback_div = (min_feed_div + max_feed_div) / 2;
987
988 tmp = (uint64_t)pll->reference_freq * feedback_div;
989 vco = radeon_div(tmp, ref_div);
990
991 if (vco < pll_out_min) {
992 min_feed_div = feedback_div + 1;
993 continue;
994 } else if (vco > pll_out_max) {
995 max_feed_div = feedback_div;
996 continue;
997 }
998
999 while (min_frac_feed_div < max_frac_feed_div) {
1000 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1001 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1002 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1003 current_freq = radeon_div(tmp, ref_div * post_div);
1004
1005 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1006 if (freq < current_freq)
1007 error = 0xffffffff;
1008 else
1009 error = freq - current_freq;
1010 } else
1011 error = abs(current_freq - freq);
1012 vco_diff = abs(vco - best_vco);
1013
1014 if ((best_vco == 0 && error < best_error) ||
1015 (best_vco != 0 &&
1016 ((best_error > 100 && error < best_error - 100) ||
1017 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1018 best_post_div = post_div;
1019 best_ref_div = ref_div;
1020 best_feedback_div = feedback_div;
1021 best_frac_feedback_div = frac_feedback_div;
1022 best_freq = current_freq;
1023 best_error = error;
1024 best_vco_diff = vco_diff;
1025 } else if (current_freq == freq) {
1026 if (best_freq == -1) {
1027 best_post_div = post_div;
1028 best_ref_div = ref_div;
1029 best_feedback_div = feedback_div;
1030 best_frac_feedback_div = frac_feedback_div;
1031 best_freq = current_freq;
1032 best_error = error;
1033 best_vco_diff = vco_diff;
1034 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1035 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1036 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1037 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1038 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1039 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1040 best_post_div = post_div;
1041 best_ref_div = ref_div;
1042 best_feedback_div = feedback_div;
1043 best_frac_feedback_div = frac_feedback_div;
1044 best_freq = current_freq;
1045 best_error = error;
1046 best_vco_diff = vco_diff;
1047 }
1048 }
1049 if (current_freq < freq)
1050 min_frac_feed_div = frac_feedback_div + 1;
1051 else
1052 max_frac_feed_div = frac_feedback_div;
1053 }
1054 if (current_freq < freq)
1055 min_feed_div = feedback_div + 1;
1056 else
1057 max_feed_div = feedback_div;
1058 }
1059 }
1060 }
1061
1062 *dot_clock_p = best_freq / 10000;
1063 *fb_div_p = best_feedback_div;
1064 *frac_fb_div_p = best_frac_feedback_div;
1065 *ref_div_p = best_ref_div;
1066 *post_div_p = best_post_div;
1067 DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1068 (long long)freq,
1069 best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1070 best_ref_div, best_post_div);
1071
1072 }
1073
radeon_user_framebuffer_destroy(struct drm_framebuffer * fb)1074 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1075 {
1076 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1077
1078 if (radeon_fb->obj) {
1079 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1080 }
1081 drm_framebuffer_cleanup(fb);
1082 kfree(radeon_fb);
1083 }
1084
radeon_user_framebuffer_create_handle(struct drm_framebuffer * fb,struct drm_file * file_priv,unsigned int * handle)1085 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1086 struct drm_file *file_priv,
1087 unsigned int *handle)
1088 {
1089 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1090
1091 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1092 }
1093
1094 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1095 .destroy = radeon_user_framebuffer_destroy,
1096 .create_handle = radeon_user_framebuffer_create_handle,
1097 };
1098
1099 int
radeon_framebuffer_init(struct drm_device * dev,struct radeon_framebuffer * rfb,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_gem_object * obj)1100 radeon_framebuffer_init(struct drm_device *dev,
1101 struct radeon_framebuffer *rfb,
1102 struct drm_mode_fb_cmd2 *mode_cmd,
1103 struct drm_gem_object *obj)
1104 {
1105 int ret;
1106 rfb->obj = obj;
1107 ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1108 if (ret) {
1109 rfb->obj = NULL;
1110 return ret;
1111 }
1112 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1113 return 0;
1114 }
1115
1116 static struct drm_framebuffer *
radeon_user_framebuffer_create(struct drm_device * dev,struct drm_file * file_priv,struct drm_mode_fb_cmd2 * mode_cmd)1117 radeon_user_framebuffer_create(struct drm_device *dev,
1118 struct drm_file *file_priv,
1119 struct drm_mode_fb_cmd2 *mode_cmd)
1120 {
1121 struct drm_gem_object *obj;
1122 struct radeon_framebuffer *radeon_fb;
1123 int ret;
1124
1125 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1126 if (obj == NULL) {
1127 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1128 "can't create framebuffer\n", mode_cmd->handles[0]);
1129 return ERR_PTR(-ENOENT);
1130 }
1131
1132 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1133 if (radeon_fb == NULL) {
1134 drm_gem_object_unreference_unlocked(obj);
1135 return ERR_PTR(-ENOMEM);
1136 }
1137
1138 ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1139 if (ret) {
1140 kfree(radeon_fb);
1141 drm_gem_object_unreference_unlocked(obj);
1142 return ERR_PTR(ret);
1143 }
1144
1145 return &radeon_fb->base;
1146 }
1147
radeon_output_poll_changed(struct drm_device * dev)1148 static void radeon_output_poll_changed(struct drm_device *dev)
1149 {
1150 struct radeon_device *rdev = dev->dev_private;
1151 radeon_fb_output_poll_changed(rdev);
1152 }
1153
1154 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1155 .fb_create = radeon_user_framebuffer_create,
1156 .output_poll_changed = radeon_output_poll_changed
1157 };
1158
1159 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1160 { { 0, "driver" },
1161 { 1, "bios" },
1162 };
1163
1164 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1165 { { TV_STD_NTSC, "ntsc" },
1166 { TV_STD_PAL, "pal" },
1167 { TV_STD_PAL_M, "pal-m" },
1168 { TV_STD_PAL_60, "pal-60" },
1169 { TV_STD_NTSC_J, "ntsc-j" },
1170 { TV_STD_SCART_PAL, "scart-pal" },
1171 { TV_STD_PAL_CN, "pal-cn" },
1172 { TV_STD_SECAM, "secam" },
1173 };
1174
1175 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1176 { { UNDERSCAN_OFF, "off" },
1177 { UNDERSCAN_ON, "on" },
1178 { UNDERSCAN_AUTO, "auto" },
1179 };
1180
radeon_modeset_create_props(struct radeon_device * rdev)1181 static int radeon_modeset_create_props(struct radeon_device *rdev)
1182 {
1183 int sz;
1184
1185 if (rdev->is_atom_bios) {
1186 rdev->mode_info.coherent_mode_property =
1187 drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1188 if (!rdev->mode_info.coherent_mode_property)
1189 return -ENOMEM;
1190 }
1191
1192 if (!ASIC_IS_AVIVO(rdev)) {
1193 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1194 rdev->mode_info.tmds_pll_property =
1195 drm_property_create_enum(rdev->ddev, 0,
1196 "tmds_pll",
1197 radeon_tmds_pll_enum_list, sz);
1198 }
1199
1200 rdev->mode_info.load_detect_property =
1201 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1202 if (!rdev->mode_info.load_detect_property)
1203 return -ENOMEM;
1204
1205 drm_mode_create_scaling_mode_property(rdev->ddev);
1206
1207 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1208 rdev->mode_info.tv_std_property =
1209 drm_property_create_enum(rdev->ddev, 0,
1210 "tv standard",
1211 radeon_tv_std_enum_list, sz);
1212
1213 sz = ARRAY_SIZE(radeon_underscan_enum_list);
1214 rdev->mode_info.underscan_property =
1215 drm_property_create_enum(rdev->ddev, 0,
1216 "underscan",
1217 radeon_underscan_enum_list, sz);
1218
1219 rdev->mode_info.underscan_hborder_property =
1220 drm_property_create_range(rdev->ddev, 0,
1221 "underscan hborder", 0, 128);
1222 if (!rdev->mode_info.underscan_hborder_property)
1223 return -ENOMEM;
1224
1225 rdev->mode_info.underscan_vborder_property =
1226 drm_property_create_range(rdev->ddev, 0,
1227 "underscan vborder", 0, 128);
1228 if (!rdev->mode_info.underscan_vborder_property)
1229 return -ENOMEM;
1230
1231 return 0;
1232 }
1233
radeon_update_display_priority(struct radeon_device * rdev)1234 void radeon_update_display_priority(struct radeon_device *rdev)
1235 {
1236 /* adjustment options for the display watermarks */
1237 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1238 /* set display priority to high for r3xx, rv515 chips
1239 * this avoids flickering due to underflow to the
1240 * display controllers during heavy acceleration.
1241 * Don't force high on rs4xx igp chips as it seems to
1242 * affect the sound card. See kernel bug 15982.
1243 */
1244 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1245 !(rdev->flags & RADEON_IS_IGP))
1246 rdev->disp_priority = 2;
1247 else
1248 rdev->disp_priority = 0;
1249 } else
1250 rdev->disp_priority = radeon_disp_priority;
1251
1252 }
1253
radeon_modeset_init(struct radeon_device * rdev)1254 int radeon_modeset_init(struct radeon_device *rdev)
1255 {
1256 int i;
1257 int ret;
1258
1259 drm_mode_config_init(rdev->ddev);
1260 rdev->mode_info.mode_config_initialized = true;
1261
1262 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1263
1264 if (ASIC_IS_DCE5(rdev)) {
1265 rdev->ddev->mode_config.max_width = 16384;
1266 rdev->ddev->mode_config.max_height = 16384;
1267 } else if (ASIC_IS_AVIVO(rdev)) {
1268 rdev->ddev->mode_config.max_width = 8192;
1269 rdev->ddev->mode_config.max_height = 8192;
1270 } else {
1271 rdev->ddev->mode_config.max_width = 4096;
1272 rdev->ddev->mode_config.max_height = 4096;
1273 }
1274
1275 rdev->ddev->mode_config.preferred_depth = 24;
1276 rdev->ddev->mode_config.prefer_shadow = 1;
1277
1278 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1279
1280 ret = radeon_modeset_create_props(rdev);
1281 if (ret) {
1282 return ret;
1283 }
1284
1285 /* init i2c buses */
1286 radeon_i2c_init(rdev);
1287
1288 /* check combios for a valid hardcoded EDID - Sun servers */
1289 if (!rdev->is_atom_bios) {
1290 /* check for hardcoded EDID in BIOS */
1291 radeon_combios_check_hardcoded_edid(rdev);
1292 }
1293
1294 /* allocate crtcs */
1295 for (i = 0; i < rdev->num_crtc; i++) {
1296 radeon_crtc_init(rdev->ddev, i);
1297 }
1298
1299 /* okay we should have all the bios connectors */
1300 ret = radeon_setup_enc_conn(rdev->ddev);
1301 if (!ret) {
1302 return ret;
1303 }
1304
1305 /* init dig PHYs, disp eng pll */
1306 if (rdev->is_atom_bios) {
1307 radeon_atom_encoder_init(rdev);
1308 radeon_atom_disp_eng_pll_init(rdev);
1309 }
1310
1311 /* initialize hpd */
1312 radeon_hpd_init(rdev);
1313
1314 /* Initialize power management */
1315 radeon_pm_init(rdev);
1316
1317 radeon_fbdev_init(rdev);
1318 drm_kms_helper_poll_init(rdev->ddev);
1319
1320 return 0;
1321 }
1322
radeon_modeset_fini(struct radeon_device * rdev)1323 void radeon_modeset_fini(struct radeon_device *rdev)
1324 {
1325 radeon_fbdev_fini(rdev);
1326 kfree(rdev->mode_info.bios_hardcoded_edid);
1327 radeon_pm_fini(rdev);
1328
1329 if (rdev->mode_info.mode_config_initialized) {
1330 drm_kms_helper_poll_fini(rdev->ddev);
1331 radeon_hpd_fini(rdev);
1332 drm_mode_config_cleanup(rdev->ddev);
1333 rdev->mode_info.mode_config_initialized = false;
1334 }
1335 /* free i2c buses */
1336 radeon_i2c_fini(rdev);
1337 }
1338
is_hdtv_mode(struct drm_display_mode * mode)1339 static bool is_hdtv_mode(struct drm_display_mode *mode)
1340 {
1341 /* try and guess if this is a tv or a monitor */
1342 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1343 (mode->vdisplay == 576) || /* 576p */
1344 (mode->vdisplay == 720) || /* 720p */
1345 (mode->vdisplay == 1080)) /* 1080p */
1346 return true;
1347 else
1348 return false;
1349 }
1350
radeon_crtc_scaling_mode_fixup(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1351 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1352 struct drm_display_mode *mode,
1353 struct drm_display_mode *adjusted_mode)
1354 {
1355 struct drm_device *dev = crtc->dev;
1356 struct radeon_device *rdev = dev->dev_private;
1357 struct drm_encoder *encoder;
1358 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1359 struct radeon_encoder *radeon_encoder;
1360 struct drm_connector *connector;
1361 struct radeon_connector *radeon_connector;
1362 bool first = true;
1363 u32 src_v = 1, dst_v = 1;
1364 u32 src_h = 1, dst_h = 1;
1365
1366 radeon_crtc->h_border = 0;
1367 radeon_crtc->v_border = 0;
1368
1369 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1370 if (encoder->crtc != crtc)
1371 continue;
1372 radeon_encoder = to_radeon_encoder(encoder);
1373 connector = radeon_get_connector_for_encoder(encoder);
1374 radeon_connector = to_radeon_connector(connector);
1375
1376 if (first) {
1377 /* set scaling */
1378 if (radeon_encoder->rmx_type == RMX_OFF)
1379 radeon_crtc->rmx_type = RMX_OFF;
1380 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1381 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1382 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1383 else
1384 radeon_crtc->rmx_type = RMX_OFF;
1385 /* copy native mode */
1386 memcpy(&radeon_crtc->native_mode,
1387 &radeon_encoder->native_mode,
1388 sizeof(struct drm_display_mode));
1389 src_v = crtc->mode.vdisplay;
1390 dst_v = radeon_crtc->native_mode.vdisplay;
1391 src_h = crtc->mode.hdisplay;
1392 dst_h = radeon_crtc->native_mode.hdisplay;
1393
1394 /* fix up for overscan on hdmi */
1395 if (ASIC_IS_AVIVO(rdev) &&
1396 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1397 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1398 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1399 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1400 is_hdtv_mode(mode)))) {
1401 if (radeon_encoder->underscan_hborder != 0)
1402 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1403 else
1404 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1405 if (radeon_encoder->underscan_vborder != 0)
1406 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1407 else
1408 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1409 radeon_crtc->rmx_type = RMX_FULL;
1410 src_v = crtc->mode.vdisplay;
1411 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1412 src_h = crtc->mode.hdisplay;
1413 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1414 }
1415 first = false;
1416 } else {
1417 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1418 /* WARNING: Right now this can't happen but
1419 * in the future we need to check that scaling
1420 * are consistent across different encoder
1421 * (ie all encoder can work with the same
1422 * scaling).
1423 */
1424 DRM_ERROR("Scaling not consistent across encoder.\n");
1425 return false;
1426 }
1427 }
1428 }
1429 if (radeon_crtc->rmx_type != RMX_OFF) {
1430 fixed20_12 a, b;
1431 a.full = dfixed_const(src_v);
1432 b.full = dfixed_const(dst_v);
1433 radeon_crtc->vsc.full = dfixed_div(a, b);
1434 a.full = dfixed_const(src_h);
1435 b.full = dfixed_const(dst_h);
1436 radeon_crtc->hsc.full = dfixed_div(a, b);
1437 } else {
1438 radeon_crtc->vsc.full = dfixed_const(1);
1439 radeon_crtc->hsc.full = dfixed_const(1);
1440 }
1441 return true;
1442 }
1443
1444 /*
1445 * Retrieve current video scanout position of crtc on a given gpu.
1446 *
1447 * \param dev Device to query.
1448 * \param crtc Crtc to query.
1449 * \param *vpos Location where vertical scanout position should be stored.
1450 * \param *hpos Location where horizontal scanout position should go.
1451 *
1452 * Returns vpos as a positive number while in active scanout area.
1453 * Returns vpos as a negative number inside vblank, counting the number
1454 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1455 * until start of active scanout / end of vblank."
1456 *
1457 * \return Flags, or'ed together as follows:
1458 *
1459 * DRM_SCANOUTPOS_VALID = Query successful.
1460 * DRM_SCANOUTPOS_INVBL = Inside vblank.
1461 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1462 * this flag means that returned position may be offset by a constant but
1463 * unknown small number of scanlines wrt. real scanout position.
1464 *
1465 */
radeon_get_crtc_scanoutpos(struct drm_device * dev,int crtc,int * vpos,int * hpos)1466 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1467 {
1468 u32 stat_crtc = 0, vbl = 0, position = 0;
1469 int vbl_start, vbl_end, vtotal, ret = 0;
1470 bool in_vbl = true;
1471
1472 struct radeon_device *rdev = dev->dev_private;
1473
1474 if (ASIC_IS_DCE4(rdev)) {
1475 if (crtc == 0) {
1476 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1477 EVERGREEN_CRTC0_REGISTER_OFFSET);
1478 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1479 EVERGREEN_CRTC0_REGISTER_OFFSET);
1480 ret |= DRM_SCANOUTPOS_VALID;
1481 }
1482 if (crtc == 1) {
1483 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1484 EVERGREEN_CRTC1_REGISTER_OFFSET);
1485 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1486 EVERGREEN_CRTC1_REGISTER_OFFSET);
1487 ret |= DRM_SCANOUTPOS_VALID;
1488 }
1489 if (crtc == 2) {
1490 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1491 EVERGREEN_CRTC2_REGISTER_OFFSET);
1492 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1493 EVERGREEN_CRTC2_REGISTER_OFFSET);
1494 ret |= DRM_SCANOUTPOS_VALID;
1495 }
1496 if (crtc == 3) {
1497 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1498 EVERGREEN_CRTC3_REGISTER_OFFSET);
1499 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1500 EVERGREEN_CRTC3_REGISTER_OFFSET);
1501 ret |= DRM_SCANOUTPOS_VALID;
1502 }
1503 if (crtc == 4) {
1504 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1505 EVERGREEN_CRTC4_REGISTER_OFFSET);
1506 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1507 EVERGREEN_CRTC4_REGISTER_OFFSET);
1508 ret |= DRM_SCANOUTPOS_VALID;
1509 }
1510 if (crtc == 5) {
1511 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1512 EVERGREEN_CRTC5_REGISTER_OFFSET);
1513 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1514 EVERGREEN_CRTC5_REGISTER_OFFSET);
1515 ret |= DRM_SCANOUTPOS_VALID;
1516 }
1517 } else if (ASIC_IS_AVIVO(rdev)) {
1518 if (crtc == 0) {
1519 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1520 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1521 ret |= DRM_SCANOUTPOS_VALID;
1522 }
1523 if (crtc == 1) {
1524 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1525 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1526 ret |= DRM_SCANOUTPOS_VALID;
1527 }
1528 } else {
1529 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1530 if (crtc == 0) {
1531 /* Assume vbl_end == 0, get vbl_start from
1532 * upper 16 bits.
1533 */
1534 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1535 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1536 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1537 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1538 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1539 if (!(stat_crtc & 1))
1540 in_vbl = false;
1541
1542 ret |= DRM_SCANOUTPOS_VALID;
1543 }
1544 if (crtc == 1) {
1545 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1546 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1547 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1548 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1549 if (!(stat_crtc & 1))
1550 in_vbl = false;
1551
1552 ret |= DRM_SCANOUTPOS_VALID;
1553 }
1554 }
1555
1556 /* Decode into vertical and horizontal scanout position. */
1557 *vpos = position & 0x1fff;
1558 *hpos = (position >> 16) & 0x1fff;
1559
1560 /* Valid vblank area boundaries from gpu retrieved? */
1561 if (vbl > 0) {
1562 /* Yes: Decode. */
1563 ret |= DRM_SCANOUTPOS_ACCURATE;
1564 vbl_start = vbl & 0x1fff;
1565 vbl_end = (vbl >> 16) & 0x1fff;
1566 }
1567 else {
1568 /* No: Fake something reasonable which gives at least ok results. */
1569 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1570 vbl_end = 0;
1571 }
1572
1573 /* Test scanout position against vblank region. */
1574 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1575 in_vbl = false;
1576
1577 /* Check if inside vblank area and apply corrective offsets:
1578 * vpos will then be >=0 in video scanout area, but negative
1579 * within vblank area, counting down the number of lines until
1580 * start of scanout.
1581 */
1582
1583 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1584 if (in_vbl && (*vpos >= vbl_start)) {
1585 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1586 *vpos = *vpos - vtotal;
1587 }
1588
1589 /* Correct for shifted end of vbl at vbl_end. */
1590 *vpos = *vpos - vbl_end;
1591
1592 /* In vblank? */
1593 if (in_vbl)
1594 ret |= DRM_SCANOUTPOS_INVBL;
1595
1596 return ret;
1597 }
1598