1 /*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 /*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <drm/drmP.h>
35 #include "radeon_drm.h"
36 #include "radeon.h"
37 #include "radeon_trace.h"
38
39
40 int radeon_ttm_init(struct radeon_device *rdev);
41 void radeon_ttm_fini(struct radeon_device *rdev);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
43
44 /*
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
47 */
48
radeon_bo_clear_va(struct radeon_bo * bo)49 void radeon_bo_clear_va(struct radeon_bo *bo)
50 {
51 struct radeon_bo_va *bo_va, *tmp;
52
53 list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
54 /* remove from all vm address space */
55 mutex_lock(&bo_va->vm->mutex);
56 list_del(&bo_va->vm_list);
57 mutex_unlock(&bo_va->vm->mutex);
58 list_del(&bo_va->bo_list);
59 kfree(bo_va);
60 }
61 }
62
radeon_ttm_bo_destroy(struct ttm_buffer_object * tbo)63 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
64 {
65 struct radeon_bo *bo;
66
67 bo = container_of(tbo, struct radeon_bo, tbo);
68 mutex_lock(&bo->rdev->gem.mutex);
69 list_del_init(&bo->list);
70 mutex_unlock(&bo->rdev->gem.mutex);
71 radeon_bo_clear_surface_reg(bo);
72 radeon_bo_clear_va(bo);
73 drm_gem_object_release(&bo->gem_base);
74 kfree(bo);
75 }
76
radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object * bo)77 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
78 {
79 if (bo->destroy == &radeon_ttm_bo_destroy)
80 return true;
81 return false;
82 }
83
radeon_ttm_placement_from_domain(struct radeon_bo * rbo,u32 domain)84 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
85 {
86 u32 c = 0;
87
88 rbo->placement.fpfn = 0;
89 rbo->placement.lpfn = 0;
90 rbo->placement.placement = rbo->placements;
91 rbo->placement.busy_placement = rbo->placements;
92 if (domain & RADEON_GEM_DOMAIN_VRAM)
93 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
94 TTM_PL_FLAG_VRAM;
95 if (domain & RADEON_GEM_DOMAIN_GTT)
96 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
97 if (domain & RADEON_GEM_DOMAIN_CPU)
98 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
99 if (!c)
100 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
101 rbo->placement.num_placement = c;
102 rbo->placement.num_busy_placement = c;
103 }
104
radeon_bo_create(struct radeon_device * rdev,unsigned long size,int byte_align,bool kernel,u32 domain,struct radeon_bo ** bo_ptr)105 int radeon_bo_create(struct radeon_device *rdev,
106 unsigned long size, int byte_align, bool kernel, u32 domain,
107 struct radeon_bo **bo_ptr)
108 {
109 struct radeon_bo *bo;
110 enum ttm_bo_type type;
111 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
112 unsigned long max_size = 0;
113 size_t acc_size;
114 int r;
115
116 size = ALIGN(size, PAGE_SIZE);
117
118 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
119 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
120 }
121 if (kernel) {
122 type = ttm_bo_type_kernel;
123 } else {
124 type = ttm_bo_type_device;
125 }
126 *bo_ptr = NULL;
127
128 /* maximun bo size is the minimun btw visible vram and gtt size */
129 max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
130 if ((page_align << PAGE_SHIFT) >= max_size) {
131 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
132 __func__, __LINE__, page_align >> (20 - PAGE_SHIFT), max_size >> 20);
133 return -ENOMEM;
134 }
135
136 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
137 sizeof(struct radeon_bo));
138
139 retry:
140 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
141 if (bo == NULL)
142 return -ENOMEM;
143 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
144 if (unlikely(r)) {
145 kfree(bo);
146 return r;
147 }
148 bo->rdev = rdev;
149 bo->gem_base.driver_private = NULL;
150 bo->surface_reg = -1;
151 INIT_LIST_HEAD(&bo->list);
152 INIT_LIST_HEAD(&bo->va);
153 radeon_ttm_placement_from_domain(bo, domain);
154 /* Kernel allocation are uninterruptible */
155 mutex_lock(&rdev->vram_mutex);
156 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
157 &bo->placement, page_align, 0, !kernel, NULL,
158 acc_size, &radeon_ttm_bo_destroy);
159 mutex_unlock(&rdev->vram_mutex);
160 if (unlikely(r != 0)) {
161 if (r != -ERESTARTSYS) {
162 if (domain == RADEON_GEM_DOMAIN_VRAM) {
163 domain |= RADEON_GEM_DOMAIN_GTT;
164 goto retry;
165 }
166 dev_err(rdev->dev,
167 "object_init failed for (%lu, 0x%08X)\n",
168 size, domain);
169 }
170 return r;
171 }
172 *bo_ptr = bo;
173
174 trace_radeon_bo_create(bo);
175
176 return 0;
177 }
178
radeon_bo_kmap(struct radeon_bo * bo,void ** ptr)179 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
180 {
181 bool is_iomem;
182 int r;
183
184 if (bo->kptr) {
185 if (ptr) {
186 *ptr = bo->kptr;
187 }
188 return 0;
189 }
190 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
191 if (r) {
192 return r;
193 }
194 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
195 if (ptr) {
196 *ptr = bo->kptr;
197 }
198 radeon_bo_check_tiling(bo, 0, 0);
199 return 0;
200 }
201
radeon_bo_kunmap(struct radeon_bo * bo)202 void radeon_bo_kunmap(struct radeon_bo *bo)
203 {
204 if (bo->kptr == NULL)
205 return;
206 bo->kptr = NULL;
207 radeon_bo_check_tiling(bo, 0, 0);
208 ttm_bo_kunmap(&bo->kmap);
209 }
210
radeon_bo_unref(struct radeon_bo ** bo)211 void radeon_bo_unref(struct radeon_bo **bo)
212 {
213 struct ttm_buffer_object *tbo;
214 struct radeon_device *rdev;
215
216 if ((*bo) == NULL)
217 return;
218 rdev = (*bo)->rdev;
219 tbo = &((*bo)->tbo);
220 mutex_lock(&rdev->vram_mutex);
221 ttm_bo_unref(&tbo);
222 mutex_unlock(&rdev->vram_mutex);
223 if (tbo == NULL)
224 *bo = NULL;
225 }
226
radeon_bo_pin_restricted(struct radeon_bo * bo,u32 domain,u64 max_offset,u64 * gpu_addr)227 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
228 u64 *gpu_addr)
229 {
230 int r, i;
231
232 if (bo->pin_count) {
233 bo->pin_count++;
234 if (gpu_addr)
235 *gpu_addr = radeon_bo_gpu_offset(bo);
236
237 if (max_offset != 0) {
238 u64 domain_start;
239
240 if (domain == RADEON_GEM_DOMAIN_VRAM)
241 domain_start = bo->rdev->mc.vram_start;
242 else
243 domain_start = bo->rdev->mc.gtt_start;
244 WARN_ON_ONCE(max_offset <
245 (radeon_bo_gpu_offset(bo) - domain_start));
246 }
247
248 return 0;
249 }
250 radeon_ttm_placement_from_domain(bo, domain);
251 if (domain == RADEON_GEM_DOMAIN_VRAM) {
252 /* force to pin into visible video ram */
253 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
254 }
255 if (max_offset) {
256 u64 lpfn = max_offset >> PAGE_SHIFT;
257
258 if (!bo->placement.lpfn)
259 bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
260
261 if (lpfn < bo->placement.lpfn)
262 bo->placement.lpfn = lpfn;
263 }
264 for (i = 0; i < bo->placement.num_placement; i++)
265 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
266 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
267 if (likely(r == 0)) {
268 bo->pin_count = 1;
269 if (gpu_addr != NULL)
270 *gpu_addr = radeon_bo_gpu_offset(bo);
271 }
272 if (unlikely(r != 0))
273 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
274 return r;
275 }
276
radeon_bo_pin(struct radeon_bo * bo,u32 domain,u64 * gpu_addr)277 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
278 {
279 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
280 }
281
radeon_bo_unpin(struct radeon_bo * bo)282 int radeon_bo_unpin(struct radeon_bo *bo)
283 {
284 int r, i;
285
286 if (!bo->pin_count) {
287 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
288 return 0;
289 }
290 bo->pin_count--;
291 if (bo->pin_count)
292 return 0;
293 for (i = 0; i < bo->placement.num_placement; i++)
294 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
295 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
296 if (unlikely(r != 0))
297 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
298 return r;
299 }
300
radeon_bo_evict_vram(struct radeon_device * rdev)301 int radeon_bo_evict_vram(struct radeon_device *rdev)
302 {
303 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
304 if (0 && (rdev->flags & RADEON_IS_IGP)) {
305 if (rdev->mc.igp_sideport_enabled == false)
306 /* Useless to evict on IGP chips */
307 return 0;
308 }
309 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
310 }
311
radeon_bo_force_delete(struct radeon_device * rdev)312 void radeon_bo_force_delete(struct radeon_device *rdev)
313 {
314 struct radeon_bo *bo, *n;
315
316 if (list_empty(&rdev->gem.objects)) {
317 return;
318 }
319 dev_err(rdev->dev, "Userspace still has active objects !\n");
320 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
321 mutex_lock(&rdev->ddev->struct_mutex);
322 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
323 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
324 *((unsigned long *)&bo->gem_base.refcount));
325 mutex_lock(&bo->rdev->gem.mutex);
326 list_del_init(&bo->list);
327 mutex_unlock(&bo->rdev->gem.mutex);
328 /* this should unref the ttm bo */
329 drm_gem_object_unreference(&bo->gem_base);
330 mutex_unlock(&rdev->ddev->struct_mutex);
331 }
332 }
333
radeon_bo_init(struct radeon_device * rdev)334 int radeon_bo_init(struct radeon_device *rdev)
335 {
336 /* Add an MTRR for the VRAM */
337 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
338 MTRR_TYPE_WRCOMB, 1);
339 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
340 rdev->mc.mc_vram_size >> 20,
341 (unsigned long long)rdev->mc.aper_size >> 20);
342 DRM_INFO("RAM width %dbits %cDR\n",
343 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
344 return radeon_ttm_init(rdev);
345 }
346
radeon_bo_fini(struct radeon_device * rdev)347 void radeon_bo_fini(struct radeon_device *rdev)
348 {
349 radeon_ttm_fini(rdev);
350 }
351
radeon_bo_list_add_object(struct radeon_bo_list * lobj,struct list_head * head)352 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
353 struct list_head *head)
354 {
355 if (lobj->wdomain) {
356 list_add(&lobj->tv.head, head);
357 } else {
358 list_add_tail(&lobj->tv.head, head);
359 }
360 }
361
radeon_bo_list_validate(struct list_head * head)362 int radeon_bo_list_validate(struct list_head *head)
363 {
364 struct radeon_bo_list *lobj;
365 struct radeon_bo *bo;
366 u32 domain;
367 int r;
368
369 r = ttm_eu_reserve_buffers(head);
370 if (unlikely(r != 0)) {
371 return r;
372 }
373 list_for_each_entry(lobj, head, tv.head) {
374 bo = lobj->bo;
375 if (!bo->pin_count) {
376 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
377
378 retry:
379 radeon_ttm_placement_from_domain(bo, domain);
380 r = ttm_bo_validate(&bo->tbo, &bo->placement,
381 true, false, false);
382 if (unlikely(r)) {
383 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
384 domain |= RADEON_GEM_DOMAIN_GTT;
385 goto retry;
386 }
387 return r;
388 }
389 }
390 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
391 lobj->tiling_flags = bo->tiling_flags;
392 }
393 return 0;
394 }
395
radeon_bo_fbdev_mmap(struct radeon_bo * bo,struct vm_area_struct * vma)396 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
397 struct vm_area_struct *vma)
398 {
399 return ttm_fbdev_mmap(vma, &bo->tbo);
400 }
401
radeon_bo_get_surface_reg(struct radeon_bo * bo)402 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
403 {
404 struct radeon_device *rdev = bo->rdev;
405 struct radeon_surface_reg *reg;
406 struct radeon_bo *old_object;
407 int steal;
408 int i;
409
410 BUG_ON(!atomic_read(&bo->tbo.reserved));
411
412 if (!bo->tiling_flags)
413 return 0;
414
415 if (bo->surface_reg >= 0) {
416 reg = &rdev->surface_regs[bo->surface_reg];
417 i = bo->surface_reg;
418 goto out;
419 }
420
421 steal = -1;
422 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
423
424 reg = &rdev->surface_regs[i];
425 if (!reg->bo)
426 break;
427
428 old_object = reg->bo;
429 if (old_object->pin_count == 0)
430 steal = i;
431 }
432
433 /* if we are all out */
434 if (i == RADEON_GEM_MAX_SURFACES) {
435 if (steal == -1)
436 return -ENOMEM;
437 /* find someone with a surface reg and nuke their BO */
438 reg = &rdev->surface_regs[steal];
439 old_object = reg->bo;
440 /* blow away the mapping */
441 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
442 ttm_bo_unmap_virtual(&old_object->tbo);
443 old_object->surface_reg = -1;
444 i = steal;
445 }
446
447 bo->surface_reg = i;
448 reg->bo = bo;
449
450 out:
451 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
452 bo->tbo.mem.start << PAGE_SHIFT,
453 bo->tbo.num_pages << PAGE_SHIFT);
454 return 0;
455 }
456
radeon_bo_clear_surface_reg(struct radeon_bo * bo)457 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
458 {
459 struct radeon_device *rdev = bo->rdev;
460 struct radeon_surface_reg *reg;
461
462 if (bo->surface_reg == -1)
463 return;
464
465 reg = &rdev->surface_regs[bo->surface_reg];
466 radeon_clear_surface_reg(rdev, bo->surface_reg);
467
468 reg->bo = NULL;
469 bo->surface_reg = -1;
470 }
471
radeon_bo_set_tiling_flags(struct radeon_bo * bo,uint32_t tiling_flags,uint32_t pitch)472 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
473 uint32_t tiling_flags, uint32_t pitch)
474 {
475 struct radeon_device *rdev = bo->rdev;
476 int r;
477
478 if (rdev->family >= CHIP_CEDAR) {
479 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
480
481 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
482 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
483 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
484 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
485 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
486 switch (bankw) {
487 case 0:
488 case 1:
489 case 2:
490 case 4:
491 case 8:
492 break;
493 default:
494 return -EINVAL;
495 }
496 switch (bankh) {
497 case 0:
498 case 1:
499 case 2:
500 case 4:
501 case 8:
502 break;
503 default:
504 return -EINVAL;
505 }
506 switch (mtaspect) {
507 case 0:
508 case 1:
509 case 2:
510 case 4:
511 case 8:
512 break;
513 default:
514 return -EINVAL;
515 }
516 if (tilesplit > 6) {
517 return -EINVAL;
518 }
519 if (stilesplit > 6) {
520 return -EINVAL;
521 }
522 }
523 r = radeon_bo_reserve(bo, false);
524 if (unlikely(r != 0))
525 return r;
526 bo->tiling_flags = tiling_flags;
527 bo->pitch = pitch;
528 radeon_bo_unreserve(bo);
529 return 0;
530 }
531
radeon_bo_get_tiling_flags(struct radeon_bo * bo,uint32_t * tiling_flags,uint32_t * pitch)532 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
533 uint32_t *tiling_flags,
534 uint32_t *pitch)
535 {
536 BUG_ON(!atomic_read(&bo->tbo.reserved));
537 if (tiling_flags)
538 *tiling_flags = bo->tiling_flags;
539 if (pitch)
540 *pitch = bo->pitch;
541 }
542
radeon_bo_check_tiling(struct radeon_bo * bo,bool has_moved,bool force_drop)543 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
544 bool force_drop)
545 {
546 BUG_ON(!atomic_read(&bo->tbo.reserved));
547
548 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
549 return 0;
550
551 if (force_drop) {
552 radeon_bo_clear_surface_reg(bo);
553 return 0;
554 }
555
556 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
557 if (!has_moved)
558 return 0;
559
560 if (bo->surface_reg >= 0)
561 radeon_bo_clear_surface_reg(bo);
562 return 0;
563 }
564
565 if ((bo->surface_reg >= 0) && !has_moved)
566 return 0;
567
568 return radeon_bo_get_surface_reg(bo);
569 }
570
radeon_bo_move_notify(struct ttm_buffer_object * bo,struct ttm_mem_reg * mem)571 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
572 struct ttm_mem_reg *mem)
573 {
574 struct radeon_bo *rbo;
575 if (!radeon_ttm_bo_is_radeon_bo(bo))
576 return;
577 rbo = container_of(bo, struct radeon_bo, tbo);
578 radeon_bo_check_tiling(rbo, 0, 1);
579 radeon_vm_bo_invalidate(rbo->rdev, rbo);
580 }
581
radeon_bo_fault_reserve_notify(struct ttm_buffer_object * bo)582 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
583 {
584 struct radeon_device *rdev;
585 struct radeon_bo *rbo;
586 unsigned long offset, size;
587 int r;
588
589 if (!radeon_ttm_bo_is_radeon_bo(bo))
590 return 0;
591 rbo = container_of(bo, struct radeon_bo, tbo);
592 radeon_bo_check_tiling(rbo, 0, 0);
593 rdev = rbo->rdev;
594 if (bo->mem.mem_type == TTM_PL_VRAM) {
595 size = bo->mem.num_pages << PAGE_SHIFT;
596 offset = bo->mem.start << PAGE_SHIFT;
597 if ((offset + size) > rdev->mc.visible_vram_size) {
598 /* hurrah the memory is not visible ! */
599 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
600 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
601 r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
602 if (unlikely(r != 0))
603 return r;
604 offset = bo->mem.start << PAGE_SHIFT;
605 /* this should not happen */
606 if ((offset + size) > rdev->mc.visible_vram_size)
607 return -EINVAL;
608 }
609 }
610 return 0;
611 }
612
radeon_bo_wait(struct radeon_bo * bo,u32 * mem_type,bool no_wait)613 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
614 {
615 int r;
616
617 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
618 if (unlikely(r != 0))
619 return r;
620 spin_lock(&bo->tbo.bdev->fence_lock);
621 if (mem_type)
622 *mem_type = bo->tbo.mem.mem_type;
623 if (bo->tbo.sync_obj)
624 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
625 spin_unlock(&bo->tbo.bdev->fence_lock);
626 ttm_bo_unreserve(&bo->tbo);
627 return r;
628 }
629
630
631 /**
632 * radeon_bo_reserve - reserve bo
633 * @bo: bo structure
634 * @no_wait: don't sleep while trying to reserve (return -EBUSY)
635 *
636 * Returns:
637 * -EBUSY: buffer is busy and @no_wait is true
638 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
639 * a signal. Release all buffer reservations and return to user-space.
640 */
radeon_bo_reserve(struct radeon_bo * bo,bool no_wait)641 int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait)
642 {
643 int r;
644
645 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
646 if (unlikely(r != 0)) {
647 if (r != -ERESTARTSYS)
648 dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
649 return r;
650 }
651 return 0;
652 }
653
654 /* object have to be reserved */
radeon_bo_va(struct radeon_bo * rbo,struct radeon_vm * vm)655 struct radeon_bo_va *radeon_bo_va(struct radeon_bo *rbo, struct radeon_vm *vm)
656 {
657 struct radeon_bo_va *bo_va;
658
659 list_for_each_entry(bo_va, &rbo->va, bo_list) {
660 if (bo_va->vm == vm) {
661 return bo_va;
662 }
663 }
664 return NULL;
665 }
666