1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30 
31 /* TODO: Here are things that needs to be done :
32  *	- surface allocator & initializer : (bit like scratch reg) should
33  *	  initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34  *	  related to surface
35  *	- WB : write back stuff (do it bit like scratch reg things)
36  *	- Vblank : look at Jesse's rework and what we should do
37  *	- r600/r700: gart & cp
38  *	- cs : clean cs ioctl use bitmap & things like that.
39  *	- power management stuff
40  *	- Barrier in gart code
41  *	- Unmappabled vram ?
42  *	- TESTING, TESTING, TESTING
43  */
44 
45 /* Initialization path:
46  *  We expect that acceleration initialization might fail for various
47  *  reasons even thought we work hard to make it works on most
48  *  configurations. In order to still have a working userspace in such
49  *  situation the init path must succeed up to the memory controller
50  *  initialization point. Failure before this point are considered as
51  *  fatal error. Here is the init callchain :
52  *      radeon_device_init  perform common structure, mutex initialization
53  *      asic_init           setup the GPU memory layout and perform all
54  *                          one time initialization (failure in this
55  *                          function are considered fatal)
56  *      asic_startup        setup the GPU acceleration, in order to
57  *                          follow guideline the first thing this
58  *                          function should do is setting the GPU
59  *                          memory controller (only MC setup failure
60  *                          are considered as fatal)
61  */
62 
63 #include <linux/agp_backend.h>
64 #include <linux/atomic.h>
65 #include <linux/wait.h>
66 #include <linux/list.h>
67 #include <linux/kref.h>
68 #include <linux/interval_tree.h>
69 #include <linux/hashtable.h>
70 #include <linux/dma-fence.h>
71 
72 #ifdef CONFIG_MMU_NOTIFIER
73 #include <linux/mmu_notifier.h>
74 #endif
75 
76 #include <drm/ttm/ttm_bo_api.h>
77 #include <drm/ttm/ttm_bo_driver.h>
78 #include <drm/ttm/ttm_placement.h>
79 #include <drm/ttm/ttm_execbuf_util.h>
80 
81 #include <drm/drm_gem.h>
82 
83 #include "radeon_family.h"
84 #include "radeon_mode.h"
85 #include "radeon_reg.h"
86 
87 /*
88  * Modules parameters.
89  */
90 extern int radeon_no_wb;
91 extern int radeon_modeset;
92 extern int radeon_dynclks;
93 extern int radeon_r4xx_atom;
94 extern int radeon_agpmode;
95 extern int radeon_vram_limit;
96 extern int radeon_gart_size;
97 extern int radeon_benchmarking;
98 extern int radeon_testing;
99 extern int radeon_connector_table;
100 extern int radeon_tv;
101 extern int radeon_audio;
102 extern int radeon_disp_priority;
103 extern int radeon_hw_i2c;
104 extern int radeon_pcie_gen2;
105 extern int radeon_msi;
106 extern int radeon_lockup_timeout;
107 extern int radeon_fastfb;
108 extern int radeon_dpm;
109 extern int radeon_aspm;
110 extern int radeon_runtime_pm;
111 extern int radeon_hard_reset;
112 extern int radeon_vm_size;
113 extern int radeon_vm_block_size;
114 extern int radeon_deep_color;
115 extern int radeon_use_pflipirq;
116 extern int radeon_bapm;
117 extern int radeon_backlight;
118 extern int radeon_auxch;
119 extern int radeon_uvd;
120 extern int radeon_vce;
121 extern int radeon_si_support;
122 extern int radeon_cik_support;
123 
124 /*
125  * Copy from radeon_drv.h so we don't have to include both and have conflicting
126  * symbol;
127  */
128 #define RADEON_MAX_USEC_TIMEOUT			100000	/* 100 ms */
129 #define RADEON_FENCE_JIFFIES_TIMEOUT		(HZ / 2)
130 #define RADEON_USEC_IB_TEST_TIMEOUT		1000000 /* 1s */
131 /* RADEON_IB_POOL_SIZE must be a power of 2 */
132 #define RADEON_IB_POOL_SIZE			16
133 #define RADEON_DEBUGFS_MAX_COMPONENTS		32
134 #define RADEONFB_CONN_LIMIT			4
135 #define RADEON_BIOS_NUM_SCRATCH			8
136 
137 /* internal ring indices */
138 /* r1xx+ has gfx CP ring */
139 #define RADEON_RING_TYPE_GFX_INDEX		0
140 
141 /* cayman has 2 compute CP rings */
142 #define CAYMAN_RING_TYPE_CP1_INDEX		1
143 #define CAYMAN_RING_TYPE_CP2_INDEX		2
144 
145 /* R600+ has an async dma ring */
146 #define R600_RING_TYPE_DMA_INDEX		3
147 /* cayman add a second async dma ring */
148 #define CAYMAN_RING_TYPE_DMA1_INDEX		4
149 
150 /* R600+ */
151 #define R600_RING_TYPE_UVD_INDEX		5
152 
153 /* TN+ */
154 #define TN_RING_TYPE_VCE1_INDEX			6
155 #define TN_RING_TYPE_VCE2_INDEX			7
156 
157 /* max number of rings */
158 #define RADEON_NUM_RINGS			8
159 
160 /* number of hw syncs before falling back on blocking */
161 #define RADEON_NUM_SYNCS			4
162 
163 /* hardcode those limit for now */
164 #define RADEON_VA_IB_OFFSET			(1 << 20)
165 #define RADEON_VA_RESERVED_SIZE			(8 << 20)
166 #define RADEON_IB_VM_MAX_SIZE			(64 << 10)
167 
168 /* hard reset data */
169 #define RADEON_ASIC_RESET_DATA                  0x39d5e86b
170 
171 /* reset flags */
172 #define RADEON_RESET_GFX			(1 << 0)
173 #define RADEON_RESET_COMPUTE			(1 << 1)
174 #define RADEON_RESET_DMA			(1 << 2)
175 #define RADEON_RESET_CP				(1 << 3)
176 #define RADEON_RESET_GRBM			(1 << 4)
177 #define RADEON_RESET_DMA1			(1 << 5)
178 #define RADEON_RESET_RLC			(1 << 6)
179 #define RADEON_RESET_SEM			(1 << 7)
180 #define RADEON_RESET_IH				(1 << 8)
181 #define RADEON_RESET_VMC			(1 << 9)
182 #define RADEON_RESET_MC				(1 << 10)
183 #define RADEON_RESET_DISPLAY			(1 << 11)
184 
185 /* CG block flags */
186 #define RADEON_CG_BLOCK_GFX			(1 << 0)
187 #define RADEON_CG_BLOCK_MC			(1 << 1)
188 #define RADEON_CG_BLOCK_SDMA			(1 << 2)
189 #define RADEON_CG_BLOCK_UVD			(1 << 3)
190 #define RADEON_CG_BLOCK_VCE			(1 << 4)
191 #define RADEON_CG_BLOCK_HDP			(1 << 5)
192 #define RADEON_CG_BLOCK_BIF			(1 << 6)
193 
194 /* CG flags */
195 #define RADEON_CG_SUPPORT_GFX_MGCG		(1 << 0)
196 #define RADEON_CG_SUPPORT_GFX_MGLS		(1 << 1)
197 #define RADEON_CG_SUPPORT_GFX_CGCG		(1 << 2)
198 #define RADEON_CG_SUPPORT_GFX_CGLS		(1 << 3)
199 #define RADEON_CG_SUPPORT_GFX_CGTS		(1 << 4)
200 #define RADEON_CG_SUPPORT_GFX_CGTS_LS		(1 << 5)
201 #define RADEON_CG_SUPPORT_GFX_CP_LS		(1 << 6)
202 #define RADEON_CG_SUPPORT_GFX_RLC_LS		(1 << 7)
203 #define RADEON_CG_SUPPORT_MC_LS			(1 << 8)
204 #define RADEON_CG_SUPPORT_MC_MGCG		(1 << 9)
205 #define RADEON_CG_SUPPORT_SDMA_LS		(1 << 10)
206 #define RADEON_CG_SUPPORT_SDMA_MGCG		(1 << 11)
207 #define RADEON_CG_SUPPORT_BIF_LS		(1 << 12)
208 #define RADEON_CG_SUPPORT_UVD_MGCG		(1 << 13)
209 #define RADEON_CG_SUPPORT_VCE_MGCG		(1 << 14)
210 #define RADEON_CG_SUPPORT_HDP_LS		(1 << 15)
211 #define RADEON_CG_SUPPORT_HDP_MGCG		(1 << 16)
212 
213 /* PG flags */
214 #define RADEON_PG_SUPPORT_GFX_PG		(1 << 0)
215 #define RADEON_PG_SUPPORT_GFX_SMG		(1 << 1)
216 #define RADEON_PG_SUPPORT_GFX_DMG		(1 << 2)
217 #define RADEON_PG_SUPPORT_UVD			(1 << 3)
218 #define RADEON_PG_SUPPORT_VCE			(1 << 4)
219 #define RADEON_PG_SUPPORT_CP			(1 << 5)
220 #define RADEON_PG_SUPPORT_GDS			(1 << 6)
221 #define RADEON_PG_SUPPORT_RLC_SMU_HS		(1 << 7)
222 #define RADEON_PG_SUPPORT_SDMA			(1 << 8)
223 #define RADEON_PG_SUPPORT_ACP			(1 << 9)
224 #define RADEON_PG_SUPPORT_SAMU			(1 << 10)
225 
226 /* max cursor sizes (in pixels) */
227 #define CURSOR_WIDTH 64
228 #define CURSOR_HEIGHT 64
229 
230 #define CIK_CURSOR_WIDTH 128
231 #define CIK_CURSOR_HEIGHT 128
232 
233 /*
234  * Errata workarounds.
235  */
236 enum radeon_pll_errata {
237 	CHIP_ERRATA_R300_CG             = 0x00000001,
238 	CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
239 	CHIP_ERRATA_PLL_DELAY           = 0x00000004
240 };
241 
242 
243 struct radeon_device;
244 
245 
246 /*
247  * BIOS.
248  */
249 bool radeon_get_bios(struct radeon_device *rdev);
250 
251 /*
252  * Dummy page
253  */
254 struct radeon_dummy_page {
255 	uint64_t	entry;
256 	struct page	*page;
257 	dma_addr_t	addr;
258 };
259 int radeon_dummy_page_init(struct radeon_device *rdev);
260 void radeon_dummy_page_fini(struct radeon_device *rdev);
261 
262 
263 /*
264  * Clocks
265  */
266 struct radeon_clock {
267 	struct radeon_pll p1pll;
268 	struct radeon_pll p2pll;
269 	struct radeon_pll dcpll;
270 	struct radeon_pll spll;
271 	struct radeon_pll mpll;
272 	/* 10 Khz units */
273 	uint32_t default_mclk;
274 	uint32_t default_sclk;
275 	uint32_t default_dispclk;
276 	uint32_t current_dispclk;
277 	uint32_t dp_extclk;
278 	uint32_t max_pixel_clock;
279 	uint32_t vco_freq;
280 };
281 
282 /*
283  * Power management
284  */
285 int radeon_pm_init(struct radeon_device *rdev);
286 int radeon_pm_late_init(struct radeon_device *rdev);
287 void radeon_pm_fini(struct radeon_device *rdev);
288 void radeon_pm_compute_clocks(struct radeon_device *rdev);
289 void radeon_pm_suspend(struct radeon_device *rdev);
290 void radeon_pm_resume(struct radeon_device *rdev);
291 void radeon_combios_get_power_modes(struct radeon_device *rdev);
292 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
293 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
294 				   u8 clock_type,
295 				   u32 clock,
296 				   bool strobe_mode,
297 				   struct atom_clock_dividers *dividers);
298 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
299 					u32 clock,
300 					bool strobe_mode,
301 					struct atom_mpll_param *mpll_param);
302 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
303 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
304 					  u16 voltage_level, u8 voltage_type,
305 					  u32 *gpio_value, u32 *gpio_mask);
306 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
307 					 u32 eng_clock, u32 mem_clock);
308 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
309 				 u8 voltage_type, u16 *voltage_step);
310 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
311 			     u16 voltage_id, u16 *voltage);
312 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
313 						      u16 *voltage,
314 						      u16 leakage_idx);
315 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
316 					  u16 *leakage_id);
317 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
318 							 u16 *vddc, u16 *vddci,
319 							 u16 virtual_voltage_id,
320 							 u16 vbios_voltage_id);
321 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
322 				u16 virtual_voltage_id,
323 				u16 *voltage);
324 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
325 				      u8 voltage_type,
326 				      u16 nominal_voltage,
327 				      u16 *true_voltage);
328 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
329 				u8 voltage_type, u16 *min_voltage);
330 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
331 				u8 voltage_type, u16 *max_voltage);
332 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
333 				  u8 voltage_type, u8 voltage_mode,
334 				  struct atom_voltage_table *voltage_table);
335 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
336 				 u8 voltage_type, u8 voltage_mode);
337 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
338 			      u8 voltage_type,
339 			      u8 *svd_gpio_id, u8 *svc_gpio_id);
340 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
341 				   u32 mem_clock);
342 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
343 			       u32 mem_clock);
344 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
345 				  u8 module_index,
346 				  struct atom_mc_reg_table *reg_table);
347 int radeon_atom_get_memory_info(struct radeon_device *rdev,
348 				u8 module_index, struct atom_memory_info *mem_info);
349 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
350 				     bool gddr5, u8 module_index,
351 				     struct atom_memory_clock_range_table *mclk_range_table);
352 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
353 			     u16 voltage_id, u16 *voltage);
354 void rs690_pm_info(struct radeon_device *rdev);
355 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
356 				    unsigned *bankh, unsigned *mtaspect,
357 				    unsigned *tile_split);
358 
359 /*
360  * Fences.
361  */
362 struct radeon_fence_driver {
363 	struct radeon_device		*rdev;
364 	uint32_t			scratch_reg;
365 	uint64_t			gpu_addr;
366 	volatile uint32_t		*cpu_addr;
367 	/* sync_seq is protected by ring emission lock */
368 	uint64_t			sync_seq[RADEON_NUM_RINGS];
369 	atomic64_t			last_seq;
370 	bool				initialized, delayed_irq;
371 	struct delayed_work		lockup_work;
372 };
373 
374 struct radeon_fence {
375 	struct dma_fence		base;
376 
377 	struct radeon_device	*rdev;
378 	uint64_t		seq;
379 	/* RB, DMA, etc. */
380 	unsigned		ring;
381 	bool			is_vm_update;
382 
383 	wait_queue_entry_t		fence_wake;
384 };
385 
386 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
387 void radeon_fence_driver_init(struct radeon_device *rdev);
388 void radeon_fence_driver_fini(struct radeon_device *rdev);
389 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
390 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
391 void radeon_fence_process(struct radeon_device *rdev, int ring);
392 bool radeon_fence_signaled(struct radeon_fence *fence);
393 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
394 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
395 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
396 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
397 int radeon_fence_wait_any(struct radeon_device *rdev,
398 			  struct radeon_fence **fences,
399 			  bool intr);
400 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
401 void radeon_fence_unref(struct radeon_fence **fence);
402 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
403 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
404 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
radeon_fence_later(struct radeon_fence * a,struct radeon_fence * b)405 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
406 						      struct radeon_fence *b)
407 {
408 	if (!a) {
409 		return b;
410 	}
411 
412 	if (!b) {
413 		return a;
414 	}
415 
416 	BUG_ON(a->ring != b->ring);
417 
418 	if (a->seq > b->seq) {
419 		return a;
420 	} else {
421 		return b;
422 	}
423 }
424 
radeon_fence_is_earlier(struct radeon_fence * a,struct radeon_fence * b)425 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
426 					   struct radeon_fence *b)
427 {
428 	if (!a) {
429 		return false;
430 	}
431 
432 	if (!b) {
433 		return true;
434 	}
435 
436 	BUG_ON(a->ring != b->ring);
437 
438 	return a->seq < b->seq;
439 }
440 
441 /*
442  * Tiling registers
443  */
444 struct radeon_surface_reg {
445 	struct radeon_bo *bo;
446 };
447 
448 #define RADEON_GEM_MAX_SURFACES 8
449 
450 /*
451  * TTM.
452  */
453 struct radeon_mman {
454 	struct ttm_device		bdev;
455 	bool				initialized;
456 };
457 
458 struct radeon_bo_list {
459 	struct radeon_bo		*robj;
460 	struct ttm_validate_buffer	tv;
461 	uint64_t			gpu_offset;
462 	unsigned			preferred_domains;
463 	unsigned			allowed_domains;
464 	uint32_t			tiling_flags;
465 };
466 
467 /* bo virtual address in a specific vm */
468 struct radeon_bo_va {
469 	/* protected by bo being reserved */
470 	struct list_head		bo_list;
471 	uint32_t			flags;
472 	struct radeon_fence		*last_pt_update;
473 	unsigned			ref_count;
474 
475 	/* protected by vm mutex */
476 	struct interval_tree_node	it;
477 	struct list_head		vm_status;
478 
479 	/* constant after initialization */
480 	struct radeon_vm		*vm;
481 	struct radeon_bo		*bo;
482 };
483 
484 struct radeon_bo {
485 	/* Protected by gem.mutex */
486 	struct list_head		list;
487 	/* Protected by tbo.reserved */
488 	u32				initial_domain;
489 	struct ttm_place		placements[4];
490 	struct ttm_placement		placement;
491 	struct ttm_buffer_object	tbo;
492 	struct ttm_bo_kmap_obj		kmap;
493 	u32				flags;
494 	void				*kptr;
495 	u32				tiling_flags;
496 	u32				pitch;
497 	int				surface_reg;
498 	unsigned			prime_shared_count;
499 	/* list of all virtual address to which this bo
500 	 * is associated to
501 	 */
502 	struct list_head		va;
503 	/* Constant after initialization */
504 	struct radeon_device		*rdev;
505 
506 	pid_t				pid;
507 
508 #ifdef CONFIG_MMU_NOTIFIER
509 	struct mmu_interval_notifier	notifier;
510 #endif
511 };
512 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, tbo.base)
513 
514 /* sub-allocation manager, it has to be protected by another lock.
515  * By conception this is an helper for other part of the driver
516  * like the indirect buffer or semaphore, which both have their
517  * locking.
518  *
519  * Principe is simple, we keep a list of sub allocation in offset
520  * order (first entry has offset == 0, last entry has the highest
521  * offset).
522  *
523  * When allocating new object we first check if there is room at
524  * the end total_size - (last_object_offset + last_object_size) >=
525  * alloc_size. If so we allocate new object there.
526  *
527  * When there is not enough room at the end, we start waiting for
528  * each sub object until we reach object_offset+object_size >=
529  * alloc_size, this object then become the sub object we return.
530  *
531  * Alignment can't be bigger than page size.
532  *
533  * Hole are not considered for allocation to keep things simple.
534  * Assumption is that there won't be hole (all object on same
535  * alignment).
536  */
537 struct radeon_sa_manager {
538 	wait_queue_head_t	wq;
539 	struct radeon_bo	*bo;
540 	struct list_head	*hole;
541 	struct list_head	flist[RADEON_NUM_RINGS];
542 	struct list_head	olist;
543 	unsigned		size;
544 	uint64_t		gpu_addr;
545 	void			*cpu_ptr;
546 	uint32_t		domain;
547 	uint32_t		align;
548 };
549 
550 struct radeon_sa_bo;
551 
552 /* sub-allocation buffer */
553 struct radeon_sa_bo {
554 	struct list_head		olist;
555 	struct list_head		flist;
556 	struct radeon_sa_manager	*manager;
557 	unsigned			soffset;
558 	unsigned			eoffset;
559 	struct radeon_fence		*fence;
560 };
561 
562 /*
563  * GEM objects.
564  */
565 struct radeon_gem {
566 	struct mutex		mutex;
567 	struct list_head	objects;
568 };
569 
570 extern const struct drm_gem_object_funcs radeon_gem_object_funcs;
571 
572 int radeon_gem_init(struct radeon_device *rdev);
573 void radeon_gem_fini(struct radeon_device *rdev);
574 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
575 				int alignment, int initial_domain,
576 				u32 flags, bool kernel,
577 				struct drm_gem_object **obj);
578 
579 int radeon_mode_dumb_create(struct drm_file *file_priv,
580 			    struct drm_device *dev,
581 			    struct drm_mode_create_dumb *args);
582 int radeon_mode_dumb_mmap(struct drm_file *filp,
583 			  struct drm_device *dev,
584 			  uint32_t handle, uint64_t *offset_p);
585 
586 /*
587  * Semaphores.
588  */
589 struct radeon_semaphore {
590 	struct radeon_sa_bo	*sa_bo;
591 	signed			waiters;
592 	uint64_t		gpu_addr;
593 };
594 
595 int radeon_semaphore_create(struct radeon_device *rdev,
596 			    struct radeon_semaphore **semaphore);
597 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
598 				  struct radeon_semaphore *semaphore);
599 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
600 				struct radeon_semaphore *semaphore);
601 void radeon_semaphore_free(struct radeon_device *rdev,
602 			   struct radeon_semaphore **semaphore,
603 			   struct radeon_fence *fence);
604 
605 /*
606  * Synchronization
607  */
608 struct radeon_sync {
609 	struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
610 	struct radeon_fence	*sync_to[RADEON_NUM_RINGS];
611 	struct radeon_fence	*last_vm_update;
612 };
613 
614 void radeon_sync_create(struct radeon_sync *sync);
615 void radeon_sync_fence(struct radeon_sync *sync,
616 		       struct radeon_fence *fence);
617 int radeon_sync_resv(struct radeon_device *rdev,
618 		     struct radeon_sync *sync,
619 		     struct dma_resv *resv,
620 		     bool shared);
621 int radeon_sync_rings(struct radeon_device *rdev,
622 		      struct radeon_sync *sync,
623 		      int waiting_ring);
624 void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
625 		      struct radeon_fence *fence);
626 
627 /*
628  * GART structures, functions & helpers
629  */
630 struct radeon_mc;
631 
632 #define RADEON_GPU_PAGE_SIZE 4096
633 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
634 #define RADEON_GPU_PAGE_SHIFT 12
635 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
636 
637 #define RADEON_GART_PAGE_DUMMY  0
638 #define RADEON_GART_PAGE_VALID	(1 << 0)
639 #define RADEON_GART_PAGE_READ	(1 << 1)
640 #define RADEON_GART_PAGE_WRITE	(1 << 2)
641 #define RADEON_GART_PAGE_SNOOP	(1 << 3)
642 
643 struct radeon_gart {
644 	dma_addr_t			table_addr;
645 	struct radeon_bo		*robj;
646 	void				*ptr;
647 	unsigned			num_gpu_pages;
648 	unsigned			num_cpu_pages;
649 	unsigned			table_size;
650 	struct page			**pages;
651 	uint64_t			*pages_entry;
652 	bool				ready;
653 };
654 
655 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
656 void radeon_gart_table_ram_free(struct radeon_device *rdev);
657 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
658 void radeon_gart_table_vram_free(struct radeon_device *rdev);
659 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
660 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
661 int radeon_gart_init(struct radeon_device *rdev);
662 void radeon_gart_fini(struct radeon_device *rdev);
663 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
664 			int pages);
665 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
666 		     int pages, struct page **pagelist,
667 		     dma_addr_t *dma_addr, uint32_t flags);
668 
669 
670 /*
671  * GPU MC structures, functions & helpers
672  */
673 struct radeon_mc {
674 	resource_size_t		aper_size;
675 	resource_size_t		aper_base;
676 	resource_size_t		agp_base;
677 	/* for some chips with <= 32MB we need to lie
678 	 * about vram size near mc fb location */
679 	u64			mc_vram_size;
680 	u64			visible_vram_size;
681 	u64			gtt_size;
682 	u64			gtt_start;
683 	u64			gtt_end;
684 	u64			vram_start;
685 	u64			vram_end;
686 	unsigned		vram_width;
687 	u64			real_vram_size;
688 	int			vram_mtrr;
689 	bool			vram_is_ddr;
690 	bool			igp_sideport_enabled;
691 	u64                     gtt_base_align;
692 	u64                     mc_mask;
693 };
694 
695 bool radeon_combios_sideport_present(struct radeon_device *rdev);
696 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
697 
698 /*
699  * GPU scratch registers structures, functions & helpers
700  */
701 struct radeon_scratch {
702 	unsigned		num_reg;
703 	uint32_t                reg_base;
704 	bool			free[32];
705 	uint32_t		reg[32];
706 };
707 
708 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
709 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
710 
711 /*
712  * GPU doorbell structures, functions & helpers
713  */
714 #define RADEON_MAX_DOORBELLS 1024	/* Reserve at most 1024 doorbell slots for radeon-owned rings. */
715 
716 struct radeon_doorbell {
717 	/* doorbell mmio */
718 	resource_size_t		base;
719 	resource_size_t		size;
720 	u32 __iomem		*ptr;
721 	u32			num_doorbells;	/* Number of doorbells actually reserved for radeon. */
722 	DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
723 };
724 
725 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
726 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
727 
728 /*
729  * IRQS.
730  */
731 
732 struct radeon_flip_work {
733 	struct work_struct		flip_work;
734 	struct work_struct		unpin_work;
735 	struct radeon_device		*rdev;
736 	int				crtc_id;
737 	u32				target_vblank;
738 	uint64_t			base;
739 	struct drm_pending_vblank_event *event;
740 	struct radeon_bo		*old_rbo;
741 	struct dma_fence		*fence;
742 	bool				async;
743 };
744 
745 struct r500_irq_stat_regs {
746 	u32 disp_int;
747 	u32 hdmi0_status;
748 };
749 
750 struct r600_irq_stat_regs {
751 	u32 disp_int;
752 	u32 disp_int_cont;
753 	u32 disp_int_cont2;
754 	u32 d1grph_int;
755 	u32 d2grph_int;
756 	u32 hdmi0_status;
757 	u32 hdmi1_status;
758 };
759 
760 struct evergreen_irq_stat_regs {
761 	u32 disp_int[6];
762 	u32 grph_int[6];
763 	u32 afmt_status[6];
764 };
765 
766 struct cik_irq_stat_regs {
767 	u32 disp_int;
768 	u32 disp_int_cont;
769 	u32 disp_int_cont2;
770 	u32 disp_int_cont3;
771 	u32 disp_int_cont4;
772 	u32 disp_int_cont5;
773 	u32 disp_int_cont6;
774 	u32 d1grph_int;
775 	u32 d2grph_int;
776 	u32 d3grph_int;
777 	u32 d4grph_int;
778 	u32 d5grph_int;
779 	u32 d6grph_int;
780 };
781 
782 union radeon_irq_stat_regs {
783 	struct r500_irq_stat_regs r500;
784 	struct r600_irq_stat_regs r600;
785 	struct evergreen_irq_stat_regs evergreen;
786 	struct cik_irq_stat_regs cik;
787 };
788 
789 struct radeon_irq {
790 	bool				installed;
791 	spinlock_t			lock;
792 	atomic_t			ring_int[RADEON_NUM_RINGS];
793 	bool				crtc_vblank_int[RADEON_MAX_CRTCS];
794 	atomic_t			pflip[RADEON_MAX_CRTCS];
795 	wait_queue_head_t		vblank_queue;
796 	bool				hpd[RADEON_MAX_HPD_PINS];
797 	bool				afmt[RADEON_MAX_AFMT_BLOCKS];
798 	union radeon_irq_stat_regs	stat_regs;
799 	bool				dpm_thermal;
800 };
801 
802 int radeon_irq_kms_init(struct radeon_device *rdev);
803 void radeon_irq_kms_fini(struct radeon_device *rdev);
804 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
805 bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
806 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
807 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
808 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
809 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
810 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
811 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
812 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
813 
814 /*
815  * CP & rings.
816  */
817 
818 struct radeon_ib {
819 	struct radeon_sa_bo		*sa_bo;
820 	uint32_t			length_dw;
821 	uint64_t			gpu_addr;
822 	uint32_t			*ptr;
823 	int				ring;
824 	struct radeon_fence		*fence;
825 	struct radeon_vm		*vm;
826 	bool				is_const_ib;
827 	struct radeon_sync		sync;
828 };
829 
830 struct radeon_ring {
831 	struct radeon_device	*rdev;
832 	struct radeon_bo	*ring_obj;
833 	volatile uint32_t	*ring;
834 	unsigned		rptr_offs;
835 	unsigned		rptr_save_reg;
836 	u64			next_rptr_gpu_addr;
837 	volatile u32		*next_rptr_cpu_addr;
838 	unsigned		wptr;
839 	unsigned		wptr_old;
840 	unsigned		ring_size;
841 	unsigned		ring_free_dw;
842 	int			count_dw;
843 	atomic_t		last_rptr;
844 	atomic64_t		last_activity;
845 	uint64_t		gpu_addr;
846 	uint32_t		align_mask;
847 	uint32_t		ptr_mask;
848 	bool			ready;
849 	u32			nop;
850 	u32			idx;
851 	u64			last_semaphore_signal_addr;
852 	u64			last_semaphore_wait_addr;
853 	/* for CIK queues */
854 	u32 me;
855 	u32 pipe;
856 	u32 queue;
857 	struct radeon_bo	*mqd_obj;
858 	u32 doorbell_index;
859 	unsigned		wptr_offs;
860 };
861 
862 struct radeon_mec {
863 	struct radeon_bo	*hpd_eop_obj;
864 	u64			hpd_eop_gpu_addr;
865 	u32 num_pipe;
866 	u32 num_mec;
867 	u32 num_queue;
868 };
869 
870 /*
871  * VM
872  */
873 
874 /* maximum number of VMIDs */
875 #define RADEON_NUM_VM	16
876 
877 /* number of entries in page table */
878 #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
879 
880 /* PTBs (Page Table Blocks) need to be aligned to 32K */
881 #define RADEON_VM_PTB_ALIGN_SIZE   32768
882 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
883 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
884 
885 #define R600_PTE_VALID		(1 << 0)
886 #define R600_PTE_SYSTEM		(1 << 1)
887 #define R600_PTE_SNOOPED	(1 << 2)
888 #define R600_PTE_READABLE	(1 << 5)
889 #define R600_PTE_WRITEABLE	(1 << 6)
890 
891 /* PTE (Page Table Entry) fragment field for different page sizes */
892 #define R600_PTE_FRAG_4KB	(0 << 7)
893 #define R600_PTE_FRAG_64KB	(4 << 7)
894 #define R600_PTE_FRAG_256KB	(6 << 7)
895 
896 /* flags needed to be set so we can copy directly from the GART table */
897 #define R600_PTE_GART_MASK	( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
898 				  R600_PTE_SYSTEM | R600_PTE_VALID )
899 
900 struct radeon_vm_pt {
901 	struct radeon_bo		*bo;
902 	uint64_t			addr;
903 };
904 
905 struct radeon_vm_id {
906 	unsigned		id;
907 	uint64_t		pd_gpu_addr;
908 	/* last flushed PD/PT update */
909 	struct radeon_fence	*flushed_updates;
910 	/* last use of vmid */
911 	struct radeon_fence	*last_id_use;
912 };
913 
914 struct radeon_vm {
915 	struct mutex		mutex;
916 
917 	struct rb_root_cached	va;
918 
919 	/* protecting invalidated and freed */
920 	spinlock_t		status_lock;
921 
922 	/* BOs moved, but not yet updated in the PT */
923 	struct list_head	invalidated;
924 
925 	/* BOs freed, but not yet updated in the PT */
926 	struct list_head	freed;
927 
928 	/* BOs cleared in the PT */
929 	struct list_head	cleared;
930 
931 	/* contains the page directory */
932 	struct radeon_bo	*page_directory;
933 	unsigned		max_pde_used;
934 
935 	/* array of page tables, one for each page directory entry */
936 	struct radeon_vm_pt	*page_tables;
937 
938 	struct radeon_bo_va	*ib_bo_va;
939 
940 	/* for id and flush management per ring */
941 	struct radeon_vm_id	ids[RADEON_NUM_RINGS];
942 };
943 
944 struct radeon_vm_manager {
945 	struct radeon_fence		*active[RADEON_NUM_VM];
946 	uint32_t			max_pfn;
947 	/* number of VMIDs */
948 	unsigned			nvm;
949 	/* vram base address for page table entry  */
950 	u64				vram_base_offset;
951 	/* is vm enabled? */
952 	bool				enabled;
953 	/* for hw to save the PD addr on suspend/resume */
954 	uint32_t			saved_table_addr[RADEON_NUM_VM];
955 };
956 
957 /*
958  * file private structure
959  */
960 struct radeon_fpriv {
961 	struct radeon_vm		vm;
962 };
963 
964 /*
965  * R6xx+ IH ring
966  */
967 struct r600_ih {
968 	struct radeon_bo	*ring_obj;
969 	volatile uint32_t	*ring;
970 	unsigned		rptr;
971 	unsigned		ring_size;
972 	uint64_t		gpu_addr;
973 	uint32_t		ptr_mask;
974 	atomic_t		lock;
975 	bool                    enabled;
976 };
977 
978 /*
979  * RLC stuff
980  */
981 #include "clearstate_defs.h"
982 
983 struct radeon_rlc {
984 	/* for power gating */
985 	struct radeon_bo	*save_restore_obj;
986 	uint64_t		save_restore_gpu_addr;
987 	volatile uint32_t	*sr_ptr;
988 	const u32               *reg_list;
989 	u32                     reg_list_size;
990 	/* for clear state */
991 	struct radeon_bo	*clear_state_obj;
992 	uint64_t		clear_state_gpu_addr;
993 	volatile uint32_t	*cs_ptr;
994 	const struct cs_section_def   *cs_data;
995 	u32                     clear_state_size;
996 	/* for cp tables */
997 	struct radeon_bo	*cp_table_obj;
998 	uint64_t		cp_table_gpu_addr;
999 	volatile uint32_t	*cp_table_ptr;
1000 	u32                     cp_table_size;
1001 };
1002 
1003 int radeon_ib_get(struct radeon_device *rdev, int ring,
1004 		  struct radeon_ib *ib, struct radeon_vm *vm,
1005 		  unsigned size);
1006 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1007 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1008 		       struct radeon_ib *const_ib, bool hdp_flush);
1009 int radeon_ib_pool_init(struct radeon_device *rdev);
1010 void radeon_ib_pool_fini(struct radeon_device *rdev);
1011 int radeon_ib_ring_tests(struct radeon_device *rdev);
1012 /* Ring access between begin & end cannot sleep */
1013 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1014 				      struct radeon_ring *ring);
1015 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1016 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1017 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1018 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1019 			bool hdp_flush);
1020 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1021 			       bool hdp_flush);
1022 void radeon_ring_undo(struct radeon_ring *ring);
1023 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1024 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1025 void radeon_ring_lockup_update(struct radeon_device *rdev,
1026 			       struct radeon_ring *ring);
1027 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1028 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1029 			    uint32_t **data);
1030 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1031 			unsigned size, uint32_t *data);
1032 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1033 		     unsigned rptr_offs, u32 nop);
1034 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1035 
1036 
1037 /* r600 async dma */
1038 void r600_dma_stop(struct radeon_device *rdev);
1039 int r600_dma_resume(struct radeon_device *rdev);
1040 void r600_dma_fini(struct radeon_device *rdev);
1041 
1042 void cayman_dma_stop(struct radeon_device *rdev);
1043 int cayman_dma_resume(struct radeon_device *rdev);
1044 void cayman_dma_fini(struct radeon_device *rdev);
1045 
1046 /*
1047  * CS.
1048  */
1049 struct radeon_cs_chunk {
1050 	uint32_t		length_dw;
1051 	uint32_t		*kdata;
1052 	void __user		*user_ptr;
1053 };
1054 
1055 struct radeon_cs_parser {
1056 	struct device		*dev;
1057 	struct radeon_device	*rdev;
1058 	struct drm_file		*filp;
1059 	/* chunks */
1060 	unsigned		nchunks;
1061 	struct radeon_cs_chunk	*chunks;
1062 	uint64_t		*chunks_array;
1063 	/* IB */
1064 	unsigned		idx;
1065 	/* relocations */
1066 	unsigned		nrelocs;
1067 	struct radeon_bo_list	*relocs;
1068 	struct radeon_bo_list	*vm_bos;
1069 	struct list_head	validated;
1070 	unsigned		dma_reloc_idx;
1071 	/* indices of various chunks */
1072 	struct radeon_cs_chunk  *chunk_ib;
1073 	struct radeon_cs_chunk  *chunk_relocs;
1074 	struct radeon_cs_chunk  *chunk_flags;
1075 	struct radeon_cs_chunk  *chunk_const_ib;
1076 	struct radeon_ib	ib;
1077 	struct radeon_ib	const_ib;
1078 	void			*track;
1079 	unsigned		family;
1080 	int			parser_error;
1081 	u32			cs_flags;
1082 	u32			ring;
1083 	s32			priority;
1084 	struct ww_acquire_ctx	ticket;
1085 };
1086 
radeon_get_ib_value(struct radeon_cs_parser * p,int idx)1087 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1088 {
1089 	struct radeon_cs_chunk *ibc = p->chunk_ib;
1090 
1091 	if (ibc->kdata)
1092 		return ibc->kdata[idx];
1093 	return p->ib.ptr[idx];
1094 }
1095 
1096 
1097 struct radeon_cs_packet {
1098 	unsigned	idx;
1099 	unsigned	type;
1100 	unsigned	reg;
1101 	unsigned	opcode;
1102 	int		count;
1103 	unsigned	one_reg_wr;
1104 };
1105 
1106 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1107 				      struct radeon_cs_packet *pkt,
1108 				      unsigned idx, unsigned reg);
1109 
1110 /*
1111  * AGP
1112  */
1113 
1114 struct radeon_agp_mode {
1115 	unsigned long mode;	/**< AGP mode */
1116 };
1117 
1118 struct radeon_agp_info {
1119 	int agp_version_major;
1120 	int agp_version_minor;
1121 	unsigned long mode;
1122 	unsigned long aperture_base;	/* physical address */
1123 	unsigned long aperture_size;	/* bytes */
1124 	unsigned long memory_allowed;	/* bytes */
1125 	unsigned long memory_used;
1126 
1127 	/* PCI information */
1128 	unsigned short id_vendor;
1129 	unsigned short id_device;
1130 };
1131 
1132 struct radeon_agp_head {
1133 	struct agp_kern_info agp_info;
1134 	struct list_head memory;
1135 	unsigned long mode;
1136 	struct agp_bridge_data *bridge;
1137 	int enabled;
1138 	int acquired;
1139 	unsigned long base;
1140 	int agp_mtrr;
1141 	int cant_use_aperture;
1142 	unsigned long page_mask;
1143 };
1144 
1145 #if IS_ENABLED(CONFIG_AGP)
1146 struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev);
1147 #else
radeon_agp_head_init(struct drm_device * dev)1148 static inline struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev)
1149 {
1150 	return NULL;
1151 }
1152 #endif
1153 int radeon_agp_init(struct radeon_device *rdev);
1154 void radeon_agp_resume(struct radeon_device *rdev);
1155 void radeon_agp_suspend(struct radeon_device *rdev);
1156 void radeon_agp_fini(struct radeon_device *rdev);
1157 
1158 
1159 /*
1160  * Writeback
1161  */
1162 struct radeon_wb {
1163 	struct radeon_bo	*wb_obj;
1164 	volatile uint32_t	*wb;
1165 	uint64_t		gpu_addr;
1166 	bool                    enabled;
1167 	bool                    use_event;
1168 };
1169 
1170 #define RADEON_WB_SCRATCH_OFFSET 0
1171 #define RADEON_WB_RING0_NEXT_RPTR 256
1172 #define RADEON_WB_CP_RPTR_OFFSET 1024
1173 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1174 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1175 #define R600_WB_DMA_RPTR_OFFSET   1792
1176 #define R600_WB_IH_WPTR_OFFSET   2048
1177 #define CAYMAN_WB_DMA1_RPTR_OFFSET   2304
1178 #define R600_WB_EVENT_OFFSET     3072
1179 #define CIK_WB_CP1_WPTR_OFFSET     3328
1180 #define CIK_WB_CP2_WPTR_OFFSET     3584
1181 #define R600_WB_DMA_RING_TEST_OFFSET 3588
1182 #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1183 
1184 /**
1185  * struct radeon_pm - power management datas
1186  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
1187  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1188  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
1189  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
1190  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
1191  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
1192  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1193  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
1194  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
1195  * @sclk:          	GPU clock Mhz (core bandwidth depends of this clock)
1196  * @needed_bandwidth:   current bandwidth needs
1197  *
1198  * It keeps track of various data needed to take powermanagement decision.
1199  * Bandwidth need is used to determine minimun clock of the GPU and memory.
1200  * Equation between gpu/memory clock and available bandwidth is hw dependent
1201  * (type of memory, bus size, efficiency, ...)
1202  */
1203 
1204 enum radeon_pm_method {
1205 	PM_METHOD_PROFILE,
1206 	PM_METHOD_DYNPM,
1207 	PM_METHOD_DPM,
1208 };
1209 
1210 enum radeon_dynpm_state {
1211 	DYNPM_STATE_DISABLED,
1212 	DYNPM_STATE_MINIMUM,
1213 	DYNPM_STATE_PAUSED,
1214 	DYNPM_STATE_ACTIVE,
1215 	DYNPM_STATE_SUSPENDED,
1216 };
1217 enum radeon_dynpm_action {
1218 	DYNPM_ACTION_NONE,
1219 	DYNPM_ACTION_MINIMUM,
1220 	DYNPM_ACTION_DOWNCLOCK,
1221 	DYNPM_ACTION_UPCLOCK,
1222 	DYNPM_ACTION_DEFAULT
1223 };
1224 
1225 enum radeon_voltage_type {
1226 	VOLTAGE_NONE = 0,
1227 	VOLTAGE_GPIO,
1228 	VOLTAGE_VDDC,
1229 	VOLTAGE_SW
1230 };
1231 
1232 enum radeon_pm_state_type {
1233 	/* not used for dpm */
1234 	POWER_STATE_TYPE_DEFAULT,
1235 	POWER_STATE_TYPE_POWERSAVE,
1236 	/* user selectable states */
1237 	POWER_STATE_TYPE_BATTERY,
1238 	POWER_STATE_TYPE_BALANCED,
1239 	POWER_STATE_TYPE_PERFORMANCE,
1240 	/* internal states */
1241 	POWER_STATE_TYPE_INTERNAL_UVD,
1242 	POWER_STATE_TYPE_INTERNAL_UVD_SD,
1243 	POWER_STATE_TYPE_INTERNAL_UVD_HD,
1244 	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1245 	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1246 	POWER_STATE_TYPE_INTERNAL_BOOT,
1247 	POWER_STATE_TYPE_INTERNAL_THERMAL,
1248 	POWER_STATE_TYPE_INTERNAL_ACPI,
1249 	POWER_STATE_TYPE_INTERNAL_ULV,
1250 	POWER_STATE_TYPE_INTERNAL_3DPERF,
1251 };
1252 
1253 enum radeon_pm_profile_type {
1254 	PM_PROFILE_DEFAULT,
1255 	PM_PROFILE_AUTO,
1256 	PM_PROFILE_LOW,
1257 	PM_PROFILE_MID,
1258 	PM_PROFILE_HIGH,
1259 };
1260 
1261 #define PM_PROFILE_DEFAULT_IDX 0
1262 #define PM_PROFILE_LOW_SH_IDX  1
1263 #define PM_PROFILE_MID_SH_IDX  2
1264 #define PM_PROFILE_HIGH_SH_IDX 3
1265 #define PM_PROFILE_LOW_MH_IDX  4
1266 #define PM_PROFILE_MID_MH_IDX  5
1267 #define PM_PROFILE_HIGH_MH_IDX 6
1268 #define PM_PROFILE_MAX         7
1269 
1270 struct radeon_pm_profile {
1271 	int dpms_off_ps_idx;
1272 	int dpms_on_ps_idx;
1273 	int dpms_off_cm_idx;
1274 	int dpms_on_cm_idx;
1275 };
1276 
1277 enum radeon_int_thermal_type {
1278 	THERMAL_TYPE_NONE,
1279 	THERMAL_TYPE_EXTERNAL,
1280 	THERMAL_TYPE_EXTERNAL_GPIO,
1281 	THERMAL_TYPE_RV6XX,
1282 	THERMAL_TYPE_RV770,
1283 	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1284 	THERMAL_TYPE_EVERGREEN,
1285 	THERMAL_TYPE_SUMO,
1286 	THERMAL_TYPE_NI,
1287 	THERMAL_TYPE_SI,
1288 	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1289 	THERMAL_TYPE_CI,
1290 	THERMAL_TYPE_KV,
1291 };
1292 
1293 struct radeon_voltage {
1294 	enum radeon_voltage_type type;
1295 	/* gpio voltage */
1296 	struct radeon_gpio_rec gpio;
1297 	u32 delay; /* delay in usec from voltage drop to sclk change */
1298 	bool active_high; /* voltage drop is active when bit is high */
1299 	/* VDDC voltage */
1300 	u8 vddc_id; /* index into vddc voltage table */
1301 	u8 vddci_id; /* index into vddci voltage table */
1302 	bool vddci_enabled;
1303 	/* r6xx+ sw */
1304 	u16 voltage;
1305 	/* evergreen+ vddci */
1306 	u16 vddci;
1307 };
1308 
1309 /* clock mode flags */
1310 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
1311 
1312 struct radeon_pm_clock_info {
1313 	/* memory clock */
1314 	u32 mclk;
1315 	/* engine clock */
1316 	u32 sclk;
1317 	/* voltage info */
1318 	struct radeon_voltage voltage;
1319 	/* standardized clock flags */
1320 	u32 flags;
1321 };
1322 
1323 /* state flags */
1324 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1325 
1326 struct radeon_power_state {
1327 	enum radeon_pm_state_type type;
1328 	struct radeon_pm_clock_info *clock_info;
1329 	/* number of valid clock modes in this power state */
1330 	int num_clock_modes;
1331 	struct radeon_pm_clock_info *default_clock_mode;
1332 	/* standardized state flags */
1333 	u32 flags;
1334 	u32 misc; /* vbios specific flags */
1335 	u32 misc2; /* vbios specific flags */
1336 	int pcie_lanes; /* pcie lanes */
1337 };
1338 
1339 /*
1340  * Some modes are overclocked by very low value, accept them
1341  */
1342 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1343 
1344 enum radeon_dpm_auto_throttle_src {
1345 	RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1346 	RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1347 };
1348 
1349 enum radeon_dpm_event_src {
1350 	RADEON_DPM_EVENT_SRC_ANALOG = 0,
1351 	RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1352 	RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1353 	RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1354 	RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1355 };
1356 
1357 #define RADEON_MAX_VCE_LEVELS 6
1358 
1359 enum radeon_vce_level {
1360 	RADEON_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
1361 	RADEON_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
1362 	RADEON_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
1363 	RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1364 	RADEON_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
1365 	RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1366 };
1367 
1368 struct radeon_ps {
1369 	u32 caps; /* vbios flags */
1370 	u32 class; /* vbios flags */
1371 	u32 class2; /* vbios flags */
1372 	/* UVD clocks */
1373 	u32 vclk;
1374 	u32 dclk;
1375 	/* VCE clocks */
1376 	u32 evclk;
1377 	u32 ecclk;
1378 	bool vce_active;
1379 	enum radeon_vce_level vce_level;
1380 	/* asic priv */
1381 	void *ps_priv;
1382 };
1383 
1384 struct radeon_dpm_thermal {
1385 	/* thermal interrupt work */
1386 	struct work_struct work;
1387 	/* low temperature threshold */
1388 	int                min_temp;
1389 	/* high temperature threshold */
1390 	int                max_temp;
1391 	/* was interrupt low to high or high to low */
1392 	bool               high_to_low;
1393 };
1394 
1395 enum radeon_clk_action
1396 {
1397 	RADEON_SCLK_UP = 1,
1398 	RADEON_SCLK_DOWN
1399 };
1400 
1401 struct radeon_blacklist_clocks
1402 {
1403 	u32 sclk;
1404 	u32 mclk;
1405 	enum radeon_clk_action action;
1406 };
1407 
1408 struct radeon_clock_and_voltage_limits {
1409 	u32 sclk;
1410 	u32 mclk;
1411 	u16 vddc;
1412 	u16 vddci;
1413 };
1414 
1415 struct radeon_clock_array {
1416 	u32 count;
1417 	u32 *values;
1418 };
1419 
1420 struct radeon_clock_voltage_dependency_entry {
1421 	u32 clk;
1422 	u16 v;
1423 };
1424 
1425 struct radeon_clock_voltage_dependency_table {
1426 	u32 count;
1427 	struct radeon_clock_voltage_dependency_entry *entries;
1428 };
1429 
1430 union radeon_cac_leakage_entry {
1431 	struct {
1432 		u16 vddc;
1433 		u32 leakage;
1434 	};
1435 	struct {
1436 		u16 vddc1;
1437 		u16 vddc2;
1438 		u16 vddc3;
1439 	};
1440 };
1441 
1442 struct radeon_cac_leakage_table {
1443 	u32 count;
1444 	union radeon_cac_leakage_entry *entries;
1445 };
1446 
1447 struct radeon_phase_shedding_limits_entry {
1448 	u16 voltage;
1449 	u32 sclk;
1450 	u32 mclk;
1451 };
1452 
1453 struct radeon_phase_shedding_limits_table {
1454 	u32 count;
1455 	struct radeon_phase_shedding_limits_entry *entries;
1456 };
1457 
1458 struct radeon_uvd_clock_voltage_dependency_entry {
1459 	u32 vclk;
1460 	u32 dclk;
1461 	u16 v;
1462 };
1463 
1464 struct radeon_uvd_clock_voltage_dependency_table {
1465 	u8 count;
1466 	struct radeon_uvd_clock_voltage_dependency_entry *entries;
1467 };
1468 
1469 struct radeon_vce_clock_voltage_dependency_entry {
1470 	u32 ecclk;
1471 	u32 evclk;
1472 	u16 v;
1473 };
1474 
1475 struct radeon_vce_clock_voltage_dependency_table {
1476 	u8 count;
1477 	struct radeon_vce_clock_voltage_dependency_entry *entries;
1478 };
1479 
1480 struct radeon_ppm_table {
1481 	u8 ppm_design;
1482 	u16 cpu_core_number;
1483 	u32 platform_tdp;
1484 	u32 small_ac_platform_tdp;
1485 	u32 platform_tdc;
1486 	u32 small_ac_platform_tdc;
1487 	u32 apu_tdp;
1488 	u32 dgpu_tdp;
1489 	u32 dgpu_ulv_power;
1490 	u32 tj_max;
1491 };
1492 
1493 struct radeon_cac_tdp_table {
1494 	u16 tdp;
1495 	u16 configurable_tdp;
1496 	u16 tdc;
1497 	u16 battery_power_limit;
1498 	u16 small_power_limit;
1499 	u16 low_cac_leakage;
1500 	u16 high_cac_leakage;
1501 	u16 maximum_power_delivery_limit;
1502 };
1503 
1504 struct radeon_dpm_dynamic_state {
1505 	struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1506 	struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1507 	struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1508 	struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1509 	struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1510 	struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1511 	struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1512 	struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1513 	struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1514 	struct radeon_clock_array valid_sclk_values;
1515 	struct radeon_clock_array valid_mclk_values;
1516 	struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1517 	struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1518 	u32 mclk_sclk_ratio;
1519 	u32 sclk_mclk_delta;
1520 	u16 vddc_vddci_delta;
1521 	u16 min_vddc_for_pcie_gen2;
1522 	struct radeon_cac_leakage_table cac_leakage_table;
1523 	struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1524 	struct radeon_ppm_table *ppm_table;
1525 	struct radeon_cac_tdp_table *cac_tdp_table;
1526 };
1527 
1528 struct radeon_dpm_fan {
1529 	u16 t_min;
1530 	u16 t_med;
1531 	u16 t_high;
1532 	u16 pwm_min;
1533 	u16 pwm_med;
1534 	u16 pwm_high;
1535 	u8 t_hyst;
1536 	u32 cycle_delay;
1537 	u16 t_max;
1538 	u8 control_mode;
1539 	u16 default_max_fan_pwm;
1540 	u16 default_fan_output_sensitivity;
1541 	u16 fan_output_sensitivity;
1542 	bool ucode_fan_control;
1543 };
1544 
1545 enum radeon_pcie_gen {
1546 	RADEON_PCIE_GEN1 = 0,
1547 	RADEON_PCIE_GEN2 = 1,
1548 	RADEON_PCIE_GEN3 = 2,
1549 	RADEON_PCIE_GEN_INVALID = 0xffff
1550 };
1551 
1552 enum radeon_dpm_forced_level {
1553 	RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1554 	RADEON_DPM_FORCED_LEVEL_LOW = 1,
1555 	RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1556 };
1557 
1558 struct radeon_vce_state {
1559 	/* vce clocks */
1560 	u32 evclk;
1561 	u32 ecclk;
1562 	/* gpu clocks */
1563 	u32 sclk;
1564 	u32 mclk;
1565 	u8 clk_idx;
1566 	u8 pstate;
1567 };
1568 
1569 struct radeon_dpm {
1570 	struct radeon_ps        *ps;
1571 	/* number of valid power states */
1572 	int                     num_ps;
1573 	/* current power state that is active */
1574 	struct radeon_ps        *current_ps;
1575 	/* requested power state */
1576 	struct radeon_ps        *requested_ps;
1577 	/* boot up power state */
1578 	struct radeon_ps        *boot_ps;
1579 	/* default uvd power state */
1580 	struct radeon_ps        *uvd_ps;
1581 	/* vce requirements */
1582 	struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1583 	enum radeon_vce_level vce_level;
1584 	enum radeon_pm_state_type state;
1585 	enum radeon_pm_state_type user_state;
1586 	u32                     platform_caps;
1587 	u32                     voltage_response_time;
1588 	u32                     backbias_response_time;
1589 	void                    *priv;
1590 	u32			new_active_crtcs;
1591 	int			new_active_crtc_count;
1592 	int			high_pixelclock_count;
1593 	u32			current_active_crtcs;
1594 	int			current_active_crtc_count;
1595 	bool single_display;
1596 	struct radeon_dpm_dynamic_state dyn_state;
1597 	struct radeon_dpm_fan fan;
1598 	u32 tdp_limit;
1599 	u32 near_tdp_limit;
1600 	u32 near_tdp_limit_adjusted;
1601 	u32 sq_ramping_threshold;
1602 	u32 cac_leakage;
1603 	u16 tdp_od_limit;
1604 	u32 tdp_adjustment;
1605 	u16 load_line_slope;
1606 	bool power_control;
1607 	bool ac_power;
1608 	/* special states active */
1609 	bool                    thermal_active;
1610 	bool                    uvd_active;
1611 	bool                    vce_active;
1612 	/* thermal handling */
1613 	struct radeon_dpm_thermal thermal;
1614 	/* forced levels */
1615 	enum radeon_dpm_forced_level forced_level;
1616 	/* track UVD streams */
1617 	unsigned sd;
1618 	unsigned hd;
1619 };
1620 
1621 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1622 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1623 
1624 struct radeon_pm {
1625 	struct mutex		mutex;
1626 	/* write locked while reprogramming mclk */
1627 	struct rw_semaphore	mclk_lock;
1628 	u32			active_crtcs;
1629 	int			active_crtc_count;
1630 	int			req_vblank;
1631 	bool			vblank_sync;
1632 	fixed20_12		max_bandwidth;
1633 	fixed20_12		igp_sideport_mclk;
1634 	fixed20_12		igp_system_mclk;
1635 	fixed20_12		igp_ht_link_clk;
1636 	fixed20_12		igp_ht_link_width;
1637 	fixed20_12		k8_bandwidth;
1638 	fixed20_12		sideport_bandwidth;
1639 	fixed20_12		ht_bandwidth;
1640 	fixed20_12		core_bandwidth;
1641 	fixed20_12		sclk;
1642 	fixed20_12		mclk;
1643 	fixed20_12		needed_bandwidth;
1644 	struct radeon_power_state *power_state;
1645 	/* number of valid power states */
1646 	int                     num_power_states;
1647 	int                     current_power_state_index;
1648 	int                     current_clock_mode_index;
1649 	int                     requested_power_state_index;
1650 	int                     requested_clock_mode_index;
1651 	int                     default_power_state_index;
1652 	u32                     current_sclk;
1653 	u32                     current_mclk;
1654 	u16                     current_vddc;
1655 	u16                     current_vddci;
1656 	u32                     default_sclk;
1657 	u32                     default_mclk;
1658 	u16                     default_vddc;
1659 	u16                     default_vddci;
1660 	struct radeon_i2c_chan *i2c_bus;
1661 	/* selected pm method */
1662 	enum radeon_pm_method     pm_method;
1663 	/* dynpm power management */
1664 	struct delayed_work	dynpm_idle_work;
1665 	enum radeon_dynpm_state	dynpm_state;
1666 	enum radeon_dynpm_action	dynpm_planned_action;
1667 	unsigned long		dynpm_action_timeout;
1668 	bool                    dynpm_can_upclock;
1669 	bool                    dynpm_can_downclock;
1670 	/* profile-based power management */
1671 	enum radeon_pm_profile_type profile;
1672 	int                     profile_index;
1673 	struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1674 	/* internal thermal controller on rv6xx+ */
1675 	enum radeon_int_thermal_type int_thermal_type;
1676 	struct device	        *int_hwmon_dev;
1677 	/* fan control parameters */
1678 	bool                    no_fan;
1679 	u8                      fan_pulses_per_revolution;
1680 	u8                      fan_min_rpm;
1681 	u8                      fan_max_rpm;
1682 	/* dpm */
1683 	bool                    dpm_enabled;
1684 	bool                    sysfs_initialized;
1685 	struct radeon_dpm       dpm;
1686 };
1687 
1688 #define RADEON_PCIE_SPEED_25 1
1689 #define RADEON_PCIE_SPEED_50 2
1690 #define RADEON_PCIE_SPEED_80 4
1691 
1692 int radeon_pm_get_type_index(struct radeon_device *rdev,
1693 			     enum radeon_pm_state_type ps_type,
1694 			     int instance);
1695 /*
1696  * UVD
1697  */
1698 #define RADEON_DEFAULT_UVD_HANDLES	10
1699 #define RADEON_MAX_UVD_HANDLES		30
1700 #define RADEON_UVD_STACK_SIZE		(200*1024)
1701 #define RADEON_UVD_HEAP_SIZE		(256*1024)
1702 #define RADEON_UVD_SESSION_SIZE		(50*1024)
1703 
1704 struct radeon_uvd {
1705 	bool			fw_header_present;
1706 	struct radeon_bo	*vcpu_bo;
1707 	void			*cpu_addr;
1708 	uint64_t		gpu_addr;
1709 	unsigned		max_handles;
1710 	atomic_t		handles[RADEON_MAX_UVD_HANDLES];
1711 	struct drm_file		*filp[RADEON_MAX_UVD_HANDLES];
1712 	unsigned		img_size[RADEON_MAX_UVD_HANDLES];
1713 	struct delayed_work	idle_work;
1714 };
1715 
1716 int radeon_uvd_init(struct radeon_device *rdev);
1717 void radeon_uvd_fini(struct radeon_device *rdev);
1718 int radeon_uvd_suspend(struct radeon_device *rdev);
1719 int radeon_uvd_resume(struct radeon_device *rdev);
1720 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1721 			      uint32_t handle, struct radeon_fence **fence);
1722 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1723 			       uint32_t handle, struct radeon_fence **fence);
1724 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1725 				       uint32_t allowed_domains);
1726 void radeon_uvd_free_handles(struct radeon_device *rdev,
1727 			     struct drm_file *filp);
1728 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1729 void radeon_uvd_note_usage(struct radeon_device *rdev);
1730 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1731 				  unsigned vclk, unsigned dclk,
1732 				  unsigned vco_min, unsigned vco_max,
1733 				  unsigned fb_factor, unsigned fb_mask,
1734 				  unsigned pd_min, unsigned pd_max,
1735 				  unsigned pd_even,
1736 				  unsigned *optimal_fb_div,
1737 				  unsigned *optimal_vclk_div,
1738 				  unsigned *optimal_dclk_div);
1739 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1740                                 unsigned cg_upll_func_cntl);
1741 
1742 /*
1743  * VCE
1744  */
1745 #define RADEON_MAX_VCE_HANDLES	16
1746 
1747 struct radeon_vce {
1748 	struct radeon_bo	*vcpu_bo;
1749 	uint64_t		gpu_addr;
1750 	unsigned		fw_version;
1751 	unsigned		fb_version;
1752 	atomic_t		handles[RADEON_MAX_VCE_HANDLES];
1753 	struct drm_file		*filp[RADEON_MAX_VCE_HANDLES];
1754 	unsigned		img_size[RADEON_MAX_VCE_HANDLES];
1755 	struct delayed_work	idle_work;
1756 	uint32_t		keyselect;
1757 };
1758 
1759 int radeon_vce_init(struct radeon_device *rdev);
1760 void radeon_vce_fini(struct radeon_device *rdev);
1761 int radeon_vce_suspend(struct radeon_device *rdev);
1762 int radeon_vce_resume(struct radeon_device *rdev);
1763 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1764 			      uint32_t handle, struct radeon_fence **fence);
1765 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1766 			       uint32_t handle, struct radeon_fence **fence);
1767 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1768 void radeon_vce_note_usage(struct radeon_device *rdev);
1769 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1770 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1771 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1772 			       struct radeon_ring *ring,
1773 			       struct radeon_semaphore *semaphore,
1774 			       bool emit_wait);
1775 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1776 void radeon_vce_fence_emit(struct radeon_device *rdev,
1777 			   struct radeon_fence *fence);
1778 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1779 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1780 
1781 struct r600_audio_pin {
1782 	int			channels;
1783 	int			rate;
1784 	int			bits_per_sample;
1785 	u8			status_bits;
1786 	u8			category_code;
1787 	u32			offset;
1788 	bool			connected;
1789 	u32			id;
1790 };
1791 
1792 struct r600_audio {
1793 	bool enabled;
1794 	struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1795 	int num_pins;
1796 	struct radeon_audio_funcs *hdmi_funcs;
1797 	struct radeon_audio_funcs *dp_funcs;
1798 	struct radeon_audio_basic_funcs *funcs;
1799 };
1800 
1801 /*
1802  * Benchmarking
1803  */
1804 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1805 
1806 
1807 /*
1808  * Testing
1809  */
1810 void radeon_test_moves(struct radeon_device *rdev);
1811 void radeon_test_ring_sync(struct radeon_device *rdev,
1812 			   struct radeon_ring *cpA,
1813 			   struct radeon_ring *cpB);
1814 void radeon_test_syncing(struct radeon_device *rdev);
1815 
1816 /*
1817  * MMU Notifier
1818  */
1819 #if defined(CONFIG_MMU_NOTIFIER)
1820 int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1821 void radeon_mn_unregister(struct radeon_bo *bo);
1822 #else
radeon_mn_register(struct radeon_bo * bo,unsigned long addr)1823 static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1824 {
1825 	return -ENODEV;
1826 }
radeon_mn_unregister(struct radeon_bo * bo)1827 static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1828 #endif
1829 
1830 /*
1831  * Debugfs
1832  */
1833 void radeon_debugfs_fence_init(struct radeon_device *rdev);
1834 void radeon_gem_debugfs_init(struct radeon_device *rdev);
1835 
1836 /*
1837  * ASIC ring specific functions.
1838  */
1839 struct radeon_asic_ring {
1840 	/* ring read/write ptr handling */
1841 	u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1842 	u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1843 	void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1844 
1845 	/* validating and patching of IBs */
1846 	int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1847 	int (*cs_parse)(struct radeon_cs_parser *p);
1848 
1849 	/* command emmit functions */
1850 	void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1851 	void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1852 	void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1853 	bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1854 			       struct radeon_semaphore *semaphore, bool emit_wait);
1855 	void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1856 			 unsigned vm_id, uint64_t pd_addr);
1857 
1858 	/* testing functions */
1859 	int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1860 	int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1861 	bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1862 
1863 	/* deprecated */
1864 	void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1865 };
1866 
1867 /*
1868  * ASIC specific functions.
1869  */
1870 struct radeon_asic {
1871 	int (*init)(struct radeon_device *rdev);
1872 	void (*fini)(struct radeon_device *rdev);
1873 	int (*resume)(struct radeon_device *rdev);
1874 	int (*suspend)(struct radeon_device *rdev);
1875 	void (*vga_set_state)(struct radeon_device *rdev, bool state);
1876 	int (*asic_reset)(struct radeon_device *rdev, bool hard);
1877 	/* Flush the HDP cache via MMIO */
1878 	void (*mmio_hdp_flush)(struct radeon_device *rdev);
1879 	/* check if 3D engine is idle */
1880 	bool (*gui_idle)(struct radeon_device *rdev);
1881 	/* wait for mc_idle */
1882 	int (*mc_wait_for_idle)(struct radeon_device *rdev);
1883 	/* get the reference clock */
1884 	u32 (*get_xclk)(struct radeon_device *rdev);
1885 	/* get the gpu clock counter */
1886 	uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1887 	/* get register for info ioctl */
1888 	int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1889 	/* gart */
1890 	struct {
1891 		void (*tlb_flush)(struct radeon_device *rdev);
1892 		uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1893 		void (*set_page)(struct radeon_device *rdev, unsigned i,
1894 				 uint64_t entry);
1895 	} gart;
1896 	struct {
1897 		int (*init)(struct radeon_device *rdev);
1898 		void (*fini)(struct radeon_device *rdev);
1899 		void (*copy_pages)(struct radeon_device *rdev,
1900 				   struct radeon_ib *ib,
1901 				   uint64_t pe, uint64_t src,
1902 				   unsigned count);
1903 		void (*write_pages)(struct radeon_device *rdev,
1904 				    struct radeon_ib *ib,
1905 				    uint64_t pe,
1906 				    uint64_t addr, unsigned count,
1907 				    uint32_t incr, uint32_t flags);
1908 		void (*set_pages)(struct radeon_device *rdev,
1909 				  struct radeon_ib *ib,
1910 				  uint64_t pe,
1911 				  uint64_t addr, unsigned count,
1912 				  uint32_t incr, uint32_t flags);
1913 		void (*pad_ib)(struct radeon_ib *ib);
1914 	} vm;
1915 	/* ring specific callbacks */
1916 	const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1917 	/* irqs */
1918 	struct {
1919 		int (*set)(struct radeon_device *rdev);
1920 		int (*process)(struct radeon_device *rdev);
1921 	} irq;
1922 	/* displays */
1923 	struct {
1924 		/* display watermarks */
1925 		void (*bandwidth_update)(struct radeon_device *rdev);
1926 		/* get frame count */
1927 		u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1928 		/* wait for vblank */
1929 		void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1930 		/* set backlight level */
1931 		void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1932 		/* get backlight level */
1933 		u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1934 		/* audio callbacks */
1935 		void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1936 		void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1937 	} display;
1938 	/* copy functions for bo handling */
1939 	struct {
1940 		struct radeon_fence *(*blit)(struct radeon_device *rdev,
1941 					     uint64_t src_offset,
1942 					     uint64_t dst_offset,
1943 					     unsigned num_gpu_pages,
1944 					     struct dma_resv *resv);
1945 		u32 blit_ring_index;
1946 		struct radeon_fence *(*dma)(struct radeon_device *rdev,
1947 					    uint64_t src_offset,
1948 					    uint64_t dst_offset,
1949 					    unsigned num_gpu_pages,
1950 					    struct dma_resv *resv);
1951 		u32 dma_ring_index;
1952 		/* method used for bo copy */
1953 		struct radeon_fence *(*copy)(struct radeon_device *rdev,
1954 					     uint64_t src_offset,
1955 					     uint64_t dst_offset,
1956 					     unsigned num_gpu_pages,
1957 					     struct dma_resv *resv);
1958 		/* ring used for bo copies */
1959 		u32 copy_ring_index;
1960 	} copy;
1961 	/* surfaces */
1962 	struct {
1963 		int (*set_reg)(struct radeon_device *rdev, int reg,
1964 				       uint32_t tiling_flags, uint32_t pitch,
1965 				       uint32_t offset, uint32_t obj_size);
1966 		void (*clear_reg)(struct radeon_device *rdev, int reg);
1967 	} surface;
1968 	/* hotplug detect */
1969 	struct {
1970 		void (*init)(struct radeon_device *rdev);
1971 		void (*fini)(struct radeon_device *rdev);
1972 		bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1973 		void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1974 	} hpd;
1975 	/* static power management */
1976 	struct {
1977 		void (*misc)(struct radeon_device *rdev);
1978 		void (*prepare)(struct radeon_device *rdev);
1979 		void (*finish)(struct radeon_device *rdev);
1980 		void (*init_profile)(struct radeon_device *rdev);
1981 		void (*get_dynpm_state)(struct radeon_device *rdev);
1982 		uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1983 		void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1984 		uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1985 		void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1986 		int (*get_pcie_lanes)(struct radeon_device *rdev);
1987 		void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1988 		void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1989 		int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1990 		int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1991 		int (*get_temperature)(struct radeon_device *rdev);
1992 	} pm;
1993 	/* dynamic power management */
1994 	struct {
1995 		int (*init)(struct radeon_device *rdev);
1996 		void (*setup_asic)(struct radeon_device *rdev);
1997 		int (*enable)(struct radeon_device *rdev);
1998 		int (*late_enable)(struct radeon_device *rdev);
1999 		void (*disable)(struct radeon_device *rdev);
2000 		int (*pre_set_power_state)(struct radeon_device *rdev);
2001 		int (*set_power_state)(struct radeon_device *rdev);
2002 		void (*post_set_power_state)(struct radeon_device *rdev);
2003 		void (*display_configuration_changed)(struct radeon_device *rdev);
2004 		void (*fini)(struct radeon_device *rdev);
2005 		u32 (*get_sclk)(struct radeon_device *rdev, bool low);
2006 		u32 (*get_mclk)(struct radeon_device *rdev, bool low);
2007 		void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
2008 		void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
2009 		int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
2010 		bool (*vblank_too_short)(struct radeon_device *rdev);
2011 		void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
2012 		void (*enable_bapm)(struct radeon_device *rdev, bool enable);
2013 		void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
2014 		u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
2015 		int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
2016 		int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
2017 		u32 (*get_current_sclk)(struct radeon_device *rdev);
2018 		u32 (*get_current_mclk)(struct radeon_device *rdev);
2019 		u16 (*get_current_vddc)(struct radeon_device *rdev);
2020 	} dpm;
2021 	/* pageflipping */
2022 	struct {
2023 		void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
2024 		bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
2025 	} pflip;
2026 };
2027 
2028 /*
2029  * Asic structures
2030  */
2031 struct r100_asic {
2032 	const unsigned		*reg_safe_bm;
2033 	unsigned		reg_safe_bm_size;
2034 	u32			hdp_cntl;
2035 };
2036 
2037 struct r300_asic {
2038 	const unsigned		*reg_safe_bm;
2039 	unsigned		reg_safe_bm_size;
2040 	u32			resync_scratch;
2041 	u32			hdp_cntl;
2042 };
2043 
2044 struct r600_asic {
2045 	unsigned		max_pipes;
2046 	unsigned		max_tile_pipes;
2047 	unsigned		max_simds;
2048 	unsigned		max_backends;
2049 	unsigned		max_gprs;
2050 	unsigned		max_threads;
2051 	unsigned		max_stack_entries;
2052 	unsigned		max_hw_contexts;
2053 	unsigned		max_gs_threads;
2054 	unsigned		sx_max_export_size;
2055 	unsigned		sx_max_export_pos_size;
2056 	unsigned		sx_max_export_smx_size;
2057 	unsigned		sq_num_cf_insts;
2058 	unsigned		tiling_nbanks;
2059 	unsigned		tiling_npipes;
2060 	unsigned		tiling_group_size;
2061 	unsigned		tile_config;
2062 	unsigned		backend_map;
2063 	unsigned		active_simds;
2064 };
2065 
2066 struct rv770_asic {
2067 	unsigned		max_pipes;
2068 	unsigned		max_tile_pipes;
2069 	unsigned		max_simds;
2070 	unsigned		max_backends;
2071 	unsigned		max_gprs;
2072 	unsigned		max_threads;
2073 	unsigned		max_stack_entries;
2074 	unsigned		max_hw_contexts;
2075 	unsigned		max_gs_threads;
2076 	unsigned		sx_max_export_size;
2077 	unsigned		sx_max_export_pos_size;
2078 	unsigned		sx_max_export_smx_size;
2079 	unsigned		sq_num_cf_insts;
2080 	unsigned		sx_num_of_sets;
2081 	unsigned		sc_prim_fifo_size;
2082 	unsigned		sc_hiz_tile_fifo_size;
2083 	unsigned		sc_earlyz_tile_fifo_fize;
2084 	unsigned		tiling_nbanks;
2085 	unsigned		tiling_npipes;
2086 	unsigned		tiling_group_size;
2087 	unsigned		tile_config;
2088 	unsigned		backend_map;
2089 	unsigned		active_simds;
2090 };
2091 
2092 struct evergreen_asic {
2093 	unsigned num_ses;
2094 	unsigned max_pipes;
2095 	unsigned max_tile_pipes;
2096 	unsigned max_simds;
2097 	unsigned max_backends;
2098 	unsigned max_gprs;
2099 	unsigned max_threads;
2100 	unsigned max_stack_entries;
2101 	unsigned max_hw_contexts;
2102 	unsigned max_gs_threads;
2103 	unsigned sx_max_export_size;
2104 	unsigned sx_max_export_pos_size;
2105 	unsigned sx_max_export_smx_size;
2106 	unsigned sq_num_cf_insts;
2107 	unsigned sx_num_of_sets;
2108 	unsigned sc_prim_fifo_size;
2109 	unsigned sc_hiz_tile_fifo_size;
2110 	unsigned sc_earlyz_tile_fifo_size;
2111 	unsigned tiling_nbanks;
2112 	unsigned tiling_npipes;
2113 	unsigned tiling_group_size;
2114 	unsigned tile_config;
2115 	unsigned backend_map;
2116 	unsigned active_simds;
2117 };
2118 
2119 struct cayman_asic {
2120 	unsigned max_shader_engines;
2121 	unsigned max_pipes_per_simd;
2122 	unsigned max_tile_pipes;
2123 	unsigned max_simds_per_se;
2124 	unsigned max_backends_per_se;
2125 	unsigned max_texture_channel_caches;
2126 	unsigned max_gprs;
2127 	unsigned max_threads;
2128 	unsigned max_gs_threads;
2129 	unsigned max_stack_entries;
2130 	unsigned sx_num_of_sets;
2131 	unsigned sx_max_export_size;
2132 	unsigned sx_max_export_pos_size;
2133 	unsigned sx_max_export_smx_size;
2134 	unsigned max_hw_contexts;
2135 	unsigned sq_num_cf_insts;
2136 	unsigned sc_prim_fifo_size;
2137 	unsigned sc_hiz_tile_fifo_size;
2138 	unsigned sc_earlyz_tile_fifo_size;
2139 
2140 	unsigned num_shader_engines;
2141 	unsigned num_shader_pipes_per_simd;
2142 	unsigned num_tile_pipes;
2143 	unsigned num_simds_per_se;
2144 	unsigned num_backends_per_se;
2145 	unsigned backend_disable_mask_per_asic;
2146 	unsigned backend_map;
2147 	unsigned num_texture_channel_caches;
2148 	unsigned mem_max_burst_length_bytes;
2149 	unsigned mem_row_size_in_kb;
2150 	unsigned shader_engine_tile_size;
2151 	unsigned num_gpus;
2152 	unsigned multi_gpu_tile_size;
2153 
2154 	unsigned tile_config;
2155 	unsigned active_simds;
2156 };
2157 
2158 struct si_asic {
2159 	unsigned max_shader_engines;
2160 	unsigned max_tile_pipes;
2161 	unsigned max_cu_per_sh;
2162 	unsigned max_sh_per_se;
2163 	unsigned max_backends_per_se;
2164 	unsigned max_texture_channel_caches;
2165 	unsigned max_gprs;
2166 	unsigned max_gs_threads;
2167 	unsigned max_hw_contexts;
2168 	unsigned sc_prim_fifo_size_frontend;
2169 	unsigned sc_prim_fifo_size_backend;
2170 	unsigned sc_hiz_tile_fifo_size;
2171 	unsigned sc_earlyz_tile_fifo_size;
2172 
2173 	unsigned num_tile_pipes;
2174 	unsigned backend_enable_mask;
2175 	unsigned backend_disable_mask_per_asic;
2176 	unsigned backend_map;
2177 	unsigned num_texture_channel_caches;
2178 	unsigned mem_max_burst_length_bytes;
2179 	unsigned mem_row_size_in_kb;
2180 	unsigned shader_engine_tile_size;
2181 	unsigned num_gpus;
2182 	unsigned multi_gpu_tile_size;
2183 
2184 	unsigned tile_config;
2185 	uint32_t tile_mode_array[32];
2186 	uint32_t active_cus;
2187 };
2188 
2189 struct cik_asic {
2190 	unsigned max_shader_engines;
2191 	unsigned max_tile_pipes;
2192 	unsigned max_cu_per_sh;
2193 	unsigned max_sh_per_se;
2194 	unsigned max_backends_per_se;
2195 	unsigned max_texture_channel_caches;
2196 	unsigned max_gprs;
2197 	unsigned max_gs_threads;
2198 	unsigned max_hw_contexts;
2199 	unsigned sc_prim_fifo_size_frontend;
2200 	unsigned sc_prim_fifo_size_backend;
2201 	unsigned sc_hiz_tile_fifo_size;
2202 	unsigned sc_earlyz_tile_fifo_size;
2203 
2204 	unsigned num_tile_pipes;
2205 	unsigned backend_enable_mask;
2206 	unsigned backend_disable_mask_per_asic;
2207 	unsigned backend_map;
2208 	unsigned num_texture_channel_caches;
2209 	unsigned mem_max_burst_length_bytes;
2210 	unsigned mem_row_size_in_kb;
2211 	unsigned shader_engine_tile_size;
2212 	unsigned num_gpus;
2213 	unsigned multi_gpu_tile_size;
2214 
2215 	unsigned tile_config;
2216 	uint32_t tile_mode_array[32];
2217 	uint32_t macrotile_mode_array[16];
2218 	uint32_t active_cus;
2219 };
2220 
2221 union radeon_asic_config {
2222 	struct r300_asic	r300;
2223 	struct r100_asic	r100;
2224 	struct r600_asic	r600;
2225 	struct rv770_asic	rv770;
2226 	struct evergreen_asic	evergreen;
2227 	struct cayman_asic	cayman;
2228 	struct si_asic		si;
2229 	struct cik_asic		cik;
2230 };
2231 
2232 /*
2233  * asic initizalization from radeon_asic.c
2234  */
2235 void radeon_agp_disable(struct radeon_device *rdev);
2236 int radeon_asic_init(struct radeon_device *rdev);
2237 
2238 
2239 /*
2240  * IOCTL.
2241  */
2242 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2243 			  struct drm_file *filp);
2244 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2245 			    struct drm_file *filp);
2246 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2247 			     struct drm_file *filp);
2248 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2249 			 struct drm_file *file_priv);
2250 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2251 			   struct drm_file *file_priv);
2252 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2253 			    struct drm_file *file_priv);
2254 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2255 			   struct drm_file *file_priv);
2256 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2257 				struct drm_file *filp);
2258 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2259 			  struct drm_file *filp);
2260 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2261 			  struct drm_file *filp);
2262 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2263 			      struct drm_file *filp);
2264 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2265 			  struct drm_file *filp);
2266 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2267 			struct drm_file *filp);
2268 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2269 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2270 				struct drm_file *filp);
2271 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2272 				struct drm_file *filp);
2273 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2274 
2275 /* VRAM scratch page for HDP bug, default vram page */
2276 struct r600_vram_scratch {
2277 	struct radeon_bo		*robj;
2278 	volatile uint32_t		*ptr;
2279 	u64				gpu_addr;
2280 };
2281 
2282 /*
2283  * ACPI
2284  */
2285 struct radeon_atif_notification_cfg {
2286 	bool enabled;
2287 	int command_code;
2288 };
2289 
2290 struct radeon_atif_notifications {
2291 	bool display_switch;
2292 	bool expansion_mode_change;
2293 	bool thermal_state;
2294 	bool forced_power_state;
2295 	bool system_power_state;
2296 	bool display_conf_change;
2297 	bool px_gfx_switch;
2298 	bool brightness_change;
2299 	bool dgpu_display_event;
2300 };
2301 
2302 struct radeon_atif_functions {
2303 	bool system_params;
2304 	bool sbios_requests;
2305 	bool select_active_disp;
2306 	bool lid_state;
2307 	bool get_tv_standard;
2308 	bool set_tv_standard;
2309 	bool get_panel_expansion_mode;
2310 	bool set_panel_expansion_mode;
2311 	bool temperature_change;
2312 	bool graphics_device_types;
2313 };
2314 
2315 struct radeon_atif {
2316 	struct radeon_atif_notifications notifications;
2317 	struct radeon_atif_functions functions;
2318 	struct radeon_atif_notification_cfg notification_cfg;
2319 	struct radeon_encoder *encoder_for_bl;
2320 };
2321 
2322 struct radeon_atcs_functions {
2323 	bool get_ext_state;
2324 	bool pcie_perf_req;
2325 	bool pcie_dev_rdy;
2326 	bool pcie_bus_width;
2327 };
2328 
2329 struct radeon_atcs {
2330 	struct radeon_atcs_functions functions;
2331 };
2332 
2333 /*
2334  * Core structure, functions and helpers.
2335  */
2336 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2337 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2338 
2339 struct radeon_device {
2340 	struct device			*dev;
2341 	struct drm_device		*ddev;
2342 	struct pci_dev			*pdev;
2343 #ifdef __alpha__
2344 	struct pci_controller		*hose;
2345 #endif
2346 	struct radeon_agp_head		*agp;
2347 	struct rw_semaphore		exclusive_lock;
2348 	/* ASIC */
2349 	union radeon_asic_config	config;
2350 	enum radeon_family		family;
2351 	unsigned long			flags;
2352 	int				usec_timeout;
2353 	enum radeon_pll_errata		pll_errata;
2354 	int				num_gb_pipes;
2355 	int				num_z_pipes;
2356 	int				disp_priority;
2357 	/* BIOS */
2358 	uint8_t				*bios;
2359 	bool				is_atom_bios;
2360 	uint16_t			bios_header_start;
2361 	struct radeon_bo		*stolen_vga_memory;
2362 	/* Register mmio */
2363 	resource_size_t			rmmio_base;
2364 	resource_size_t			rmmio_size;
2365 	/* protects concurrent MM_INDEX/DATA based register access */
2366 	spinlock_t mmio_idx_lock;
2367 	/* protects concurrent SMC based register access */
2368 	spinlock_t smc_idx_lock;
2369 	/* protects concurrent PLL register access */
2370 	spinlock_t pll_idx_lock;
2371 	/* protects concurrent MC register access */
2372 	spinlock_t mc_idx_lock;
2373 	/* protects concurrent PCIE register access */
2374 	spinlock_t pcie_idx_lock;
2375 	/* protects concurrent PCIE_PORT register access */
2376 	spinlock_t pciep_idx_lock;
2377 	/* protects concurrent PIF register access */
2378 	spinlock_t pif_idx_lock;
2379 	/* protects concurrent CG register access */
2380 	spinlock_t cg_idx_lock;
2381 	/* protects concurrent UVD register access */
2382 	spinlock_t uvd_idx_lock;
2383 	/* protects concurrent RCU register access */
2384 	spinlock_t rcu_idx_lock;
2385 	/* protects concurrent DIDT register access */
2386 	spinlock_t didt_idx_lock;
2387 	/* protects concurrent ENDPOINT (audio) register access */
2388 	spinlock_t end_idx_lock;
2389 	void __iomem			*rmmio;
2390 	radeon_rreg_t			mc_rreg;
2391 	radeon_wreg_t			mc_wreg;
2392 	radeon_rreg_t			pll_rreg;
2393 	radeon_wreg_t			pll_wreg;
2394 	uint32_t                        pcie_reg_mask;
2395 	radeon_rreg_t			pciep_rreg;
2396 	radeon_wreg_t			pciep_wreg;
2397 	/* io port */
2398 	void __iomem                    *rio_mem;
2399 	resource_size_t			rio_mem_size;
2400 	struct radeon_clock             clock;
2401 	struct radeon_mc		mc;
2402 	struct radeon_gart		gart;
2403 	struct radeon_mode_info		mode_info;
2404 	struct radeon_scratch		scratch;
2405 	struct radeon_doorbell		doorbell;
2406 	struct radeon_mman		mman;
2407 	struct radeon_fence_driver	fence_drv[RADEON_NUM_RINGS];
2408 	wait_queue_head_t		fence_queue;
2409 	u64				fence_context;
2410 	struct mutex			ring_lock;
2411 	struct radeon_ring		ring[RADEON_NUM_RINGS];
2412 	bool				ib_pool_ready;
2413 	struct radeon_sa_manager	ring_tmp_bo;
2414 	struct radeon_irq		irq;
2415 	struct radeon_asic		*asic;
2416 	struct radeon_gem		gem;
2417 	struct radeon_pm		pm;
2418 	struct radeon_uvd		uvd;
2419 	struct radeon_vce		vce;
2420 	uint32_t			bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2421 	struct radeon_wb		wb;
2422 	struct radeon_dummy_page	dummy_page;
2423 	bool				shutdown;
2424 	bool				need_swiotlb;
2425 	bool				accel_working;
2426 	bool				fastfb_working; /* IGP feature*/
2427 	bool				needs_reset, in_reset;
2428 	struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2429 	const struct firmware *me_fw;	/* all family ME firmware */
2430 	const struct firmware *pfp_fw;	/* r6/700 PFP firmware */
2431 	const struct firmware *rlc_fw;	/* r6/700 RLC firmware */
2432 	const struct firmware *mc_fw;	/* NI MC firmware */
2433 	const struct firmware *ce_fw;	/* SI CE firmware */
2434 	const struct firmware *mec_fw;	/* CIK MEC firmware */
2435 	const struct firmware *mec2_fw;	/* KV MEC2 firmware */
2436 	const struct firmware *sdma_fw;	/* CIK SDMA firmware */
2437 	const struct firmware *smc_fw;	/* SMC firmware */
2438 	const struct firmware *uvd_fw;	/* UVD firmware */
2439 	const struct firmware *vce_fw;	/* VCE firmware */
2440 	bool new_fw;
2441 	struct r600_vram_scratch vram_scratch;
2442 	int msi_enabled; /* msi enabled */
2443 	struct r600_ih ih; /* r6/700 interrupt ring */
2444 	struct radeon_rlc rlc;
2445 	struct radeon_mec mec;
2446 	struct delayed_work hotplug_work;
2447 	struct work_struct dp_work;
2448 	struct work_struct audio_work;
2449 	int num_crtc; /* number of crtcs */
2450 	struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2451 	bool has_uvd;
2452 	bool has_vce;
2453 	struct r600_audio audio; /* audio stuff */
2454 	struct notifier_block acpi_nb;
2455 	/* only one userspace can use Hyperz features or CMASK at a time */
2456 	struct drm_file *hyperz_filp;
2457 	struct drm_file *cmask_filp;
2458 	/* i2c buses */
2459 	struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2460 	/* virtual memory */
2461 	struct radeon_vm_manager	vm_manager;
2462 	struct mutex			gpu_clock_mutex;
2463 	/* memory stats */
2464 	atomic64_t			num_bytes_moved;
2465 	atomic_t			gpu_reset_counter;
2466 	/* ACPI interface */
2467 	struct radeon_atif		atif;
2468 	struct radeon_atcs		atcs;
2469 	/* srbm instance registers */
2470 	struct mutex			srbm_mutex;
2471 	/* clock, powergating flags */
2472 	u32 cg_flags;
2473 	u32 pg_flags;
2474 
2475 	struct dev_pm_domain vga_pm_domain;
2476 	bool have_disp_power_ref;
2477 	u32 px_quirk_flags;
2478 
2479 	/* tracking pinned memory */
2480 	u64 vram_pin_size;
2481 	u64 gart_pin_size;
2482 };
2483 
2484 bool radeon_is_px(struct drm_device *dev);
2485 int radeon_device_init(struct radeon_device *rdev,
2486 		       struct drm_device *ddev,
2487 		       struct pci_dev *pdev,
2488 		       uint32_t flags);
2489 void radeon_device_fini(struct radeon_device *rdev);
2490 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2491 
2492 #define RADEON_MIN_MMIO_SIZE 0x10000
2493 
2494 uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2495 void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
r100_mm_rreg(struct radeon_device * rdev,uint32_t reg,bool always_indirect)2496 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2497 				    bool always_indirect)
2498 {
2499 	/* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2500 	if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2501 		return readl(((void __iomem *)rdev->rmmio) + reg);
2502 	else
2503 		return r100_mm_rreg_slow(rdev, reg);
2504 }
r100_mm_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v,bool always_indirect)2505 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2506 				bool always_indirect)
2507 {
2508 	if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2509 		writel(v, ((void __iomem *)rdev->rmmio) + reg);
2510 	else
2511 		r100_mm_wreg_slow(rdev, reg, v);
2512 }
2513 
2514 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2515 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2516 
2517 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2518 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2519 
2520 /*
2521  * Cast helper
2522  */
2523 extern const struct dma_fence_ops radeon_fence_ops;
2524 
to_radeon_fence(struct dma_fence * f)2525 static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
2526 {
2527 	struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2528 
2529 	if (__f->base.ops == &radeon_fence_ops)
2530 		return __f;
2531 
2532 	return NULL;
2533 }
2534 
2535 /*
2536  * Registers read & write functions.
2537  */
2538 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2539 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2540 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2541 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2542 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2543 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2544 #define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n",	\
2545 			    r100_mm_rreg(rdev, (reg), false))
2546 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2547 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2548 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2549 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2550 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2551 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2552 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2553 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2554 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2555 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2556 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2557 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2558 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2559 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2560 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2561 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2562 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2563 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2564 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2565 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2566 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2567 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2568 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2569 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2570 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2571 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2572 #define WREG32_P(reg, val, mask)				\
2573 	do {							\
2574 		uint32_t tmp_ = RREG32(reg);			\
2575 		tmp_ &= (mask);					\
2576 		tmp_ |= ((val) & ~(mask));			\
2577 		WREG32(reg, tmp_);				\
2578 	} while (0)
2579 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2580 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2581 #define WREG32_PLL_P(reg, val, mask)				\
2582 	do {							\
2583 		uint32_t tmp_ = RREG32_PLL(reg);		\
2584 		tmp_ &= (mask);					\
2585 		tmp_ |= ((val) & ~(mask));			\
2586 		WREG32_PLL(reg, tmp_);				\
2587 	} while (0)
2588 #define WREG32_SMC_P(reg, val, mask)				\
2589 	do {							\
2590 		uint32_t tmp_ = RREG32_SMC(reg);		\
2591 		tmp_ &= (mask);					\
2592 		tmp_ |= ((val) & ~(mask));			\
2593 		WREG32_SMC(reg, tmp_);				\
2594 	} while (0)
2595 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2596 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2597 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2598 
2599 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2600 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2601 
2602 /*
2603  * Indirect registers accessors.
2604  * They used to be inlined, but this increases code size by ~65 kbytes.
2605  * Since each performs a pair of MMIO ops
2606  * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2607  * the cost of call+ret is almost negligible. MMIO and locking
2608  * costs several dozens of cycles each at best, call+ret is ~5 cycles.
2609  */
2610 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2611 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2612 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2613 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2614 u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2615 void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2616 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2617 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2618 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2619 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2620 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2621 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2622 u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2623 void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2624 u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2625 void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2626 
2627 void r100_pll_errata_after_index(struct radeon_device *rdev);
2628 
2629 
2630 /*
2631  * ASICs helpers.
2632  */
2633 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2634 			    (rdev->pdev->device == 0x5969))
2635 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2636 		(rdev->family == CHIP_RV200) || \
2637 		(rdev->family == CHIP_RS100) || \
2638 		(rdev->family == CHIP_RS200) || \
2639 		(rdev->family == CHIP_RV250) || \
2640 		(rdev->family == CHIP_RV280) || \
2641 		(rdev->family == CHIP_RS300))
2642 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||	\
2643 		(rdev->family == CHIP_RV350) ||			\
2644 		(rdev->family == CHIP_R350)  ||			\
2645 		(rdev->family == CHIP_RV380) ||			\
2646 		(rdev->family == CHIP_R420)  ||			\
2647 		(rdev->family == CHIP_R423)  ||			\
2648 		(rdev->family == CHIP_RV410) ||			\
2649 		(rdev->family == CHIP_RS400) ||			\
2650 		(rdev->family == CHIP_RS480))
2651 #define ASIC_IS_X2(rdev) ((rdev->pdev->device == 0x9441) || \
2652 		(rdev->pdev->device == 0x9443) || \
2653 		(rdev->pdev->device == 0x944B) || \
2654 		(rdev->pdev->device == 0x9506) || \
2655 		(rdev->pdev->device == 0x9509) || \
2656 		(rdev->pdev->device == 0x950F) || \
2657 		(rdev->pdev->device == 0x689C) || \
2658 		(rdev->pdev->device == 0x689D))
2659 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2660 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||	\
2661 			    (rdev->family == CHIP_RS690)  ||	\
2662 			    (rdev->family == CHIP_RS740)  ||	\
2663 			    (rdev->family >= CHIP_R600))
2664 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2665 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2666 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2667 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2668 			     (rdev->flags & RADEON_IS_IGP))
2669 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2670 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2671 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2672 			     (rdev->flags & RADEON_IS_IGP))
2673 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2674 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2675 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2676 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2677 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2678 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2679 			     (rdev->family == CHIP_MULLINS))
2680 
2681 #define ASIC_IS_LOMBOK(rdev) ((rdev->pdev->device == 0x6849) || \
2682 			      (rdev->pdev->device == 0x6850) || \
2683 			      (rdev->pdev->device == 0x6858) || \
2684 			      (rdev->pdev->device == 0x6859) || \
2685 			      (rdev->pdev->device == 0x6840) || \
2686 			      (rdev->pdev->device == 0x6841) || \
2687 			      (rdev->pdev->device == 0x6842) || \
2688 			      (rdev->pdev->device == 0x6843))
2689 
2690 /*
2691  * BIOS helpers.
2692  */
2693 #define RBIOS8(i) (rdev->bios[i])
2694 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2695 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2696 
2697 int radeon_combios_init(struct radeon_device *rdev);
2698 void radeon_combios_fini(struct radeon_device *rdev);
2699 int radeon_atombios_init(struct radeon_device *rdev);
2700 void radeon_atombios_fini(struct radeon_device *rdev);
2701 
2702 
2703 /*
2704  * RING helpers.
2705  */
2706 
2707 /**
2708  * radeon_ring_write - write a value to the ring
2709  *
2710  * @ring: radeon_ring structure holding ring information
2711  * @v: dword (dw) value to write
2712  *
2713  * Write a value to the requested ring buffer (all asics).
2714  */
radeon_ring_write(struct radeon_ring * ring,uint32_t v)2715 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2716 {
2717 	if (ring->count_dw <= 0)
2718 		DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2719 
2720 	ring->ring[ring->wptr++] = v;
2721 	ring->wptr &= ring->ptr_mask;
2722 	ring->count_dw--;
2723 	ring->ring_free_dw--;
2724 }
2725 
2726 /*
2727  * ASICs macro.
2728  */
2729 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2730 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2731 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2732 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2733 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2734 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2735 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2736 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2737 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2738 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2739 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2740 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2741 #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2742 #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2743 #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2744 #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2745 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2746 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2747 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2748 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2749 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2750 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2751 #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2752 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2753 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2754 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2755 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2756 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2757 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2758 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2759 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2760 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2761 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2762 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2763 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2764 #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2765 #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2766 #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2767 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2768 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2769 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2770 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2771 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2772 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2773 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2774 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2775 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2776 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2777 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2778 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2779 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2780 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2781 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2782 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2783 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2784 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2785 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2786 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2787 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2788 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2789 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2790 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2791 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2792 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2793 #define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2794 #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2795 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2796 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2797 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2798 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2799 #define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2800 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2801 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2802 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2803 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2804 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2805 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2806 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2807 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2808 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2809 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2810 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2811 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2812 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2813 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2814 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2815 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2816 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2817 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2818 #define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2819 #define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2820 
2821 /* Common functions */
2822 /* AGP */
2823 extern int radeon_gpu_reset(struct radeon_device *rdev);
2824 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2825 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2826 extern void radeon_agp_disable(struct radeon_device *rdev);
2827 extern int radeon_modeset_init(struct radeon_device *rdev);
2828 extern void radeon_modeset_fini(struct radeon_device *rdev);
2829 extern bool radeon_card_posted(struct radeon_device *rdev);
2830 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2831 extern void radeon_update_display_priority(struct radeon_device *rdev);
2832 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2833 extern void radeon_scratch_init(struct radeon_device *rdev);
2834 extern void radeon_wb_fini(struct radeon_device *rdev);
2835 extern int radeon_wb_init(struct radeon_device *rdev);
2836 extern void radeon_wb_disable(struct radeon_device *rdev);
2837 extern void radeon_surface_init(struct radeon_device *rdev);
2838 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2839 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2840 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2841 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2842 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2843 extern int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
2844 				     struct ttm_tt *ttm, uint64_t addr,
2845 				     uint32_t flags);
2846 extern bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev, struct ttm_tt *ttm);
2847 extern bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev, struct ttm_tt *ttm);
2848 bool radeon_ttm_tt_is_bound(struct ttm_device *bdev, struct ttm_tt *ttm);
2849 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2850 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2851 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2852 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2853 			      bool fbcon, bool freeze);
2854 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2855 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2856 					     const u32 *registers,
2857 					     const u32 array_size);
2858 struct radeon_device *radeon_get_rdev(struct ttm_device *bdev);
2859 
2860 /* KMS */
2861 
2862 u32 radeon_get_vblank_counter_kms(struct drm_crtc *crtc);
2863 int radeon_enable_vblank_kms(struct drm_crtc *crtc);
2864 void radeon_disable_vblank_kms(struct drm_crtc *crtc);
2865 
2866 /*
2867  * vm
2868  */
2869 int radeon_vm_manager_init(struct radeon_device *rdev);
2870 void radeon_vm_manager_fini(struct radeon_device *rdev);
2871 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2872 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2873 struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2874 					  struct radeon_vm *vm,
2875                                           struct list_head *head);
2876 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2877 				       struct radeon_vm *vm, int ring);
2878 void radeon_vm_flush(struct radeon_device *rdev,
2879                      struct radeon_vm *vm,
2880 		     int ring, struct radeon_fence *fence);
2881 void radeon_vm_fence(struct radeon_device *rdev,
2882 		     struct radeon_vm *vm,
2883 		     struct radeon_fence *fence);
2884 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2885 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2886 				    struct radeon_vm *vm);
2887 int radeon_vm_clear_freed(struct radeon_device *rdev,
2888 			  struct radeon_vm *vm);
2889 int radeon_vm_clear_invalids(struct radeon_device *rdev,
2890 			     struct radeon_vm *vm);
2891 int radeon_vm_bo_update(struct radeon_device *rdev,
2892 			struct radeon_bo_va *bo_va,
2893 			struct ttm_resource *mem);
2894 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2895 			     struct radeon_bo *bo);
2896 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2897 				       struct radeon_bo *bo);
2898 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2899 				      struct radeon_vm *vm,
2900 				      struct radeon_bo *bo);
2901 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2902 			  struct radeon_bo_va *bo_va,
2903 			  uint64_t offset,
2904 			  uint32_t flags);
2905 void radeon_vm_bo_rmv(struct radeon_device *rdev,
2906 		      struct radeon_bo_va *bo_va);
2907 
2908 /* audio */
2909 void r600_audio_update_hdmi(struct work_struct *work);
2910 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2911 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2912 void r600_audio_enable(struct radeon_device *rdev,
2913 		       struct r600_audio_pin *pin,
2914 		       u8 enable_mask);
2915 void dce6_audio_enable(struct radeon_device *rdev,
2916 		       struct r600_audio_pin *pin,
2917 		       u8 enable_mask);
2918 
2919 /*
2920  * R600 vram scratch functions
2921  */
2922 int r600_vram_scratch_init(struct radeon_device *rdev);
2923 void r600_vram_scratch_fini(struct radeon_device *rdev);
2924 
2925 /*
2926  * r600 cs checking helper
2927  */
2928 unsigned r600_mip_minify(unsigned size, unsigned level);
2929 bool r600_fmt_is_valid_color(u32 format);
2930 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2931 int r600_fmt_get_blocksize(u32 format);
2932 int r600_fmt_get_nblocksx(u32 format, u32 w);
2933 int r600_fmt_get_nblocksy(u32 format, u32 h);
2934 
2935 /*
2936  * r600 functions used by radeon_encoder.c
2937  */
2938 struct radeon_hdmi_acr {
2939 	u32 clock;
2940 
2941 	int n_32khz;
2942 	int cts_32khz;
2943 
2944 	int n_44_1khz;
2945 	int cts_44_1khz;
2946 
2947 	int n_48khz;
2948 	int cts_48khz;
2949 
2950 };
2951 
2952 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2953 				     u32 tiling_pipe_num,
2954 				     u32 max_rb_num,
2955 				     u32 total_max_rb_num,
2956 				     u32 enabled_rb_mask);
2957 
2958 /*
2959  * evergreen functions used by radeon_encoder.c
2960  */
2961 
2962 extern int ni_init_microcode(struct radeon_device *rdev);
2963 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2964 
2965 /* radeon_acpi.c */
2966 #if defined(CONFIG_ACPI)
2967 extern int radeon_acpi_init(struct radeon_device *rdev);
2968 extern void radeon_acpi_fini(struct radeon_device *rdev);
2969 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2970 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2971 						u8 perf_req, bool advertise);
2972 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2973 #else
radeon_acpi_init(struct radeon_device * rdev)2974 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
radeon_acpi_fini(struct radeon_device * rdev)2975 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2976 #endif
2977 
2978 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2979 			   struct radeon_cs_packet *pkt,
2980 			   unsigned idx);
2981 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2982 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2983 			   struct radeon_cs_packet *pkt);
2984 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2985 				struct radeon_bo_list **cs_reloc,
2986 				int nomm);
2987 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2988 			       uint32_t *vline_start_end,
2989 			       uint32_t *vline_status);
2990 
2991 /* interrupt control register helpers */
2992 void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
2993 				      u32 reg, u32 mask,
2994 				      bool enable, const char *name,
2995 				      unsigned n);
2996 
2997 #include "radeon_object.h"
2998 
2999 #endif
3000