1 /*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27 #include "drmP.h"
28 #include "radeon_drm.h"
29 #include "radeon_reg.h"
30 #include "radeon.h"
31
32 void r100_cs_dump_packet(struct radeon_cs_parser *p,
33 struct radeon_cs_packet *pkt);
34
radeon_cs_parser_relocs(struct radeon_cs_parser * p)35 int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
36 {
37 struct drm_device *ddev = p->rdev->ddev;
38 struct radeon_cs_chunk *chunk;
39 unsigned i, j;
40 bool duplicate;
41
42 if (p->chunk_relocs_idx == -1) {
43 return 0;
44 }
45 chunk = &p->chunks[p->chunk_relocs_idx];
46 /* FIXME: we assume that each relocs use 4 dwords */
47 p->nrelocs = chunk->length_dw / 4;
48 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
49 if (p->relocs_ptr == NULL) {
50 return -ENOMEM;
51 }
52 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
53 if (p->relocs == NULL) {
54 return -ENOMEM;
55 }
56 for (i = 0; i < p->nrelocs; i++) {
57 struct drm_radeon_cs_reloc *r;
58
59 duplicate = false;
60 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
61 for (j = 0; j < i; j++) {
62 if (r->handle == p->relocs[j].handle) {
63 p->relocs_ptr[i] = &p->relocs[j];
64 duplicate = true;
65 break;
66 }
67 }
68 if (!duplicate) {
69 p->relocs[i].gobj = drm_gem_object_lookup(ddev,
70 p->filp,
71 r->handle);
72 if (p->relocs[i].gobj == NULL) {
73 DRM_ERROR("gem object lookup failed 0x%x\n",
74 r->handle);
75 return -ENOENT;
76 }
77 p->relocs_ptr[i] = &p->relocs[i];
78 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
79 p->relocs[i].lobj.bo = p->relocs[i].robj;
80 p->relocs[i].lobj.wdomain = r->write_domain;
81 p->relocs[i].lobj.rdomain = r->read_domains;
82 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
83 p->relocs[i].handle = r->handle;
84 p->relocs[i].flags = r->flags;
85 radeon_bo_list_add_object(&p->relocs[i].lobj,
86 &p->validated);
87
88 } else
89 p->relocs[i].handle = 0;
90 }
91 return radeon_bo_list_validate(&p->validated);
92 }
93
radeon_cs_get_ring(struct radeon_cs_parser * p,u32 ring,s32 priority)94 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
95 {
96 p->priority = priority;
97
98 switch (ring) {
99 default:
100 DRM_ERROR("unknown ring id: %d\n", ring);
101 return -EINVAL;
102 case RADEON_CS_RING_GFX:
103 p->ring = RADEON_RING_TYPE_GFX_INDEX;
104 break;
105 case RADEON_CS_RING_COMPUTE:
106 if (p->rdev->family >= CHIP_TAHITI) {
107 if (p->priority > 0)
108 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
109 else
110 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
111 } else
112 p->ring = RADEON_RING_TYPE_GFX_INDEX;
113 break;
114 }
115 return 0;
116 }
117
radeon_cs_sync_rings(struct radeon_cs_parser * p)118 static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
119 {
120 bool sync_to_ring[RADEON_NUM_RINGS] = { };
121 int i, r;
122
123 for (i = 0; i < p->nrelocs; i++) {
124 if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
125 continue;
126
127 if (!(p->relocs[i].flags & RADEON_RELOC_DONT_SYNC)) {
128 struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj;
129 if (!radeon_fence_signaled(fence)) {
130 sync_to_ring[fence->ring] = true;
131 }
132 }
133 }
134
135 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
136 /* no need to sync to our own or unused rings */
137 if (i == p->ring || !sync_to_ring[i] || !p->rdev->ring[i].ready)
138 continue;
139
140 if (!p->ib->fence->semaphore) {
141 r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore);
142 if (r)
143 return r;
144 }
145
146 r = radeon_ring_lock(p->rdev, &p->rdev->ring[i], 3);
147 if (r)
148 return r;
149 radeon_semaphore_emit_signal(p->rdev, i, p->ib->fence->semaphore);
150 radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[i]);
151
152 r = radeon_ring_lock(p->rdev, &p->rdev->ring[p->ring], 3);
153 if (r)
154 return r;
155 radeon_semaphore_emit_wait(p->rdev, p->ring, p->ib->fence->semaphore);
156 radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[p->ring]);
157 }
158 return 0;
159 }
160
161 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
radeon_cs_parser_init(struct radeon_cs_parser * p,void * data)162 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
163 {
164 struct drm_radeon_cs *cs = data;
165 uint64_t *chunk_array_ptr;
166 unsigned size, i;
167 u32 ring = RADEON_CS_RING_GFX;
168 s32 priority = 0;
169
170 if (!cs->num_chunks) {
171 return 0;
172 }
173 /* get chunks */
174 INIT_LIST_HEAD(&p->validated);
175 p->idx = 0;
176 p->chunk_ib_idx = -1;
177 p->chunk_relocs_idx = -1;
178 p->chunk_flags_idx = -1;
179 p->chunk_const_ib_idx = -1;
180 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
181 if (p->chunks_array == NULL) {
182 return -ENOMEM;
183 }
184 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
185 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
186 sizeof(uint64_t)*cs->num_chunks)) {
187 return -EFAULT;
188 }
189 p->cs_flags = 0;
190 p->nchunks = cs->num_chunks;
191 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
192 if (p->chunks == NULL) {
193 return -ENOMEM;
194 }
195 for (i = 0; i < p->nchunks; i++) {
196 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
197 struct drm_radeon_cs_chunk user_chunk;
198 uint32_t __user *cdata;
199
200 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
201 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
202 sizeof(struct drm_radeon_cs_chunk))) {
203 return -EFAULT;
204 }
205 p->chunks[i].length_dw = user_chunk.length_dw;
206 p->chunks[i].kdata = NULL;
207 p->chunks[i].chunk_id = user_chunk.chunk_id;
208
209 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
210 p->chunk_relocs_idx = i;
211 }
212 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
213 p->chunk_ib_idx = i;
214 /* zero length IB isn't useful */
215 if (p->chunks[i].length_dw == 0)
216 return -EINVAL;
217 }
218 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
219 p->chunk_const_ib_idx = i;
220 /* zero length CONST IB isn't useful */
221 if (p->chunks[i].length_dw == 0)
222 return -EINVAL;
223 }
224 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
225 p->chunk_flags_idx = i;
226 /* zero length flags aren't useful */
227 if (p->chunks[i].length_dw == 0)
228 return -EINVAL;
229 }
230
231 p->chunks[i].length_dw = user_chunk.length_dw;
232 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
233
234 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
235 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
236 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
237 size = p->chunks[i].length_dw * sizeof(uint32_t);
238 p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
239 if (p->chunks[i].kdata == NULL) {
240 return -ENOMEM;
241 }
242 if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
243 p->chunks[i].user_ptr, size)) {
244 return -EFAULT;
245 }
246 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
247 p->cs_flags = p->chunks[i].kdata[0];
248 if (p->chunks[i].length_dw > 1)
249 ring = p->chunks[i].kdata[1];
250 if (p->chunks[i].length_dw > 2)
251 priority = (s32)p->chunks[i].kdata[2];
252 }
253 }
254 }
255
256 /* these are KMS only */
257 if (p->rdev) {
258 if ((p->cs_flags & RADEON_CS_USE_VM) &&
259 !p->rdev->vm_manager.enabled) {
260 DRM_ERROR("VM not active on asic!\n");
261 return -EINVAL;
262 }
263
264 /* we only support VM on SI+ */
265 if ((p->rdev->family >= CHIP_TAHITI) &&
266 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
267 DRM_ERROR("VM required on SI+!\n");
268 return -EINVAL;
269 }
270
271 if (radeon_cs_get_ring(p, ring, priority))
272 return -EINVAL;
273 }
274
275 /* deal with non-vm */
276 if ((p->chunk_ib_idx != -1) &&
277 ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
278 (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
279 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
280 DRM_ERROR("cs IB too big: %d\n",
281 p->chunks[p->chunk_ib_idx].length_dw);
282 return -EINVAL;
283 }
284 p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
285 p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
286 if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
287 p->chunks[p->chunk_ib_idx].kpage[1] == NULL)
288 return -ENOMEM;
289 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
290 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
291 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
292 p->chunks[p->chunk_ib_idx].last_page_index =
293 ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
294 }
295
296 return 0;
297 }
298
299 /**
300 * cs_parser_fini() - clean parser states
301 * @parser: parser structure holding parsing context.
302 * @error: error number
303 *
304 * If error is set than unvalidate buffer, otherwise just free memory
305 * used by parsing context.
306 **/
radeon_cs_parser_fini(struct radeon_cs_parser * parser,int error)307 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
308 {
309 unsigned i;
310
311
312 if (!error && parser->ib)
313 ttm_eu_fence_buffer_objects(&parser->validated,
314 parser->ib->fence);
315 else
316 ttm_eu_backoff_reservation(&parser->validated);
317
318 if (parser->relocs != NULL) {
319 for (i = 0; i < parser->nrelocs; i++) {
320 if (parser->relocs[i].gobj)
321 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
322 }
323 }
324 kfree(parser->track);
325 kfree(parser->relocs);
326 kfree(parser->relocs_ptr);
327 for (i = 0; i < parser->nchunks; i++) {
328 kfree(parser->chunks[i].kdata);
329 kfree(parser->chunks[i].kpage[0]);
330 kfree(parser->chunks[i].kpage[1]);
331 }
332 kfree(parser->chunks);
333 kfree(parser->chunks_array);
334 radeon_ib_free(parser->rdev, &parser->ib);
335 }
336
radeon_cs_ib_chunk(struct radeon_device * rdev,struct radeon_cs_parser * parser)337 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
338 struct radeon_cs_parser *parser)
339 {
340 struct radeon_cs_chunk *ib_chunk;
341 int r;
342
343 if (parser->chunk_ib_idx == -1)
344 return 0;
345
346 if (parser->cs_flags & RADEON_CS_USE_VM)
347 return 0;
348
349 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
350 /* Copy the packet into the IB, the parser will read from the
351 * input memory (cached) and write to the IB (which can be
352 * uncached).
353 */
354 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
355 ib_chunk->length_dw * 4);
356 if (r) {
357 DRM_ERROR("Failed to get ib !\n");
358 return r;
359 }
360 parser->ib->length_dw = ib_chunk->length_dw;
361 r = radeon_cs_parse(rdev, parser->ring, parser);
362 if (r || parser->parser_error) {
363 DRM_ERROR("Invalid command stream !\n");
364 return r;
365 }
366 r = radeon_cs_finish_pages(parser);
367 if (r) {
368 DRM_ERROR("Invalid command stream !\n");
369 return r;
370 }
371 r = radeon_cs_sync_rings(parser);
372 if (r) {
373 DRM_ERROR("Failed to synchronize rings !\n");
374 }
375 parser->ib->vm_id = 0;
376 r = radeon_ib_schedule(rdev, parser->ib);
377 if (r) {
378 DRM_ERROR("Failed to schedule IB !\n");
379 }
380 return r;
381 }
382
radeon_bo_vm_update_pte(struct radeon_cs_parser * parser,struct radeon_vm * vm)383 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
384 struct radeon_vm *vm)
385 {
386 struct radeon_bo_list *lobj;
387 struct radeon_bo *bo;
388 int r;
389
390 list_for_each_entry(lobj, &parser->validated, tv.head) {
391 bo = lobj->bo;
392 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
393 if (r) {
394 return r;
395 }
396 }
397 return 0;
398 }
399
radeon_cs_ib_vm_chunk(struct radeon_device * rdev,struct radeon_cs_parser * parser)400 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
401 struct radeon_cs_parser *parser)
402 {
403 struct radeon_cs_chunk *ib_chunk;
404 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
405 struct radeon_vm *vm = &fpriv->vm;
406 int r;
407
408 if (parser->chunk_ib_idx == -1)
409 return 0;
410
411 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
412 return 0;
413
414 if ((rdev->family >= CHIP_TAHITI) &&
415 (parser->chunk_const_ib_idx != -1)) {
416 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
417 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
418 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
419 return -EINVAL;
420 }
421 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
422 ib_chunk->length_dw * 4);
423 if (r) {
424 DRM_ERROR("Failed to get const ib !\n");
425 return r;
426 }
427 parser->const_ib->is_const_ib = true;
428 parser->const_ib->length_dw = ib_chunk->length_dw;
429 /* Copy the packet into the IB */
430 if (DRM_COPY_FROM_USER(parser->const_ib->ptr, ib_chunk->user_ptr,
431 ib_chunk->length_dw * 4)) {
432 return -EFAULT;
433 }
434 r = radeon_ring_ib_parse(rdev, parser->ring, parser->const_ib);
435 if (r) {
436 return r;
437 }
438 }
439
440 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
441 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
442 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
443 return -EINVAL;
444 }
445 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
446 ib_chunk->length_dw * 4);
447 if (r) {
448 DRM_ERROR("Failed to get ib !\n");
449 return r;
450 }
451 parser->ib->length_dw = ib_chunk->length_dw;
452 /* Copy the packet into the IB */
453 if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
454 ib_chunk->length_dw * 4)) {
455 return -EFAULT;
456 }
457 r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
458 if (r) {
459 return r;
460 }
461
462 mutex_lock(&vm->mutex);
463 r = radeon_vm_bind(rdev, vm);
464 if (r) {
465 goto out;
466 }
467 r = radeon_bo_vm_update_pte(parser, vm);
468 if (r) {
469 goto out;
470 }
471 r = radeon_cs_sync_rings(parser);
472 if (r) {
473 DRM_ERROR("Failed to synchronize rings !\n");
474 }
475
476 if ((rdev->family >= CHIP_TAHITI) &&
477 (parser->chunk_const_ib_idx != -1)) {
478 parser->const_ib->vm_id = vm->id;
479 /* ib pool is bind at 0 in virtual address space to gpu_addr is the
480 * offset inside the pool bo
481 */
482 parser->const_ib->gpu_addr = parser->const_ib->sa_bo.offset;
483 r = radeon_ib_schedule(rdev, parser->const_ib);
484 if (r)
485 goto out;
486 }
487
488 parser->ib->vm_id = vm->id;
489 /* ib pool is bind at 0 in virtual address space to gpu_addr is the
490 * offset inside the pool bo
491 */
492 parser->ib->gpu_addr = parser->ib->sa_bo.offset;
493 parser->ib->is_const_ib = false;
494 r = radeon_ib_schedule(rdev, parser->ib);
495 out:
496 if (!r) {
497 if (vm->fence) {
498 radeon_fence_unref(&vm->fence);
499 }
500 vm->fence = radeon_fence_ref(parser->ib->fence);
501 }
502 mutex_unlock(&fpriv->vm.mutex);
503 return r;
504 }
505
radeon_cs_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)506 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
507 {
508 struct radeon_device *rdev = dev->dev_private;
509 struct radeon_cs_parser parser;
510 int r;
511
512 radeon_mutex_lock(&rdev->cs_mutex);
513 if (!rdev->accel_working) {
514 radeon_mutex_unlock(&rdev->cs_mutex);
515 return -EBUSY;
516 }
517 /* initialize parser */
518 memset(&parser, 0, sizeof(struct radeon_cs_parser));
519 parser.filp = filp;
520 parser.rdev = rdev;
521 parser.dev = rdev->dev;
522 parser.family = rdev->family;
523 r = radeon_cs_parser_init(&parser, data);
524 if (r) {
525 DRM_ERROR("Failed to initialize parser !\n");
526 radeon_cs_parser_fini(&parser, r);
527 radeon_mutex_unlock(&rdev->cs_mutex);
528 return r;
529 }
530 r = radeon_cs_parser_relocs(&parser);
531 if (r) {
532 if (r != -ERESTARTSYS)
533 DRM_ERROR("Failed to parse relocation %d!\n", r);
534 radeon_cs_parser_fini(&parser, r);
535 radeon_mutex_unlock(&rdev->cs_mutex);
536 return r;
537 }
538 r = radeon_cs_ib_chunk(rdev, &parser);
539 if (r) {
540 goto out;
541 }
542 r = radeon_cs_ib_vm_chunk(rdev, &parser);
543 if (r) {
544 goto out;
545 }
546 out:
547 radeon_cs_parser_fini(&parser, r);
548 radeon_mutex_unlock(&rdev->cs_mutex);
549 return r;
550 }
551
radeon_cs_finish_pages(struct radeon_cs_parser * p)552 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
553 {
554 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
555 int i;
556 int size = PAGE_SIZE;
557
558 for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
559 if (i == ibc->last_page_index) {
560 size = (ibc->length_dw * 4) % PAGE_SIZE;
561 if (size == 0)
562 size = PAGE_SIZE;
563 }
564
565 if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
566 ibc->user_ptr + (i * PAGE_SIZE),
567 size))
568 return -EFAULT;
569 }
570 return 0;
571 }
572
radeon_cs_update_pages(struct radeon_cs_parser * p,int pg_idx)573 int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
574 {
575 int new_page;
576 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
577 int i;
578 int size = PAGE_SIZE;
579
580 for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
581 if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
582 ibc->user_ptr + (i * PAGE_SIZE),
583 PAGE_SIZE)) {
584 p->parser_error = -EFAULT;
585 return 0;
586 }
587 }
588
589 new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
590
591 if (pg_idx == ibc->last_page_index) {
592 size = (ibc->length_dw * 4) % PAGE_SIZE;
593 if (size == 0)
594 size = PAGE_SIZE;
595 }
596
597 if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
598 ibc->user_ptr + (pg_idx * PAGE_SIZE),
599 size)) {
600 p->parser_error = -EFAULT;
601 return 0;
602 }
603
604 /* copy to IB here */
605 memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
606
607 ibc->last_copied_page = pg_idx;
608 ibc->kpage_idx[new_page] = pg_idx;
609
610 return new_page;
611 }
612