1 /*
2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 */
27 #include "drmP.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 #ifdef CONFIG_PPC_PMAC
33 /* not sure which of these are needed */
34 #include <asm/machdep.h>
35 #include <asm/pmac_feature.h>
36 #include <asm/prom.h>
37 #include <asm/pci-bridge.h>
38 #endif /* CONFIG_PPC_PMAC */
39
40 /* from radeon_encoder.c */
41 extern uint32_t
42 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44 extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46 /* from radeon_connector.c */
47 extern void
48 radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
55
56 /* from radeon_legacy_encoder.c */
57 extern void
58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
59 uint32_t supported_device);
60
61 /* old legacy ATI BIOS routines */
62
63 /* COMBIOS table offsets */
64 enum radeon_combios_table_offset {
65 /* absolute offset tables */
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100 /* relative offset tables */
101 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */
102 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */
103 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */
104 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */
105 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */
106 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */
107 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */
108 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */
109 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */
110 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */
111 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */
112 };
113
114 enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122 };
123
124 enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133 };
134
135 const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144 };
145
combios_get_table_offset(struct drm_device * dev,enum radeon_combios_table_offset table)146 static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148 {
149 struct radeon_device *rdev = dev->dev_private;
150 int rev, size;
151 uint16_t offset = 0, check_offset;
152
153 if (!rdev->bios)
154 return 0;
155
156 switch (table) {
157 /* absolute offset tables */
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = 0xc;
160 break;
161 case COMBIOS_BIOS_SUPPORT_TABLE:
162 check_offset = 0x14;
163 break;
164 case COMBIOS_DAC_PROGRAMMING_TABLE:
165 check_offset = 0x2a;
166 break;
167 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
168 check_offset = 0x2c;
169 break;
170 case COMBIOS_CRTC_INFO_TABLE:
171 check_offset = 0x2e;
172 break;
173 case COMBIOS_PLL_INFO_TABLE:
174 check_offset = 0x30;
175 break;
176 case COMBIOS_TV_INFO_TABLE:
177 check_offset = 0x32;
178 break;
179 case COMBIOS_DFP_INFO_TABLE:
180 check_offset = 0x34;
181 break;
182 case COMBIOS_HW_CONFIG_INFO_TABLE:
183 check_offset = 0x36;
184 break;
185 case COMBIOS_MULTIMEDIA_INFO_TABLE:
186 check_offset = 0x38;
187 break;
188 case COMBIOS_TV_STD_PATCH_TABLE:
189 check_offset = 0x3e;
190 break;
191 case COMBIOS_LCD_INFO_TABLE:
192 check_offset = 0x40;
193 break;
194 case COMBIOS_MOBILE_INFO_TABLE:
195 check_offset = 0x42;
196 break;
197 case COMBIOS_PLL_INIT_TABLE:
198 check_offset = 0x46;
199 break;
200 case COMBIOS_MEM_CONFIG_TABLE:
201 check_offset = 0x48;
202 break;
203 case COMBIOS_SAVE_MASK_TABLE:
204 check_offset = 0x4a;
205 break;
206 case COMBIOS_HARDCODED_EDID_TABLE:
207 check_offset = 0x4c;
208 break;
209 case COMBIOS_ASIC_INIT_2_TABLE:
210 check_offset = 0x4e;
211 break;
212 case COMBIOS_CONNECTOR_INFO_TABLE:
213 check_offset = 0x50;
214 break;
215 case COMBIOS_DYN_CLK_1_TABLE:
216 check_offset = 0x52;
217 break;
218 case COMBIOS_RESERVED_MEM_TABLE:
219 check_offset = 0x54;
220 break;
221 case COMBIOS_EXT_TMDS_INFO_TABLE:
222 check_offset = 0x58;
223 break;
224 case COMBIOS_MEM_CLK_INFO_TABLE:
225 check_offset = 0x5a;
226 break;
227 case COMBIOS_EXT_DAC_INFO_TABLE:
228 check_offset = 0x5c;
229 break;
230 case COMBIOS_MISC_INFO_TABLE:
231 check_offset = 0x5e;
232 break;
233 case COMBIOS_CRT_INFO_TABLE:
234 check_offset = 0x60;
235 break;
236 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
237 check_offset = 0x62;
238 break;
239 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
240 check_offset = 0x64;
241 break;
242 case COMBIOS_FAN_SPEED_INFO_TABLE:
243 check_offset = 0x66;
244 break;
245 case COMBIOS_OVERDRIVE_INFO_TABLE:
246 check_offset = 0x68;
247 break;
248 case COMBIOS_OEM_INFO_TABLE:
249 check_offset = 0x6a;
250 break;
251 case COMBIOS_DYN_CLK_2_TABLE:
252 check_offset = 0x6c;
253 break;
254 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
255 check_offset = 0x6e;
256 break;
257 case COMBIOS_I2C_INFO_TABLE:
258 check_offset = 0x70;
259 break;
260 /* relative offset tables */
261 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
262 check_offset =
263 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
264 if (check_offset) {
265 rev = RBIOS8(check_offset);
266 if (rev > 0) {
267 check_offset = RBIOS16(check_offset + 0x3);
268 if (check_offset)
269 offset = check_offset;
270 }
271 }
272 break;
273 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
274 check_offset =
275 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
276 if (check_offset) {
277 rev = RBIOS8(check_offset);
278 if (rev > 0) {
279 check_offset = RBIOS16(check_offset + 0x5);
280 if (check_offset)
281 offset = check_offset;
282 }
283 }
284 break;
285 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */
286 check_offset =
287 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
288 if (check_offset) {
289 rev = RBIOS8(check_offset);
290 if (rev > 0) {
291 check_offset = RBIOS16(check_offset + 0x7);
292 if (check_offset)
293 offset = check_offset;
294 }
295 }
296 break;
297 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
298 check_offset =
299 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
300 if (check_offset) {
301 rev = RBIOS8(check_offset);
302 if (rev == 2) {
303 check_offset = RBIOS16(check_offset + 0x9);
304 if (check_offset)
305 offset = check_offset;
306 }
307 }
308 break;
309 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */
310 check_offset =
311 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
312 if (check_offset) {
313 while (RBIOS8(check_offset++));
314 check_offset += 2;
315 if (check_offset)
316 offset = check_offset;
317 }
318 break;
319 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */
320 check_offset =
321 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
322 if (check_offset) {
323 check_offset = RBIOS16(check_offset + 0x11);
324 if (check_offset)
325 offset = check_offset;
326 }
327 break;
328 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */
329 check_offset =
330 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
331 if (check_offset) {
332 check_offset = RBIOS16(check_offset + 0x13);
333 if (check_offset)
334 offset = check_offset;
335 }
336 break;
337 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */
338 check_offset =
339 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
340 if (check_offset) {
341 check_offset = RBIOS16(check_offset + 0x15);
342 if (check_offset)
343 offset = check_offset;
344 }
345 break;
346 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */
347 check_offset =
348 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
349 if (check_offset) {
350 check_offset = RBIOS16(check_offset + 0x17);
351 if (check_offset)
352 offset = check_offset;
353 }
354 break;
355 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */
356 check_offset =
357 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
358 if (check_offset) {
359 check_offset = RBIOS16(check_offset + 0x2);
360 if (check_offset)
361 offset = check_offset;
362 }
363 break;
364 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */
365 check_offset =
366 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
367 if (check_offset) {
368 check_offset = RBIOS16(check_offset + 0x4);
369 if (check_offset)
370 offset = check_offset;
371 }
372 break;
373 default:
374 check_offset = 0;
375 break;
376 }
377
378 size = RBIOS8(rdev->bios_header_start + 0x6);
379 /* check absolute offset tables */
380 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
381 offset = RBIOS16(rdev->bios_header_start + check_offset);
382
383 return offset;
384 }
385
radeon_combios_check_hardcoded_edid(struct radeon_device * rdev)386 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
387 {
388 int edid_info, size;
389 struct edid *edid;
390 unsigned char *raw;
391 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
392 if (!edid_info)
393 return false;
394
395 raw = rdev->bios + edid_info;
396 size = EDID_LENGTH * (raw[0x7e] + 1);
397 edid = kmalloc(size, GFP_KERNEL);
398 if (edid == NULL)
399 return false;
400
401 memcpy((unsigned char *)edid, raw, size);
402
403 if (!drm_edid_is_valid(edid)) {
404 kfree(edid);
405 return false;
406 }
407
408 rdev->mode_info.bios_hardcoded_edid = edid;
409 rdev->mode_info.bios_hardcoded_edid_size = size;
410 return true;
411 }
412
413 /* this is used for atom LCDs as well */
414 struct edid *
radeon_bios_get_hardcoded_edid(struct radeon_device * rdev)415 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
416 {
417 struct edid *edid;
418
419 if (rdev->mode_info.bios_hardcoded_edid) {
420 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
421 if (edid) {
422 memcpy((unsigned char *)edid,
423 (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
424 rdev->mode_info.bios_hardcoded_edid_size);
425 return edid;
426 }
427 }
428 return NULL;
429 }
430
combios_setup_i2c_bus(struct radeon_device * rdev,enum radeon_combios_ddc ddc,u32 clk_mask,u32 data_mask)431 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
432 enum radeon_combios_ddc ddc,
433 u32 clk_mask,
434 u32 data_mask)
435 {
436 struct radeon_i2c_bus_rec i2c;
437 int ddc_line = 0;
438
439 /* ddc id = mask reg
440 * DDC_NONE_DETECTED = none
441 * DDC_DVI = RADEON_GPIO_DVI_DDC
442 * DDC_VGA = RADEON_GPIO_VGA_DDC
443 * DDC_LCD = RADEON_GPIOPAD_MASK
444 * DDC_GPIO = RADEON_MDGPIO_MASK
445 * r1xx
446 * DDC_MONID = RADEON_GPIO_MONID
447 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC
448 * r200
449 * DDC_MONID = RADEON_GPIO_MONID
450 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
451 * r300/r350
452 * DDC_MONID = RADEON_GPIO_DVI_DDC
453 * DDC_CRT2 = RADEON_GPIO_DVI_DDC
454 * rv2xx/rv3xx
455 * DDC_MONID = RADEON_GPIO_MONID
456 * DDC_CRT2 = RADEON_GPIO_MONID
457 * rs3xx/rs4xx
458 * DDC_MONID = RADEON_GPIOPAD_MASK
459 * DDC_CRT2 = RADEON_GPIO_MONID
460 */
461 switch (ddc) {
462 case DDC_NONE_DETECTED:
463 default:
464 ddc_line = 0;
465 break;
466 case DDC_DVI:
467 ddc_line = RADEON_GPIO_DVI_DDC;
468 break;
469 case DDC_VGA:
470 ddc_line = RADEON_GPIO_VGA_DDC;
471 break;
472 case DDC_LCD:
473 ddc_line = RADEON_GPIOPAD_MASK;
474 break;
475 case DDC_GPIO:
476 ddc_line = RADEON_MDGPIO_MASK;
477 break;
478 case DDC_MONID:
479 if (rdev->family == CHIP_RS300 ||
480 rdev->family == CHIP_RS400 ||
481 rdev->family == CHIP_RS480)
482 ddc_line = RADEON_GPIOPAD_MASK;
483 else if (rdev->family == CHIP_R300 ||
484 rdev->family == CHIP_R350) {
485 ddc_line = RADEON_GPIO_DVI_DDC;
486 ddc = DDC_DVI;
487 } else
488 ddc_line = RADEON_GPIO_MONID;
489 break;
490 case DDC_CRT2:
491 if (rdev->family == CHIP_R200 ||
492 rdev->family == CHIP_R300 ||
493 rdev->family == CHIP_R350) {
494 ddc_line = RADEON_GPIO_DVI_DDC;
495 ddc = DDC_DVI;
496 } else if (rdev->family == CHIP_RS300 ||
497 rdev->family == CHIP_RS400 ||
498 rdev->family == CHIP_RS480)
499 ddc_line = RADEON_GPIO_MONID;
500 else if (rdev->family >= CHIP_RV350) {
501 ddc_line = RADEON_GPIO_MONID;
502 ddc = DDC_MONID;
503 } else
504 ddc_line = RADEON_GPIO_CRT2_DDC;
505 break;
506 }
507
508 if (ddc_line == RADEON_GPIOPAD_MASK) {
509 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
510 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
511 i2c.a_clk_reg = RADEON_GPIOPAD_A;
512 i2c.a_data_reg = RADEON_GPIOPAD_A;
513 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
514 i2c.en_data_reg = RADEON_GPIOPAD_EN;
515 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
516 i2c.y_data_reg = RADEON_GPIOPAD_Y;
517 } else if (ddc_line == RADEON_MDGPIO_MASK) {
518 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
519 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
520 i2c.a_clk_reg = RADEON_MDGPIO_A;
521 i2c.a_data_reg = RADEON_MDGPIO_A;
522 i2c.en_clk_reg = RADEON_MDGPIO_EN;
523 i2c.en_data_reg = RADEON_MDGPIO_EN;
524 i2c.y_clk_reg = RADEON_MDGPIO_Y;
525 i2c.y_data_reg = RADEON_MDGPIO_Y;
526 } else {
527 i2c.mask_clk_reg = ddc_line;
528 i2c.mask_data_reg = ddc_line;
529 i2c.a_clk_reg = ddc_line;
530 i2c.a_data_reg = ddc_line;
531 i2c.en_clk_reg = ddc_line;
532 i2c.en_data_reg = ddc_line;
533 i2c.y_clk_reg = ddc_line;
534 i2c.y_data_reg = ddc_line;
535 }
536
537 if (clk_mask && data_mask) {
538 /* system specific masks */
539 i2c.mask_clk_mask = clk_mask;
540 i2c.mask_data_mask = data_mask;
541 i2c.a_clk_mask = clk_mask;
542 i2c.a_data_mask = data_mask;
543 i2c.en_clk_mask = clk_mask;
544 i2c.en_data_mask = data_mask;
545 i2c.y_clk_mask = clk_mask;
546 i2c.y_data_mask = data_mask;
547 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
548 (ddc_line == RADEON_MDGPIO_MASK)) {
549 /* default gpiopad masks */
550 i2c.mask_clk_mask = (0x20 << 8);
551 i2c.mask_data_mask = 0x80;
552 i2c.a_clk_mask = (0x20 << 8);
553 i2c.a_data_mask = 0x80;
554 i2c.en_clk_mask = (0x20 << 8);
555 i2c.en_data_mask = 0x80;
556 i2c.y_clk_mask = (0x20 << 8);
557 i2c.y_data_mask = 0x80;
558 } else {
559 /* default masks for ddc pads */
560 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
561 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
562 i2c.a_clk_mask = RADEON_GPIO_A_1;
563 i2c.a_data_mask = RADEON_GPIO_A_0;
564 i2c.en_clk_mask = RADEON_GPIO_EN_1;
565 i2c.en_data_mask = RADEON_GPIO_EN_0;
566 i2c.y_clk_mask = RADEON_GPIO_Y_1;
567 i2c.y_data_mask = RADEON_GPIO_Y_0;
568 }
569
570 switch (rdev->family) {
571 case CHIP_R100:
572 case CHIP_RV100:
573 case CHIP_RS100:
574 case CHIP_RV200:
575 case CHIP_RS200:
576 case CHIP_RS300:
577 switch (ddc_line) {
578 case RADEON_GPIO_DVI_DDC:
579 i2c.hw_capable = true;
580 break;
581 default:
582 i2c.hw_capable = false;
583 break;
584 }
585 break;
586 case CHIP_R200:
587 switch (ddc_line) {
588 case RADEON_GPIO_DVI_DDC:
589 case RADEON_GPIO_MONID:
590 i2c.hw_capable = true;
591 break;
592 default:
593 i2c.hw_capable = false;
594 break;
595 }
596 break;
597 case CHIP_RV250:
598 case CHIP_RV280:
599 switch (ddc_line) {
600 case RADEON_GPIO_VGA_DDC:
601 case RADEON_GPIO_DVI_DDC:
602 case RADEON_GPIO_CRT2_DDC:
603 i2c.hw_capable = true;
604 break;
605 default:
606 i2c.hw_capable = false;
607 break;
608 }
609 break;
610 case CHIP_R300:
611 case CHIP_R350:
612 switch (ddc_line) {
613 case RADEON_GPIO_VGA_DDC:
614 case RADEON_GPIO_DVI_DDC:
615 i2c.hw_capable = true;
616 break;
617 default:
618 i2c.hw_capable = false;
619 break;
620 }
621 break;
622 case CHIP_RV350:
623 case CHIP_RV380:
624 case CHIP_RS400:
625 case CHIP_RS480:
626 switch (ddc_line) {
627 case RADEON_GPIO_VGA_DDC:
628 case RADEON_GPIO_DVI_DDC:
629 i2c.hw_capable = true;
630 break;
631 case RADEON_GPIO_MONID:
632 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
633 * reliably on some pre-r4xx hardware; not sure why.
634 */
635 i2c.hw_capable = false;
636 break;
637 default:
638 i2c.hw_capable = false;
639 break;
640 }
641 break;
642 default:
643 i2c.hw_capable = false;
644 break;
645 }
646 i2c.mm_i2c = false;
647
648 i2c.i2c_id = ddc;
649 i2c.hpd = RADEON_HPD_NONE;
650
651 if (ddc_line)
652 i2c.valid = true;
653 else
654 i2c.valid = false;
655
656 return i2c;
657 }
658
radeon_combios_i2c_init(struct radeon_device * rdev)659 void radeon_combios_i2c_init(struct radeon_device *rdev)
660 {
661 struct drm_device *dev = rdev->ddev;
662 struct radeon_i2c_bus_rec i2c;
663
664 /* actual hw pads
665 * r1xx/rs2xx/rs3xx
666 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
667 * r200
668 * 0x60, 0x64, 0x68, mm
669 * r300/r350
670 * 0x60, 0x64, mm
671 * rv2xx/rv3xx/rs4xx
672 * 0x60, 0x64, 0x68, gpiopads, mm
673 */
674
675 /* 0x60 */
676 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
677 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
678 /* 0x64 */
679 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
680 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
681
682 /* mm i2c */
683 i2c.valid = true;
684 i2c.hw_capable = true;
685 i2c.mm_i2c = true;
686 i2c.i2c_id = 0xa0;
687 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
688
689 if (rdev->family == CHIP_R300 ||
690 rdev->family == CHIP_R350) {
691 /* only 2 sw i2c pads */
692 } else if (rdev->family == CHIP_RS300 ||
693 rdev->family == CHIP_RS400 ||
694 rdev->family == CHIP_RS480) {
695 u16 offset;
696 u8 id, blocks, clk, data;
697 int i;
698
699 /* 0x68 */
700 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
701 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
702
703 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
704 if (offset) {
705 blocks = RBIOS8(offset + 2);
706 for (i = 0; i < blocks; i++) {
707 id = RBIOS8(offset + 3 + (i * 5) + 0);
708 if (id == 136) {
709 clk = RBIOS8(offset + 3 + (i * 5) + 3);
710 data = RBIOS8(offset + 3 + (i * 5) + 4);
711 /* gpiopad */
712 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
713 (1 << clk), (1 << data));
714 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
715 break;
716 }
717 }
718 }
719 } else if ((rdev->family == CHIP_R200) ||
720 (rdev->family >= CHIP_R300)) {
721 /* 0x68 */
722 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
723 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
724 } else {
725 /* 0x68 */
726 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
727 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
728 /* 0x6c */
729 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
730 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
731 }
732 }
733
radeon_combios_get_clock_info(struct drm_device * dev)734 bool radeon_combios_get_clock_info(struct drm_device *dev)
735 {
736 struct radeon_device *rdev = dev->dev_private;
737 uint16_t pll_info;
738 struct radeon_pll *p1pll = &rdev->clock.p1pll;
739 struct radeon_pll *p2pll = &rdev->clock.p2pll;
740 struct radeon_pll *spll = &rdev->clock.spll;
741 struct radeon_pll *mpll = &rdev->clock.mpll;
742 int8_t rev;
743 uint16_t sclk, mclk;
744
745 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
746 if (pll_info) {
747 rev = RBIOS8(pll_info);
748
749 /* pixel clocks */
750 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
751 p1pll->reference_div = RBIOS16(pll_info + 0x10);
752 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
753 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
754 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
755 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
756
757 if (rev > 9) {
758 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
759 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
760 } else {
761 p1pll->pll_in_min = 40;
762 p1pll->pll_in_max = 500;
763 }
764 *p2pll = *p1pll;
765
766 /* system clock */
767 spll->reference_freq = RBIOS16(pll_info + 0x1a);
768 spll->reference_div = RBIOS16(pll_info + 0x1c);
769 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
770 spll->pll_out_max = RBIOS32(pll_info + 0x22);
771
772 if (rev > 10) {
773 spll->pll_in_min = RBIOS32(pll_info + 0x48);
774 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
775 } else {
776 /* ??? */
777 spll->pll_in_min = 40;
778 spll->pll_in_max = 500;
779 }
780
781 /* memory clock */
782 mpll->reference_freq = RBIOS16(pll_info + 0x26);
783 mpll->reference_div = RBIOS16(pll_info + 0x28);
784 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
785 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
786
787 if (rev > 10) {
788 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
789 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
790 } else {
791 /* ??? */
792 mpll->pll_in_min = 40;
793 mpll->pll_in_max = 500;
794 }
795
796 /* default sclk/mclk */
797 sclk = RBIOS16(pll_info + 0xa);
798 mclk = RBIOS16(pll_info + 0x8);
799 if (sclk == 0)
800 sclk = 200 * 100;
801 if (mclk == 0)
802 mclk = 200 * 100;
803
804 rdev->clock.default_sclk = sclk;
805 rdev->clock.default_mclk = mclk;
806
807 if (RBIOS32(pll_info + 0x16))
808 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
809 else
810 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
811
812 return true;
813 }
814 return false;
815 }
816
radeon_combios_sideport_present(struct radeon_device * rdev)817 bool radeon_combios_sideport_present(struct radeon_device *rdev)
818 {
819 struct drm_device *dev = rdev->ddev;
820 u16 igp_info;
821
822 /* sideport is AMD only */
823 if (rdev->family == CHIP_RS400)
824 return false;
825
826 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
827
828 if (igp_info) {
829 if (RBIOS16(igp_info + 0x4))
830 return true;
831 }
832 return false;
833 }
834
835 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
836 0x00000808, /* r100 */
837 0x00000808, /* rv100 */
838 0x00000808, /* rs100 */
839 0x00000808, /* rv200 */
840 0x00000808, /* rs200 */
841 0x00000808, /* r200 */
842 0x00000808, /* rv250 */
843 0x00000000, /* rs300 */
844 0x00000808, /* rv280 */
845 0x00000808, /* r300 */
846 0x00000808, /* r350 */
847 0x00000808, /* rv350 */
848 0x00000808, /* rv380 */
849 0x00000808, /* r420 */
850 0x00000808, /* r423 */
851 0x00000808, /* rv410 */
852 0x00000000, /* rs400 */
853 0x00000000, /* rs480 */
854 };
855
radeon_legacy_get_primary_dac_info_from_table(struct radeon_device * rdev,struct radeon_encoder_primary_dac * p_dac)856 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
857 struct radeon_encoder_primary_dac *p_dac)
858 {
859 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
860 return;
861 }
862
radeon_combios_get_primary_dac_info(struct radeon_encoder * encoder)863 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
864 radeon_encoder
865 *encoder)
866 {
867 struct drm_device *dev = encoder->base.dev;
868 struct radeon_device *rdev = dev->dev_private;
869 uint16_t dac_info;
870 uint8_t rev, bg, dac;
871 struct radeon_encoder_primary_dac *p_dac = NULL;
872 int found = 0;
873
874 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
875 GFP_KERNEL);
876
877 if (!p_dac)
878 return NULL;
879
880 /* check CRT table */
881 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
882 if (dac_info) {
883 rev = RBIOS8(dac_info) & 0x3;
884 if (rev < 2) {
885 bg = RBIOS8(dac_info + 0x2) & 0xf;
886 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
887 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
888 } else {
889 bg = RBIOS8(dac_info + 0x2) & 0xf;
890 dac = RBIOS8(dac_info + 0x3) & 0xf;
891 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
892 }
893 /* if the values are zeros, use the table */
894 if ((dac == 0) || (bg == 0))
895 found = 0;
896 else
897 found = 1;
898 }
899
900 /* quirks */
901 /* Radeon 7000 (RV100) */
902 if (((dev->pdev->device == 0x5159) &&
903 (dev->pdev->subsystem_vendor == 0x174B) &&
904 (dev->pdev->subsystem_device == 0x7c28)) ||
905 /* Radeon 9100 (R200) */
906 ((dev->pdev->device == 0x514D) &&
907 (dev->pdev->subsystem_vendor == 0x174B) &&
908 (dev->pdev->subsystem_device == 0x7149))) {
909 /* vbios value is bad, use the default */
910 found = 0;
911 }
912
913 if (!found) /* fallback to defaults */
914 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
915
916 return p_dac;
917 }
918
919 enum radeon_tv_std
radeon_combios_get_tv_info(struct radeon_device * rdev)920 radeon_combios_get_tv_info(struct radeon_device *rdev)
921 {
922 struct drm_device *dev = rdev->ddev;
923 uint16_t tv_info;
924 enum radeon_tv_std tv_std = TV_STD_NTSC;
925
926 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
927 if (tv_info) {
928 if (RBIOS8(tv_info + 6) == 'T') {
929 switch (RBIOS8(tv_info + 7) & 0xf) {
930 case 1:
931 tv_std = TV_STD_NTSC;
932 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
933 break;
934 case 2:
935 tv_std = TV_STD_PAL;
936 DRM_DEBUG_KMS("Default TV standard: PAL\n");
937 break;
938 case 3:
939 tv_std = TV_STD_PAL_M;
940 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
941 break;
942 case 4:
943 tv_std = TV_STD_PAL_60;
944 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
945 break;
946 case 5:
947 tv_std = TV_STD_NTSC_J;
948 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
949 break;
950 case 6:
951 tv_std = TV_STD_SCART_PAL;
952 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
953 break;
954 default:
955 tv_std = TV_STD_NTSC;
956 DRM_DEBUG_KMS
957 ("Unknown TV standard; defaulting to NTSC\n");
958 break;
959 }
960
961 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
962 case 0:
963 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
964 break;
965 case 1:
966 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
967 break;
968 case 2:
969 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
970 break;
971 case 3:
972 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
973 break;
974 default:
975 break;
976 }
977 }
978 }
979 return tv_std;
980 }
981
982 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
983 0x00000000, /* r100 */
984 0x00280000, /* rv100 */
985 0x00000000, /* rs100 */
986 0x00880000, /* rv200 */
987 0x00000000, /* rs200 */
988 0x00000000, /* r200 */
989 0x00770000, /* rv250 */
990 0x00290000, /* rs300 */
991 0x00560000, /* rv280 */
992 0x00780000, /* r300 */
993 0x00770000, /* r350 */
994 0x00780000, /* rv350 */
995 0x00780000, /* rv380 */
996 0x01080000, /* r420 */
997 0x01080000, /* r423 */
998 0x01080000, /* rv410 */
999 0x00780000, /* rs400 */
1000 0x00780000, /* rs480 */
1001 };
1002
radeon_legacy_get_tv_dac_info_from_table(struct radeon_device * rdev,struct radeon_encoder_tv_dac * tv_dac)1003 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1004 struct radeon_encoder_tv_dac *tv_dac)
1005 {
1006 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1007 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1008 tv_dac->ps2_tvdac_adj = 0x00880000;
1009 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1010 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1011 return;
1012 }
1013
radeon_combios_get_tv_dac_info(struct radeon_encoder * encoder)1014 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1015 radeon_encoder
1016 *encoder)
1017 {
1018 struct drm_device *dev = encoder->base.dev;
1019 struct radeon_device *rdev = dev->dev_private;
1020 uint16_t dac_info;
1021 uint8_t rev, bg, dac;
1022 struct radeon_encoder_tv_dac *tv_dac = NULL;
1023 int found = 0;
1024
1025 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1026 if (!tv_dac)
1027 return NULL;
1028
1029 /* first check TV table */
1030 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1031 if (dac_info) {
1032 rev = RBIOS8(dac_info + 0x3);
1033 if (rev > 4) {
1034 bg = RBIOS8(dac_info + 0xc) & 0xf;
1035 dac = RBIOS8(dac_info + 0xd) & 0xf;
1036 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1037
1038 bg = RBIOS8(dac_info + 0xe) & 0xf;
1039 dac = RBIOS8(dac_info + 0xf) & 0xf;
1040 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1041
1042 bg = RBIOS8(dac_info + 0x10) & 0xf;
1043 dac = RBIOS8(dac_info + 0x11) & 0xf;
1044 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1045 /* if the values are all zeros, use the table */
1046 if (tv_dac->ps2_tvdac_adj)
1047 found = 1;
1048 } else if (rev > 1) {
1049 bg = RBIOS8(dac_info + 0xc) & 0xf;
1050 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1051 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1052
1053 bg = RBIOS8(dac_info + 0xd) & 0xf;
1054 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1055 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1056
1057 bg = RBIOS8(dac_info + 0xe) & 0xf;
1058 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1059 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1060 /* if the values are all zeros, use the table */
1061 if (tv_dac->ps2_tvdac_adj)
1062 found = 1;
1063 }
1064 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1065 }
1066 if (!found) {
1067 /* then check CRT table */
1068 dac_info =
1069 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1070 if (dac_info) {
1071 rev = RBIOS8(dac_info) & 0x3;
1072 if (rev < 2) {
1073 bg = RBIOS8(dac_info + 0x3) & 0xf;
1074 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1075 tv_dac->ps2_tvdac_adj =
1076 (bg << 16) | (dac << 20);
1077 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1078 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1079 /* if the values are all zeros, use the table */
1080 if (tv_dac->ps2_tvdac_adj)
1081 found = 1;
1082 } else {
1083 bg = RBIOS8(dac_info + 0x4) & 0xf;
1084 dac = RBIOS8(dac_info + 0x5) & 0xf;
1085 tv_dac->ps2_tvdac_adj =
1086 (bg << 16) | (dac << 20);
1087 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1088 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1089 /* if the values are all zeros, use the table */
1090 if (tv_dac->ps2_tvdac_adj)
1091 found = 1;
1092 }
1093 } else {
1094 DRM_INFO("No TV DAC info found in BIOS\n");
1095 }
1096 }
1097
1098 if (!found) /* fallback to defaults */
1099 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1100
1101 return tv_dac;
1102 }
1103
radeon_legacy_get_lvds_info_from_regs(struct radeon_device * rdev)1104 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1105 radeon_device
1106 *rdev)
1107 {
1108 struct radeon_encoder_lvds *lvds = NULL;
1109 uint32_t fp_vert_stretch, fp_horz_stretch;
1110 uint32_t ppll_div_sel, ppll_val;
1111 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1112
1113 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1114
1115 if (!lvds)
1116 return NULL;
1117
1118 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1119 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1120
1121 /* These should be fail-safe defaults, fingers crossed */
1122 lvds->panel_pwr_delay = 200;
1123 lvds->panel_vcc_delay = 2000;
1124
1125 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1126 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1127 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1128
1129 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1130 lvds->native_mode.vdisplay =
1131 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1132 RADEON_VERT_PANEL_SHIFT) + 1;
1133 else
1134 lvds->native_mode.vdisplay =
1135 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1136
1137 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1138 lvds->native_mode.hdisplay =
1139 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1140 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1141 else
1142 lvds->native_mode.hdisplay =
1143 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1144
1145 if ((lvds->native_mode.hdisplay < 640) ||
1146 (lvds->native_mode.vdisplay < 480)) {
1147 lvds->native_mode.hdisplay = 640;
1148 lvds->native_mode.vdisplay = 480;
1149 }
1150
1151 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1152 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1153 if ((ppll_val & 0x000707ff) == 0x1bb)
1154 lvds->use_bios_dividers = false;
1155 else {
1156 lvds->panel_ref_divider =
1157 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1158 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1159 lvds->panel_fb_divider = ppll_val & 0x7ff;
1160
1161 if ((lvds->panel_ref_divider != 0) &&
1162 (lvds->panel_fb_divider > 3))
1163 lvds->use_bios_dividers = true;
1164 }
1165 lvds->panel_vcc_delay = 200;
1166
1167 DRM_INFO("Panel info derived from registers\n");
1168 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1169 lvds->native_mode.vdisplay);
1170
1171 return lvds;
1172 }
1173
radeon_combios_get_lvds_info(struct radeon_encoder * encoder)1174 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1175 *encoder)
1176 {
1177 struct drm_device *dev = encoder->base.dev;
1178 struct radeon_device *rdev = dev->dev_private;
1179 uint16_t lcd_info;
1180 uint32_t panel_setup;
1181 char stmp[30];
1182 int tmp, i;
1183 struct radeon_encoder_lvds *lvds = NULL;
1184
1185 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1186
1187 if (lcd_info) {
1188 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1189
1190 if (!lvds)
1191 return NULL;
1192
1193 for (i = 0; i < 24; i++)
1194 stmp[i] = RBIOS8(lcd_info + i + 1);
1195 stmp[24] = 0;
1196
1197 DRM_INFO("Panel ID String: %s\n", stmp);
1198
1199 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1200 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1201
1202 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1203 lvds->native_mode.vdisplay);
1204
1205 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1206 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1207
1208 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1209 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1210 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1211
1212 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1213 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1214 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1215 if ((lvds->panel_ref_divider != 0) &&
1216 (lvds->panel_fb_divider > 3))
1217 lvds->use_bios_dividers = true;
1218
1219 panel_setup = RBIOS32(lcd_info + 0x39);
1220 lvds->lvds_gen_cntl = 0xff00;
1221 if (panel_setup & 0x1)
1222 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1223
1224 if ((panel_setup >> 4) & 0x1)
1225 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1226
1227 switch ((panel_setup >> 8) & 0x7) {
1228 case 0:
1229 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1230 break;
1231 case 1:
1232 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1233 break;
1234 case 2:
1235 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1236 break;
1237 default:
1238 break;
1239 }
1240
1241 if ((panel_setup >> 16) & 0x1)
1242 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1243
1244 if ((panel_setup >> 17) & 0x1)
1245 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1246
1247 if ((panel_setup >> 18) & 0x1)
1248 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1249
1250 if ((panel_setup >> 23) & 0x1)
1251 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1252
1253 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1254
1255 for (i = 0; i < 32; i++) {
1256 tmp = RBIOS16(lcd_info + 64 + i * 2);
1257 if (tmp == 0)
1258 break;
1259
1260 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1261 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1262 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1263 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1264 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1265 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1266 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1267 (RBIOS8(tmp + 23) * 8);
1268
1269 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1270 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1271 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1272 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1273 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1274 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1275
1276 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1277 lvds->native_mode.flags = 0;
1278 /* set crtc values */
1279 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1280
1281 }
1282 }
1283 } else {
1284 DRM_INFO("No panel info found in BIOS\n");
1285 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1286 }
1287
1288 if (lvds)
1289 encoder->native_mode = lvds->native_mode;
1290 return lvds;
1291 }
1292
1293 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1294 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */
1295 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */
1296 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */
1297 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */
1298 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */
1299 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */
1300 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */
1301 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */
1302 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */
1303 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */
1304 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */
1305 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */
1306 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */
1307 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */
1308 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */
1309 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */
1310 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */
1311 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */
1312 };
1313
radeon_legacy_get_tmds_info_from_table(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1314 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1315 struct radeon_encoder_int_tmds *tmds)
1316 {
1317 struct drm_device *dev = encoder->base.dev;
1318 struct radeon_device *rdev = dev->dev_private;
1319 int i;
1320
1321 for (i = 0; i < 4; i++) {
1322 tmds->tmds_pll[i].value =
1323 default_tmds_pll[rdev->family][i].value;
1324 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1325 }
1326
1327 return true;
1328 }
1329
radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder * encoder,struct radeon_encoder_int_tmds * tmds)1330 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1331 struct radeon_encoder_int_tmds *tmds)
1332 {
1333 struct drm_device *dev = encoder->base.dev;
1334 struct radeon_device *rdev = dev->dev_private;
1335 uint16_t tmds_info;
1336 int i, n;
1337 uint8_t ver;
1338
1339 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1340
1341 if (tmds_info) {
1342 ver = RBIOS8(tmds_info);
1343 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1344 if (ver == 3) {
1345 n = RBIOS8(tmds_info + 5) + 1;
1346 if (n > 4)
1347 n = 4;
1348 for (i = 0; i < n; i++) {
1349 tmds->tmds_pll[i].value =
1350 RBIOS32(tmds_info + i * 10 + 0x08);
1351 tmds->tmds_pll[i].freq =
1352 RBIOS16(tmds_info + i * 10 + 0x10);
1353 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1354 tmds->tmds_pll[i].freq,
1355 tmds->tmds_pll[i].value);
1356 }
1357 } else if (ver == 4) {
1358 int stride = 0;
1359 n = RBIOS8(tmds_info + 5) + 1;
1360 if (n > 4)
1361 n = 4;
1362 for (i = 0; i < n; i++) {
1363 tmds->tmds_pll[i].value =
1364 RBIOS32(tmds_info + stride + 0x08);
1365 tmds->tmds_pll[i].freq =
1366 RBIOS16(tmds_info + stride + 0x10);
1367 if (i == 0)
1368 stride += 10;
1369 else
1370 stride += 6;
1371 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1372 tmds->tmds_pll[i].freq,
1373 tmds->tmds_pll[i].value);
1374 }
1375 }
1376 } else {
1377 DRM_INFO("No TMDS info found in BIOS\n");
1378 return false;
1379 }
1380 return true;
1381 }
1382
radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder * encoder,struct radeon_encoder_ext_tmds * tmds)1383 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1384 struct radeon_encoder_ext_tmds *tmds)
1385 {
1386 struct drm_device *dev = encoder->base.dev;
1387 struct radeon_device *rdev = dev->dev_private;
1388 struct radeon_i2c_bus_rec i2c_bus;
1389
1390 /* default for macs */
1391 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1392 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1393
1394 /* XXX some macs have duallink chips */
1395 switch (rdev->mode_info.connector_table) {
1396 case CT_POWERBOOK_EXTERNAL:
1397 case CT_MINI_EXTERNAL:
1398 default:
1399 tmds->dvo_chip = DVO_SIL164;
1400 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1401 break;
1402 }
1403
1404 return true;
1405 }
1406
radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder * encoder,struct radeon_encoder_ext_tmds * tmds)1407 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1408 struct radeon_encoder_ext_tmds *tmds)
1409 {
1410 struct drm_device *dev = encoder->base.dev;
1411 struct radeon_device *rdev = dev->dev_private;
1412 uint16_t offset;
1413 uint8_t ver;
1414 enum radeon_combios_ddc gpio;
1415 struct radeon_i2c_bus_rec i2c_bus;
1416
1417 tmds->i2c_bus = NULL;
1418 if (rdev->flags & RADEON_IS_IGP) {
1419 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1420 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1421 tmds->dvo_chip = DVO_SIL164;
1422 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1423 } else {
1424 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1425 if (offset) {
1426 ver = RBIOS8(offset);
1427 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1428 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1429 tmds->slave_addr >>= 1; /* 7 bit addressing */
1430 gpio = RBIOS8(offset + 4 + 3);
1431 if (gpio == DDC_LCD) {
1432 /* MM i2c */
1433 i2c_bus.valid = true;
1434 i2c_bus.hw_capable = true;
1435 i2c_bus.mm_i2c = true;
1436 i2c_bus.i2c_id = 0xa0;
1437 } else
1438 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1439 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1440 }
1441 }
1442
1443 if (!tmds->i2c_bus) {
1444 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1445 return false;
1446 }
1447
1448 return true;
1449 }
1450
radeon_get_legacy_connector_info_from_table(struct drm_device * dev)1451 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1452 {
1453 struct radeon_device *rdev = dev->dev_private;
1454 struct radeon_i2c_bus_rec ddc_i2c;
1455 struct radeon_hpd hpd;
1456
1457 rdev->mode_info.connector_table = radeon_connector_table;
1458 if (rdev->mode_info.connector_table == CT_NONE) {
1459 #ifdef CONFIG_PPC_PMAC
1460 if (of_machine_is_compatible("PowerBook3,3")) {
1461 /* powerbook with VGA */
1462 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1463 } else if (of_machine_is_compatible("PowerBook3,4") ||
1464 of_machine_is_compatible("PowerBook3,5")) {
1465 /* powerbook with internal tmds */
1466 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1467 } else if (of_machine_is_compatible("PowerBook5,1") ||
1468 of_machine_is_compatible("PowerBook5,2") ||
1469 of_machine_is_compatible("PowerBook5,3") ||
1470 of_machine_is_compatible("PowerBook5,4") ||
1471 of_machine_is_compatible("PowerBook5,5")) {
1472 /* powerbook with external single link tmds (sil164) */
1473 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1474 } else if (of_machine_is_compatible("PowerBook5,6")) {
1475 /* powerbook with external dual or single link tmds */
1476 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1477 } else if (of_machine_is_compatible("PowerBook5,7") ||
1478 of_machine_is_compatible("PowerBook5,8") ||
1479 of_machine_is_compatible("PowerBook5,9")) {
1480 /* PowerBook6,2 ? */
1481 /* powerbook with external dual link tmds (sil1178?) */
1482 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1483 } else if (of_machine_is_compatible("PowerBook4,1") ||
1484 of_machine_is_compatible("PowerBook4,2") ||
1485 of_machine_is_compatible("PowerBook4,3") ||
1486 of_machine_is_compatible("PowerBook6,3") ||
1487 of_machine_is_compatible("PowerBook6,5") ||
1488 of_machine_is_compatible("PowerBook6,7")) {
1489 /* ibook */
1490 rdev->mode_info.connector_table = CT_IBOOK;
1491 } else if (of_machine_is_compatible("PowerMac3,5")) {
1492 /* PowerMac G4 Silver radeon 7500 */
1493 rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1494 } else if (of_machine_is_compatible("PowerMac4,4")) {
1495 /* emac */
1496 rdev->mode_info.connector_table = CT_EMAC;
1497 } else if (of_machine_is_compatible("PowerMac10,1")) {
1498 /* mini with internal tmds */
1499 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1500 } else if (of_machine_is_compatible("PowerMac10,2")) {
1501 /* mini with external tmds */
1502 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1503 } else if (of_machine_is_compatible("PowerMac12,1")) {
1504 /* PowerMac8,1 ? */
1505 /* imac g5 isight */
1506 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1507 } else if ((rdev->pdev->device == 0x4a48) &&
1508 (rdev->pdev->subsystem_vendor == 0x1002) &&
1509 (rdev->pdev->subsystem_device == 0x4a48)) {
1510 /* Mac X800 */
1511 rdev->mode_info.connector_table = CT_MAC_X800;
1512 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1513 of_machine_is_compatible("PowerMac7,3")) &&
1514 (rdev->pdev->device == 0x4150) &&
1515 (rdev->pdev->subsystem_vendor == 0x1002) &&
1516 (rdev->pdev->subsystem_device == 0x4150)) {
1517 /* Mac G5 tower 9600 */
1518 rdev->mode_info.connector_table = CT_MAC_G5_9600;
1519 } else if ((rdev->pdev->device == 0x4c66) &&
1520 (rdev->pdev->subsystem_vendor == 0x1002) &&
1521 (rdev->pdev->subsystem_device == 0x4c66)) {
1522 /* SAM440ep RV250 embedded board */
1523 rdev->mode_info.connector_table = CT_SAM440EP;
1524 } else
1525 #endif /* CONFIG_PPC_PMAC */
1526 #ifdef CONFIG_PPC64
1527 if (ASIC_IS_RN50(rdev))
1528 rdev->mode_info.connector_table = CT_RN50_POWER;
1529 else
1530 #endif
1531 rdev->mode_info.connector_table = CT_GENERIC;
1532 }
1533
1534 switch (rdev->mode_info.connector_table) {
1535 case CT_GENERIC:
1536 DRM_INFO("Connector Table: %d (generic)\n",
1537 rdev->mode_info.connector_table);
1538 /* these are the most common settings */
1539 if (rdev->flags & RADEON_SINGLE_CRTC) {
1540 /* VGA - primary dac */
1541 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1542 hpd.hpd = RADEON_HPD_NONE;
1543 radeon_add_legacy_encoder(dev,
1544 radeon_get_encoder_enum(dev,
1545 ATOM_DEVICE_CRT1_SUPPORT,
1546 1),
1547 ATOM_DEVICE_CRT1_SUPPORT);
1548 radeon_add_legacy_connector(dev, 0,
1549 ATOM_DEVICE_CRT1_SUPPORT,
1550 DRM_MODE_CONNECTOR_VGA,
1551 &ddc_i2c,
1552 CONNECTOR_OBJECT_ID_VGA,
1553 &hpd);
1554 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1555 /* LVDS */
1556 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1557 hpd.hpd = RADEON_HPD_NONE;
1558 radeon_add_legacy_encoder(dev,
1559 radeon_get_encoder_enum(dev,
1560 ATOM_DEVICE_LCD1_SUPPORT,
1561 0),
1562 ATOM_DEVICE_LCD1_SUPPORT);
1563 radeon_add_legacy_connector(dev, 0,
1564 ATOM_DEVICE_LCD1_SUPPORT,
1565 DRM_MODE_CONNECTOR_LVDS,
1566 &ddc_i2c,
1567 CONNECTOR_OBJECT_ID_LVDS,
1568 &hpd);
1569
1570 /* VGA - primary dac */
1571 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1572 hpd.hpd = RADEON_HPD_NONE;
1573 radeon_add_legacy_encoder(dev,
1574 radeon_get_encoder_enum(dev,
1575 ATOM_DEVICE_CRT1_SUPPORT,
1576 1),
1577 ATOM_DEVICE_CRT1_SUPPORT);
1578 radeon_add_legacy_connector(dev, 1,
1579 ATOM_DEVICE_CRT1_SUPPORT,
1580 DRM_MODE_CONNECTOR_VGA,
1581 &ddc_i2c,
1582 CONNECTOR_OBJECT_ID_VGA,
1583 &hpd);
1584 } else {
1585 /* DVI-I - tv dac, int tmds */
1586 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1587 hpd.hpd = RADEON_HPD_1;
1588 radeon_add_legacy_encoder(dev,
1589 radeon_get_encoder_enum(dev,
1590 ATOM_DEVICE_DFP1_SUPPORT,
1591 0),
1592 ATOM_DEVICE_DFP1_SUPPORT);
1593 radeon_add_legacy_encoder(dev,
1594 radeon_get_encoder_enum(dev,
1595 ATOM_DEVICE_CRT2_SUPPORT,
1596 2),
1597 ATOM_DEVICE_CRT2_SUPPORT);
1598 radeon_add_legacy_connector(dev, 0,
1599 ATOM_DEVICE_DFP1_SUPPORT |
1600 ATOM_DEVICE_CRT2_SUPPORT,
1601 DRM_MODE_CONNECTOR_DVII,
1602 &ddc_i2c,
1603 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1604 &hpd);
1605
1606 /* VGA - primary dac */
1607 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1608 hpd.hpd = RADEON_HPD_NONE;
1609 radeon_add_legacy_encoder(dev,
1610 radeon_get_encoder_enum(dev,
1611 ATOM_DEVICE_CRT1_SUPPORT,
1612 1),
1613 ATOM_DEVICE_CRT1_SUPPORT);
1614 radeon_add_legacy_connector(dev, 1,
1615 ATOM_DEVICE_CRT1_SUPPORT,
1616 DRM_MODE_CONNECTOR_VGA,
1617 &ddc_i2c,
1618 CONNECTOR_OBJECT_ID_VGA,
1619 &hpd);
1620 }
1621
1622 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1623 /* TV - tv dac */
1624 ddc_i2c.valid = false;
1625 hpd.hpd = RADEON_HPD_NONE;
1626 radeon_add_legacy_encoder(dev,
1627 radeon_get_encoder_enum(dev,
1628 ATOM_DEVICE_TV1_SUPPORT,
1629 2),
1630 ATOM_DEVICE_TV1_SUPPORT);
1631 radeon_add_legacy_connector(dev, 2,
1632 ATOM_DEVICE_TV1_SUPPORT,
1633 DRM_MODE_CONNECTOR_SVIDEO,
1634 &ddc_i2c,
1635 CONNECTOR_OBJECT_ID_SVIDEO,
1636 &hpd);
1637 }
1638 break;
1639 case CT_IBOOK:
1640 DRM_INFO("Connector Table: %d (ibook)\n",
1641 rdev->mode_info.connector_table);
1642 /* LVDS */
1643 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1644 hpd.hpd = RADEON_HPD_NONE;
1645 radeon_add_legacy_encoder(dev,
1646 radeon_get_encoder_enum(dev,
1647 ATOM_DEVICE_LCD1_SUPPORT,
1648 0),
1649 ATOM_DEVICE_LCD1_SUPPORT);
1650 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1651 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1652 CONNECTOR_OBJECT_ID_LVDS,
1653 &hpd);
1654 /* VGA - TV DAC */
1655 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1656 hpd.hpd = RADEON_HPD_NONE;
1657 radeon_add_legacy_encoder(dev,
1658 radeon_get_encoder_enum(dev,
1659 ATOM_DEVICE_CRT2_SUPPORT,
1660 2),
1661 ATOM_DEVICE_CRT2_SUPPORT);
1662 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1663 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1664 CONNECTOR_OBJECT_ID_VGA,
1665 &hpd);
1666 /* TV - TV DAC */
1667 ddc_i2c.valid = false;
1668 hpd.hpd = RADEON_HPD_NONE;
1669 radeon_add_legacy_encoder(dev,
1670 radeon_get_encoder_enum(dev,
1671 ATOM_DEVICE_TV1_SUPPORT,
1672 2),
1673 ATOM_DEVICE_TV1_SUPPORT);
1674 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1675 DRM_MODE_CONNECTOR_SVIDEO,
1676 &ddc_i2c,
1677 CONNECTOR_OBJECT_ID_SVIDEO,
1678 &hpd);
1679 break;
1680 case CT_POWERBOOK_EXTERNAL:
1681 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1682 rdev->mode_info.connector_table);
1683 /* LVDS */
1684 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1685 hpd.hpd = RADEON_HPD_NONE;
1686 radeon_add_legacy_encoder(dev,
1687 radeon_get_encoder_enum(dev,
1688 ATOM_DEVICE_LCD1_SUPPORT,
1689 0),
1690 ATOM_DEVICE_LCD1_SUPPORT);
1691 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1692 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1693 CONNECTOR_OBJECT_ID_LVDS,
1694 &hpd);
1695 /* DVI-I - primary dac, ext tmds */
1696 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1697 hpd.hpd = RADEON_HPD_2; /* ??? */
1698 radeon_add_legacy_encoder(dev,
1699 radeon_get_encoder_enum(dev,
1700 ATOM_DEVICE_DFP2_SUPPORT,
1701 0),
1702 ATOM_DEVICE_DFP2_SUPPORT);
1703 radeon_add_legacy_encoder(dev,
1704 radeon_get_encoder_enum(dev,
1705 ATOM_DEVICE_CRT1_SUPPORT,
1706 1),
1707 ATOM_DEVICE_CRT1_SUPPORT);
1708 /* XXX some are SL */
1709 radeon_add_legacy_connector(dev, 1,
1710 ATOM_DEVICE_DFP2_SUPPORT |
1711 ATOM_DEVICE_CRT1_SUPPORT,
1712 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1713 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1714 &hpd);
1715 /* TV - TV DAC */
1716 ddc_i2c.valid = false;
1717 hpd.hpd = RADEON_HPD_NONE;
1718 radeon_add_legacy_encoder(dev,
1719 radeon_get_encoder_enum(dev,
1720 ATOM_DEVICE_TV1_SUPPORT,
1721 2),
1722 ATOM_DEVICE_TV1_SUPPORT);
1723 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1724 DRM_MODE_CONNECTOR_SVIDEO,
1725 &ddc_i2c,
1726 CONNECTOR_OBJECT_ID_SVIDEO,
1727 &hpd);
1728 break;
1729 case CT_POWERBOOK_INTERNAL:
1730 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1731 rdev->mode_info.connector_table);
1732 /* LVDS */
1733 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1734 hpd.hpd = RADEON_HPD_NONE;
1735 radeon_add_legacy_encoder(dev,
1736 radeon_get_encoder_enum(dev,
1737 ATOM_DEVICE_LCD1_SUPPORT,
1738 0),
1739 ATOM_DEVICE_LCD1_SUPPORT);
1740 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1741 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1742 CONNECTOR_OBJECT_ID_LVDS,
1743 &hpd);
1744 /* DVI-I - primary dac, int tmds */
1745 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1746 hpd.hpd = RADEON_HPD_1; /* ??? */
1747 radeon_add_legacy_encoder(dev,
1748 radeon_get_encoder_enum(dev,
1749 ATOM_DEVICE_DFP1_SUPPORT,
1750 0),
1751 ATOM_DEVICE_DFP1_SUPPORT);
1752 radeon_add_legacy_encoder(dev,
1753 radeon_get_encoder_enum(dev,
1754 ATOM_DEVICE_CRT1_SUPPORT,
1755 1),
1756 ATOM_DEVICE_CRT1_SUPPORT);
1757 radeon_add_legacy_connector(dev, 1,
1758 ATOM_DEVICE_DFP1_SUPPORT |
1759 ATOM_DEVICE_CRT1_SUPPORT,
1760 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1761 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1762 &hpd);
1763 /* TV - TV DAC */
1764 ddc_i2c.valid = false;
1765 hpd.hpd = RADEON_HPD_NONE;
1766 radeon_add_legacy_encoder(dev,
1767 radeon_get_encoder_enum(dev,
1768 ATOM_DEVICE_TV1_SUPPORT,
1769 2),
1770 ATOM_DEVICE_TV1_SUPPORT);
1771 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1772 DRM_MODE_CONNECTOR_SVIDEO,
1773 &ddc_i2c,
1774 CONNECTOR_OBJECT_ID_SVIDEO,
1775 &hpd);
1776 break;
1777 case CT_POWERBOOK_VGA:
1778 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1779 rdev->mode_info.connector_table);
1780 /* LVDS */
1781 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1782 hpd.hpd = RADEON_HPD_NONE;
1783 radeon_add_legacy_encoder(dev,
1784 radeon_get_encoder_enum(dev,
1785 ATOM_DEVICE_LCD1_SUPPORT,
1786 0),
1787 ATOM_DEVICE_LCD1_SUPPORT);
1788 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1789 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1790 CONNECTOR_OBJECT_ID_LVDS,
1791 &hpd);
1792 /* VGA - primary dac */
1793 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1794 hpd.hpd = RADEON_HPD_NONE;
1795 radeon_add_legacy_encoder(dev,
1796 radeon_get_encoder_enum(dev,
1797 ATOM_DEVICE_CRT1_SUPPORT,
1798 1),
1799 ATOM_DEVICE_CRT1_SUPPORT);
1800 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1801 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1802 CONNECTOR_OBJECT_ID_VGA,
1803 &hpd);
1804 /* TV - TV DAC */
1805 ddc_i2c.valid = false;
1806 hpd.hpd = RADEON_HPD_NONE;
1807 radeon_add_legacy_encoder(dev,
1808 radeon_get_encoder_enum(dev,
1809 ATOM_DEVICE_TV1_SUPPORT,
1810 2),
1811 ATOM_DEVICE_TV1_SUPPORT);
1812 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1813 DRM_MODE_CONNECTOR_SVIDEO,
1814 &ddc_i2c,
1815 CONNECTOR_OBJECT_ID_SVIDEO,
1816 &hpd);
1817 break;
1818 case CT_MINI_EXTERNAL:
1819 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1820 rdev->mode_info.connector_table);
1821 /* DVI-I - tv dac, ext tmds */
1822 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1823 hpd.hpd = RADEON_HPD_2; /* ??? */
1824 radeon_add_legacy_encoder(dev,
1825 radeon_get_encoder_enum(dev,
1826 ATOM_DEVICE_DFP2_SUPPORT,
1827 0),
1828 ATOM_DEVICE_DFP2_SUPPORT);
1829 radeon_add_legacy_encoder(dev,
1830 radeon_get_encoder_enum(dev,
1831 ATOM_DEVICE_CRT2_SUPPORT,
1832 2),
1833 ATOM_DEVICE_CRT2_SUPPORT);
1834 /* XXX are any DL? */
1835 radeon_add_legacy_connector(dev, 0,
1836 ATOM_DEVICE_DFP2_SUPPORT |
1837 ATOM_DEVICE_CRT2_SUPPORT,
1838 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1839 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1840 &hpd);
1841 /* TV - TV DAC */
1842 ddc_i2c.valid = false;
1843 hpd.hpd = RADEON_HPD_NONE;
1844 radeon_add_legacy_encoder(dev,
1845 radeon_get_encoder_enum(dev,
1846 ATOM_DEVICE_TV1_SUPPORT,
1847 2),
1848 ATOM_DEVICE_TV1_SUPPORT);
1849 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1850 DRM_MODE_CONNECTOR_SVIDEO,
1851 &ddc_i2c,
1852 CONNECTOR_OBJECT_ID_SVIDEO,
1853 &hpd);
1854 break;
1855 case CT_MINI_INTERNAL:
1856 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1857 rdev->mode_info.connector_table);
1858 /* DVI-I - tv dac, int tmds */
1859 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1860 hpd.hpd = RADEON_HPD_1; /* ??? */
1861 radeon_add_legacy_encoder(dev,
1862 radeon_get_encoder_enum(dev,
1863 ATOM_DEVICE_DFP1_SUPPORT,
1864 0),
1865 ATOM_DEVICE_DFP1_SUPPORT);
1866 radeon_add_legacy_encoder(dev,
1867 radeon_get_encoder_enum(dev,
1868 ATOM_DEVICE_CRT2_SUPPORT,
1869 2),
1870 ATOM_DEVICE_CRT2_SUPPORT);
1871 radeon_add_legacy_connector(dev, 0,
1872 ATOM_DEVICE_DFP1_SUPPORT |
1873 ATOM_DEVICE_CRT2_SUPPORT,
1874 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1875 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1876 &hpd);
1877 /* TV - TV DAC */
1878 ddc_i2c.valid = false;
1879 hpd.hpd = RADEON_HPD_NONE;
1880 radeon_add_legacy_encoder(dev,
1881 radeon_get_encoder_enum(dev,
1882 ATOM_DEVICE_TV1_SUPPORT,
1883 2),
1884 ATOM_DEVICE_TV1_SUPPORT);
1885 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1886 DRM_MODE_CONNECTOR_SVIDEO,
1887 &ddc_i2c,
1888 CONNECTOR_OBJECT_ID_SVIDEO,
1889 &hpd);
1890 break;
1891 case CT_IMAC_G5_ISIGHT:
1892 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1893 rdev->mode_info.connector_table);
1894 /* DVI-D - int tmds */
1895 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1896 hpd.hpd = RADEON_HPD_1; /* ??? */
1897 radeon_add_legacy_encoder(dev,
1898 radeon_get_encoder_enum(dev,
1899 ATOM_DEVICE_DFP1_SUPPORT,
1900 0),
1901 ATOM_DEVICE_DFP1_SUPPORT);
1902 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1903 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1904 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1905 &hpd);
1906 /* VGA - tv dac */
1907 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1908 hpd.hpd = RADEON_HPD_NONE;
1909 radeon_add_legacy_encoder(dev,
1910 radeon_get_encoder_enum(dev,
1911 ATOM_DEVICE_CRT2_SUPPORT,
1912 2),
1913 ATOM_DEVICE_CRT2_SUPPORT);
1914 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1915 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1916 CONNECTOR_OBJECT_ID_VGA,
1917 &hpd);
1918 /* TV - TV DAC */
1919 ddc_i2c.valid = false;
1920 hpd.hpd = RADEON_HPD_NONE;
1921 radeon_add_legacy_encoder(dev,
1922 radeon_get_encoder_enum(dev,
1923 ATOM_DEVICE_TV1_SUPPORT,
1924 2),
1925 ATOM_DEVICE_TV1_SUPPORT);
1926 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1927 DRM_MODE_CONNECTOR_SVIDEO,
1928 &ddc_i2c,
1929 CONNECTOR_OBJECT_ID_SVIDEO,
1930 &hpd);
1931 break;
1932 case CT_EMAC:
1933 DRM_INFO("Connector Table: %d (emac)\n",
1934 rdev->mode_info.connector_table);
1935 /* VGA - primary dac */
1936 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1937 hpd.hpd = RADEON_HPD_NONE;
1938 radeon_add_legacy_encoder(dev,
1939 radeon_get_encoder_enum(dev,
1940 ATOM_DEVICE_CRT1_SUPPORT,
1941 1),
1942 ATOM_DEVICE_CRT1_SUPPORT);
1943 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1944 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1945 CONNECTOR_OBJECT_ID_VGA,
1946 &hpd);
1947 /* VGA - tv dac */
1948 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1949 hpd.hpd = RADEON_HPD_NONE;
1950 radeon_add_legacy_encoder(dev,
1951 radeon_get_encoder_enum(dev,
1952 ATOM_DEVICE_CRT2_SUPPORT,
1953 2),
1954 ATOM_DEVICE_CRT2_SUPPORT);
1955 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1956 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1957 CONNECTOR_OBJECT_ID_VGA,
1958 &hpd);
1959 /* TV - TV DAC */
1960 ddc_i2c.valid = false;
1961 hpd.hpd = RADEON_HPD_NONE;
1962 radeon_add_legacy_encoder(dev,
1963 radeon_get_encoder_enum(dev,
1964 ATOM_DEVICE_TV1_SUPPORT,
1965 2),
1966 ATOM_DEVICE_TV1_SUPPORT);
1967 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1968 DRM_MODE_CONNECTOR_SVIDEO,
1969 &ddc_i2c,
1970 CONNECTOR_OBJECT_ID_SVIDEO,
1971 &hpd);
1972 break;
1973 case CT_RN50_POWER:
1974 DRM_INFO("Connector Table: %d (rn50-power)\n",
1975 rdev->mode_info.connector_table);
1976 /* VGA - primary dac */
1977 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1978 hpd.hpd = RADEON_HPD_NONE;
1979 radeon_add_legacy_encoder(dev,
1980 radeon_get_encoder_enum(dev,
1981 ATOM_DEVICE_CRT1_SUPPORT,
1982 1),
1983 ATOM_DEVICE_CRT1_SUPPORT);
1984 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1985 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1986 CONNECTOR_OBJECT_ID_VGA,
1987 &hpd);
1988 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1989 hpd.hpd = RADEON_HPD_NONE;
1990 radeon_add_legacy_encoder(dev,
1991 radeon_get_encoder_enum(dev,
1992 ATOM_DEVICE_CRT2_SUPPORT,
1993 2),
1994 ATOM_DEVICE_CRT2_SUPPORT);
1995 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1996 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1997 CONNECTOR_OBJECT_ID_VGA,
1998 &hpd);
1999 break;
2000 case CT_MAC_X800:
2001 DRM_INFO("Connector Table: %d (mac x800)\n",
2002 rdev->mode_info.connector_table);
2003 /* DVI - primary dac, internal tmds */
2004 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2005 hpd.hpd = RADEON_HPD_1; /* ??? */
2006 radeon_add_legacy_encoder(dev,
2007 radeon_get_encoder_enum(dev,
2008 ATOM_DEVICE_DFP1_SUPPORT,
2009 0),
2010 ATOM_DEVICE_DFP1_SUPPORT);
2011 radeon_add_legacy_encoder(dev,
2012 radeon_get_encoder_enum(dev,
2013 ATOM_DEVICE_CRT1_SUPPORT,
2014 1),
2015 ATOM_DEVICE_CRT1_SUPPORT);
2016 radeon_add_legacy_connector(dev, 0,
2017 ATOM_DEVICE_DFP1_SUPPORT |
2018 ATOM_DEVICE_CRT1_SUPPORT,
2019 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2020 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2021 &hpd);
2022 /* DVI - tv dac, dvo */
2023 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2024 hpd.hpd = RADEON_HPD_2; /* ??? */
2025 radeon_add_legacy_encoder(dev,
2026 radeon_get_encoder_enum(dev,
2027 ATOM_DEVICE_DFP2_SUPPORT,
2028 0),
2029 ATOM_DEVICE_DFP2_SUPPORT);
2030 radeon_add_legacy_encoder(dev,
2031 radeon_get_encoder_enum(dev,
2032 ATOM_DEVICE_CRT2_SUPPORT,
2033 2),
2034 ATOM_DEVICE_CRT2_SUPPORT);
2035 radeon_add_legacy_connector(dev, 1,
2036 ATOM_DEVICE_DFP2_SUPPORT |
2037 ATOM_DEVICE_CRT2_SUPPORT,
2038 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2039 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2040 &hpd);
2041 break;
2042 case CT_MAC_G5_9600:
2043 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2044 rdev->mode_info.connector_table);
2045 /* DVI - tv dac, dvo */
2046 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2047 hpd.hpd = RADEON_HPD_1; /* ??? */
2048 radeon_add_legacy_encoder(dev,
2049 radeon_get_encoder_enum(dev,
2050 ATOM_DEVICE_DFP2_SUPPORT,
2051 0),
2052 ATOM_DEVICE_DFP2_SUPPORT);
2053 radeon_add_legacy_encoder(dev,
2054 radeon_get_encoder_enum(dev,
2055 ATOM_DEVICE_CRT2_SUPPORT,
2056 2),
2057 ATOM_DEVICE_CRT2_SUPPORT);
2058 radeon_add_legacy_connector(dev, 0,
2059 ATOM_DEVICE_DFP2_SUPPORT |
2060 ATOM_DEVICE_CRT2_SUPPORT,
2061 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2062 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2063 &hpd);
2064 /* ADC - primary dac, internal tmds */
2065 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2066 hpd.hpd = RADEON_HPD_2; /* ??? */
2067 radeon_add_legacy_encoder(dev,
2068 radeon_get_encoder_enum(dev,
2069 ATOM_DEVICE_DFP1_SUPPORT,
2070 0),
2071 ATOM_DEVICE_DFP1_SUPPORT);
2072 radeon_add_legacy_encoder(dev,
2073 radeon_get_encoder_enum(dev,
2074 ATOM_DEVICE_CRT1_SUPPORT,
2075 1),
2076 ATOM_DEVICE_CRT1_SUPPORT);
2077 radeon_add_legacy_connector(dev, 1,
2078 ATOM_DEVICE_DFP1_SUPPORT |
2079 ATOM_DEVICE_CRT1_SUPPORT,
2080 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2081 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2082 &hpd);
2083 /* TV - TV DAC */
2084 ddc_i2c.valid = false;
2085 hpd.hpd = RADEON_HPD_NONE;
2086 radeon_add_legacy_encoder(dev,
2087 radeon_get_encoder_enum(dev,
2088 ATOM_DEVICE_TV1_SUPPORT,
2089 2),
2090 ATOM_DEVICE_TV1_SUPPORT);
2091 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2092 DRM_MODE_CONNECTOR_SVIDEO,
2093 &ddc_i2c,
2094 CONNECTOR_OBJECT_ID_SVIDEO,
2095 &hpd);
2096 break;
2097 case CT_SAM440EP:
2098 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2099 rdev->mode_info.connector_table);
2100 /* LVDS */
2101 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2102 hpd.hpd = RADEON_HPD_NONE;
2103 radeon_add_legacy_encoder(dev,
2104 radeon_get_encoder_enum(dev,
2105 ATOM_DEVICE_LCD1_SUPPORT,
2106 0),
2107 ATOM_DEVICE_LCD1_SUPPORT);
2108 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2109 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2110 CONNECTOR_OBJECT_ID_LVDS,
2111 &hpd);
2112 /* DVI-I - secondary dac, int tmds */
2113 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2114 hpd.hpd = RADEON_HPD_1; /* ??? */
2115 radeon_add_legacy_encoder(dev,
2116 radeon_get_encoder_enum(dev,
2117 ATOM_DEVICE_DFP1_SUPPORT,
2118 0),
2119 ATOM_DEVICE_DFP1_SUPPORT);
2120 radeon_add_legacy_encoder(dev,
2121 radeon_get_encoder_enum(dev,
2122 ATOM_DEVICE_CRT2_SUPPORT,
2123 2),
2124 ATOM_DEVICE_CRT2_SUPPORT);
2125 radeon_add_legacy_connector(dev, 1,
2126 ATOM_DEVICE_DFP1_SUPPORT |
2127 ATOM_DEVICE_CRT2_SUPPORT,
2128 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2129 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2130 &hpd);
2131 /* VGA - primary dac */
2132 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2133 hpd.hpd = RADEON_HPD_NONE;
2134 radeon_add_legacy_encoder(dev,
2135 radeon_get_encoder_enum(dev,
2136 ATOM_DEVICE_CRT1_SUPPORT,
2137 1),
2138 ATOM_DEVICE_CRT1_SUPPORT);
2139 radeon_add_legacy_connector(dev, 2,
2140 ATOM_DEVICE_CRT1_SUPPORT,
2141 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2142 CONNECTOR_OBJECT_ID_VGA,
2143 &hpd);
2144 /* TV - TV DAC */
2145 ddc_i2c.valid = false;
2146 hpd.hpd = RADEON_HPD_NONE;
2147 radeon_add_legacy_encoder(dev,
2148 radeon_get_encoder_enum(dev,
2149 ATOM_DEVICE_TV1_SUPPORT,
2150 2),
2151 ATOM_DEVICE_TV1_SUPPORT);
2152 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2153 DRM_MODE_CONNECTOR_SVIDEO,
2154 &ddc_i2c,
2155 CONNECTOR_OBJECT_ID_SVIDEO,
2156 &hpd);
2157 break;
2158 case CT_MAC_G4_SILVER:
2159 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2160 rdev->mode_info.connector_table);
2161 /* DVI-I - tv dac, int tmds */
2162 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2163 hpd.hpd = RADEON_HPD_1; /* ??? */
2164 radeon_add_legacy_encoder(dev,
2165 radeon_get_encoder_enum(dev,
2166 ATOM_DEVICE_DFP1_SUPPORT,
2167 0),
2168 ATOM_DEVICE_DFP1_SUPPORT);
2169 radeon_add_legacy_encoder(dev,
2170 radeon_get_encoder_enum(dev,
2171 ATOM_DEVICE_CRT2_SUPPORT,
2172 2),
2173 ATOM_DEVICE_CRT2_SUPPORT);
2174 radeon_add_legacy_connector(dev, 0,
2175 ATOM_DEVICE_DFP1_SUPPORT |
2176 ATOM_DEVICE_CRT2_SUPPORT,
2177 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2178 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2179 &hpd);
2180 /* VGA - primary dac */
2181 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2182 hpd.hpd = RADEON_HPD_NONE;
2183 radeon_add_legacy_encoder(dev,
2184 radeon_get_encoder_enum(dev,
2185 ATOM_DEVICE_CRT1_SUPPORT,
2186 1),
2187 ATOM_DEVICE_CRT1_SUPPORT);
2188 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2189 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2190 CONNECTOR_OBJECT_ID_VGA,
2191 &hpd);
2192 /* TV - TV DAC */
2193 ddc_i2c.valid = false;
2194 hpd.hpd = RADEON_HPD_NONE;
2195 radeon_add_legacy_encoder(dev,
2196 radeon_get_encoder_enum(dev,
2197 ATOM_DEVICE_TV1_SUPPORT,
2198 2),
2199 ATOM_DEVICE_TV1_SUPPORT);
2200 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2201 DRM_MODE_CONNECTOR_SVIDEO,
2202 &ddc_i2c,
2203 CONNECTOR_OBJECT_ID_SVIDEO,
2204 &hpd);
2205 break;
2206 default:
2207 DRM_INFO("Connector table: %d (invalid)\n",
2208 rdev->mode_info.connector_table);
2209 return false;
2210 }
2211
2212 radeon_link_encoder_connector(dev);
2213
2214 return true;
2215 }
2216
radeon_apply_legacy_quirks(struct drm_device * dev,int bios_index,enum radeon_combios_connector * legacy_connector,struct radeon_i2c_bus_rec * ddc_i2c,struct radeon_hpd * hpd)2217 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2218 int bios_index,
2219 enum radeon_combios_connector
2220 *legacy_connector,
2221 struct radeon_i2c_bus_rec *ddc_i2c,
2222 struct radeon_hpd *hpd)
2223 {
2224
2225 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2226 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2227 if (dev->pdev->device == 0x515e &&
2228 dev->pdev->subsystem_vendor == 0x1014) {
2229 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2230 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2231 return false;
2232 }
2233
2234 /* X300 card with extra non-existent DVI port */
2235 if (dev->pdev->device == 0x5B60 &&
2236 dev->pdev->subsystem_vendor == 0x17af &&
2237 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2238 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2239 return false;
2240 }
2241
2242 return true;
2243 }
2244
radeon_apply_legacy_tv_quirks(struct drm_device * dev)2245 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2246 {
2247 /* Acer 5102 has non-existent TV port */
2248 if (dev->pdev->device == 0x5975 &&
2249 dev->pdev->subsystem_vendor == 0x1025 &&
2250 dev->pdev->subsystem_device == 0x009f)
2251 return false;
2252
2253 /* HP dc5750 has non-existent TV port */
2254 if (dev->pdev->device == 0x5974 &&
2255 dev->pdev->subsystem_vendor == 0x103c &&
2256 dev->pdev->subsystem_device == 0x280a)
2257 return false;
2258
2259 /* MSI S270 has non-existent TV port */
2260 if (dev->pdev->device == 0x5955 &&
2261 dev->pdev->subsystem_vendor == 0x1462 &&
2262 dev->pdev->subsystem_device == 0x0131)
2263 return false;
2264
2265 return true;
2266 }
2267
combios_check_dl_dvi(struct drm_device * dev,int is_dvi_d)2268 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2269 {
2270 struct radeon_device *rdev = dev->dev_private;
2271 uint32_t ext_tmds_info;
2272
2273 if (rdev->flags & RADEON_IS_IGP) {
2274 if (is_dvi_d)
2275 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2276 else
2277 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2278 }
2279 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2280 if (ext_tmds_info) {
2281 uint8_t rev = RBIOS8(ext_tmds_info);
2282 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2283 if (rev >= 3) {
2284 if (is_dvi_d)
2285 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2286 else
2287 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2288 } else {
2289 if (flags & 1) {
2290 if (is_dvi_d)
2291 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2292 else
2293 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2294 }
2295 }
2296 }
2297 if (is_dvi_d)
2298 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2299 else
2300 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2301 }
2302
radeon_get_legacy_connector_info_from_bios(struct drm_device * dev)2303 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2304 {
2305 struct radeon_device *rdev = dev->dev_private;
2306 uint32_t conn_info, entry, devices;
2307 uint16_t tmp, connector_object_id;
2308 enum radeon_combios_ddc ddc_type;
2309 enum radeon_combios_connector connector;
2310 int i = 0;
2311 struct radeon_i2c_bus_rec ddc_i2c;
2312 struct radeon_hpd hpd;
2313
2314 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2315 if (conn_info) {
2316 for (i = 0; i < 4; i++) {
2317 entry = conn_info + 2 + i * 2;
2318
2319 if (!RBIOS16(entry))
2320 break;
2321
2322 tmp = RBIOS16(entry);
2323
2324 connector = (tmp >> 12) & 0xf;
2325
2326 ddc_type = (tmp >> 8) & 0xf;
2327 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2328
2329 switch (connector) {
2330 case CONNECTOR_PROPRIETARY_LEGACY:
2331 case CONNECTOR_DVI_I_LEGACY:
2332 case CONNECTOR_DVI_D_LEGACY:
2333 if ((tmp >> 4) & 0x1)
2334 hpd.hpd = RADEON_HPD_2;
2335 else
2336 hpd.hpd = RADEON_HPD_1;
2337 break;
2338 default:
2339 hpd.hpd = RADEON_HPD_NONE;
2340 break;
2341 }
2342
2343 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2344 &ddc_i2c, &hpd))
2345 continue;
2346
2347 switch (connector) {
2348 case CONNECTOR_PROPRIETARY_LEGACY:
2349 if ((tmp >> 4) & 0x1)
2350 devices = ATOM_DEVICE_DFP2_SUPPORT;
2351 else
2352 devices = ATOM_DEVICE_DFP1_SUPPORT;
2353 radeon_add_legacy_encoder(dev,
2354 radeon_get_encoder_enum
2355 (dev, devices, 0),
2356 devices);
2357 radeon_add_legacy_connector(dev, i, devices,
2358 legacy_connector_convert
2359 [connector],
2360 &ddc_i2c,
2361 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2362 &hpd);
2363 break;
2364 case CONNECTOR_CRT_LEGACY:
2365 if (tmp & 0x1) {
2366 devices = ATOM_DEVICE_CRT2_SUPPORT;
2367 radeon_add_legacy_encoder(dev,
2368 radeon_get_encoder_enum
2369 (dev,
2370 ATOM_DEVICE_CRT2_SUPPORT,
2371 2),
2372 ATOM_DEVICE_CRT2_SUPPORT);
2373 } else {
2374 devices = ATOM_DEVICE_CRT1_SUPPORT;
2375 radeon_add_legacy_encoder(dev,
2376 radeon_get_encoder_enum
2377 (dev,
2378 ATOM_DEVICE_CRT1_SUPPORT,
2379 1),
2380 ATOM_DEVICE_CRT1_SUPPORT);
2381 }
2382 radeon_add_legacy_connector(dev,
2383 i,
2384 devices,
2385 legacy_connector_convert
2386 [connector],
2387 &ddc_i2c,
2388 CONNECTOR_OBJECT_ID_VGA,
2389 &hpd);
2390 break;
2391 case CONNECTOR_DVI_I_LEGACY:
2392 devices = 0;
2393 if (tmp & 0x1) {
2394 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2395 radeon_add_legacy_encoder(dev,
2396 radeon_get_encoder_enum
2397 (dev,
2398 ATOM_DEVICE_CRT2_SUPPORT,
2399 2),
2400 ATOM_DEVICE_CRT2_SUPPORT);
2401 } else {
2402 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2403 radeon_add_legacy_encoder(dev,
2404 radeon_get_encoder_enum
2405 (dev,
2406 ATOM_DEVICE_CRT1_SUPPORT,
2407 1),
2408 ATOM_DEVICE_CRT1_SUPPORT);
2409 }
2410 /* RV100 board with external TDMS bit mis-set.
2411 * Actually uses internal TMDS, clear the bit.
2412 */
2413 if (dev->pdev->device == 0x5159 &&
2414 dev->pdev->subsystem_vendor == 0x1014 &&
2415 dev->pdev->subsystem_device == 0x029A) {
2416 tmp &= ~(1 << 4);
2417 }
2418 if ((tmp >> 4) & 0x1) {
2419 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2420 radeon_add_legacy_encoder(dev,
2421 radeon_get_encoder_enum
2422 (dev,
2423 ATOM_DEVICE_DFP2_SUPPORT,
2424 0),
2425 ATOM_DEVICE_DFP2_SUPPORT);
2426 connector_object_id = combios_check_dl_dvi(dev, 0);
2427 } else {
2428 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2429 radeon_add_legacy_encoder(dev,
2430 radeon_get_encoder_enum
2431 (dev,
2432 ATOM_DEVICE_DFP1_SUPPORT,
2433 0),
2434 ATOM_DEVICE_DFP1_SUPPORT);
2435 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2436 }
2437 radeon_add_legacy_connector(dev,
2438 i,
2439 devices,
2440 legacy_connector_convert
2441 [connector],
2442 &ddc_i2c,
2443 connector_object_id,
2444 &hpd);
2445 break;
2446 case CONNECTOR_DVI_D_LEGACY:
2447 if ((tmp >> 4) & 0x1) {
2448 devices = ATOM_DEVICE_DFP2_SUPPORT;
2449 connector_object_id = combios_check_dl_dvi(dev, 1);
2450 } else {
2451 devices = ATOM_DEVICE_DFP1_SUPPORT;
2452 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2453 }
2454 radeon_add_legacy_encoder(dev,
2455 radeon_get_encoder_enum
2456 (dev, devices, 0),
2457 devices);
2458 radeon_add_legacy_connector(dev, i, devices,
2459 legacy_connector_convert
2460 [connector],
2461 &ddc_i2c,
2462 connector_object_id,
2463 &hpd);
2464 break;
2465 case CONNECTOR_CTV_LEGACY:
2466 case CONNECTOR_STV_LEGACY:
2467 radeon_add_legacy_encoder(dev,
2468 radeon_get_encoder_enum
2469 (dev,
2470 ATOM_DEVICE_TV1_SUPPORT,
2471 2),
2472 ATOM_DEVICE_TV1_SUPPORT);
2473 radeon_add_legacy_connector(dev, i,
2474 ATOM_DEVICE_TV1_SUPPORT,
2475 legacy_connector_convert
2476 [connector],
2477 &ddc_i2c,
2478 CONNECTOR_OBJECT_ID_SVIDEO,
2479 &hpd);
2480 break;
2481 default:
2482 DRM_ERROR("Unknown connector type: %d\n",
2483 connector);
2484 continue;
2485 }
2486
2487 }
2488 } else {
2489 uint16_t tmds_info =
2490 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2491 if (tmds_info) {
2492 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2493
2494 radeon_add_legacy_encoder(dev,
2495 radeon_get_encoder_enum(dev,
2496 ATOM_DEVICE_CRT1_SUPPORT,
2497 1),
2498 ATOM_DEVICE_CRT1_SUPPORT);
2499 radeon_add_legacy_encoder(dev,
2500 radeon_get_encoder_enum(dev,
2501 ATOM_DEVICE_DFP1_SUPPORT,
2502 0),
2503 ATOM_DEVICE_DFP1_SUPPORT);
2504
2505 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2506 hpd.hpd = RADEON_HPD_1;
2507 radeon_add_legacy_connector(dev,
2508 0,
2509 ATOM_DEVICE_CRT1_SUPPORT |
2510 ATOM_DEVICE_DFP1_SUPPORT,
2511 DRM_MODE_CONNECTOR_DVII,
2512 &ddc_i2c,
2513 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2514 &hpd);
2515 } else {
2516 uint16_t crt_info =
2517 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2518 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2519 if (crt_info) {
2520 radeon_add_legacy_encoder(dev,
2521 radeon_get_encoder_enum(dev,
2522 ATOM_DEVICE_CRT1_SUPPORT,
2523 1),
2524 ATOM_DEVICE_CRT1_SUPPORT);
2525 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2526 hpd.hpd = RADEON_HPD_NONE;
2527 radeon_add_legacy_connector(dev,
2528 0,
2529 ATOM_DEVICE_CRT1_SUPPORT,
2530 DRM_MODE_CONNECTOR_VGA,
2531 &ddc_i2c,
2532 CONNECTOR_OBJECT_ID_VGA,
2533 &hpd);
2534 } else {
2535 DRM_DEBUG_KMS("No connector info found\n");
2536 return false;
2537 }
2538 }
2539 }
2540
2541 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2542 uint16_t lcd_info =
2543 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2544 if (lcd_info) {
2545 uint16_t lcd_ddc_info =
2546 combios_get_table_offset(dev,
2547 COMBIOS_LCD_DDC_INFO_TABLE);
2548
2549 radeon_add_legacy_encoder(dev,
2550 radeon_get_encoder_enum(dev,
2551 ATOM_DEVICE_LCD1_SUPPORT,
2552 0),
2553 ATOM_DEVICE_LCD1_SUPPORT);
2554
2555 if (lcd_ddc_info) {
2556 ddc_type = RBIOS8(lcd_ddc_info + 2);
2557 switch (ddc_type) {
2558 case DDC_LCD:
2559 ddc_i2c =
2560 combios_setup_i2c_bus(rdev,
2561 DDC_LCD,
2562 RBIOS32(lcd_ddc_info + 3),
2563 RBIOS32(lcd_ddc_info + 7));
2564 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2565 break;
2566 case DDC_GPIO:
2567 ddc_i2c =
2568 combios_setup_i2c_bus(rdev,
2569 DDC_GPIO,
2570 RBIOS32(lcd_ddc_info + 3),
2571 RBIOS32(lcd_ddc_info + 7));
2572 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2573 break;
2574 default:
2575 ddc_i2c =
2576 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2577 break;
2578 }
2579 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2580 } else
2581 ddc_i2c.valid = false;
2582
2583 hpd.hpd = RADEON_HPD_NONE;
2584 radeon_add_legacy_connector(dev,
2585 5,
2586 ATOM_DEVICE_LCD1_SUPPORT,
2587 DRM_MODE_CONNECTOR_LVDS,
2588 &ddc_i2c,
2589 CONNECTOR_OBJECT_ID_LVDS,
2590 &hpd);
2591 }
2592 }
2593
2594 /* check TV table */
2595 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2596 uint32_t tv_info =
2597 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2598 if (tv_info) {
2599 if (RBIOS8(tv_info + 6) == 'T') {
2600 if (radeon_apply_legacy_tv_quirks(dev)) {
2601 hpd.hpd = RADEON_HPD_NONE;
2602 ddc_i2c.valid = false;
2603 radeon_add_legacy_encoder(dev,
2604 radeon_get_encoder_enum
2605 (dev,
2606 ATOM_DEVICE_TV1_SUPPORT,
2607 2),
2608 ATOM_DEVICE_TV1_SUPPORT);
2609 radeon_add_legacy_connector(dev, 6,
2610 ATOM_DEVICE_TV1_SUPPORT,
2611 DRM_MODE_CONNECTOR_SVIDEO,
2612 &ddc_i2c,
2613 CONNECTOR_OBJECT_ID_SVIDEO,
2614 &hpd);
2615 }
2616 }
2617 }
2618 }
2619
2620 radeon_link_encoder_connector(dev);
2621
2622 return true;
2623 }
2624
2625 static const char *thermal_controller_names[] = {
2626 "NONE",
2627 "lm63",
2628 "adm1032",
2629 };
2630
radeon_combios_get_power_modes(struct radeon_device * rdev)2631 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2632 {
2633 struct drm_device *dev = rdev->ddev;
2634 u16 offset, misc, misc2 = 0;
2635 u8 rev, blocks, tmp;
2636 int state_index = 0;
2637 struct radeon_i2c_bus_rec i2c_bus;
2638
2639 rdev->pm.default_power_state_index = -1;
2640
2641 /* allocate 2 power states */
2642 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2643 if (rdev->pm.power_state) {
2644 /* allocate 1 clock mode per state */
2645 rdev->pm.power_state[0].clock_info =
2646 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2647 rdev->pm.power_state[1].clock_info =
2648 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2649 if (!rdev->pm.power_state[0].clock_info ||
2650 !rdev->pm.power_state[1].clock_info)
2651 goto pm_failed;
2652 } else
2653 goto pm_failed;
2654
2655 /* check for a thermal chip */
2656 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2657 if (offset) {
2658 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2659
2660 rev = RBIOS8(offset);
2661
2662 if (rev == 0) {
2663 thermal_controller = RBIOS8(offset + 3);
2664 gpio = RBIOS8(offset + 4) & 0x3f;
2665 i2c_addr = RBIOS8(offset + 5);
2666 } else if (rev == 1) {
2667 thermal_controller = RBIOS8(offset + 4);
2668 gpio = RBIOS8(offset + 5) & 0x3f;
2669 i2c_addr = RBIOS8(offset + 6);
2670 } else if (rev == 2) {
2671 thermal_controller = RBIOS8(offset + 4);
2672 gpio = RBIOS8(offset + 5) & 0x3f;
2673 i2c_addr = RBIOS8(offset + 6);
2674 clk_bit = RBIOS8(offset + 0xa);
2675 data_bit = RBIOS8(offset + 0xb);
2676 }
2677 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2678 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2679 thermal_controller_names[thermal_controller],
2680 i2c_addr >> 1);
2681 if (gpio == DDC_LCD) {
2682 /* MM i2c */
2683 i2c_bus.valid = true;
2684 i2c_bus.hw_capable = true;
2685 i2c_bus.mm_i2c = true;
2686 i2c_bus.i2c_id = 0xa0;
2687 } else if (gpio == DDC_GPIO)
2688 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2689 else
2690 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2691 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2692 if (rdev->pm.i2c_bus) {
2693 struct i2c_board_info info = { };
2694 const char *name = thermal_controller_names[thermal_controller];
2695 info.addr = i2c_addr >> 1;
2696 strlcpy(info.type, name, sizeof(info.type));
2697 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2698 }
2699 }
2700 } else {
2701 /* boards with a thermal chip, but no overdrive table */
2702
2703 /* Asus 9600xt has an f75375 on the monid bus */
2704 if ((dev->pdev->device == 0x4152) &&
2705 (dev->pdev->subsystem_vendor == 0x1043) &&
2706 (dev->pdev->subsystem_device == 0xc002)) {
2707 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2708 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2709 if (rdev->pm.i2c_bus) {
2710 struct i2c_board_info info = { };
2711 const char *name = "f75375";
2712 info.addr = 0x28;
2713 strlcpy(info.type, name, sizeof(info.type));
2714 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2715 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2716 name, info.addr);
2717 }
2718 }
2719 }
2720
2721 if (rdev->flags & RADEON_IS_MOBILITY) {
2722 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2723 if (offset) {
2724 rev = RBIOS8(offset);
2725 blocks = RBIOS8(offset + 0x2);
2726 /* power mode 0 tends to be the only valid one */
2727 rdev->pm.power_state[state_index].num_clock_modes = 1;
2728 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2729 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2730 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2731 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2732 goto default_mode;
2733 rdev->pm.power_state[state_index].type =
2734 POWER_STATE_TYPE_BATTERY;
2735 misc = RBIOS16(offset + 0x5 + 0x0);
2736 if (rev > 4)
2737 misc2 = RBIOS16(offset + 0x5 + 0xe);
2738 rdev->pm.power_state[state_index].misc = misc;
2739 rdev->pm.power_state[state_index].misc2 = misc2;
2740 if (misc & 0x4) {
2741 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2742 if (misc & 0x8)
2743 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2744 true;
2745 else
2746 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2747 false;
2748 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2749 if (rev < 6) {
2750 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2751 RBIOS16(offset + 0x5 + 0xb) * 4;
2752 tmp = RBIOS8(offset + 0x5 + 0xd);
2753 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2754 } else {
2755 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2756 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2757 if (entries && voltage_table_offset) {
2758 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2759 RBIOS16(voltage_table_offset) * 4;
2760 tmp = RBIOS8(voltage_table_offset + 0x2);
2761 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2762 } else
2763 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2764 }
2765 switch ((misc2 & 0x700) >> 8) {
2766 case 0:
2767 default:
2768 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2769 break;
2770 case 1:
2771 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2772 break;
2773 case 2:
2774 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2775 break;
2776 case 3:
2777 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2778 break;
2779 case 4:
2780 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2781 break;
2782 }
2783 } else
2784 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2785 if (rev > 6)
2786 rdev->pm.power_state[state_index].pcie_lanes =
2787 RBIOS8(offset + 0x5 + 0x10);
2788 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2789 state_index++;
2790 } else {
2791 /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2792 }
2793 } else {
2794 /* XXX figure out some good default low power mode for desktop cards */
2795 }
2796
2797 default_mode:
2798 /* add the default mode */
2799 rdev->pm.power_state[state_index].type =
2800 POWER_STATE_TYPE_DEFAULT;
2801 rdev->pm.power_state[state_index].num_clock_modes = 1;
2802 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2803 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2804 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2805 if ((state_index > 0) &&
2806 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2807 rdev->pm.power_state[state_index].clock_info[0].voltage =
2808 rdev->pm.power_state[0].clock_info[0].voltage;
2809 else
2810 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2811 rdev->pm.power_state[state_index].pcie_lanes = 16;
2812 rdev->pm.power_state[state_index].flags = 0;
2813 rdev->pm.default_power_state_index = state_index;
2814 rdev->pm.num_power_states = state_index + 1;
2815
2816 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2817 rdev->pm.current_clock_mode_index = 0;
2818 return;
2819
2820 pm_failed:
2821 rdev->pm.default_power_state_index = state_index;
2822 rdev->pm.num_power_states = 0;
2823
2824 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2825 rdev->pm.current_clock_mode_index = 0;
2826 }
2827
radeon_external_tmds_setup(struct drm_encoder * encoder)2828 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2829 {
2830 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2831 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2832
2833 if (!tmds)
2834 return;
2835
2836 switch (tmds->dvo_chip) {
2837 case DVO_SIL164:
2838 /* sil 164 */
2839 radeon_i2c_put_byte(tmds->i2c_bus,
2840 tmds->slave_addr,
2841 0x08, 0x30);
2842 radeon_i2c_put_byte(tmds->i2c_bus,
2843 tmds->slave_addr,
2844 0x09, 0x00);
2845 radeon_i2c_put_byte(tmds->i2c_bus,
2846 tmds->slave_addr,
2847 0x0a, 0x90);
2848 radeon_i2c_put_byte(tmds->i2c_bus,
2849 tmds->slave_addr,
2850 0x0c, 0x89);
2851 radeon_i2c_put_byte(tmds->i2c_bus,
2852 tmds->slave_addr,
2853 0x08, 0x3b);
2854 break;
2855 case DVO_SIL1178:
2856 /* sil 1178 - untested */
2857 /*
2858 * 0x0f, 0x44
2859 * 0x0f, 0x4c
2860 * 0x0e, 0x01
2861 * 0x0a, 0x80
2862 * 0x09, 0x30
2863 * 0x0c, 0xc9
2864 * 0x0d, 0x70
2865 * 0x08, 0x32
2866 * 0x08, 0x33
2867 */
2868 break;
2869 default:
2870 break;
2871 }
2872
2873 }
2874
radeon_combios_external_tmds_setup(struct drm_encoder * encoder)2875 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2876 {
2877 struct drm_device *dev = encoder->dev;
2878 struct radeon_device *rdev = dev->dev_private;
2879 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2880 uint16_t offset;
2881 uint8_t blocks, slave_addr, rev;
2882 uint32_t index, id;
2883 uint32_t reg, val, and_mask, or_mask;
2884 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2885
2886 if (!tmds)
2887 return false;
2888
2889 if (rdev->flags & RADEON_IS_IGP) {
2890 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2891 rev = RBIOS8(offset);
2892 if (offset) {
2893 rev = RBIOS8(offset);
2894 if (rev > 1) {
2895 blocks = RBIOS8(offset + 3);
2896 index = offset + 4;
2897 while (blocks > 0) {
2898 id = RBIOS16(index);
2899 index += 2;
2900 switch (id >> 13) {
2901 case 0:
2902 reg = (id & 0x1fff) * 4;
2903 val = RBIOS32(index);
2904 index += 4;
2905 WREG32(reg, val);
2906 break;
2907 case 2:
2908 reg = (id & 0x1fff) * 4;
2909 and_mask = RBIOS32(index);
2910 index += 4;
2911 or_mask = RBIOS32(index);
2912 index += 4;
2913 val = RREG32(reg);
2914 val = (val & and_mask) | or_mask;
2915 WREG32(reg, val);
2916 break;
2917 case 3:
2918 val = RBIOS16(index);
2919 index += 2;
2920 udelay(val);
2921 break;
2922 case 4:
2923 val = RBIOS16(index);
2924 index += 2;
2925 mdelay(val);
2926 break;
2927 case 6:
2928 slave_addr = id & 0xff;
2929 slave_addr >>= 1; /* 7 bit addressing */
2930 index++;
2931 reg = RBIOS8(index);
2932 index++;
2933 val = RBIOS8(index);
2934 index++;
2935 radeon_i2c_put_byte(tmds->i2c_bus,
2936 slave_addr,
2937 reg, val);
2938 break;
2939 default:
2940 DRM_ERROR("Unknown id %d\n", id >> 13);
2941 break;
2942 }
2943 blocks--;
2944 }
2945 return true;
2946 }
2947 }
2948 } else {
2949 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2950 if (offset) {
2951 index = offset + 10;
2952 id = RBIOS16(index);
2953 while (id != 0xffff) {
2954 index += 2;
2955 switch (id >> 13) {
2956 case 0:
2957 reg = (id & 0x1fff) * 4;
2958 val = RBIOS32(index);
2959 WREG32(reg, val);
2960 break;
2961 case 2:
2962 reg = (id & 0x1fff) * 4;
2963 and_mask = RBIOS32(index);
2964 index += 4;
2965 or_mask = RBIOS32(index);
2966 index += 4;
2967 val = RREG32(reg);
2968 val = (val & and_mask) | or_mask;
2969 WREG32(reg, val);
2970 break;
2971 case 4:
2972 val = RBIOS16(index);
2973 index += 2;
2974 udelay(val);
2975 break;
2976 case 5:
2977 reg = id & 0x1fff;
2978 and_mask = RBIOS32(index);
2979 index += 4;
2980 or_mask = RBIOS32(index);
2981 index += 4;
2982 val = RREG32_PLL(reg);
2983 val = (val & and_mask) | or_mask;
2984 WREG32_PLL(reg, val);
2985 break;
2986 case 6:
2987 reg = id & 0x1fff;
2988 val = RBIOS8(index);
2989 index += 1;
2990 radeon_i2c_put_byte(tmds->i2c_bus,
2991 tmds->slave_addr,
2992 reg, val);
2993 break;
2994 default:
2995 DRM_ERROR("Unknown id %d\n", id >> 13);
2996 break;
2997 }
2998 id = RBIOS16(index);
2999 }
3000 return true;
3001 }
3002 }
3003 return false;
3004 }
3005
combios_parse_mmio_table(struct drm_device * dev,uint16_t offset)3006 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3007 {
3008 struct radeon_device *rdev = dev->dev_private;
3009
3010 if (offset) {
3011 while (RBIOS16(offset)) {
3012 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3013 uint32_t addr = (RBIOS16(offset) & 0x1fff);
3014 uint32_t val, and_mask, or_mask;
3015 uint32_t tmp;
3016
3017 offset += 2;
3018 switch (cmd) {
3019 case 0:
3020 val = RBIOS32(offset);
3021 offset += 4;
3022 WREG32(addr, val);
3023 break;
3024 case 1:
3025 val = RBIOS32(offset);
3026 offset += 4;
3027 WREG32(addr, val);
3028 break;
3029 case 2:
3030 and_mask = RBIOS32(offset);
3031 offset += 4;
3032 or_mask = RBIOS32(offset);
3033 offset += 4;
3034 tmp = RREG32(addr);
3035 tmp &= and_mask;
3036 tmp |= or_mask;
3037 WREG32(addr, tmp);
3038 break;
3039 case 3:
3040 and_mask = RBIOS32(offset);
3041 offset += 4;
3042 or_mask = RBIOS32(offset);
3043 offset += 4;
3044 tmp = RREG32(addr);
3045 tmp &= and_mask;
3046 tmp |= or_mask;
3047 WREG32(addr, tmp);
3048 break;
3049 case 4:
3050 val = RBIOS16(offset);
3051 offset += 2;
3052 udelay(val);
3053 break;
3054 case 5:
3055 val = RBIOS16(offset);
3056 offset += 2;
3057 switch (addr) {
3058 case 8:
3059 while (val--) {
3060 if (!
3061 (RREG32_PLL
3062 (RADEON_CLK_PWRMGT_CNTL) &
3063 RADEON_MC_BUSY))
3064 break;
3065 }
3066 break;
3067 case 9:
3068 while (val--) {
3069 if ((RREG32(RADEON_MC_STATUS) &
3070 RADEON_MC_IDLE))
3071 break;
3072 }
3073 break;
3074 default:
3075 break;
3076 }
3077 break;
3078 default:
3079 break;
3080 }
3081 }
3082 }
3083 }
3084
combios_parse_pll_table(struct drm_device * dev,uint16_t offset)3085 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3086 {
3087 struct radeon_device *rdev = dev->dev_private;
3088
3089 if (offset) {
3090 while (RBIOS8(offset)) {
3091 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3092 uint8_t addr = (RBIOS8(offset) & 0x3f);
3093 uint32_t val, shift, tmp;
3094 uint32_t and_mask, or_mask;
3095
3096 offset++;
3097 switch (cmd) {
3098 case 0:
3099 val = RBIOS32(offset);
3100 offset += 4;
3101 WREG32_PLL(addr, val);
3102 break;
3103 case 1:
3104 shift = RBIOS8(offset) * 8;
3105 offset++;
3106 and_mask = RBIOS8(offset) << shift;
3107 and_mask |= ~(0xff << shift);
3108 offset++;
3109 or_mask = RBIOS8(offset) << shift;
3110 offset++;
3111 tmp = RREG32_PLL(addr);
3112 tmp &= and_mask;
3113 tmp |= or_mask;
3114 WREG32_PLL(addr, tmp);
3115 break;
3116 case 2:
3117 case 3:
3118 tmp = 1000;
3119 switch (addr) {
3120 case 1:
3121 udelay(150);
3122 break;
3123 case 2:
3124 mdelay(1);
3125 break;
3126 case 3:
3127 while (tmp--) {
3128 if (!
3129 (RREG32_PLL
3130 (RADEON_CLK_PWRMGT_CNTL) &
3131 RADEON_MC_BUSY))
3132 break;
3133 }
3134 break;
3135 case 4:
3136 while (tmp--) {
3137 if (RREG32_PLL
3138 (RADEON_CLK_PWRMGT_CNTL) &
3139 RADEON_DLL_READY)
3140 break;
3141 }
3142 break;
3143 case 5:
3144 tmp =
3145 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3146 if (tmp & RADEON_CG_NO1_DEBUG_0) {
3147 #if 0
3148 uint32_t mclk_cntl =
3149 RREG32_PLL
3150 (RADEON_MCLK_CNTL);
3151 mclk_cntl &= 0xffff0000;
3152 /*mclk_cntl |= 0x00001111;*//* ??? */
3153 WREG32_PLL(RADEON_MCLK_CNTL,
3154 mclk_cntl);
3155 mdelay(10);
3156 #endif
3157 WREG32_PLL
3158 (RADEON_CLK_PWRMGT_CNTL,
3159 tmp &
3160 ~RADEON_CG_NO1_DEBUG_0);
3161 mdelay(10);
3162 }
3163 break;
3164 default:
3165 break;
3166 }
3167 break;
3168 default:
3169 break;
3170 }
3171 }
3172 }
3173 }
3174
combios_parse_ram_reset_table(struct drm_device * dev,uint16_t offset)3175 static void combios_parse_ram_reset_table(struct drm_device *dev,
3176 uint16_t offset)
3177 {
3178 struct radeon_device *rdev = dev->dev_private;
3179 uint32_t tmp;
3180
3181 if (offset) {
3182 uint8_t val = RBIOS8(offset);
3183 while (val != 0xff) {
3184 offset++;
3185
3186 if (val == 0x0f) {
3187 uint32_t channel_complete_mask;
3188
3189 if (ASIC_IS_R300(rdev))
3190 channel_complete_mask =
3191 R300_MEM_PWRUP_COMPLETE;
3192 else
3193 channel_complete_mask =
3194 RADEON_MEM_PWRUP_COMPLETE;
3195 tmp = 20000;
3196 while (tmp--) {
3197 if ((RREG32(RADEON_MEM_STR_CNTL) &
3198 channel_complete_mask) ==
3199 channel_complete_mask)
3200 break;
3201 }
3202 } else {
3203 uint32_t or_mask = RBIOS16(offset);
3204 offset += 2;
3205
3206 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3207 tmp &= RADEON_SDRAM_MODE_MASK;
3208 tmp |= or_mask;
3209 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3210
3211 or_mask = val << 24;
3212 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3213 tmp &= RADEON_B3MEM_RESET_MASK;
3214 tmp |= or_mask;
3215 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3216 }
3217 val = RBIOS8(offset);
3218 }
3219 }
3220 }
3221
combios_detect_ram(struct drm_device * dev,int ram,int mem_addr_mapping)3222 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3223 int mem_addr_mapping)
3224 {
3225 struct radeon_device *rdev = dev->dev_private;
3226 uint32_t mem_cntl;
3227 uint32_t mem_size;
3228 uint32_t addr = 0;
3229
3230 mem_cntl = RREG32(RADEON_MEM_CNTL);
3231 if (mem_cntl & RV100_HALF_MODE)
3232 ram /= 2;
3233 mem_size = ram;
3234 mem_cntl &= ~(0xff << 8);
3235 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3236 WREG32(RADEON_MEM_CNTL, mem_cntl);
3237 RREG32(RADEON_MEM_CNTL);
3238
3239 /* sdram reset ? */
3240
3241 /* something like this???? */
3242 while (ram--) {
3243 addr = ram * 1024 * 1024;
3244 /* write to each page */
3245 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3246 WREG32(RADEON_MM_DATA, 0xdeadbeef);
3247 /* read back and verify */
3248 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3249 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3250 return 0;
3251 }
3252
3253 return mem_size;
3254 }
3255
combios_write_ram_size(struct drm_device * dev)3256 static void combios_write_ram_size(struct drm_device *dev)
3257 {
3258 struct radeon_device *rdev = dev->dev_private;
3259 uint8_t rev;
3260 uint16_t offset;
3261 uint32_t mem_size = 0;
3262 uint32_t mem_cntl = 0;
3263
3264 /* should do something smarter here I guess... */
3265 if (rdev->flags & RADEON_IS_IGP)
3266 return;
3267
3268 /* first check detected mem table */
3269 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3270 if (offset) {
3271 rev = RBIOS8(offset);
3272 if (rev < 3) {
3273 mem_cntl = RBIOS32(offset + 1);
3274 mem_size = RBIOS16(offset + 5);
3275 if ((rdev->family < CHIP_R200) &&
3276 !ASIC_IS_RN50(rdev))
3277 WREG32(RADEON_MEM_CNTL, mem_cntl);
3278 }
3279 }
3280
3281 if (!mem_size) {
3282 offset =
3283 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3284 if (offset) {
3285 rev = RBIOS8(offset - 1);
3286 if (rev < 1) {
3287 if ((rdev->family < CHIP_R200)
3288 && !ASIC_IS_RN50(rdev)) {
3289 int ram = 0;
3290 int mem_addr_mapping = 0;
3291
3292 while (RBIOS8(offset)) {
3293 ram = RBIOS8(offset);
3294 mem_addr_mapping =
3295 RBIOS8(offset + 1);
3296 if (mem_addr_mapping != 0x25)
3297 ram *= 2;
3298 mem_size =
3299 combios_detect_ram(dev, ram,
3300 mem_addr_mapping);
3301 if (mem_size)
3302 break;
3303 offset += 2;
3304 }
3305 } else
3306 mem_size = RBIOS8(offset);
3307 } else {
3308 mem_size = RBIOS8(offset);
3309 mem_size *= 2; /* convert to MB */
3310 }
3311 }
3312 }
3313
3314 mem_size *= (1024 * 1024); /* convert to bytes */
3315 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3316 }
3317
radeon_combios_dyn_clk_setup(struct drm_device * dev,int enable)3318 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3319 {
3320 uint16_t dyn_clk_info =
3321 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3322
3323 if (dyn_clk_info)
3324 combios_parse_pll_table(dev, dyn_clk_info);
3325 }
3326
radeon_combios_asic_init(struct drm_device * dev)3327 void radeon_combios_asic_init(struct drm_device *dev)
3328 {
3329 struct radeon_device *rdev = dev->dev_private;
3330 uint16_t table;
3331
3332 /* port hardcoded mac stuff from radeonfb */
3333 if (rdev->bios == NULL)
3334 return;
3335
3336 /* ASIC INIT 1 */
3337 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3338 if (table)
3339 combios_parse_mmio_table(dev, table);
3340
3341 /* PLL INIT */
3342 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3343 if (table)
3344 combios_parse_pll_table(dev, table);
3345
3346 /* ASIC INIT 2 */
3347 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3348 if (table)
3349 combios_parse_mmio_table(dev, table);
3350
3351 if (!(rdev->flags & RADEON_IS_IGP)) {
3352 /* ASIC INIT 4 */
3353 table =
3354 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3355 if (table)
3356 combios_parse_mmio_table(dev, table);
3357
3358 /* RAM RESET */
3359 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3360 if (table)
3361 combios_parse_ram_reset_table(dev, table);
3362
3363 /* ASIC INIT 3 */
3364 table =
3365 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3366 if (table)
3367 combios_parse_mmio_table(dev, table);
3368
3369 /* write CONFIG_MEMSIZE */
3370 combios_write_ram_size(dev);
3371 }
3372
3373 /* quirk for rs4xx HP nx6125 laptop to make it resume
3374 * - it hangs on resume inside the dynclk 1 table.
3375 */
3376 if (rdev->family == CHIP_RS480 &&
3377 rdev->pdev->subsystem_vendor == 0x103c &&
3378 rdev->pdev->subsystem_device == 0x308b)
3379 return;
3380
3381 /* quirk for rs4xx HP dv5000 laptop to make it resume
3382 * - it hangs on resume inside the dynclk 1 table.
3383 */
3384 if (rdev->family == CHIP_RS480 &&
3385 rdev->pdev->subsystem_vendor == 0x103c &&
3386 rdev->pdev->subsystem_device == 0x30a4)
3387 return;
3388
3389 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3390 * - it hangs on resume inside the dynclk 1 table.
3391 */
3392 if (rdev->family == CHIP_RS480 &&
3393 rdev->pdev->subsystem_vendor == 0x103c &&
3394 rdev->pdev->subsystem_device == 0x30ae)
3395 return;
3396
3397 /* DYN CLK 1 */
3398 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3399 if (table)
3400 combios_parse_pll_table(dev, table);
3401
3402 }
3403
radeon_combios_initialize_bios_scratch_regs(struct drm_device * dev)3404 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3405 {
3406 struct radeon_device *rdev = dev->dev_private;
3407 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3408
3409 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3410 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3411 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3412
3413 /* let the bios control the backlight */
3414 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3415
3416 /* tell the bios not to handle mode switching */
3417 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3418 RADEON_ACC_MODE_CHANGE);
3419
3420 /* tell the bios a driver is loaded */
3421 bios_7_scratch |= RADEON_DRV_LOADED;
3422
3423 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3424 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3425 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3426 }
3427
radeon_combios_output_lock(struct drm_encoder * encoder,bool lock)3428 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3429 {
3430 struct drm_device *dev = encoder->dev;
3431 struct radeon_device *rdev = dev->dev_private;
3432 uint32_t bios_6_scratch;
3433
3434 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3435
3436 if (lock)
3437 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3438 else
3439 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3440
3441 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3442 }
3443
3444 void
radeon_combios_connected_scratch_regs(struct drm_connector * connector,struct drm_encoder * encoder,bool connected)3445 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3446 struct drm_encoder *encoder,
3447 bool connected)
3448 {
3449 struct drm_device *dev = connector->dev;
3450 struct radeon_device *rdev = dev->dev_private;
3451 struct radeon_connector *radeon_connector =
3452 to_radeon_connector(connector);
3453 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3454 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3455 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3456
3457 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3458 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3459 if (connected) {
3460 DRM_DEBUG_KMS("TV1 connected\n");
3461 /* fix me */
3462 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3463 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3464 bios_5_scratch |= RADEON_TV1_ON;
3465 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3466 } else {
3467 DRM_DEBUG_KMS("TV1 disconnected\n");
3468 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3469 bios_5_scratch &= ~RADEON_TV1_ON;
3470 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3471 }
3472 }
3473 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3474 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3475 if (connected) {
3476 DRM_DEBUG_KMS("LCD1 connected\n");
3477 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3478 bios_5_scratch |= RADEON_LCD1_ON;
3479 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3480 } else {
3481 DRM_DEBUG_KMS("LCD1 disconnected\n");
3482 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3483 bios_5_scratch &= ~RADEON_LCD1_ON;
3484 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3485 }
3486 }
3487 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3488 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3489 if (connected) {
3490 DRM_DEBUG_KMS("CRT1 connected\n");
3491 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3492 bios_5_scratch |= RADEON_CRT1_ON;
3493 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3494 } else {
3495 DRM_DEBUG_KMS("CRT1 disconnected\n");
3496 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3497 bios_5_scratch &= ~RADEON_CRT1_ON;
3498 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3499 }
3500 }
3501 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3502 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3503 if (connected) {
3504 DRM_DEBUG_KMS("CRT2 connected\n");
3505 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3506 bios_5_scratch |= RADEON_CRT2_ON;
3507 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3508 } else {
3509 DRM_DEBUG_KMS("CRT2 disconnected\n");
3510 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3511 bios_5_scratch &= ~RADEON_CRT2_ON;
3512 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3513 }
3514 }
3515 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3516 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3517 if (connected) {
3518 DRM_DEBUG_KMS("DFP1 connected\n");
3519 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3520 bios_5_scratch |= RADEON_DFP1_ON;
3521 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3522 } else {
3523 DRM_DEBUG_KMS("DFP1 disconnected\n");
3524 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3525 bios_5_scratch &= ~RADEON_DFP1_ON;
3526 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3527 }
3528 }
3529 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3530 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3531 if (connected) {
3532 DRM_DEBUG_KMS("DFP2 connected\n");
3533 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3534 bios_5_scratch |= RADEON_DFP2_ON;
3535 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3536 } else {
3537 DRM_DEBUG_KMS("DFP2 disconnected\n");
3538 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3539 bios_5_scratch &= ~RADEON_DFP2_ON;
3540 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3541 }
3542 }
3543 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3544 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3545 }
3546
3547 void
radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder * encoder,int crtc)3548 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3549 {
3550 struct drm_device *dev = encoder->dev;
3551 struct radeon_device *rdev = dev->dev_private;
3552 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3553 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3554
3555 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3556 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3557 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3558 }
3559 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3560 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3561 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3562 }
3563 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3564 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3565 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3566 }
3567 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3568 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3569 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3570 }
3571 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3572 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3573 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3574 }
3575 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3576 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3577 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3578 }
3579 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3580 }
3581
3582 void
radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder * encoder,bool on)3583 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3584 {
3585 struct drm_device *dev = encoder->dev;
3586 struct radeon_device *rdev = dev->dev_private;
3587 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3588 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3589
3590 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3591 if (on)
3592 bios_6_scratch |= RADEON_TV_DPMS_ON;
3593 else
3594 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3595 }
3596 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3597 if (on)
3598 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3599 else
3600 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3601 }
3602 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3603 if (on)
3604 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3605 else
3606 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3607 }
3608 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3609 if (on)
3610 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3611 else
3612 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3613 }
3614 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3615 }
3616