1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31 #include <linux/backlight.h>
32 #ifdef CONFIG_PMAC_BACKLIGHT
33 #include <asm/backlight.h>
34 #endif
35
radeon_legacy_encoder_disable(struct drm_encoder * encoder)36 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
37 {
38 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
39 struct drm_encoder_helper_funcs *encoder_funcs;
40
41 encoder_funcs = encoder->helper_private;
42 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
43 radeon_encoder->active_device = 0;
44 }
45
radeon_legacy_lvds_update(struct drm_encoder * encoder,int mode)46 static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
47 {
48 struct drm_device *dev = encoder->dev;
49 struct radeon_device *rdev = dev->dev_private;
50 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
51 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
52 int panel_pwr_delay = 2000;
53 bool is_mac = false;
54 uint8_t backlight_level;
55 DRM_DEBUG_KMS("\n");
56
57 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
58 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
59
60 if (radeon_encoder->enc_priv) {
61 if (rdev->is_atom_bios) {
62 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
63 panel_pwr_delay = lvds->panel_pwr_delay;
64 if (lvds->bl_dev)
65 backlight_level = lvds->backlight_level;
66 } else {
67 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
68 panel_pwr_delay = lvds->panel_pwr_delay;
69 if (lvds->bl_dev)
70 backlight_level = lvds->backlight_level;
71 }
72 }
73
74 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
75 * Taken from radeonfb.
76 */
77 if ((rdev->mode_info.connector_table == CT_IBOOK) ||
78 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
79 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
80 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
81 is_mac = true;
82
83 switch (mode) {
84 case DRM_MODE_DPMS_ON:
85 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
86 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
87 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
88 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
89 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
90 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
91 mdelay(1);
92
93 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
94 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
95 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
96
97 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
98 RADEON_LVDS_BL_MOD_LEVEL_MASK);
99 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
100 RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
101 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
102 if (is_mac)
103 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
104 mdelay(panel_pwr_delay);
105 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
106 break;
107 case DRM_MODE_DPMS_STANDBY:
108 case DRM_MODE_DPMS_SUSPEND:
109 case DRM_MODE_DPMS_OFF:
110 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
111 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
112 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
113 if (is_mac) {
114 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
115 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
116 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
117 } else {
118 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
119 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
120 }
121 mdelay(panel_pwr_delay);
122 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
123 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
124 mdelay(panel_pwr_delay);
125 break;
126 }
127
128 if (rdev->is_atom_bios)
129 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
130 else
131 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
132
133 }
134
radeon_legacy_lvds_dpms(struct drm_encoder * encoder,int mode)135 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
136 {
137 struct radeon_device *rdev = encoder->dev->dev_private;
138 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
139 DRM_DEBUG("\n");
140
141 if (radeon_encoder->enc_priv) {
142 if (rdev->is_atom_bios) {
143 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
144 lvds->dpms_mode = mode;
145 } else {
146 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
147 lvds->dpms_mode = mode;
148 }
149 }
150
151 radeon_legacy_lvds_update(encoder, mode);
152 }
153
radeon_legacy_lvds_prepare(struct drm_encoder * encoder)154 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
155 {
156 struct radeon_device *rdev = encoder->dev->dev_private;
157
158 if (rdev->is_atom_bios)
159 radeon_atom_output_lock(encoder, true);
160 else
161 radeon_combios_output_lock(encoder, true);
162 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
163 }
164
radeon_legacy_lvds_commit(struct drm_encoder * encoder)165 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
166 {
167 struct radeon_device *rdev = encoder->dev->dev_private;
168
169 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
170 if (rdev->is_atom_bios)
171 radeon_atom_output_lock(encoder, false);
172 else
173 radeon_combios_output_lock(encoder, false);
174 }
175
radeon_legacy_lvds_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)176 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
177 struct drm_display_mode *mode,
178 struct drm_display_mode *adjusted_mode)
179 {
180 struct drm_device *dev = encoder->dev;
181 struct radeon_device *rdev = dev->dev_private;
182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
183 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
184 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
185
186 DRM_DEBUG_KMS("\n");
187
188 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
189 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
190
191 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
192 if (rdev->is_atom_bios) {
193 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
194 * need to call that on resume to set up the reg properly.
195 */
196 radeon_encoder->pixel_clock = adjusted_mode->clock;
197 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
198 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
199 } else {
200 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
201 if (lvds) {
202 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
203 lvds_gen_cntl = lvds->lvds_gen_cntl;
204 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
205 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
206 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
207 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
208 } else
209 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
210 }
211 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
212 lvds_gen_cntl &= ~(RADEON_LVDS_ON |
213 RADEON_LVDS_BLON |
214 RADEON_LVDS_EN |
215 RADEON_LVDS_RST_FM);
216
217 if (ASIC_IS_R300(rdev))
218 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
219
220 if (radeon_crtc->crtc_id == 0) {
221 if (ASIC_IS_R300(rdev)) {
222 if (radeon_encoder->rmx_type != RMX_OFF)
223 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
224 } else
225 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
226 } else {
227 if (ASIC_IS_R300(rdev))
228 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
229 else
230 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
231 }
232
233 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
234 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
235 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
236
237 if (rdev->family == CHIP_RV410)
238 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
239
240 if (rdev->is_atom_bios)
241 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
242 else
243 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
244 }
245
radeon_legacy_mode_fixup(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)246 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
247 struct drm_display_mode *mode,
248 struct drm_display_mode *adjusted_mode)
249 {
250 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
251
252 /* set the active encoder to connector routing */
253 radeon_encoder_set_active_device(encoder);
254 drm_mode_set_crtcinfo(adjusted_mode, 0);
255
256 /* get the native mode for LVDS */
257 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
258 radeon_panel_mode_fixup(encoder, adjusted_mode);
259
260 return true;
261 }
262
263 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
264 .dpms = radeon_legacy_lvds_dpms,
265 .mode_fixup = radeon_legacy_mode_fixup,
266 .prepare = radeon_legacy_lvds_prepare,
267 .mode_set = radeon_legacy_lvds_mode_set,
268 .commit = radeon_legacy_lvds_commit,
269 .disable = radeon_legacy_encoder_disable,
270 };
271
272 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
273
274 #define MAX_RADEON_LEVEL 0xFF
275
276 struct radeon_backlight_privdata {
277 struct radeon_encoder *encoder;
278 uint8_t negative;
279 };
280
radeon_legacy_lvds_level(struct backlight_device * bd)281 static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
282 {
283 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
284 uint8_t level;
285
286 /* Convert brightness to hardware level */
287 if (bd->props.brightness < 0)
288 level = 0;
289 else if (bd->props.brightness > MAX_RADEON_LEVEL)
290 level = MAX_RADEON_LEVEL;
291 else
292 level = bd->props.brightness;
293
294 if (pdata->negative)
295 level = MAX_RADEON_LEVEL - level;
296
297 return level;
298 }
299
radeon_legacy_backlight_update_status(struct backlight_device * bd)300 static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
301 {
302 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
303 struct radeon_encoder *radeon_encoder = pdata->encoder;
304 struct drm_device *dev = radeon_encoder->base.dev;
305 struct radeon_device *rdev = dev->dev_private;
306 int dpms_mode = DRM_MODE_DPMS_ON;
307
308 if (radeon_encoder->enc_priv) {
309 if (rdev->is_atom_bios) {
310 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
311 dpms_mode = lvds->dpms_mode;
312 lvds->backlight_level = radeon_legacy_lvds_level(bd);
313 } else {
314 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
315 dpms_mode = lvds->dpms_mode;
316 lvds->backlight_level = radeon_legacy_lvds_level(bd);
317 }
318 }
319
320 if (bd->props.brightness > 0)
321 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
322 else
323 radeon_legacy_lvds_update(&radeon_encoder->base, DRM_MODE_DPMS_OFF);
324
325 return 0;
326 }
327
radeon_legacy_backlight_get_brightness(struct backlight_device * bd)328 static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
329 {
330 struct radeon_backlight_privdata *pdata = bl_get_data(bd);
331 struct radeon_encoder *radeon_encoder = pdata->encoder;
332 struct drm_device *dev = radeon_encoder->base.dev;
333 struct radeon_device *rdev = dev->dev_private;
334 uint8_t backlight_level;
335
336 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
337 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
338
339 return pdata->negative ? MAX_RADEON_LEVEL - backlight_level : backlight_level;
340 }
341
342 static const struct backlight_ops radeon_backlight_ops = {
343 .get_brightness = radeon_legacy_backlight_get_brightness,
344 .update_status = radeon_legacy_backlight_update_status,
345 };
346
radeon_legacy_backlight_init(struct radeon_encoder * radeon_encoder,struct drm_connector * drm_connector)347 void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
348 struct drm_connector *drm_connector)
349 {
350 struct drm_device *dev = radeon_encoder->base.dev;
351 struct radeon_device *rdev = dev->dev_private;
352 struct backlight_device *bd;
353 struct backlight_properties props;
354 struct radeon_backlight_privdata *pdata;
355 uint8_t backlight_level;
356
357 if (!radeon_encoder->enc_priv)
358 return;
359
360 #ifdef CONFIG_PMAC_BACKLIGHT
361 if (!pmac_has_backlight_type("ati") &&
362 !pmac_has_backlight_type("mnca"))
363 return;
364 #endif
365
366 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
367 if (!pdata) {
368 DRM_ERROR("Memory allocation failed\n");
369 goto error;
370 }
371
372 props.max_brightness = MAX_RADEON_LEVEL;
373 props.type = BACKLIGHT_RAW;
374 bd = backlight_device_register("radeon_bl", &drm_connector->kdev,
375 pdata, &radeon_backlight_ops, &props);
376 if (IS_ERR(bd)) {
377 DRM_ERROR("Backlight registration failed\n");
378 goto error;
379 }
380
381 pdata->encoder = radeon_encoder;
382
383 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
384 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
385
386 /* First, try to detect backlight level sense based on the assumption
387 * that firmware set it up at full brightness
388 */
389 if (backlight_level == 0)
390 pdata->negative = true;
391 else if (backlight_level == 0xff)
392 pdata->negative = false;
393 else {
394 /* XXX hack... maybe some day we can figure out in what direction
395 * backlight should work on a given panel?
396 */
397 pdata->negative = (rdev->family != CHIP_RV200 &&
398 rdev->family != CHIP_RV250 &&
399 rdev->family != CHIP_RV280 &&
400 rdev->family != CHIP_RV350);
401
402 #ifdef CONFIG_PMAC_BACKLIGHT
403 pdata->negative = (pdata->negative ||
404 of_machine_is_compatible("PowerBook4,3") ||
405 of_machine_is_compatible("PowerBook6,3") ||
406 of_machine_is_compatible("PowerBook6,5"));
407 #endif
408 }
409
410 if (rdev->is_atom_bios) {
411 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
412 lvds->bl_dev = bd;
413 } else {
414 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
415 lvds->bl_dev = bd;
416 }
417
418 bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
419 bd->props.power = FB_BLANK_UNBLANK;
420 backlight_update_status(bd);
421
422 DRM_INFO("radeon legacy LVDS backlight initialized\n");
423
424 return;
425
426 error:
427 kfree(pdata);
428 return;
429 }
430
radeon_legacy_backlight_exit(struct radeon_encoder * radeon_encoder)431 static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
432 {
433 struct drm_device *dev = radeon_encoder->base.dev;
434 struct radeon_device *rdev = dev->dev_private;
435 struct backlight_device *bd = NULL;
436
437 if (!radeon_encoder->enc_priv)
438 return;
439
440 if (rdev->is_atom_bios) {
441 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
442 bd = lvds->bl_dev;
443 lvds->bl_dev = NULL;
444 } else {
445 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
446 bd = lvds->bl_dev;
447 lvds->bl_dev = NULL;
448 }
449
450 if (bd) {
451 struct radeon_legacy_backlight_privdata *pdata;
452
453 pdata = bl_get_data(bd);
454 backlight_device_unregister(bd);
455 kfree(pdata);
456
457 DRM_INFO("radeon legacy LVDS backlight unloaded\n");
458 }
459 }
460
461 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
462
radeon_legacy_backlight_init(struct radeon_encoder * encoder)463 void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
464 {
465 }
466
radeon_legacy_backlight_exit(struct radeon_encoder * encoder)467 static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
468 {
469 }
470
471 #endif
472
473
radeon_lvds_enc_destroy(struct drm_encoder * encoder)474 static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
475 {
476 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
477
478 if (radeon_encoder->enc_priv) {
479 radeon_legacy_backlight_exit(radeon_encoder);
480 kfree(radeon_encoder->enc_priv);
481 }
482 drm_encoder_cleanup(encoder);
483 kfree(radeon_encoder);
484 }
485
486 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
487 .destroy = radeon_lvds_enc_destroy,
488 };
489
radeon_legacy_primary_dac_dpms(struct drm_encoder * encoder,int mode)490 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
491 {
492 struct drm_device *dev = encoder->dev;
493 struct radeon_device *rdev = dev->dev_private;
494 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
495 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
496 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
497
498 DRM_DEBUG_KMS("\n");
499
500 switch (mode) {
501 case DRM_MODE_DPMS_ON:
502 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
503 dac_cntl &= ~RADEON_DAC_PDWN;
504 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
505 RADEON_DAC_PDWN_G |
506 RADEON_DAC_PDWN_B);
507 break;
508 case DRM_MODE_DPMS_STANDBY:
509 case DRM_MODE_DPMS_SUSPEND:
510 case DRM_MODE_DPMS_OFF:
511 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
512 dac_cntl |= RADEON_DAC_PDWN;
513 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
514 RADEON_DAC_PDWN_G |
515 RADEON_DAC_PDWN_B);
516 break;
517 }
518
519 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
520 WREG32(RADEON_DAC_CNTL, dac_cntl);
521 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
522
523 if (rdev->is_atom_bios)
524 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
525 else
526 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
527
528 }
529
radeon_legacy_primary_dac_prepare(struct drm_encoder * encoder)530 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
531 {
532 struct radeon_device *rdev = encoder->dev->dev_private;
533
534 if (rdev->is_atom_bios)
535 radeon_atom_output_lock(encoder, true);
536 else
537 radeon_combios_output_lock(encoder, true);
538 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
539 }
540
radeon_legacy_primary_dac_commit(struct drm_encoder * encoder)541 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
542 {
543 struct radeon_device *rdev = encoder->dev->dev_private;
544
545 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
546
547 if (rdev->is_atom_bios)
548 radeon_atom_output_lock(encoder, false);
549 else
550 radeon_combios_output_lock(encoder, false);
551 }
552
radeon_legacy_primary_dac_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)553 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
554 struct drm_display_mode *mode,
555 struct drm_display_mode *adjusted_mode)
556 {
557 struct drm_device *dev = encoder->dev;
558 struct radeon_device *rdev = dev->dev_private;
559 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
560 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
561 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
562
563 DRM_DEBUG_KMS("\n");
564
565 if (radeon_crtc->crtc_id == 0) {
566 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
567 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
568 ~(RADEON_DISP_DAC_SOURCE_MASK);
569 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
570 } else {
571 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
572 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
573 }
574 } else {
575 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
576 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
577 ~(RADEON_DISP_DAC_SOURCE_MASK);
578 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
579 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
580 } else {
581 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
582 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
583 }
584 }
585
586 dac_cntl = (RADEON_DAC_MASK_ALL |
587 RADEON_DAC_VGA_ADR_EN |
588 /* TODO 6-bits */
589 RADEON_DAC_8BIT_EN);
590
591 WREG32_P(RADEON_DAC_CNTL,
592 dac_cntl,
593 RADEON_DAC_RANGE_CNTL |
594 RADEON_DAC_BLANKING);
595
596 if (radeon_encoder->enc_priv) {
597 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
598 dac_macro_cntl = p_dac->ps2_pdac_adj;
599 } else
600 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
601 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
602 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
603
604 if (rdev->is_atom_bios)
605 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
606 else
607 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
608 }
609
radeon_legacy_primary_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector)610 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
611 struct drm_connector *connector)
612 {
613 struct drm_device *dev = encoder->dev;
614 struct radeon_device *rdev = dev->dev_private;
615 uint32_t vclk_ecp_cntl, crtc_ext_cntl;
616 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
617 enum drm_connector_status found = connector_status_disconnected;
618 bool color = true;
619
620 /* just don't bother on RN50 those chip are often connected to remoting
621 * console hw and often we get failure to load detect those. So to make
622 * everyone happy report the encoder as always connected.
623 */
624 if (ASIC_IS_RN50(rdev)) {
625 return connector_status_connected;
626 }
627
628 /* save the regs we need */
629 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
630 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
631 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
632 dac_cntl = RREG32(RADEON_DAC_CNTL);
633 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
634
635 tmp = vclk_ecp_cntl &
636 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
637 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
638
639 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
640 WREG32(RADEON_CRTC_EXT_CNTL, tmp);
641
642 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
643 RADEON_DAC_FORCE_DATA_EN;
644
645 if (color)
646 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
647 else
648 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
649
650 if (ASIC_IS_R300(rdev))
651 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
652 else
653 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
654
655 WREG32(RADEON_DAC_EXT_CNTL, tmp);
656
657 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
658 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
659 WREG32(RADEON_DAC_CNTL, tmp);
660
661 tmp = dac_macro_cntl;
662 tmp &= ~(RADEON_DAC_PDWN_R |
663 RADEON_DAC_PDWN_G |
664 RADEON_DAC_PDWN_B);
665
666 WREG32(RADEON_DAC_MACRO_CNTL, tmp);
667
668 mdelay(2);
669
670 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
671 found = connector_status_connected;
672
673 /* restore the regs we used */
674 WREG32(RADEON_DAC_CNTL, dac_cntl);
675 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
676 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
677 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
678 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
679
680 return found;
681 }
682
683 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
684 .dpms = radeon_legacy_primary_dac_dpms,
685 .mode_fixup = radeon_legacy_mode_fixup,
686 .prepare = radeon_legacy_primary_dac_prepare,
687 .mode_set = radeon_legacy_primary_dac_mode_set,
688 .commit = radeon_legacy_primary_dac_commit,
689 .detect = radeon_legacy_primary_dac_detect,
690 .disable = radeon_legacy_encoder_disable,
691 };
692
693
694 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
695 .destroy = radeon_enc_destroy,
696 };
697
radeon_legacy_tmds_int_dpms(struct drm_encoder * encoder,int mode)698 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
699 {
700 struct drm_device *dev = encoder->dev;
701 struct radeon_device *rdev = dev->dev_private;
702 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
703 DRM_DEBUG_KMS("\n");
704
705 switch (mode) {
706 case DRM_MODE_DPMS_ON:
707 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
708 break;
709 case DRM_MODE_DPMS_STANDBY:
710 case DRM_MODE_DPMS_SUSPEND:
711 case DRM_MODE_DPMS_OFF:
712 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
713 break;
714 }
715
716 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
717
718 if (rdev->is_atom_bios)
719 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
720 else
721 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
722
723 }
724
radeon_legacy_tmds_int_prepare(struct drm_encoder * encoder)725 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
726 {
727 struct radeon_device *rdev = encoder->dev->dev_private;
728
729 if (rdev->is_atom_bios)
730 radeon_atom_output_lock(encoder, true);
731 else
732 radeon_combios_output_lock(encoder, true);
733 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
734 }
735
radeon_legacy_tmds_int_commit(struct drm_encoder * encoder)736 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
737 {
738 struct radeon_device *rdev = encoder->dev->dev_private;
739
740 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
741
742 if (rdev->is_atom_bios)
743 radeon_atom_output_lock(encoder, true);
744 else
745 radeon_combios_output_lock(encoder, true);
746 }
747
radeon_legacy_tmds_int_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)748 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
749 struct drm_display_mode *mode,
750 struct drm_display_mode *adjusted_mode)
751 {
752 struct drm_device *dev = encoder->dev;
753 struct radeon_device *rdev = dev->dev_private;
754 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
755 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
756 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
757 int i;
758
759 DRM_DEBUG_KMS("\n");
760
761 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
762 tmp &= 0xfffff;
763 if (rdev->family == CHIP_RV280) {
764 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
765 tmp ^= (1 << 22);
766 tmds_pll_cntl ^= (1 << 22);
767 }
768
769 if (radeon_encoder->enc_priv) {
770 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
771
772 for (i = 0; i < 4; i++) {
773 if (tmds->tmds_pll[i].freq == 0)
774 break;
775 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
776 tmp = tmds->tmds_pll[i].value ;
777 break;
778 }
779 }
780 }
781
782 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
783 if (tmp & 0xfff00000)
784 tmds_pll_cntl = tmp;
785 else {
786 tmds_pll_cntl &= 0xfff00000;
787 tmds_pll_cntl |= tmp;
788 }
789 } else
790 tmds_pll_cntl = tmp;
791
792 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
793 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
794
795 if (rdev->family == CHIP_R200 ||
796 rdev->family == CHIP_R100 ||
797 ASIC_IS_R300(rdev))
798 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
799 else /* RV chips got this bit reversed */
800 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
801
802 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
803 (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
804 RADEON_FP_CRTC_DONT_SHADOW_HEND));
805
806 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
807
808 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
809 RADEON_FP_DFP_SYNC_SEL |
810 RADEON_FP_CRT_SYNC_SEL |
811 RADEON_FP_CRTC_LOCK_8DOT |
812 RADEON_FP_USE_SHADOW_EN |
813 RADEON_FP_CRTC_USE_SHADOW_VEND |
814 RADEON_FP_CRT_SYNC_ALT);
815
816 if (1) /* FIXME rgbBits == 8 */
817 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
818 else
819 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
820
821 if (radeon_crtc->crtc_id == 0) {
822 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
823 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
824 if (radeon_encoder->rmx_type != RMX_OFF)
825 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
826 else
827 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
828 } else
829 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
830 } else {
831 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
832 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
833 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
834 } else
835 fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
836 }
837
838 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
839 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
840 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
841
842 if (rdev->is_atom_bios)
843 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
844 else
845 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
846 }
847
848 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
849 .dpms = radeon_legacy_tmds_int_dpms,
850 .mode_fixup = radeon_legacy_mode_fixup,
851 .prepare = radeon_legacy_tmds_int_prepare,
852 .mode_set = radeon_legacy_tmds_int_mode_set,
853 .commit = radeon_legacy_tmds_int_commit,
854 .disable = radeon_legacy_encoder_disable,
855 };
856
857
858 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
859 .destroy = radeon_enc_destroy,
860 };
861
radeon_legacy_tmds_ext_dpms(struct drm_encoder * encoder,int mode)862 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
863 {
864 struct drm_device *dev = encoder->dev;
865 struct radeon_device *rdev = dev->dev_private;
866 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
867 DRM_DEBUG_KMS("\n");
868
869 switch (mode) {
870 case DRM_MODE_DPMS_ON:
871 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
872 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
873 break;
874 case DRM_MODE_DPMS_STANDBY:
875 case DRM_MODE_DPMS_SUSPEND:
876 case DRM_MODE_DPMS_OFF:
877 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
878 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
879 break;
880 }
881
882 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
883
884 if (rdev->is_atom_bios)
885 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
886 else
887 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
888
889 }
890
radeon_legacy_tmds_ext_prepare(struct drm_encoder * encoder)891 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
892 {
893 struct radeon_device *rdev = encoder->dev->dev_private;
894
895 if (rdev->is_atom_bios)
896 radeon_atom_output_lock(encoder, true);
897 else
898 radeon_combios_output_lock(encoder, true);
899 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
900 }
901
radeon_legacy_tmds_ext_commit(struct drm_encoder * encoder)902 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
903 {
904 struct radeon_device *rdev = encoder->dev->dev_private;
905 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
906
907 if (rdev->is_atom_bios)
908 radeon_atom_output_lock(encoder, false);
909 else
910 radeon_combios_output_lock(encoder, false);
911 }
912
radeon_legacy_tmds_ext_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)913 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
914 struct drm_display_mode *mode,
915 struct drm_display_mode *adjusted_mode)
916 {
917 struct drm_device *dev = encoder->dev;
918 struct radeon_device *rdev = dev->dev_private;
919 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
920 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
921 uint32_t fp2_gen_cntl;
922
923 DRM_DEBUG_KMS("\n");
924
925 if (rdev->is_atom_bios) {
926 radeon_encoder->pixel_clock = adjusted_mode->clock;
927 atombios_dvo_setup(encoder, ATOM_ENABLE);
928 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
929 } else {
930 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
931
932 if (1) /* FIXME rgbBits == 8 */
933 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
934 else
935 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
936
937 fp2_gen_cntl &= ~(RADEON_FP2_ON |
938 RADEON_FP2_DVO_EN |
939 RADEON_FP2_DVO_RATE_SEL_SDR);
940
941 /* XXX: these are oem specific */
942 if (ASIC_IS_R300(rdev)) {
943 if ((dev->pdev->device == 0x4850) &&
944 (dev->pdev->subsystem_vendor == 0x1028) &&
945 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
946 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
947 else
948 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
949
950 /*if (mode->clock > 165000)
951 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
952 }
953 if (!radeon_combios_external_tmds_setup(encoder))
954 radeon_external_tmds_setup(encoder);
955 }
956
957 if (radeon_crtc->crtc_id == 0) {
958 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
959 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
960 if (radeon_encoder->rmx_type != RMX_OFF)
961 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
962 else
963 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
964 } else
965 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
966 } else {
967 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
968 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
969 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
970 } else
971 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
972 }
973
974 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
975
976 if (rdev->is_atom_bios)
977 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
978 else
979 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
980 }
981
radeon_ext_tmds_enc_destroy(struct drm_encoder * encoder)982 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
983 {
984 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
985 /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */
986 kfree(radeon_encoder->enc_priv);
987 drm_encoder_cleanup(encoder);
988 kfree(radeon_encoder);
989 }
990
991 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
992 .dpms = radeon_legacy_tmds_ext_dpms,
993 .mode_fixup = radeon_legacy_mode_fixup,
994 .prepare = radeon_legacy_tmds_ext_prepare,
995 .mode_set = radeon_legacy_tmds_ext_mode_set,
996 .commit = radeon_legacy_tmds_ext_commit,
997 .disable = radeon_legacy_encoder_disable,
998 };
999
1000
1001 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
1002 .destroy = radeon_ext_tmds_enc_destroy,
1003 };
1004
radeon_legacy_tv_dac_dpms(struct drm_encoder * encoder,int mode)1005 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1006 {
1007 struct drm_device *dev = encoder->dev;
1008 struct radeon_device *rdev = dev->dev_private;
1009 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1010 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1011 uint32_t tv_master_cntl = 0;
1012 bool is_tv;
1013 DRM_DEBUG_KMS("\n");
1014
1015 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1016
1017 if (rdev->family == CHIP_R200)
1018 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1019 else {
1020 if (is_tv)
1021 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1022 else
1023 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1024 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1025 }
1026
1027 switch (mode) {
1028 case DRM_MODE_DPMS_ON:
1029 if (rdev->family == CHIP_R200) {
1030 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1031 } else {
1032 if (is_tv)
1033 tv_master_cntl |= RADEON_TV_ON;
1034 else
1035 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1036
1037 if (rdev->family == CHIP_R420 ||
1038 rdev->family == CHIP_R423 ||
1039 rdev->family == CHIP_RV410)
1040 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1041 R420_TV_DAC_GDACPD |
1042 R420_TV_DAC_BDACPD |
1043 RADEON_TV_DAC_BGSLEEP);
1044 else
1045 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1046 RADEON_TV_DAC_GDACPD |
1047 RADEON_TV_DAC_BDACPD |
1048 RADEON_TV_DAC_BGSLEEP);
1049 }
1050 break;
1051 case DRM_MODE_DPMS_STANDBY:
1052 case DRM_MODE_DPMS_SUSPEND:
1053 case DRM_MODE_DPMS_OFF:
1054 if (rdev->family == CHIP_R200)
1055 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1056 else {
1057 if (is_tv)
1058 tv_master_cntl &= ~RADEON_TV_ON;
1059 else
1060 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1061
1062 if (rdev->family == CHIP_R420 ||
1063 rdev->family == CHIP_R423 ||
1064 rdev->family == CHIP_RV410)
1065 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1066 R420_TV_DAC_GDACPD |
1067 R420_TV_DAC_BDACPD |
1068 RADEON_TV_DAC_BGSLEEP);
1069 else
1070 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1071 RADEON_TV_DAC_GDACPD |
1072 RADEON_TV_DAC_BDACPD |
1073 RADEON_TV_DAC_BGSLEEP);
1074 }
1075 break;
1076 }
1077
1078 if (rdev->family == CHIP_R200) {
1079 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1080 } else {
1081 if (is_tv)
1082 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1083 else
1084 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1085 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1086 }
1087
1088 if (rdev->is_atom_bios)
1089 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1090 else
1091 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1092
1093 }
1094
radeon_legacy_tv_dac_prepare(struct drm_encoder * encoder)1095 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1096 {
1097 struct radeon_device *rdev = encoder->dev->dev_private;
1098
1099 if (rdev->is_atom_bios)
1100 radeon_atom_output_lock(encoder, true);
1101 else
1102 radeon_combios_output_lock(encoder, true);
1103 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1104 }
1105
radeon_legacy_tv_dac_commit(struct drm_encoder * encoder)1106 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1107 {
1108 struct radeon_device *rdev = encoder->dev->dev_private;
1109
1110 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1111
1112 if (rdev->is_atom_bios)
1113 radeon_atom_output_lock(encoder, true);
1114 else
1115 radeon_combios_output_lock(encoder, true);
1116 }
1117
radeon_legacy_tv_dac_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1118 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1119 struct drm_display_mode *mode,
1120 struct drm_display_mode *adjusted_mode)
1121 {
1122 struct drm_device *dev = encoder->dev;
1123 struct radeon_device *rdev = dev->dev_private;
1124 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1125 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1126 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1127 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1128 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1129 bool is_tv = false;
1130
1131 DRM_DEBUG_KMS("\n");
1132
1133 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1134
1135 if (rdev->family != CHIP_R200) {
1136 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1137 if (rdev->family == CHIP_R420 ||
1138 rdev->family == CHIP_R423 ||
1139 rdev->family == CHIP_RV410) {
1140 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1141 RADEON_TV_DAC_BGADJ_MASK |
1142 R420_TV_DAC_DACADJ_MASK |
1143 R420_TV_DAC_RDACPD |
1144 R420_TV_DAC_GDACPD |
1145 R420_TV_DAC_BDACPD |
1146 R420_TV_DAC_TVENABLE);
1147 } else {
1148 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1149 RADEON_TV_DAC_BGADJ_MASK |
1150 RADEON_TV_DAC_DACADJ_MASK |
1151 RADEON_TV_DAC_RDACPD |
1152 RADEON_TV_DAC_GDACPD |
1153 RADEON_TV_DAC_BDACPD);
1154 }
1155
1156 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1157
1158 if (is_tv) {
1159 if (tv_dac->tv_std == TV_STD_NTSC ||
1160 tv_dac->tv_std == TV_STD_NTSC_J ||
1161 tv_dac->tv_std == TV_STD_PAL_M ||
1162 tv_dac->tv_std == TV_STD_PAL_60)
1163 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1164 else
1165 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1166
1167 if (tv_dac->tv_std == TV_STD_NTSC ||
1168 tv_dac->tv_std == TV_STD_NTSC_J)
1169 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1170 else
1171 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
1172 } else
1173 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1174 tv_dac->ps2_tvdac_adj);
1175
1176 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1177 }
1178
1179 if (ASIC_IS_R300(rdev)) {
1180 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1181 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1182 } else if (rdev->family != CHIP_R200)
1183 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1184 else if (rdev->family == CHIP_R200)
1185 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1186
1187 if (rdev->family >= CHIP_R200)
1188 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1189
1190 if (is_tv) {
1191 uint32_t dac_cntl;
1192
1193 dac_cntl = RREG32(RADEON_DAC_CNTL);
1194 dac_cntl &= ~RADEON_DAC_TVO_EN;
1195 WREG32(RADEON_DAC_CNTL, dac_cntl);
1196
1197 if (ASIC_IS_R300(rdev))
1198 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1199
1200 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1201 if (radeon_crtc->crtc_id == 0) {
1202 if (ASIC_IS_R300(rdev)) {
1203 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1204 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1205 RADEON_DISP_TV_SOURCE_CRTC);
1206 }
1207 if (rdev->family >= CHIP_R200) {
1208 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1209 } else {
1210 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1211 }
1212 } else {
1213 if (ASIC_IS_R300(rdev)) {
1214 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1215 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1216 }
1217 if (rdev->family >= CHIP_R200) {
1218 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1219 } else {
1220 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1221 }
1222 }
1223 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1224 } else {
1225
1226 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1227
1228 if (radeon_crtc->crtc_id == 0) {
1229 if (ASIC_IS_R300(rdev)) {
1230 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1231 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1232 } else if (rdev->family == CHIP_R200) {
1233 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1234 RADEON_FP2_DVO_RATE_SEL_SDR);
1235 } else
1236 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1237 } else {
1238 if (ASIC_IS_R300(rdev)) {
1239 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1240 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1241 } else if (rdev->family == CHIP_R200) {
1242 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1243 RADEON_FP2_DVO_RATE_SEL_SDR);
1244 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1245 } else
1246 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1247 }
1248 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1249 }
1250
1251 if (ASIC_IS_R300(rdev)) {
1252 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1253 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1254 } else if (rdev->family != CHIP_R200)
1255 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1256 else if (rdev->family == CHIP_R200)
1257 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1258
1259 if (rdev->family >= CHIP_R200)
1260 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1261
1262 if (is_tv)
1263 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1264
1265 if (rdev->is_atom_bios)
1266 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1267 else
1268 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1269
1270 }
1271
r300_legacy_tv_detect(struct drm_encoder * encoder,struct drm_connector * connector)1272 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1273 struct drm_connector *connector)
1274 {
1275 struct drm_device *dev = encoder->dev;
1276 struct radeon_device *rdev = dev->dev_private;
1277 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1278 uint32_t disp_output_cntl, gpiopad_a, tmp;
1279 bool found = false;
1280
1281 /* save regs needed */
1282 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1283 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1284 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1285 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1286 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1287 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1288
1289 WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1290
1291 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1292
1293 WREG32(RADEON_CRTC2_GEN_CNTL,
1294 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1295
1296 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1297 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1298 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1299
1300 WREG32(RADEON_DAC_EXT_CNTL,
1301 RADEON_DAC2_FORCE_BLANK_OFF_EN |
1302 RADEON_DAC2_FORCE_DATA_EN |
1303 RADEON_DAC_FORCE_DATA_SEL_RGB |
1304 (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1305
1306 WREG32(RADEON_TV_DAC_CNTL,
1307 RADEON_TV_DAC_STD_NTSC |
1308 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1309 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1310
1311 RREG32(RADEON_TV_DAC_CNTL);
1312 mdelay(4);
1313
1314 WREG32(RADEON_TV_DAC_CNTL,
1315 RADEON_TV_DAC_NBLANK |
1316 RADEON_TV_DAC_NHOLD |
1317 RADEON_TV_MONITOR_DETECT_EN |
1318 RADEON_TV_DAC_STD_NTSC |
1319 (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1320 (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1321
1322 RREG32(RADEON_TV_DAC_CNTL);
1323 mdelay(6);
1324
1325 tmp = RREG32(RADEON_TV_DAC_CNTL);
1326 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1327 found = true;
1328 DRM_DEBUG_KMS("S-video TV connection detected\n");
1329 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1330 found = true;
1331 DRM_DEBUG_KMS("Composite TV connection detected\n");
1332 }
1333
1334 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1335 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1336 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1337 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1338 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1339 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1340 return found;
1341 }
1342
radeon_legacy_tv_detect(struct drm_encoder * encoder,struct drm_connector * connector)1343 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1344 struct drm_connector *connector)
1345 {
1346 struct drm_device *dev = encoder->dev;
1347 struct radeon_device *rdev = dev->dev_private;
1348 uint32_t tv_dac_cntl, dac_cntl2;
1349 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1350 bool found = false;
1351
1352 if (ASIC_IS_R300(rdev))
1353 return r300_legacy_tv_detect(encoder, connector);
1354
1355 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1356 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1357 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1358 config_cntl = RREG32(RADEON_CONFIG_CNTL);
1359 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1360
1361 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1362 WREG32(RADEON_DAC_CNTL2, tmp);
1363
1364 tmp = tv_master_cntl | RADEON_TV_ON;
1365 tmp &= ~(RADEON_TV_ASYNC_RST |
1366 RADEON_RESTART_PHASE_FIX |
1367 RADEON_CRT_FIFO_CE_EN |
1368 RADEON_TV_FIFO_CE_EN |
1369 RADEON_RE_SYNC_NOW_SEL_MASK);
1370 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1371 WREG32(RADEON_TV_MASTER_CNTL, tmp);
1372
1373 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1374 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1375 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1376
1377 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1378 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1379 else
1380 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1381 WREG32(RADEON_TV_DAC_CNTL, tmp);
1382
1383 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1384 RADEON_RED_MX_FORCE_DAC_DATA |
1385 RADEON_GRN_MX_FORCE_DAC_DATA |
1386 RADEON_BLU_MX_FORCE_DAC_DATA |
1387 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1388 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1389
1390 mdelay(3);
1391 tmp = RREG32(RADEON_TV_DAC_CNTL);
1392 if (tmp & RADEON_TV_DAC_GDACDET) {
1393 found = true;
1394 DRM_DEBUG_KMS("S-video TV connection detected\n");
1395 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1396 found = true;
1397 DRM_DEBUG_KMS("Composite TV connection detected\n");
1398 }
1399
1400 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1401 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1402 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1403 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1404 return found;
1405 }
1406
radeon_legacy_tv_dac_detect(struct drm_encoder * encoder,struct drm_connector * connector)1407 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1408 struct drm_connector *connector)
1409 {
1410 struct drm_device *dev = encoder->dev;
1411 struct radeon_device *rdev = dev->dev_private;
1412 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1413 uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1414 enum drm_connector_status found = connector_status_disconnected;
1415 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1416 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1417 bool color = true;
1418 struct drm_crtc *crtc;
1419
1420 /* find out if crtc2 is in use or if this encoder is using it */
1421 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1422 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1423 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1424 if (encoder->crtc != crtc) {
1425 return connector_status_disconnected;
1426 }
1427 }
1428 }
1429
1430 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1431 connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1432 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1433 bool tv_detect;
1434
1435 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1436 return connector_status_disconnected;
1437
1438 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1439 if (tv_detect && tv_dac)
1440 found = connector_status_connected;
1441 return found;
1442 }
1443
1444 /* don't probe if the encoder is being used for something else not CRT related */
1445 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1446 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1447 return connector_status_disconnected;
1448 }
1449
1450 /* save the regs we need */
1451 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1452 gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1453 disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1454 disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1455 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1456 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1457 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1458 dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1459
1460 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1461 | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1462 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1463
1464 if (ASIC_IS_R300(rdev))
1465 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1466
1467 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1468 tmp |= RADEON_CRTC2_CRT2_ON |
1469 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1470
1471 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1472
1473 if (ASIC_IS_R300(rdev)) {
1474 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1475 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1476 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1477 } else {
1478 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1479 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1480 }
1481
1482 tmp = RADEON_TV_DAC_NBLANK |
1483 RADEON_TV_DAC_NHOLD |
1484 RADEON_TV_MONITOR_DETECT_EN |
1485 RADEON_TV_DAC_STD_PS2;
1486
1487 WREG32(RADEON_TV_DAC_CNTL, tmp);
1488
1489 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1490 RADEON_DAC2_FORCE_DATA_EN;
1491
1492 if (color)
1493 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1494 else
1495 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1496
1497 if (ASIC_IS_R300(rdev))
1498 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1499 else
1500 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1501
1502 WREG32(RADEON_DAC_EXT_CNTL, tmp);
1503
1504 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1505 WREG32(RADEON_DAC_CNTL2, tmp);
1506
1507 mdelay(10);
1508
1509 if (ASIC_IS_R300(rdev)) {
1510 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1511 found = connector_status_connected;
1512 } else {
1513 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1514 found = connector_status_connected;
1515 }
1516
1517 /* restore regs we used */
1518 WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1519 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1520 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1521 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1522
1523 if (ASIC_IS_R300(rdev)) {
1524 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1525 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1526 } else {
1527 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1528 }
1529 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1530
1531 return found;
1532
1533 }
1534
1535 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1536 .dpms = radeon_legacy_tv_dac_dpms,
1537 .mode_fixup = radeon_legacy_mode_fixup,
1538 .prepare = radeon_legacy_tv_dac_prepare,
1539 .mode_set = radeon_legacy_tv_dac_mode_set,
1540 .commit = radeon_legacy_tv_dac_commit,
1541 .detect = radeon_legacy_tv_dac_detect,
1542 .disable = radeon_legacy_encoder_disable,
1543 };
1544
1545
1546 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1547 .destroy = radeon_enc_destroy,
1548 };
1549
1550
radeon_legacy_get_tmds_info(struct radeon_encoder * encoder)1551 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1552 {
1553 struct drm_device *dev = encoder->base.dev;
1554 struct radeon_device *rdev = dev->dev_private;
1555 struct radeon_encoder_int_tmds *tmds = NULL;
1556 bool ret;
1557
1558 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1559
1560 if (!tmds)
1561 return NULL;
1562
1563 if (rdev->is_atom_bios)
1564 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1565 else
1566 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1567
1568 if (ret == false)
1569 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1570
1571 return tmds;
1572 }
1573
radeon_legacy_get_ext_tmds_info(struct radeon_encoder * encoder)1574 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1575 {
1576 struct drm_device *dev = encoder->base.dev;
1577 struct radeon_device *rdev = dev->dev_private;
1578 struct radeon_encoder_ext_tmds *tmds = NULL;
1579 bool ret;
1580
1581 if (rdev->is_atom_bios)
1582 return NULL;
1583
1584 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1585
1586 if (!tmds)
1587 return NULL;
1588
1589 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1590
1591 if (ret == false)
1592 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1593
1594 return tmds;
1595 }
1596
1597 void
radeon_add_legacy_encoder(struct drm_device * dev,uint32_t encoder_enum,uint32_t supported_device)1598 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1599 {
1600 struct radeon_device *rdev = dev->dev_private;
1601 struct drm_encoder *encoder;
1602 struct radeon_encoder *radeon_encoder;
1603
1604 /* see if we already added it */
1605 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1606 radeon_encoder = to_radeon_encoder(encoder);
1607 if (radeon_encoder->encoder_enum == encoder_enum) {
1608 radeon_encoder->devices |= supported_device;
1609 return;
1610 }
1611
1612 }
1613
1614 /* add a new one */
1615 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1616 if (!radeon_encoder)
1617 return;
1618
1619 encoder = &radeon_encoder->base;
1620 if (rdev->flags & RADEON_SINGLE_CRTC)
1621 encoder->possible_crtcs = 0x1;
1622 else
1623 encoder->possible_crtcs = 0x3;
1624
1625 radeon_encoder->enc_priv = NULL;
1626
1627 radeon_encoder->encoder_enum = encoder_enum;
1628 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1629 radeon_encoder->devices = supported_device;
1630 radeon_encoder->rmx_type = RMX_OFF;
1631
1632 switch (radeon_encoder->encoder_id) {
1633 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1634 encoder->possible_crtcs = 0x1;
1635 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1636 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1637 if (rdev->is_atom_bios)
1638 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1639 else
1640 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1641 radeon_encoder->rmx_type = RMX_FULL;
1642 break;
1643 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1644 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1645 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1646 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1647 break;
1648 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1649 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1650 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1651 if (rdev->is_atom_bios)
1652 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1653 else
1654 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1655 break;
1656 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1657 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1658 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1659 if (rdev->is_atom_bios)
1660 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1661 else
1662 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1663 break;
1664 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1665 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1666 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1667 if (!rdev->is_atom_bios)
1668 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1669 break;
1670 }
1671 }
1672