1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/kernel.h>
29 #include "drmP.h"
30 #include "radeon.h"
31 #include "r600d.h"
32 #include "r600_reg_safe.h"
33
34 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
35 struct radeon_cs_reloc **cs_reloc);
36 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37 struct radeon_cs_reloc **cs_reloc);
38 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
40 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
41
42
43 struct r600_cs_track {
44 /* configuration we miror so that we use same code btw kms/ums */
45 u32 group_size;
46 u32 nbanks;
47 u32 npipes;
48 /* value we track */
49 u32 sq_config;
50 u32 nsamples;
51 u32 cb_color_base_last[8];
52 struct radeon_bo *cb_color_bo[8];
53 u64 cb_color_bo_mc[8];
54 u32 cb_color_bo_offset[8];
55 struct radeon_bo *cb_color_frag_bo[8]; /* unused */
56 struct radeon_bo *cb_color_tile_bo[8]; /* unused */
57 u32 cb_color_info[8];
58 u32 cb_color_view[8];
59 u32 cb_color_size_idx[8]; /* unused */
60 u32 cb_target_mask;
61 u32 cb_shader_mask; /* unused */
62 u32 cb_color_size[8];
63 u32 vgt_strmout_en;
64 u32 vgt_strmout_buffer_en;
65 struct radeon_bo *vgt_strmout_bo[4];
66 u64 vgt_strmout_bo_mc[4]; /* unused */
67 u32 vgt_strmout_bo_offset[4];
68 u32 vgt_strmout_size[4];
69 u32 db_depth_control;
70 u32 db_depth_info;
71 u32 db_depth_size_idx;
72 u32 db_depth_view;
73 u32 db_depth_size;
74 u32 db_offset;
75 struct radeon_bo *db_bo;
76 u64 db_bo_mc;
77 bool sx_misc_kill_all_prims;
78 bool cb_dirty;
79 bool db_dirty;
80 bool streamout_dirty;
81 struct radeon_bo *htile_bo;
82 u64 htile_offset;
83 u32 htile_surface;
84 };
85
86 #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
87 #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
88 #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 }
89 #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
90 #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 }
91 #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
92 #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
93 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
94
95 struct gpu_formats {
96 unsigned blockwidth;
97 unsigned blockheight;
98 unsigned blocksize;
99 unsigned valid_color;
100 enum radeon_family min_family;
101 };
102
103 static const struct gpu_formats color_formats_table[] = {
104 /* 8 bit */
105 FMT_8_BIT(V_038004_COLOR_8, 1),
106 FMT_8_BIT(V_038004_COLOR_4_4, 1),
107 FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
108 FMT_8_BIT(V_038004_FMT_1, 0),
109
110 /* 16-bit */
111 FMT_16_BIT(V_038004_COLOR_16, 1),
112 FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
113 FMT_16_BIT(V_038004_COLOR_8_8, 1),
114 FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
115 FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
116 FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
117 FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
118 FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
119
120 /* 24-bit */
121 FMT_24_BIT(V_038004_FMT_8_8_8),
122
123 /* 32-bit */
124 FMT_32_BIT(V_038004_COLOR_32, 1),
125 FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
126 FMT_32_BIT(V_038004_COLOR_16_16, 1),
127 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
128 FMT_32_BIT(V_038004_COLOR_8_24, 1),
129 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
130 FMT_32_BIT(V_038004_COLOR_24_8, 1),
131 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
132 FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
133 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
134 FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
135 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
136 FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
137 FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
138 FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
139 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
140 FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
141 FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
142
143 /* 48-bit */
144 FMT_48_BIT(V_038004_FMT_16_16_16),
145 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
146
147 /* 64-bit */
148 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
149 FMT_64_BIT(V_038004_COLOR_32_32, 1),
150 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
151 FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
152 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
153
154 FMT_96_BIT(V_038004_FMT_32_32_32),
155 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
156
157 /* 128-bit */
158 FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
159 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
160
161 [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
162 [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
163
164 /* block compressed formats */
165 [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
166 [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
167 [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
168 [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
169 [V_038004_FMT_BC5] = { 4, 4, 16, 0},
170 [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
171 [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
172
173 /* The other Evergreen formats */
174 [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
175 };
176
r600_fmt_is_valid_color(u32 format)177 bool r600_fmt_is_valid_color(u32 format)
178 {
179 if (format >= ARRAY_SIZE(color_formats_table))
180 return false;
181
182 if (color_formats_table[format].valid_color)
183 return true;
184
185 return false;
186 }
187
r600_fmt_is_valid_texture(u32 format,enum radeon_family family)188 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
189 {
190 if (format >= ARRAY_SIZE(color_formats_table))
191 return false;
192
193 if (family < color_formats_table[format].min_family)
194 return false;
195
196 if (color_formats_table[format].blockwidth > 0)
197 return true;
198
199 return false;
200 }
201
r600_fmt_get_blocksize(u32 format)202 int r600_fmt_get_blocksize(u32 format)
203 {
204 if (format >= ARRAY_SIZE(color_formats_table))
205 return 0;
206
207 return color_formats_table[format].blocksize;
208 }
209
r600_fmt_get_nblocksx(u32 format,u32 w)210 int r600_fmt_get_nblocksx(u32 format, u32 w)
211 {
212 unsigned bw;
213
214 if (format >= ARRAY_SIZE(color_formats_table))
215 return 0;
216
217 bw = color_formats_table[format].blockwidth;
218 if (bw == 0)
219 return 0;
220
221 return (w + bw - 1) / bw;
222 }
223
r600_fmt_get_nblocksy(u32 format,u32 h)224 int r600_fmt_get_nblocksy(u32 format, u32 h)
225 {
226 unsigned bh;
227
228 if (format >= ARRAY_SIZE(color_formats_table))
229 return 0;
230
231 bh = color_formats_table[format].blockheight;
232 if (bh == 0)
233 return 0;
234
235 return (h + bh - 1) / bh;
236 }
237
238 struct array_mode_checker {
239 int array_mode;
240 u32 group_size;
241 u32 nbanks;
242 u32 npipes;
243 u32 nsamples;
244 u32 blocksize;
245 };
246
247 /* returns alignment in pixels for pitch/height/depth and bytes for base */
r600_get_array_mode_alignment(struct array_mode_checker * values,u32 * pitch_align,u32 * height_align,u32 * depth_align,u64 * base_align)248 static int r600_get_array_mode_alignment(struct array_mode_checker *values,
249 u32 *pitch_align,
250 u32 *height_align,
251 u32 *depth_align,
252 u64 *base_align)
253 {
254 u32 tile_width = 8;
255 u32 tile_height = 8;
256 u32 macro_tile_width = values->nbanks;
257 u32 macro_tile_height = values->npipes;
258 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
259 u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
260
261 switch (values->array_mode) {
262 case ARRAY_LINEAR_GENERAL:
263 /* technically tile_width/_height for pitch/height */
264 *pitch_align = 1; /* tile_width */
265 *height_align = 1; /* tile_height */
266 *depth_align = 1;
267 *base_align = 1;
268 break;
269 case ARRAY_LINEAR_ALIGNED:
270 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
271 *height_align = 1;
272 *depth_align = 1;
273 *base_align = values->group_size;
274 break;
275 case ARRAY_1D_TILED_THIN1:
276 *pitch_align = max((u32)tile_width,
277 (u32)(values->group_size /
278 (tile_height * values->blocksize * values->nsamples)));
279 *height_align = tile_height;
280 *depth_align = 1;
281 *base_align = values->group_size;
282 break;
283 case ARRAY_2D_TILED_THIN1:
284 *pitch_align = max((u32)macro_tile_width * tile_width,
285 (u32)((values->group_size * values->nbanks) /
286 (values->blocksize * values->nsamples * tile_width)));
287 *height_align = macro_tile_height * tile_height;
288 *depth_align = 1;
289 *base_align = max(macro_tile_bytes,
290 (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
291 break;
292 default:
293 return -EINVAL;
294 }
295
296 return 0;
297 }
298
r600_cs_track_init(struct r600_cs_track * track)299 static void r600_cs_track_init(struct r600_cs_track *track)
300 {
301 int i;
302
303 /* assume DX9 mode */
304 track->sq_config = DX9_CONSTS;
305 for (i = 0; i < 8; i++) {
306 track->cb_color_base_last[i] = 0;
307 track->cb_color_size[i] = 0;
308 track->cb_color_size_idx[i] = 0;
309 track->cb_color_info[i] = 0;
310 track->cb_color_view[i] = 0xFFFFFFFF;
311 track->cb_color_bo[i] = NULL;
312 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
313 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
314 }
315 track->cb_target_mask = 0xFFFFFFFF;
316 track->cb_shader_mask = 0xFFFFFFFF;
317 track->cb_dirty = true;
318 track->db_bo = NULL;
319 track->db_bo_mc = 0xFFFFFFFF;
320 /* assume the biggest format and that htile is enabled */
321 track->db_depth_info = 7 | (1 << 25);
322 track->db_depth_view = 0xFFFFC000;
323 track->db_depth_size = 0xFFFFFFFF;
324 track->db_depth_size_idx = 0;
325 track->db_depth_control = 0xFFFFFFFF;
326 track->db_dirty = true;
327 track->htile_bo = NULL;
328 track->htile_offset = 0xFFFFFFFF;
329 track->htile_surface = 0;
330
331 for (i = 0; i < 4; i++) {
332 track->vgt_strmout_size[i] = 0;
333 track->vgt_strmout_bo[i] = NULL;
334 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
335 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
336 }
337 track->streamout_dirty = true;
338 track->sx_misc_kill_all_prims = false;
339 }
340
r600_cs_track_validate_cb(struct radeon_cs_parser * p,int i)341 static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
342 {
343 struct r600_cs_track *track = p->track;
344 u32 slice_tile_max, size, tmp;
345 u32 height, height_align, pitch, pitch_align, depth_align;
346 u64 base_offset, base_align;
347 struct array_mode_checker array_check;
348 volatile u32 *ib = p->ib->ptr;
349 unsigned array_mode;
350 u32 format;
351
352 if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
353 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
354 return -EINVAL;
355 }
356 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
357 format = G_0280A0_FORMAT(track->cb_color_info[i]);
358 if (!r600_fmt_is_valid_color(format)) {
359 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
360 __func__, __LINE__, format,
361 i, track->cb_color_info[i]);
362 return -EINVAL;
363 }
364 /* pitch in pixels */
365 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
366 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
367 slice_tile_max *= 64;
368 height = slice_tile_max / pitch;
369 if (height > 8192)
370 height = 8192;
371 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
372
373 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
374 array_check.array_mode = array_mode;
375 array_check.group_size = track->group_size;
376 array_check.nbanks = track->nbanks;
377 array_check.npipes = track->npipes;
378 array_check.nsamples = track->nsamples;
379 array_check.blocksize = r600_fmt_get_blocksize(format);
380 if (r600_get_array_mode_alignment(&array_check,
381 &pitch_align, &height_align, &depth_align, &base_align)) {
382 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
383 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
384 track->cb_color_info[i]);
385 return -EINVAL;
386 }
387 switch (array_mode) {
388 case V_0280A0_ARRAY_LINEAR_GENERAL:
389 break;
390 case V_0280A0_ARRAY_LINEAR_ALIGNED:
391 break;
392 case V_0280A0_ARRAY_1D_TILED_THIN1:
393 /* avoid breaking userspace */
394 if (height > 7)
395 height &= ~0x7;
396 break;
397 case V_0280A0_ARRAY_2D_TILED_THIN1:
398 break;
399 default:
400 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
401 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
402 track->cb_color_info[i]);
403 return -EINVAL;
404 }
405
406 if (!IS_ALIGNED(pitch, pitch_align)) {
407 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
408 __func__, __LINE__, pitch, pitch_align, array_mode);
409 return -EINVAL;
410 }
411 if (!IS_ALIGNED(height, height_align)) {
412 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
413 __func__, __LINE__, height, height_align, array_mode);
414 return -EINVAL;
415 }
416 if (!IS_ALIGNED(base_offset, base_align)) {
417 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
418 base_offset, base_align, array_mode);
419 return -EINVAL;
420 }
421
422 /* check offset */
423 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * r600_fmt_get_blocksize(format);
424 switch (array_mode) {
425 default:
426 case V_0280A0_ARRAY_LINEAR_GENERAL:
427 case V_0280A0_ARRAY_LINEAR_ALIGNED:
428 tmp += track->cb_color_view[i] & 0xFF;
429 break;
430 case V_0280A0_ARRAY_1D_TILED_THIN1:
431 case V_0280A0_ARRAY_2D_TILED_THIN1:
432 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
433 break;
434 }
435 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
436 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
437 /* the initial DDX does bad things with the CB size occasionally */
438 /* it rounds up height too far for slice tile max but the BO is smaller */
439 /* r600c,g also seem to flush at bad times in some apps resulting in
440 * bogus values here. So for linear just allow anything to avoid breaking
441 * broken userspace.
442 */
443 } else {
444 dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big (%d %d) (%d %d %d)\n",
445 __func__, i, array_mode,
446 track->cb_color_bo_offset[i], tmp,
447 radeon_bo_size(track->cb_color_bo[i]),
448 pitch, height, r600_fmt_get_nblocksx(format, pitch),
449 r600_fmt_get_nblocksy(format, height),
450 r600_fmt_get_blocksize(format));
451 return -EINVAL;
452 }
453 }
454 /* limit max tile */
455 tmp = (height * pitch) >> 6;
456 if (tmp < slice_tile_max)
457 slice_tile_max = tmp;
458 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
459 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
460 ib[track->cb_color_size_idx[i]] = tmp;
461 return 0;
462 }
463
r600_cs_track_validate_db(struct radeon_cs_parser * p)464 static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
465 {
466 struct r600_cs_track *track = p->track;
467 u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;
468 u32 height_align, pitch_align, depth_align;
469 u32 pitch = 8192;
470 u32 height = 8192;
471 u64 base_offset, base_align;
472 struct array_mode_checker array_check;
473 int array_mode;
474 volatile u32 *ib = p->ib->ptr;
475
476
477 if (track->db_bo == NULL) {
478 dev_warn(p->dev, "z/stencil with no depth buffer\n");
479 return -EINVAL;
480 }
481 switch (G_028010_FORMAT(track->db_depth_info)) {
482 case V_028010_DEPTH_16:
483 bpe = 2;
484 break;
485 case V_028010_DEPTH_X8_24:
486 case V_028010_DEPTH_8_24:
487 case V_028010_DEPTH_X8_24_FLOAT:
488 case V_028010_DEPTH_8_24_FLOAT:
489 case V_028010_DEPTH_32_FLOAT:
490 bpe = 4;
491 break;
492 case V_028010_DEPTH_X24_8_32_FLOAT:
493 bpe = 8;
494 break;
495 default:
496 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
497 return -EINVAL;
498 }
499 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
500 if (!track->db_depth_size_idx) {
501 dev_warn(p->dev, "z/stencil buffer size not set\n");
502 return -EINVAL;
503 }
504 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
505 tmp = (tmp / bpe) >> 6;
506 if (!tmp) {
507 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
508 track->db_depth_size, bpe, track->db_offset,
509 radeon_bo_size(track->db_bo));
510 return -EINVAL;
511 }
512 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
513 } else {
514 size = radeon_bo_size(track->db_bo);
515 /* pitch in pixels */
516 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
517 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
518 slice_tile_max *= 64;
519 height = slice_tile_max / pitch;
520 if (height > 8192)
521 height = 8192;
522 base_offset = track->db_bo_mc + track->db_offset;
523 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
524 array_check.array_mode = array_mode;
525 array_check.group_size = track->group_size;
526 array_check.nbanks = track->nbanks;
527 array_check.npipes = track->npipes;
528 array_check.nsamples = track->nsamples;
529 array_check.blocksize = bpe;
530 if (r600_get_array_mode_alignment(&array_check,
531 &pitch_align, &height_align, &depth_align, &base_align)) {
532 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
533 G_028010_ARRAY_MODE(track->db_depth_info),
534 track->db_depth_info);
535 return -EINVAL;
536 }
537 switch (array_mode) {
538 case V_028010_ARRAY_1D_TILED_THIN1:
539 /* don't break userspace */
540 height &= ~0x7;
541 break;
542 case V_028010_ARRAY_2D_TILED_THIN1:
543 break;
544 default:
545 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
546 G_028010_ARRAY_MODE(track->db_depth_info),
547 track->db_depth_info);
548 return -EINVAL;
549 }
550
551 if (!IS_ALIGNED(pitch, pitch_align)) {
552 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
553 __func__, __LINE__, pitch, pitch_align, array_mode);
554 return -EINVAL;
555 }
556 if (!IS_ALIGNED(height, height_align)) {
557 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
558 __func__, __LINE__, height, height_align, array_mode);
559 return -EINVAL;
560 }
561 if (!IS_ALIGNED(base_offset, base_align)) {
562 dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__,
563 base_offset, base_align, array_mode);
564 return -EINVAL;
565 }
566
567 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
568 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
569 tmp = ntiles * bpe * 64 * nviews;
570 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
571 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
572 array_mode,
573 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
574 radeon_bo_size(track->db_bo));
575 return -EINVAL;
576 }
577 }
578
579 /* hyperz */
580 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
581 unsigned long size;
582 unsigned nbx, nby;
583
584 if (track->htile_bo == NULL) {
585 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
586 __func__, __LINE__, track->db_depth_info);
587 return -EINVAL;
588 }
589 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
590 dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",
591 __func__, __LINE__, track->db_depth_size);
592 return -EINVAL;
593 }
594
595 nbx = pitch;
596 nby = height;
597 if (G_028D24_LINEAR(track->htile_surface)) {
598 /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
599 nbx = round_up(nbx, 16 * 8);
600 /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
601 nby = round_up(nby, track->npipes * 8);
602 } else {
603 /* htile widht & nby (8 or 4) make 2 bits number */
604 tmp = track->htile_surface & 3;
605 /* align is htile align * 8, htile align vary according to
606 * number of pipe and tile width and nby
607 */
608 switch (track->npipes) {
609 case 8:
610 switch (tmp) {
611 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
612 nbx = round_up(nbx, 64 * 8);
613 nby = round_up(nby, 64 * 8);
614 break;
615 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
616 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
617 nbx = round_up(nbx, 64 * 8);
618 nby = round_up(nby, 32 * 8);
619 break;
620 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
621 nbx = round_up(nbx, 32 * 8);
622 nby = round_up(nby, 32 * 8);
623 break;
624 default:
625 return -EINVAL;
626 }
627 break;
628 case 4:
629 switch (tmp) {
630 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
631 nbx = round_up(nbx, 64 * 8);
632 nby = round_up(nby, 32 * 8);
633 break;
634 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
635 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
636 nbx = round_up(nbx, 32 * 8);
637 nby = round_up(nby, 32 * 8);
638 break;
639 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
640 nbx = round_up(nbx, 32 * 8);
641 nby = round_up(nby, 16 * 8);
642 break;
643 default:
644 return -EINVAL;
645 }
646 break;
647 case 2:
648 switch (tmp) {
649 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
650 nbx = round_up(nbx, 32 * 8);
651 nby = round_up(nby, 32 * 8);
652 break;
653 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
654 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
655 nbx = round_up(nbx, 32 * 8);
656 nby = round_up(nby, 16 * 8);
657 break;
658 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
659 nbx = round_up(nbx, 16 * 8);
660 nby = round_up(nby, 16 * 8);
661 break;
662 default:
663 return -EINVAL;
664 }
665 break;
666 case 1:
667 switch (tmp) {
668 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
669 nbx = round_up(nbx, 32 * 8);
670 nby = round_up(nby, 16 * 8);
671 break;
672 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
673 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
674 nbx = round_up(nbx, 16 * 8);
675 nby = round_up(nby, 16 * 8);
676 break;
677 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
678 nbx = round_up(nbx, 16 * 8);
679 nby = round_up(nby, 8 * 8);
680 break;
681 default:
682 return -EINVAL;
683 }
684 break;
685 default:
686 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
687 __func__, __LINE__, track->npipes);
688 return -EINVAL;
689 }
690 }
691 /* compute number of htile */
692 nbx = G_028D24_HTILE_WIDTH(track->htile_surface) ? nbx / 8 : nbx / 4;
693 nby = G_028D24_HTILE_HEIGHT(track->htile_surface) ? nby / 8 : nby / 4;
694 size = nbx * nby * 4;
695 size += track->htile_offset;
696
697 if (size > radeon_bo_size(track->htile_bo)) {
698 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
699 __func__, __LINE__, radeon_bo_size(track->htile_bo),
700 size, nbx, nby);
701 return -EINVAL;
702 }
703 }
704
705 track->db_dirty = false;
706 return 0;
707 }
708
r600_cs_track_check(struct radeon_cs_parser * p)709 static int r600_cs_track_check(struct radeon_cs_parser *p)
710 {
711 struct r600_cs_track *track = p->track;
712 u32 tmp;
713 int r, i;
714
715 /* on legacy kernel we don't perform advanced check */
716 if (p->rdev == NULL)
717 return 0;
718
719 /* check streamout */
720 if (track->streamout_dirty && track->vgt_strmout_en) {
721 for (i = 0; i < 4; i++) {
722 if (track->vgt_strmout_buffer_en & (1 << i)) {
723 if (track->vgt_strmout_bo[i]) {
724 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
725 (u64)track->vgt_strmout_size[i];
726 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
727 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
728 i, offset,
729 radeon_bo_size(track->vgt_strmout_bo[i]));
730 return -EINVAL;
731 }
732 } else {
733 dev_warn(p->dev, "No buffer for streamout %d\n", i);
734 return -EINVAL;
735 }
736 }
737 }
738 track->streamout_dirty = false;
739 }
740
741 if (track->sx_misc_kill_all_prims)
742 return 0;
743
744 /* check that we have a cb for each enabled target, we don't check
745 * shader_mask because it seems mesa isn't always setting it :(
746 */
747 if (track->cb_dirty) {
748 tmp = track->cb_target_mask;
749 for (i = 0; i < 8; i++) {
750 u32 format = G_0280A0_FORMAT(track->cb_color_info[i]);
751
752 if (format != V_0280A0_COLOR_INVALID &&
753 (tmp >> (i * 4)) & 0xF) {
754 /* at least one component is enabled */
755 if (track->cb_color_bo[i] == NULL) {
756 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
757 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
758 return -EINVAL;
759 }
760 /* perform rewrite of CB_COLOR[0-7]_SIZE */
761 r = r600_cs_track_validate_cb(p, i);
762 if (r)
763 return r;
764 }
765 }
766 track->cb_dirty = false;
767 }
768
769 /* Check depth buffer */
770 if (track->db_dirty && (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
771 G_028800_Z_ENABLE(track->db_depth_control))) {
772 r = r600_cs_track_validate_db(p);
773 if (r)
774 return r;
775 }
776
777 return 0;
778 }
779
780 /**
781 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
782 * @parser: parser structure holding parsing context.
783 * @pkt: where to store packet informations
784 *
785 * Assume that chunk_ib_index is properly set. Will return -EINVAL
786 * if packet is bigger than remaining ib size. or if packets is unknown.
787 **/
r600_cs_packet_parse(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx)788 int r600_cs_packet_parse(struct radeon_cs_parser *p,
789 struct radeon_cs_packet *pkt,
790 unsigned idx)
791 {
792 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
793 uint32_t header;
794
795 if (idx >= ib_chunk->length_dw) {
796 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
797 idx, ib_chunk->length_dw);
798 return -EINVAL;
799 }
800 header = radeon_get_ib_value(p, idx);
801 pkt->idx = idx;
802 pkt->type = CP_PACKET_GET_TYPE(header);
803 pkt->count = CP_PACKET_GET_COUNT(header);
804 pkt->one_reg_wr = 0;
805 switch (pkt->type) {
806 case PACKET_TYPE0:
807 pkt->reg = CP_PACKET0_GET_REG(header);
808 break;
809 case PACKET_TYPE3:
810 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
811 break;
812 case PACKET_TYPE2:
813 pkt->count = -1;
814 break;
815 default:
816 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
817 return -EINVAL;
818 }
819 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
820 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
821 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
822 return -EINVAL;
823 }
824 return 0;
825 }
826
827 /**
828 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
829 * @parser: parser structure holding parsing context.
830 * @data: pointer to relocation data
831 * @offset_start: starting offset
832 * @offset_mask: offset mask (to align start offset on)
833 * @reloc: reloc informations
834 *
835 * Check next packet is relocation packet3, do bo validation and compute
836 * GPU offset using the provided start.
837 **/
r600_cs_packet_next_reloc_mm(struct radeon_cs_parser * p,struct radeon_cs_reloc ** cs_reloc)838 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
839 struct radeon_cs_reloc **cs_reloc)
840 {
841 struct radeon_cs_chunk *relocs_chunk;
842 struct radeon_cs_packet p3reloc;
843 unsigned idx;
844 int r;
845
846 if (p->chunk_relocs_idx == -1) {
847 DRM_ERROR("No relocation chunk !\n");
848 return -EINVAL;
849 }
850 *cs_reloc = NULL;
851 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
852 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
853 if (r) {
854 return r;
855 }
856 p->idx += p3reloc.count + 2;
857 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
858 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
859 p3reloc.idx);
860 return -EINVAL;
861 }
862 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
863 if (idx >= relocs_chunk->length_dw) {
864 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
865 idx, relocs_chunk->length_dw);
866 return -EINVAL;
867 }
868 /* FIXME: we assume reloc size is 4 dwords */
869 *cs_reloc = p->relocs_ptr[(idx / 4)];
870 return 0;
871 }
872
873 /**
874 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
875 * @parser: parser structure holding parsing context.
876 * @data: pointer to relocation data
877 * @offset_start: starting offset
878 * @offset_mask: offset mask (to align start offset on)
879 * @reloc: reloc informations
880 *
881 * Check next packet is relocation packet3, do bo validation and compute
882 * GPU offset using the provided start.
883 **/
r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser * p,struct radeon_cs_reloc ** cs_reloc)884 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
885 struct radeon_cs_reloc **cs_reloc)
886 {
887 struct radeon_cs_chunk *relocs_chunk;
888 struct radeon_cs_packet p3reloc;
889 unsigned idx;
890 int r;
891
892 if (p->chunk_relocs_idx == -1) {
893 DRM_ERROR("No relocation chunk !\n");
894 return -EINVAL;
895 }
896 *cs_reloc = NULL;
897 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
898 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
899 if (r) {
900 return r;
901 }
902 p->idx += p3reloc.count + 2;
903 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
904 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
905 p3reloc.idx);
906 return -EINVAL;
907 }
908 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
909 if (idx >= relocs_chunk->length_dw) {
910 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
911 idx, relocs_chunk->length_dw);
912 return -EINVAL;
913 }
914 *cs_reloc = p->relocs;
915 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
916 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
917 return 0;
918 }
919
920 /**
921 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
922 * @parser: parser structure holding parsing context.
923 *
924 * Check next packet is relocation packet3, do bo validation and compute
925 * GPU offset using the provided start.
926 **/
r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser * p)927 static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
928 {
929 struct radeon_cs_packet p3reloc;
930 int r;
931
932 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
933 if (r) {
934 return 0;
935 }
936 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
937 return 0;
938 }
939 return 1;
940 }
941
942 /**
943 * r600_cs_packet_next_vline() - parse userspace VLINE packet
944 * @parser: parser structure holding parsing context.
945 *
946 * Userspace sends a special sequence for VLINE waits.
947 * PACKET0 - VLINE_START_END + value
948 * PACKET3 - WAIT_REG_MEM poll vline status reg
949 * RELOC (P3) - crtc_id in reloc.
950 *
951 * This function parses this and relocates the VLINE START END
952 * and WAIT_REG_MEM packets to the correct crtc.
953 * It also detects a switched off crtc and nulls out the
954 * wait in that case.
955 */
r600_cs_packet_parse_vline(struct radeon_cs_parser * p)956 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
957 {
958 struct drm_mode_object *obj;
959 struct drm_crtc *crtc;
960 struct radeon_crtc *radeon_crtc;
961 struct radeon_cs_packet p3reloc, wait_reg_mem;
962 int crtc_id;
963 int r;
964 uint32_t header, h_idx, reg, wait_reg_mem_info;
965 volatile uint32_t *ib;
966
967 ib = p->ib->ptr;
968
969 /* parse the WAIT_REG_MEM */
970 r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
971 if (r)
972 return r;
973
974 /* check its a WAIT_REG_MEM */
975 if (wait_reg_mem.type != PACKET_TYPE3 ||
976 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
977 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
978 return -EINVAL;
979 }
980
981 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
982 /* bit 4 is reg (0) or mem (1) */
983 if (wait_reg_mem_info & 0x10) {
984 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
985 return -EINVAL;
986 }
987 /* waiting for value to be equal */
988 if ((wait_reg_mem_info & 0x7) != 0x3) {
989 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
990 return -EINVAL;
991 }
992 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
993 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
994 return -EINVAL;
995 }
996
997 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
998 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
999 return -EINVAL;
1000 }
1001
1002 /* jump over the NOP */
1003 r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
1004 if (r)
1005 return r;
1006
1007 h_idx = p->idx - 2;
1008 p->idx += wait_reg_mem.count + 2;
1009 p->idx += p3reloc.count + 2;
1010
1011 header = radeon_get_ib_value(p, h_idx);
1012 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
1013 reg = CP_PACKET0_GET_REG(header);
1014
1015 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1016 if (!obj) {
1017 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1018 return -EINVAL;
1019 }
1020 crtc = obj_to_crtc(obj);
1021 radeon_crtc = to_radeon_crtc(crtc);
1022 crtc_id = radeon_crtc->crtc_id;
1023
1024 if (!crtc->enabled) {
1025 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
1026 ib[h_idx + 2] = PACKET2(0);
1027 ib[h_idx + 3] = PACKET2(0);
1028 ib[h_idx + 4] = PACKET2(0);
1029 ib[h_idx + 5] = PACKET2(0);
1030 ib[h_idx + 6] = PACKET2(0);
1031 ib[h_idx + 7] = PACKET2(0);
1032 ib[h_idx + 8] = PACKET2(0);
1033 } else if (crtc_id == 1) {
1034 switch (reg) {
1035 case AVIVO_D1MODE_VLINE_START_END:
1036 header &= ~R600_CP_PACKET0_REG_MASK;
1037 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1038 break;
1039 default:
1040 DRM_ERROR("unknown crtc reloc\n");
1041 return -EINVAL;
1042 }
1043 ib[h_idx] = header;
1044 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
1045 }
1046
1047 return 0;
1048 }
1049
r600_packet0_check(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx,unsigned reg)1050 static int r600_packet0_check(struct radeon_cs_parser *p,
1051 struct radeon_cs_packet *pkt,
1052 unsigned idx, unsigned reg)
1053 {
1054 int r;
1055
1056 switch (reg) {
1057 case AVIVO_D1MODE_VLINE_START_END:
1058 r = r600_cs_packet_parse_vline(p);
1059 if (r) {
1060 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1061 idx, reg);
1062 return r;
1063 }
1064 break;
1065 default:
1066 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1067 reg, idx);
1068 return -EINVAL;
1069 }
1070 return 0;
1071 }
1072
r600_cs_parse_packet0(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt)1073 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
1074 struct radeon_cs_packet *pkt)
1075 {
1076 unsigned reg, i;
1077 unsigned idx;
1078 int r;
1079
1080 idx = pkt->idx + 1;
1081 reg = pkt->reg;
1082 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1083 r = r600_packet0_check(p, pkt, idx, reg);
1084 if (r) {
1085 return r;
1086 }
1087 }
1088 return 0;
1089 }
1090
1091 /**
1092 * r600_cs_check_reg() - check if register is authorized or not
1093 * @parser: parser structure holding parsing context
1094 * @reg: register we are testing
1095 * @idx: index into the cs buffer
1096 *
1097 * This function will test against r600_reg_safe_bm and return 0
1098 * if register is safe. If register is not flag as safe this function
1099 * will test it against a list of register needind special handling.
1100 */
r600_cs_check_reg(struct radeon_cs_parser * p,u32 reg,u32 idx)1101 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1102 {
1103 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
1104 struct radeon_cs_reloc *reloc;
1105 u32 m, i, tmp, *ib;
1106 int r;
1107
1108 i = (reg >> 7);
1109 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1110 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1111 return -EINVAL;
1112 }
1113 m = 1 << ((reg >> 2) & 31);
1114 if (!(r600_reg_safe_bm[i] & m))
1115 return 0;
1116 ib = p->ib->ptr;
1117 switch (reg) {
1118 /* force following reg to 0 in an attempt to disable out buffer
1119 * which will need us to better understand how it works to perform
1120 * security check on it (Jerome)
1121 */
1122 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
1123 case R_008C44_SQ_ESGS_RING_SIZE:
1124 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
1125 case R_008C54_SQ_ESTMP_RING_SIZE:
1126 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
1127 case R_008C74_SQ_FBUF_RING_SIZE:
1128 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
1129 case R_008C5C_SQ_GSTMP_RING_SIZE:
1130 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
1131 case R_008C4C_SQ_GSVS_RING_SIZE:
1132 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
1133 case R_008C6C_SQ_PSTMP_RING_SIZE:
1134 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
1135 case R_008C7C_SQ_REDUC_RING_SIZE:
1136 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
1137 case R_008C64_SQ_VSTMP_RING_SIZE:
1138 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
1139 /* get value to populate the IB don't remove */
1140 tmp =radeon_get_ib_value(p, idx);
1141 ib[idx] = 0;
1142 break;
1143 case SQ_CONFIG:
1144 track->sq_config = radeon_get_ib_value(p, idx);
1145 break;
1146 case R_028800_DB_DEPTH_CONTROL:
1147 track->db_depth_control = radeon_get_ib_value(p, idx);
1148 track->db_dirty = true;
1149 break;
1150 case R_028010_DB_DEPTH_INFO:
1151 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1152 r600_cs_packet_next_is_pkt3_nop(p)) {
1153 r = r600_cs_packet_next_reloc(p, &reloc);
1154 if (r) {
1155 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1156 "0x%04X\n", reg);
1157 return -EINVAL;
1158 }
1159 track->db_depth_info = radeon_get_ib_value(p, idx);
1160 ib[idx] &= C_028010_ARRAY_MODE;
1161 track->db_depth_info &= C_028010_ARRAY_MODE;
1162 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1163 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1164 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1165 } else {
1166 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1167 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1168 }
1169 } else {
1170 track->db_depth_info = radeon_get_ib_value(p, idx);
1171 }
1172 track->db_dirty = true;
1173 break;
1174 case R_028004_DB_DEPTH_VIEW:
1175 track->db_depth_view = radeon_get_ib_value(p, idx);
1176 track->db_dirty = true;
1177 break;
1178 case R_028000_DB_DEPTH_SIZE:
1179 track->db_depth_size = radeon_get_ib_value(p, idx);
1180 track->db_depth_size_idx = idx;
1181 track->db_dirty = true;
1182 break;
1183 case R_028AB0_VGT_STRMOUT_EN:
1184 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
1185 track->streamout_dirty = true;
1186 break;
1187 case R_028B20_VGT_STRMOUT_BUFFER_EN:
1188 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
1189 track->streamout_dirty = true;
1190 break;
1191 case VGT_STRMOUT_BUFFER_BASE_0:
1192 case VGT_STRMOUT_BUFFER_BASE_1:
1193 case VGT_STRMOUT_BUFFER_BASE_2:
1194 case VGT_STRMOUT_BUFFER_BASE_3:
1195 r = r600_cs_packet_next_reloc(p, &reloc);
1196 if (r) {
1197 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1198 "0x%04X\n", reg);
1199 return -EINVAL;
1200 }
1201 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1202 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1203 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1204 track->vgt_strmout_bo[tmp] = reloc->robj;
1205 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
1206 track->streamout_dirty = true;
1207 break;
1208 case VGT_STRMOUT_BUFFER_SIZE_0:
1209 case VGT_STRMOUT_BUFFER_SIZE_1:
1210 case VGT_STRMOUT_BUFFER_SIZE_2:
1211 case VGT_STRMOUT_BUFFER_SIZE_3:
1212 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1213 /* size in register is DWs, convert to bytes */
1214 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1215 track->streamout_dirty = true;
1216 break;
1217 case CP_COHER_BASE:
1218 r = r600_cs_packet_next_reloc(p, &reloc);
1219 if (r) {
1220 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1221 "0x%04X\n", reg);
1222 return -EINVAL;
1223 }
1224 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1225 break;
1226 case R_028238_CB_TARGET_MASK:
1227 track->cb_target_mask = radeon_get_ib_value(p, idx);
1228 track->cb_dirty = true;
1229 break;
1230 case R_02823C_CB_SHADER_MASK:
1231 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1232 break;
1233 case R_028C04_PA_SC_AA_CONFIG:
1234 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1235 track->nsamples = 1 << tmp;
1236 track->cb_dirty = true;
1237 break;
1238 case R_0280A0_CB_COLOR0_INFO:
1239 case R_0280A4_CB_COLOR1_INFO:
1240 case R_0280A8_CB_COLOR2_INFO:
1241 case R_0280AC_CB_COLOR3_INFO:
1242 case R_0280B0_CB_COLOR4_INFO:
1243 case R_0280B4_CB_COLOR5_INFO:
1244 case R_0280B8_CB_COLOR6_INFO:
1245 case R_0280BC_CB_COLOR7_INFO:
1246 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1247 r600_cs_packet_next_is_pkt3_nop(p)) {
1248 r = r600_cs_packet_next_reloc(p, &reloc);
1249 if (r) {
1250 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1251 return -EINVAL;
1252 }
1253 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1254 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1255 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1256 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1257 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1258 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1259 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1260 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1261 }
1262 } else {
1263 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1264 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1265 }
1266 track->cb_dirty = true;
1267 break;
1268 case R_028080_CB_COLOR0_VIEW:
1269 case R_028084_CB_COLOR1_VIEW:
1270 case R_028088_CB_COLOR2_VIEW:
1271 case R_02808C_CB_COLOR3_VIEW:
1272 case R_028090_CB_COLOR4_VIEW:
1273 case R_028094_CB_COLOR5_VIEW:
1274 case R_028098_CB_COLOR6_VIEW:
1275 case R_02809C_CB_COLOR7_VIEW:
1276 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1277 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1278 track->cb_dirty = true;
1279 break;
1280 case R_028060_CB_COLOR0_SIZE:
1281 case R_028064_CB_COLOR1_SIZE:
1282 case R_028068_CB_COLOR2_SIZE:
1283 case R_02806C_CB_COLOR3_SIZE:
1284 case R_028070_CB_COLOR4_SIZE:
1285 case R_028074_CB_COLOR5_SIZE:
1286 case R_028078_CB_COLOR6_SIZE:
1287 case R_02807C_CB_COLOR7_SIZE:
1288 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1289 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1290 track->cb_color_size_idx[tmp] = idx;
1291 track->cb_dirty = true;
1292 break;
1293 /* This register were added late, there is userspace
1294 * which does provide relocation for those but set
1295 * 0 offset. In order to avoid breaking old userspace
1296 * we detect this and set address to point to last
1297 * CB_COLOR0_BASE, note that if userspace doesn't set
1298 * CB_COLOR0_BASE before this register we will report
1299 * error. Old userspace always set CB_COLOR0_BASE
1300 * before any of this.
1301 */
1302 case R_0280E0_CB_COLOR0_FRAG:
1303 case R_0280E4_CB_COLOR1_FRAG:
1304 case R_0280E8_CB_COLOR2_FRAG:
1305 case R_0280EC_CB_COLOR3_FRAG:
1306 case R_0280F0_CB_COLOR4_FRAG:
1307 case R_0280F4_CB_COLOR5_FRAG:
1308 case R_0280F8_CB_COLOR6_FRAG:
1309 case R_0280FC_CB_COLOR7_FRAG:
1310 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1311 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1312 if (!track->cb_color_base_last[tmp]) {
1313 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1314 return -EINVAL;
1315 }
1316 ib[idx] = track->cb_color_base_last[tmp];
1317 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1318 } else {
1319 r = r600_cs_packet_next_reloc(p, &reloc);
1320 if (r) {
1321 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1322 return -EINVAL;
1323 }
1324 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1325 track->cb_color_frag_bo[tmp] = reloc->robj;
1326 }
1327 break;
1328 case R_0280C0_CB_COLOR0_TILE:
1329 case R_0280C4_CB_COLOR1_TILE:
1330 case R_0280C8_CB_COLOR2_TILE:
1331 case R_0280CC_CB_COLOR3_TILE:
1332 case R_0280D0_CB_COLOR4_TILE:
1333 case R_0280D4_CB_COLOR5_TILE:
1334 case R_0280D8_CB_COLOR6_TILE:
1335 case R_0280DC_CB_COLOR7_TILE:
1336 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1337 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1338 if (!track->cb_color_base_last[tmp]) {
1339 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1340 return -EINVAL;
1341 }
1342 ib[idx] = track->cb_color_base_last[tmp];
1343 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1344 } else {
1345 r = r600_cs_packet_next_reloc(p, &reloc);
1346 if (r) {
1347 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1348 return -EINVAL;
1349 }
1350 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1351 track->cb_color_tile_bo[tmp] = reloc->robj;
1352 }
1353 break;
1354 case CB_COLOR0_BASE:
1355 case CB_COLOR1_BASE:
1356 case CB_COLOR2_BASE:
1357 case CB_COLOR3_BASE:
1358 case CB_COLOR4_BASE:
1359 case CB_COLOR5_BASE:
1360 case CB_COLOR6_BASE:
1361 case CB_COLOR7_BASE:
1362 r = r600_cs_packet_next_reloc(p, &reloc);
1363 if (r) {
1364 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1365 "0x%04X\n", reg);
1366 return -EINVAL;
1367 }
1368 tmp = (reg - CB_COLOR0_BASE) / 4;
1369 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1370 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1371 track->cb_color_base_last[tmp] = ib[idx];
1372 track->cb_color_bo[tmp] = reloc->robj;
1373 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1374 track->cb_dirty = true;
1375 break;
1376 case DB_DEPTH_BASE:
1377 r = r600_cs_packet_next_reloc(p, &reloc);
1378 if (r) {
1379 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1380 "0x%04X\n", reg);
1381 return -EINVAL;
1382 }
1383 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1384 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1385 track->db_bo = reloc->robj;
1386 track->db_bo_mc = reloc->lobj.gpu_offset;
1387 track->db_dirty = true;
1388 break;
1389 case DB_HTILE_DATA_BASE:
1390 r = r600_cs_packet_next_reloc(p, &reloc);
1391 if (r) {
1392 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1393 "0x%04X\n", reg);
1394 return -EINVAL;
1395 }
1396 track->htile_offset = radeon_get_ib_value(p, idx) << 8;
1397 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1398 track->htile_bo = reloc->robj;
1399 track->db_dirty = true;
1400 break;
1401 case DB_HTILE_SURFACE:
1402 track->htile_surface = radeon_get_ib_value(p, idx);
1403 track->db_dirty = true;
1404 break;
1405 case SQ_PGM_START_FS:
1406 case SQ_PGM_START_ES:
1407 case SQ_PGM_START_VS:
1408 case SQ_PGM_START_GS:
1409 case SQ_PGM_START_PS:
1410 case SQ_ALU_CONST_CACHE_GS_0:
1411 case SQ_ALU_CONST_CACHE_GS_1:
1412 case SQ_ALU_CONST_CACHE_GS_2:
1413 case SQ_ALU_CONST_CACHE_GS_3:
1414 case SQ_ALU_CONST_CACHE_GS_4:
1415 case SQ_ALU_CONST_CACHE_GS_5:
1416 case SQ_ALU_CONST_CACHE_GS_6:
1417 case SQ_ALU_CONST_CACHE_GS_7:
1418 case SQ_ALU_CONST_CACHE_GS_8:
1419 case SQ_ALU_CONST_CACHE_GS_9:
1420 case SQ_ALU_CONST_CACHE_GS_10:
1421 case SQ_ALU_CONST_CACHE_GS_11:
1422 case SQ_ALU_CONST_CACHE_GS_12:
1423 case SQ_ALU_CONST_CACHE_GS_13:
1424 case SQ_ALU_CONST_CACHE_GS_14:
1425 case SQ_ALU_CONST_CACHE_GS_15:
1426 case SQ_ALU_CONST_CACHE_PS_0:
1427 case SQ_ALU_CONST_CACHE_PS_1:
1428 case SQ_ALU_CONST_CACHE_PS_2:
1429 case SQ_ALU_CONST_CACHE_PS_3:
1430 case SQ_ALU_CONST_CACHE_PS_4:
1431 case SQ_ALU_CONST_CACHE_PS_5:
1432 case SQ_ALU_CONST_CACHE_PS_6:
1433 case SQ_ALU_CONST_CACHE_PS_7:
1434 case SQ_ALU_CONST_CACHE_PS_8:
1435 case SQ_ALU_CONST_CACHE_PS_9:
1436 case SQ_ALU_CONST_CACHE_PS_10:
1437 case SQ_ALU_CONST_CACHE_PS_11:
1438 case SQ_ALU_CONST_CACHE_PS_12:
1439 case SQ_ALU_CONST_CACHE_PS_13:
1440 case SQ_ALU_CONST_CACHE_PS_14:
1441 case SQ_ALU_CONST_CACHE_PS_15:
1442 case SQ_ALU_CONST_CACHE_VS_0:
1443 case SQ_ALU_CONST_CACHE_VS_1:
1444 case SQ_ALU_CONST_CACHE_VS_2:
1445 case SQ_ALU_CONST_CACHE_VS_3:
1446 case SQ_ALU_CONST_CACHE_VS_4:
1447 case SQ_ALU_CONST_CACHE_VS_5:
1448 case SQ_ALU_CONST_CACHE_VS_6:
1449 case SQ_ALU_CONST_CACHE_VS_7:
1450 case SQ_ALU_CONST_CACHE_VS_8:
1451 case SQ_ALU_CONST_CACHE_VS_9:
1452 case SQ_ALU_CONST_CACHE_VS_10:
1453 case SQ_ALU_CONST_CACHE_VS_11:
1454 case SQ_ALU_CONST_CACHE_VS_12:
1455 case SQ_ALU_CONST_CACHE_VS_13:
1456 case SQ_ALU_CONST_CACHE_VS_14:
1457 case SQ_ALU_CONST_CACHE_VS_15:
1458 r = r600_cs_packet_next_reloc(p, &reloc);
1459 if (r) {
1460 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1461 "0x%04X\n", reg);
1462 return -EINVAL;
1463 }
1464 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1465 break;
1466 case SX_MEMORY_EXPORT_BASE:
1467 r = r600_cs_packet_next_reloc(p, &reloc);
1468 if (r) {
1469 dev_warn(p->dev, "bad SET_CONFIG_REG "
1470 "0x%04X\n", reg);
1471 return -EINVAL;
1472 }
1473 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1474 break;
1475 case SX_MISC:
1476 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1477 break;
1478 default:
1479 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1480 return -EINVAL;
1481 }
1482 return 0;
1483 }
1484
r600_mip_minify(unsigned size,unsigned level)1485 unsigned r600_mip_minify(unsigned size, unsigned level)
1486 {
1487 unsigned val;
1488
1489 val = max(1U, size >> level);
1490 if (level > 0)
1491 val = roundup_pow_of_two(val);
1492 return val;
1493 }
1494
r600_texture_size(unsigned nfaces,unsigned blevel,unsigned llevel,unsigned w0,unsigned h0,unsigned d0,unsigned format,unsigned block_align,unsigned height_align,unsigned base_align,unsigned * l0_size,unsigned * mipmap_size)1495 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1496 unsigned w0, unsigned h0, unsigned d0, unsigned format,
1497 unsigned block_align, unsigned height_align, unsigned base_align,
1498 unsigned *l0_size, unsigned *mipmap_size)
1499 {
1500 unsigned offset, i, level;
1501 unsigned width, height, depth, size;
1502 unsigned blocksize;
1503 unsigned nbx, nby;
1504 unsigned nlevels = llevel - blevel + 1;
1505
1506 *l0_size = -1;
1507 blocksize = r600_fmt_get_blocksize(format);
1508
1509 w0 = r600_mip_minify(w0, 0);
1510 h0 = r600_mip_minify(h0, 0);
1511 d0 = r600_mip_minify(d0, 0);
1512 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1513 width = r600_mip_minify(w0, i);
1514 nbx = r600_fmt_get_nblocksx(format, width);
1515
1516 nbx = round_up(nbx, block_align);
1517
1518 height = r600_mip_minify(h0, i);
1519 nby = r600_fmt_get_nblocksy(format, height);
1520 nby = round_up(nby, height_align);
1521
1522 depth = r600_mip_minify(d0, i);
1523
1524 size = nbx * nby * blocksize;
1525 if (nfaces)
1526 size *= nfaces;
1527 else
1528 size *= depth;
1529
1530 if (i == 0)
1531 *l0_size = size;
1532
1533 if (i == 0 || i == 1)
1534 offset = round_up(offset, base_align);
1535
1536 offset += size;
1537 }
1538 *mipmap_size = offset;
1539 if (llevel == 0)
1540 *mipmap_size = *l0_size;
1541 if (!blevel)
1542 *mipmap_size -= *l0_size;
1543 }
1544
1545 /**
1546 * r600_check_texture_resource() - check if register is authorized or not
1547 * @p: parser structure holding parsing context
1548 * @idx: index into the cs buffer
1549 * @texture: texture's bo structure
1550 * @mipmap: mipmap's bo structure
1551 *
1552 * This function will check that the resource has valid field and that
1553 * the texture and mipmap bo object are big enough to cover this resource.
1554 */
r600_check_texture_resource(struct radeon_cs_parser * p,u32 idx,struct radeon_bo * texture,struct radeon_bo * mipmap,u64 base_offset,u64 mip_offset,u32 tiling_flags)1555 static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
1556 struct radeon_bo *texture,
1557 struct radeon_bo *mipmap,
1558 u64 base_offset,
1559 u64 mip_offset,
1560 u32 tiling_flags)
1561 {
1562 struct r600_cs_track *track = p->track;
1563 u32 nfaces, llevel, blevel, w0, h0, d0;
1564 u32 word0, word1, l0_size, mipmap_size, word2, word3;
1565 u32 height_align, pitch, pitch_align, depth_align;
1566 u32 array, barray, larray;
1567 u64 base_align;
1568 struct array_mode_checker array_check;
1569 u32 format;
1570
1571 /* on legacy kernel we don't perform advanced check */
1572 if (p->rdev == NULL)
1573 return 0;
1574
1575 /* convert to bytes */
1576 base_offset <<= 8;
1577 mip_offset <<= 8;
1578
1579 word0 = radeon_get_ib_value(p, idx + 0);
1580 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1581 if (tiling_flags & RADEON_TILING_MACRO)
1582 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1583 else if (tiling_flags & RADEON_TILING_MICRO)
1584 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1585 }
1586 word1 = radeon_get_ib_value(p, idx + 1);
1587 w0 = G_038000_TEX_WIDTH(word0) + 1;
1588 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1589 d0 = G_038004_TEX_DEPTH(word1);
1590 nfaces = 1;
1591 array = 0;
1592 switch (G_038000_DIM(word0)) {
1593 case V_038000_SQ_TEX_DIM_1D:
1594 case V_038000_SQ_TEX_DIM_2D:
1595 case V_038000_SQ_TEX_DIM_3D:
1596 break;
1597 case V_038000_SQ_TEX_DIM_CUBEMAP:
1598 if (p->family >= CHIP_RV770)
1599 nfaces = 8;
1600 else
1601 nfaces = 6;
1602 break;
1603 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1604 case V_038000_SQ_TEX_DIM_2D_ARRAY:
1605 array = 1;
1606 break;
1607 case V_038000_SQ_TEX_DIM_2D_MSAA:
1608 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1609 default:
1610 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1611 return -EINVAL;
1612 }
1613 format = G_038004_DATA_FORMAT(word1);
1614 if (!r600_fmt_is_valid_texture(format, p->family)) {
1615 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1616 __func__, __LINE__, format);
1617 return -EINVAL;
1618 }
1619
1620 /* pitch in texels */
1621 pitch = (G_038000_PITCH(word0) + 1) * 8;
1622 array_check.array_mode = G_038000_TILE_MODE(word0);
1623 array_check.group_size = track->group_size;
1624 array_check.nbanks = track->nbanks;
1625 array_check.npipes = track->npipes;
1626 array_check.nsamples = 1;
1627 array_check.blocksize = r600_fmt_get_blocksize(format);
1628 if (r600_get_array_mode_alignment(&array_check,
1629 &pitch_align, &height_align, &depth_align, &base_align)) {
1630 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1631 __func__, __LINE__, G_038000_TILE_MODE(word0));
1632 return -EINVAL;
1633 }
1634
1635 /* XXX check height as well... */
1636
1637 if (!IS_ALIGNED(pitch, pitch_align)) {
1638 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1639 __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
1640 return -EINVAL;
1641 }
1642 if (!IS_ALIGNED(base_offset, base_align)) {
1643 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1644 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
1645 return -EINVAL;
1646 }
1647 if (!IS_ALIGNED(mip_offset, base_align)) {
1648 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1649 __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
1650 return -EINVAL;
1651 }
1652
1653 word2 = radeon_get_ib_value(p, idx + 2) << 8;
1654 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1655
1656 word0 = radeon_get_ib_value(p, idx + 4);
1657 word1 = radeon_get_ib_value(p, idx + 5);
1658 blevel = G_038010_BASE_LEVEL(word0);
1659 llevel = G_038014_LAST_LEVEL(word1);
1660 if (blevel > llevel) {
1661 dev_warn(p->dev, "texture blevel %d > llevel %d\n",
1662 blevel, llevel);
1663 }
1664 if (array == 1) {
1665 barray = G_038014_BASE_ARRAY(word1);
1666 larray = G_038014_LAST_ARRAY(word1);
1667
1668 nfaces = larray - barray + 1;
1669 }
1670 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format,
1671 pitch_align, height_align, base_align,
1672 &l0_size, &mipmap_size);
1673 /* using get ib will give us the offset into the texture bo */
1674 if ((l0_size + word2) > radeon_bo_size(texture)) {
1675 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
1676 w0, h0, pitch_align, height_align,
1677 array_check.array_mode, format, word2,
1678 l0_size, radeon_bo_size(texture));
1679 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
1680 return -EINVAL;
1681 }
1682 /* using get ib will give us the offset into the mipmap bo */
1683 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1684 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1685 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1686 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1687 }
1688 return 0;
1689 }
1690
r600_is_safe_reg(struct radeon_cs_parser * p,u32 reg,u32 idx)1691 static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1692 {
1693 u32 m, i;
1694
1695 i = (reg >> 7);
1696 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1697 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1698 return false;
1699 }
1700 m = 1 << ((reg >> 2) & 31);
1701 if (!(r600_reg_safe_bm[i] & m))
1702 return true;
1703 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1704 return false;
1705 }
1706
r600_packet3_check(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt)1707 static int r600_packet3_check(struct radeon_cs_parser *p,
1708 struct radeon_cs_packet *pkt)
1709 {
1710 struct radeon_cs_reloc *reloc;
1711 struct r600_cs_track *track;
1712 volatile u32 *ib;
1713 unsigned idx;
1714 unsigned i;
1715 unsigned start_reg, end_reg, reg;
1716 int r;
1717 u32 idx_value;
1718
1719 track = (struct r600_cs_track *)p->track;
1720 ib = p->ib->ptr;
1721 idx = pkt->idx + 1;
1722 idx_value = radeon_get_ib_value(p, idx);
1723
1724 switch (pkt->opcode) {
1725 case PACKET3_SET_PREDICATION:
1726 {
1727 int pred_op;
1728 int tmp;
1729 uint64_t offset;
1730
1731 if (pkt->count != 1) {
1732 DRM_ERROR("bad SET PREDICATION\n");
1733 return -EINVAL;
1734 }
1735
1736 tmp = radeon_get_ib_value(p, idx + 1);
1737 pred_op = (tmp >> 16) & 0x7;
1738
1739 /* for the clear predicate operation */
1740 if (pred_op == 0)
1741 return 0;
1742
1743 if (pred_op > 2) {
1744 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1745 return -EINVAL;
1746 }
1747
1748 r = r600_cs_packet_next_reloc(p, &reloc);
1749 if (r) {
1750 DRM_ERROR("bad SET PREDICATION\n");
1751 return -EINVAL;
1752 }
1753
1754 offset = reloc->lobj.gpu_offset +
1755 (idx_value & 0xfffffff0) +
1756 ((u64)(tmp & 0xff) << 32);
1757
1758 ib[idx + 0] = offset;
1759 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1760 }
1761 break;
1762
1763 case PACKET3_START_3D_CMDBUF:
1764 if (p->family >= CHIP_RV770 || pkt->count) {
1765 DRM_ERROR("bad START_3D\n");
1766 return -EINVAL;
1767 }
1768 break;
1769 case PACKET3_CONTEXT_CONTROL:
1770 if (pkt->count != 1) {
1771 DRM_ERROR("bad CONTEXT_CONTROL\n");
1772 return -EINVAL;
1773 }
1774 break;
1775 case PACKET3_INDEX_TYPE:
1776 case PACKET3_NUM_INSTANCES:
1777 if (pkt->count) {
1778 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1779 return -EINVAL;
1780 }
1781 break;
1782 case PACKET3_DRAW_INDEX:
1783 {
1784 uint64_t offset;
1785 if (pkt->count != 3) {
1786 DRM_ERROR("bad DRAW_INDEX\n");
1787 return -EINVAL;
1788 }
1789 r = r600_cs_packet_next_reloc(p, &reloc);
1790 if (r) {
1791 DRM_ERROR("bad DRAW_INDEX\n");
1792 return -EINVAL;
1793 }
1794
1795 offset = reloc->lobj.gpu_offset +
1796 idx_value +
1797 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1798
1799 ib[idx+0] = offset;
1800 ib[idx+1] = upper_32_bits(offset) & 0xff;
1801
1802 r = r600_cs_track_check(p);
1803 if (r) {
1804 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1805 return r;
1806 }
1807 break;
1808 }
1809 case PACKET3_DRAW_INDEX_AUTO:
1810 if (pkt->count != 1) {
1811 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1812 return -EINVAL;
1813 }
1814 r = r600_cs_track_check(p);
1815 if (r) {
1816 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1817 return r;
1818 }
1819 break;
1820 case PACKET3_DRAW_INDEX_IMMD_BE:
1821 case PACKET3_DRAW_INDEX_IMMD:
1822 if (pkt->count < 2) {
1823 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1824 return -EINVAL;
1825 }
1826 r = r600_cs_track_check(p);
1827 if (r) {
1828 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1829 return r;
1830 }
1831 break;
1832 case PACKET3_WAIT_REG_MEM:
1833 if (pkt->count != 5) {
1834 DRM_ERROR("bad WAIT_REG_MEM\n");
1835 return -EINVAL;
1836 }
1837 /* bit 4 is reg (0) or mem (1) */
1838 if (idx_value & 0x10) {
1839 uint64_t offset;
1840
1841 r = r600_cs_packet_next_reloc(p, &reloc);
1842 if (r) {
1843 DRM_ERROR("bad WAIT_REG_MEM\n");
1844 return -EINVAL;
1845 }
1846
1847 offset = reloc->lobj.gpu_offset +
1848 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
1849 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1850
1851 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
1852 ib[idx+2] = upper_32_bits(offset) & 0xff;
1853 }
1854 break;
1855 case PACKET3_SURFACE_SYNC:
1856 if (pkt->count != 3) {
1857 DRM_ERROR("bad SURFACE_SYNC\n");
1858 return -EINVAL;
1859 }
1860 /* 0xffffffff/0x0 is flush all cache flag */
1861 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1862 radeon_get_ib_value(p, idx + 2) != 0) {
1863 r = r600_cs_packet_next_reloc(p, &reloc);
1864 if (r) {
1865 DRM_ERROR("bad SURFACE_SYNC\n");
1866 return -EINVAL;
1867 }
1868 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1869 }
1870 break;
1871 case PACKET3_EVENT_WRITE:
1872 if (pkt->count != 2 && pkt->count != 0) {
1873 DRM_ERROR("bad EVENT_WRITE\n");
1874 return -EINVAL;
1875 }
1876 if (pkt->count) {
1877 uint64_t offset;
1878
1879 r = r600_cs_packet_next_reloc(p, &reloc);
1880 if (r) {
1881 DRM_ERROR("bad EVENT_WRITE\n");
1882 return -EINVAL;
1883 }
1884 offset = reloc->lobj.gpu_offset +
1885 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
1886 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1887
1888 ib[idx+1] = offset & 0xfffffff8;
1889 ib[idx+2] = upper_32_bits(offset) & 0xff;
1890 }
1891 break;
1892 case PACKET3_EVENT_WRITE_EOP:
1893 {
1894 uint64_t offset;
1895
1896 if (pkt->count != 4) {
1897 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1898 return -EINVAL;
1899 }
1900 r = r600_cs_packet_next_reloc(p, &reloc);
1901 if (r) {
1902 DRM_ERROR("bad EVENT_WRITE\n");
1903 return -EINVAL;
1904 }
1905
1906 offset = reloc->lobj.gpu_offset +
1907 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
1908 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1909
1910 ib[idx+1] = offset & 0xfffffffc;
1911 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1912 break;
1913 }
1914 case PACKET3_SET_CONFIG_REG:
1915 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1916 end_reg = 4 * pkt->count + start_reg - 4;
1917 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
1918 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
1919 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
1920 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
1921 return -EINVAL;
1922 }
1923 for (i = 0; i < pkt->count; i++) {
1924 reg = start_reg + (4 * i);
1925 r = r600_cs_check_reg(p, reg, idx+1+i);
1926 if (r)
1927 return r;
1928 }
1929 break;
1930 case PACKET3_SET_CONTEXT_REG:
1931 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
1932 end_reg = 4 * pkt->count + start_reg - 4;
1933 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
1934 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
1935 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
1936 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
1937 return -EINVAL;
1938 }
1939 for (i = 0; i < pkt->count; i++) {
1940 reg = start_reg + (4 * i);
1941 r = r600_cs_check_reg(p, reg, idx+1+i);
1942 if (r)
1943 return r;
1944 }
1945 break;
1946 case PACKET3_SET_RESOURCE:
1947 if (pkt->count % 7) {
1948 DRM_ERROR("bad SET_RESOURCE\n");
1949 return -EINVAL;
1950 }
1951 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
1952 end_reg = 4 * pkt->count + start_reg - 4;
1953 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
1954 (start_reg >= PACKET3_SET_RESOURCE_END) ||
1955 (end_reg >= PACKET3_SET_RESOURCE_END)) {
1956 DRM_ERROR("bad SET_RESOURCE\n");
1957 return -EINVAL;
1958 }
1959 for (i = 0; i < (pkt->count / 7); i++) {
1960 struct radeon_bo *texture, *mipmap;
1961 u32 size, offset, base_offset, mip_offset;
1962
1963 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
1964 case SQ_TEX_VTX_VALID_TEXTURE:
1965 /* tex base */
1966 r = r600_cs_packet_next_reloc(p, &reloc);
1967 if (r) {
1968 DRM_ERROR("bad SET_RESOURCE\n");
1969 return -EINVAL;
1970 }
1971 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1972 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1973 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1974 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1975 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1976 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1977 }
1978 texture = reloc->robj;
1979 /* tex mip base */
1980 r = r600_cs_packet_next_reloc(p, &reloc);
1981 if (r) {
1982 DRM_ERROR("bad SET_RESOURCE\n");
1983 return -EINVAL;
1984 }
1985 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1986 mipmap = reloc->robj;
1987 r = r600_check_texture_resource(p, idx+(i*7)+1,
1988 texture, mipmap,
1989 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
1990 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
1991 reloc->lobj.tiling_flags);
1992 if (r)
1993 return r;
1994 ib[idx+1+(i*7)+2] += base_offset;
1995 ib[idx+1+(i*7)+3] += mip_offset;
1996 break;
1997 case SQ_TEX_VTX_VALID_BUFFER:
1998 {
1999 uint64_t offset64;
2000 /* vtx base */
2001 r = r600_cs_packet_next_reloc(p, &reloc);
2002 if (r) {
2003 DRM_ERROR("bad SET_RESOURCE\n");
2004 return -EINVAL;
2005 }
2006 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
2007 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
2008 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2009 /* force size to size of the buffer */
2010 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
2011 size + offset, radeon_bo_size(reloc->robj));
2012 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
2013 }
2014
2015 offset64 = reloc->lobj.gpu_offset + offset;
2016 ib[idx+1+(i*8)+0] = offset64;
2017 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2018 (upper_32_bits(offset64) & 0xff);
2019 break;
2020 }
2021 case SQ_TEX_VTX_INVALID_TEXTURE:
2022 case SQ_TEX_VTX_INVALID_BUFFER:
2023 default:
2024 DRM_ERROR("bad SET_RESOURCE\n");
2025 return -EINVAL;
2026 }
2027 }
2028 break;
2029 case PACKET3_SET_ALU_CONST:
2030 if (track->sq_config & DX9_CONSTS) {
2031 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
2032 end_reg = 4 * pkt->count + start_reg - 4;
2033 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
2034 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
2035 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
2036 DRM_ERROR("bad SET_ALU_CONST\n");
2037 return -EINVAL;
2038 }
2039 }
2040 break;
2041 case PACKET3_SET_BOOL_CONST:
2042 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
2043 end_reg = 4 * pkt->count + start_reg - 4;
2044 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
2045 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2046 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2047 DRM_ERROR("bad SET_BOOL_CONST\n");
2048 return -EINVAL;
2049 }
2050 break;
2051 case PACKET3_SET_LOOP_CONST:
2052 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
2053 end_reg = 4 * pkt->count + start_reg - 4;
2054 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
2055 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2056 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2057 DRM_ERROR("bad SET_LOOP_CONST\n");
2058 return -EINVAL;
2059 }
2060 break;
2061 case PACKET3_SET_CTL_CONST:
2062 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
2063 end_reg = 4 * pkt->count + start_reg - 4;
2064 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
2065 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2066 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2067 DRM_ERROR("bad SET_CTL_CONST\n");
2068 return -EINVAL;
2069 }
2070 break;
2071 case PACKET3_SET_SAMPLER:
2072 if (pkt->count % 3) {
2073 DRM_ERROR("bad SET_SAMPLER\n");
2074 return -EINVAL;
2075 }
2076 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
2077 end_reg = 4 * pkt->count + start_reg - 4;
2078 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
2079 (start_reg >= PACKET3_SET_SAMPLER_END) ||
2080 (end_reg >= PACKET3_SET_SAMPLER_END)) {
2081 DRM_ERROR("bad SET_SAMPLER\n");
2082 return -EINVAL;
2083 }
2084 break;
2085 case PACKET3_SURFACE_BASE_UPDATE:
2086 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
2087 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2088 return -EINVAL;
2089 }
2090 if (pkt->count) {
2091 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2092 return -EINVAL;
2093 }
2094 break;
2095 case PACKET3_STRMOUT_BUFFER_UPDATE:
2096 if (pkt->count != 4) {
2097 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2098 return -EINVAL;
2099 }
2100 /* Updating memory at DST_ADDRESS. */
2101 if (idx_value & 0x1) {
2102 u64 offset;
2103 r = r600_cs_packet_next_reloc(p, &reloc);
2104 if (r) {
2105 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2106 return -EINVAL;
2107 }
2108 offset = radeon_get_ib_value(p, idx+1);
2109 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2110 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2111 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2112 offset + 4, radeon_bo_size(reloc->robj));
2113 return -EINVAL;
2114 }
2115 offset += reloc->lobj.gpu_offset;
2116 ib[idx+1] = offset;
2117 ib[idx+2] = upper_32_bits(offset) & 0xff;
2118 }
2119 /* Reading data from SRC_ADDRESS. */
2120 if (((idx_value >> 1) & 0x3) == 2) {
2121 u64 offset;
2122 r = r600_cs_packet_next_reloc(p, &reloc);
2123 if (r) {
2124 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2125 return -EINVAL;
2126 }
2127 offset = radeon_get_ib_value(p, idx+3);
2128 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2129 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2130 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2131 offset + 4, radeon_bo_size(reloc->robj));
2132 return -EINVAL;
2133 }
2134 offset += reloc->lobj.gpu_offset;
2135 ib[idx+3] = offset;
2136 ib[idx+4] = upper_32_bits(offset) & 0xff;
2137 }
2138 break;
2139 case PACKET3_COPY_DW:
2140 if (pkt->count != 4) {
2141 DRM_ERROR("bad COPY_DW (invalid count)\n");
2142 return -EINVAL;
2143 }
2144 if (idx_value & 0x1) {
2145 u64 offset;
2146 /* SRC is memory. */
2147 r = r600_cs_packet_next_reloc(p, &reloc);
2148 if (r) {
2149 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2150 return -EINVAL;
2151 }
2152 offset = radeon_get_ib_value(p, idx+1);
2153 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2154 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2155 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2156 offset + 4, radeon_bo_size(reloc->robj));
2157 return -EINVAL;
2158 }
2159 offset += reloc->lobj.gpu_offset;
2160 ib[idx+1] = offset;
2161 ib[idx+2] = upper_32_bits(offset) & 0xff;
2162 } else {
2163 /* SRC is a reg. */
2164 reg = radeon_get_ib_value(p, idx+1) << 2;
2165 if (!r600_is_safe_reg(p, reg, idx+1))
2166 return -EINVAL;
2167 }
2168 if (idx_value & 0x2) {
2169 u64 offset;
2170 /* DST is memory. */
2171 r = r600_cs_packet_next_reloc(p, &reloc);
2172 if (r) {
2173 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2174 return -EINVAL;
2175 }
2176 offset = radeon_get_ib_value(p, idx+3);
2177 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2178 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2179 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2180 offset + 4, radeon_bo_size(reloc->robj));
2181 return -EINVAL;
2182 }
2183 offset += reloc->lobj.gpu_offset;
2184 ib[idx+3] = offset;
2185 ib[idx+4] = upper_32_bits(offset) & 0xff;
2186 } else {
2187 /* DST is a reg. */
2188 reg = radeon_get_ib_value(p, idx+3) << 2;
2189 if (!r600_is_safe_reg(p, reg, idx+3))
2190 return -EINVAL;
2191 }
2192 break;
2193 case PACKET3_NOP:
2194 break;
2195 default:
2196 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2197 return -EINVAL;
2198 }
2199 return 0;
2200 }
2201
r600_cs_parse(struct radeon_cs_parser * p)2202 int r600_cs_parse(struct radeon_cs_parser *p)
2203 {
2204 struct radeon_cs_packet pkt;
2205 struct r600_cs_track *track;
2206 int r;
2207
2208 if (p->track == NULL) {
2209 /* initialize tracker, we are in kms */
2210 track = kzalloc(sizeof(*track), GFP_KERNEL);
2211 if (track == NULL)
2212 return -ENOMEM;
2213 r600_cs_track_init(track);
2214 if (p->rdev->family < CHIP_RV770) {
2215 track->npipes = p->rdev->config.r600.tiling_npipes;
2216 track->nbanks = p->rdev->config.r600.tiling_nbanks;
2217 track->group_size = p->rdev->config.r600.tiling_group_size;
2218 } else if (p->rdev->family <= CHIP_RV740) {
2219 track->npipes = p->rdev->config.rv770.tiling_npipes;
2220 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2221 track->group_size = p->rdev->config.rv770.tiling_group_size;
2222 }
2223 p->track = track;
2224 }
2225 do {
2226 r = r600_cs_packet_parse(p, &pkt, p->idx);
2227 if (r) {
2228 kfree(p->track);
2229 p->track = NULL;
2230 return r;
2231 }
2232 p->idx += pkt.count + 2;
2233 switch (pkt.type) {
2234 case PACKET_TYPE0:
2235 r = r600_cs_parse_packet0(p, &pkt);
2236 break;
2237 case PACKET_TYPE2:
2238 break;
2239 case PACKET_TYPE3:
2240 r = r600_packet3_check(p, &pkt);
2241 break;
2242 default:
2243 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2244 kfree(p->track);
2245 p->track = NULL;
2246 return -EINVAL;
2247 }
2248 if (r) {
2249 kfree(p->track);
2250 p->track = NULL;
2251 return r;
2252 }
2253 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2254 #if 0
2255 for (r = 0; r < p->ib->length_dw; r++) {
2256 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib->ptr[r]);
2257 mdelay(1);
2258 }
2259 #endif
2260 kfree(p->track);
2261 p->track = NULL;
2262 return 0;
2263 }
2264
r600_cs_parser_relocs_legacy(struct radeon_cs_parser * p)2265 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
2266 {
2267 if (p->chunk_relocs_idx == -1) {
2268 return 0;
2269 }
2270 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
2271 if (p->relocs == NULL) {
2272 return -ENOMEM;
2273 }
2274 return 0;
2275 }
2276
2277 /**
2278 * cs_parser_fini() - clean parser states
2279 * @parser: parser structure holding parsing context.
2280 * @error: error number
2281 *
2282 * If error is set than unvalidate buffer, otherwise just free memory
2283 * used by parsing context.
2284 **/
r600_cs_parser_fini(struct radeon_cs_parser * parser,int error)2285 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
2286 {
2287 unsigned i;
2288
2289 kfree(parser->relocs);
2290 for (i = 0; i < parser->nchunks; i++) {
2291 kfree(parser->chunks[i].kdata);
2292 kfree(parser->chunks[i].kpage[0]);
2293 kfree(parser->chunks[i].kpage[1]);
2294 }
2295 kfree(parser->chunks);
2296 kfree(parser->chunks_array);
2297 }
2298
r600_cs_legacy(struct drm_device * dev,void * data,struct drm_file * filp,unsigned family,u32 * ib,int * l)2299 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
2300 unsigned family, u32 *ib, int *l)
2301 {
2302 struct radeon_cs_parser parser;
2303 struct radeon_cs_chunk *ib_chunk;
2304 struct radeon_ib fake_ib;
2305 struct r600_cs_track *track;
2306 int r;
2307
2308 /* initialize tracker */
2309 track = kzalloc(sizeof(*track), GFP_KERNEL);
2310 if (track == NULL)
2311 return -ENOMEM;
2312 r600_cs_track_init(track);
2313 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
2314 /* initialize parser */
2315 memset(&parser, 0, sizeof(struct radeon_cs_parser));
2316 parser.filp = filp;
2317 parser.dev = &dev->pdev->dev;
2318 parser.rdev = NULL;
2319 parser.family = family;
2320 parser.ib = &fake_ib;
2321 parser.track = track;
2322 fake_ib.ptr = ib;
2323 r = radeon_cs_parser_init(&parser, data);
2324 if (r) {
2325 DRM_ERROR("Failed to initialize parser !\n");
2326 r600_cs_parser_fini(&parser, r);
2327 return r;
2328 }
2329 r = r600_cs_parser_relocs_legacy(&parser);
2330 if (r) {
2331 DRM_ERROR("Failed to parse relocation !\n");
2332 r600_cs_parser_fini(&parser, r);
2333 return r;
2334 }
2335 /* Copy the packet into the IB, the parser will read from the
2336 * input memory (cached) and write to the IB (which can be
2337 * uncached). */
2338 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
2339 parser.ib->length_dw = ib_chunk->length_dw;
2340 *l = parser.ib->length_dw;
2341 r = r600_cs_parse(&parser);
2342 if (r) {
2343 DRM_ERROR("Invalid command stream !\n");
2344 r600_cs_parser_fini(&parser, r);
2345 return r;
2346 }
2347 r = radeon_cs_finish_pages(&parser);
2348 if (r) {
2349 DRM_ERROR("Invalid command stream !\n");
2350 r600_cs_parser_fini(&parser, r);
2351 return r;
2352 }
2353 r600_cs_parser_fini(&parser, r);
2354 return r;
2355 }
2356
r600_cs_legacy_init(void)2357 void r600_cs_legacy_init(void)
2358 {
2359 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;
2360 }
2361