1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
3 *
4 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #include "r128.h"
32 #include "drmP.h"
33 #include "drm.h"
34 #include "r128_drm.h"
35 #include "r128_drv.h"
36 #include "drm_os_linux.h"
37 #include <asm/delay.h>
38
39 #define R128_FIFO_DEBUG 0
40
41 /* CCE microcode (from ATI) */
42 static u32 r128_cce_microcode[] = {
43 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0,
44 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0,
45 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1,
46 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11,
47 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28,
48 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9,
49 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656,
50 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1,
51 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071,
52 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2,
53 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1,
54 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1,
55 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1,
56 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2,
57 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1,
58 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82,
59 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729,
60 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008,
61 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0,
62 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1,
63 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1,
64 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0,
65 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370,
66 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1,
67 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793,
68 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1,
69 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1,
70 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1,
71 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1,
72 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894,
73 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14,
74 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1,
75 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1,
76 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1,
77 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
78 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
82 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
83 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
84 };
85
86 int r128_do_wait_for_idle( drm_r128_private_t *dev_priv );
87
R128_READ_PLL(drm_device_t * dev,int addr)88 int R128_READ_PLL(drm_device_t *dev, int addr)
89 {
90 drm_r128_private_t *dev_priv = dev->dev_private;
91
92 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
93 return R128_READ(R128_CLOCK_CNTL_DATA);
94 }
95
96 #if R128_FIFO_DEBUG
r128_status(drm_r128_private_t * dev_priv)97 static void r128_status( drm_r128_private_t *dev_priv )
98 {
99 printk( "GUI_STAT = 0x%08x\n",
100 (unsigned int)R128_READ( R128_GUI_STAT ) );
101 printk( "PM4_STAT = 0x%08x\n",
102 (unsigned int)R128_READ( R128_PM4_STAT ) );
103 printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n",
104 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) );
105 printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n",
106 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) );
107 printk( "PM4_MICRO_CNTL = 0x%08x\n",
108 (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) );
109 printk( "PM4_BUFFER_CNTL = 0x%08x\n",
110 (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) );
111 }
112 #endif
113
114
115 /* ================================================================
116 * Engine, FIFO control
117 */
118
r128_do_pixcache_flush(drm_r128_private_t * dev_priv)119 static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv )
120 {
121 u32 tmp;
122 int i;
123
124 tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL;
125 R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp );
126
127 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
128 if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) {
129 return 0;
130 }
131 udelay( 1 );
132 }
133
134 #if R128_FIFO_DEBUG
135 DRM_ERROR( "failed!\n" );
136 #endif
137 return -EBUSY;
138 }
139
r128_do_wait_for_fifo(drm_r128_private_t * dev_priv,int entries)140 static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries )
141 {
142 int i;
143
144 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
145 int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK;
146 if ( slots >= entries ) return 0;
147 udelay( 1 );
148 }
149
150 #if R128_FIFO_DEBUG
151 DRM_ERROR( "failed!\n" );
152 #endif
153 return -EBUSY;
154 }
155
r128_do_wait_for_idle(drm_r128_private_t * dev_priv)156 int r128_do_wait_for_idle( drm_r128_private_t *dev_priv )
157 {
158 int i, ret;
159
160 ret = r128_do_wait_for_fifo( dev_priv, 64 );
161 if ( ret ) return ret;
162
163 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
164 if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) {
165 r128_do_pixcache_flush( dev_priv );
166 return 0;
167 }
168 udelay( 1 );
169 }
170
171 #if R128_FIFO_DEBUG
172 DRM_ERROR( "failed!\n" );
173 #endif
174 return -EBUSY;
175 }
176
177
178 /* ================================================================
179 * CCE control, initialization
180 */
181
182 /* Load the microcode for the CCE */
r128_cce_load_microcode(drm_r128_private_t * dev_priv)183 static void r128_cce_load_microcode( drm_r128_private_t *dev_priv )
184 {
185 int i;
186
187 DRM_DEBUG( "\n" );
188
189 r128_do_wait_for_idle( dev_priv );
190
191 R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 );
192 for ( i = 0 ; i < 256 ; i++ ) {
193 R128_WRITE( R128_PM4_MICROCODE_DATAH,
194 r128_cce_microcode[i * 2] );
195 R128_WRITE( R128_PM4_MICROCODE_DATAL,
196 r128_cce_microcode[i * 2 + 1] );
197 }
198 }
199
200 /* Flush any pending commands to the CCE. This should only be used just
201 * prior to a wait for idle, as it informs the engine that the command
202 * stream is ending.
203 */
r128_do_cce_flush(drm_r128_private_t * dev_priv)204 static void r128_do_cce_flush( drm_r128_private_t *dev_priv )
205 {
206 u32 tmp;
207
208 tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE;
209 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp );
210 }
211
212 /* Wait for the CCE to go idle.
213 */
r128_do_cce_idle(drm_r128_private_t * dev_priv)214 int r128_do_cce_idle( drm_r128_private_t *dev_priv )
215 {
216 int i;
217
218 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
219 if ( GET_RING_HEAD( &dev_priv->ring ) == dev_priv->ring.tail ) {
220 int pm4stat = R128_READ( R128_PM4_STAT );
221 if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >=
222 dev_priv->cce_fifo_size ) &&
223 !(pm4stat & (R128_PM4_BUSY |
224 R128_PM4_GUI_ACTIVE)) ) {
225 return r128_do_pixcache_flush( dev_priv );
226 }
227 }
228 udelay( 1 );
229 }
230
231 #if R128_FIFO_DEBUG
232 DRM_ERROR( "failed!\n" );
233 r128_status( dev_priv );
234 #endif
235 return -EBUSY;
236 }
237
238 /* Start the Concurrent Command Engine.
239 */
r128_do_cce_start(drm_r128_private_t * dev_priv)240 static void r128_do_cce_start( drm_r128_private_t *dev_priv )
241 {
242 r128_do_wait_for_idle( dev_priv );
243
244 R128_WRITE( R128_PM4_BUFFER_CNTL,
245 dev_priv->cce_mode | dev_priv->ring.size_l2qw );
246 R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */
247 R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN );
248
249 dev_priv->cce_running = 1;
250 }
251
252 /* Reset the Concurrent Command Engine. This will not flush any pending
253 * commands, so you must wait for the CCE command stream to complete
254 * before calling this routine.
255 */
r128_do_cce_reset(drm_r128_private_t * dev_priv)256 static void r128_do_cce_reset( drm_r128_private_t *dev_priv )
257 {
258 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
259 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
260 SET_RING_HEAD( &dev_priv->ring, 0 );
261 dev_priv->ring.tail = 0;
262 }
263
264 /* Stop the Concurrent Command Engine. This will not flush any pending
265 * commands, so you must flush the command stream and wait for the CCE
266 * to go idle before calling this routine.
267 */
r128_do_cce_stop(drm_r128_private_t * dev_priv)268 static void r128_do_cce_stop( drm_r128_private_t *dev_priv )
269 {
270 R128_WRITE( R128_PM4_MICRO_CNTL, 0 );
271 R128_WRITE( R128_PM4_BUFFER_CNTL, R128_PM4_NONPM4 );
272
273 dev_priv->cce_running = 0;
274 }
275
276 /* Reset the engine. This will stop the CCE if it is running.
277 */
r128_do_engine_reset(drm_device_t * dev)278 static int r128_do_engine_reset( drm_device_t *dev )
279 {
280 drm_r128_private_t *dev_priv = dev->dev_private;
281 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
282
283 r128_do_pixcache_flush( dev_priv );
284
285 clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX );
286 mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL );
287
288 R128_WRITE_PLL( R128_MCLK_CNTL,
289 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP );
290
291 gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL );
292
293 /* Taken from the sample code - do not change */
294 R128_WRITE( R128_GEN_RESET_CNTL,
295 gen_reset_cntl | R128_SOFT_RESET_GUI );
296 R128_READ( R128_GEN_RESET_CNTL );
297 R128_WRITE( R128_GEN_RESET_CNTL,
298 gen_reset_cntl & ~R128_SOFT_RESET_GUI );
299 R128_READ( R128_GEN_RESET_CNTL );
300
301 R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl );
302 R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index );
303 R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl );
304
305 /* Reset the CCE ring */
306 r128_do_cce_reset( dev_priv );
307
308 /* The CCE is no longer running after an engine reset */
309 dev_priv->cce_running = 0;
310
311 /* Reset any pending vertex, indirect buffers */
312 r128_freelist_reset( dev );
313
314 return 0;
315 }
316
r128_cce_init_ring_buffer(drm_device_t * dev,drm_r128_private_t * dev_priv)317 static void r128_cce_init_ring_buffer( drm_device_t *dev,
318 drm_r128_private_t *dev_priv )
319 {
320 u32 ring_start;
321 u32 tmp;
322
323 DRM_DEBUG( "\n" );
324
325 /* The manual (p. 2) says this address is in "VM space". This
326 * means it's an offset from the start of AGP space.
327 */
328 #if __REALLY_HAVE_AGP
329 if ( !dev_priv->is_pci )
330 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
331 else
332 #endif
333 ring_start = dev_priv->cce_ring->offset - dev->sg->handle;
334
335 R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET );
336
337 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 );
338 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 );
339
340 /* DL_RPTR_ADDR is a physical address in AGP space. */
341 SET_RING_HEAD( &dev_priv->ring, 0 );
342
343 if ( !dev_priv->is_pci ) {
344 R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
345 dev_priv->ring_rptr->offset );
346 } else {
347 drm_sg_mem_t *entry = dev->sg;
348 unsigned long tmp_ofs, page_ofs;
349
350 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
351 page_ofs = tmp_ofs >> PAGE_SHIFT;
352
353 R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR,
354 entry->busaddr[page_ofs]);
355 DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n",
356 entry->busaddr[page_ofs],
357 entry->handle + tmp_ofs );
358 }
359
360 /* Set watermark control */
361 R128_WRITE( R128_PM4_BUFFER_WM_CNTL,
362 ((R128_WATERMARK_L/4) << R128_WMA_SHIFT)
363 | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT)
364 | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT)
365 | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) );
366
367 /* Force read. Why? Because it's in the examples... */
368 R128_READ( R128_PM4_BUFFER_ADDR );
369
370 /* Turn on bus mastering */
371 tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS;
372 R128_WRITE( R128_BUS_CNTL, tmp );
373 }
374
r128_do_init_cce(drm_device_t * dev,drm_r128_init_t * init)375 static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init )
376 {
377 drm_r128_private_t *dev_priv;
378
379 DRM_DEBUG( "\n" );
380
381 if (dev->dev_private) {
382 DRM_DEBUG("called when already initialized\n");
383 return -EINVAL;
384 }
385
386 dev_priv = DRM(alloc)( sizeof(drm_r128_private_t), DRM_MEM_DRIVER );
387 if ( dev_priv == NULL )
388 return -ENOMEM;
389
390 memset( dev_priv, 0, sizeof(drm_r128_private_t) );
391
392 dev_priv->is_pci = init->is_pci;
393
394 if ( dev_priv->is_pci && !dev->sg ) {
395 DRM_ERROR( "PCI GART memory not allocated!\n" );
396 dev->dev_private = (void *)dev_priv;
397 r128_do_cleanup_cce( dev );
398 return -EINVAL;
399 }
400
401 dev_priv->usec_timeout = init->usec_timeout;
402 if ( dev_priv->usec_timeout < 1 ||
403 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) {
404 DRM_DEBUG( "TIMEOUT problem!\n" );
405 dev->dev_private = (void *)dev_priv;
406 r128_do_cleanup_cce( dev );
407 return -EINVAL;
408 }
409
410 dev_priv->cce_mode = init->cce_mode;
411
412 /* GH: Simple idle check.
413 */
414 atomic_set( &dev_priv->idle_count, 0 );
415
416 /* We don't support anything other than bus-mastering ring mode,
417 * but the ring can be in either AGP or PCI space for the ring
418 * read pointer.
419 */
420 if ( ( init->cce_mode != R128_PM4_192BM ) &&
421 ( init->cce_mode != R128_PM4_128BM_64INDBM ) &&
422 ( init->cce_mode != R128_PM4_64BM_128INDBM ) &&
423 ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) {
424 DRM_DEBUG( "Bad cce_mode!\n" );
425 dev->dev_private = (void *)dev_priv;
426 r128_do_cleanup_cce( dev );
427 return -EINVAL;
428 }
429
430 switch ( init->cce_mode ) {
431 case R128_PM4_NONPM4:
432 dev_priv->cce_fifo_size = 0;
433 break;
434 case R128_PM4_192PIO:
435 case R128_PM4_192BM:
436 dev_priv->cce_fifo_size = 192;
437 break;
438 case R128_PM4_128PIO_64INDBM:
439 case R128_PM4_128BM_64INDBM:
440 dev_priv->cce_fifo_size = 128;
441 break;
442 case R128_PM4_64PIO_128INDBM:
443 case R128_PM4_64BM_128INDBM:
444 case R128_PM4_64PIO_64VCBM_64INDBM:
445 case R128_PM4_64BM_64VCBM_64INDBM:
446 case R128_PM4_64PIO_64VCPIO_64INDPIO:
447 dev_priv->cce_fifo_size = 64;
448 break;
449 }
450
451 switch ( init->fb_bpp ) {
452 case 16:
453 dev_priv->color_fmt = R128_DATATYPE_RGB565;
454 break;
455 case 32:
456 default:
457 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
458 break;
459 }
460 dev_priv->front_offset = init->front_offset;
461 dev_priv->front_pitch = init->front_pitch;
462 dev_priv->back_offset = init->back_offset;
463 dev_priv->back_pitch = init->back_pitch;
464
465 switch ( init->depth_bpp ) {
466 case 16:
467 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
468 break;
469 case 24:
470 case 32:
471 default:
472 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
473 break;
474 }
475 dev_priv->depth_offset = init->depth_offset;
476 dev_priv->depth_pitch = init->depth_pitch;
477 dev_priv->span_offset = init->span_offset;
478
479 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) |
480 (dev_priv->front_offset >> 5));
481 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) |
482 (dev_priv->back_offset >> 5));
483 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
484 (dev_priv->depth_offset >> 5) |
485 R128_DST_TILE);
486 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) |
487 (dev_priv->span_offset >> 5));
488
489 DRM_GETSAREA();
490
491 if(!dev_priv->sarea) {
492 DRM_ERROR("could not find sarea!\n");
493 dev->dev_private = (void *)dev_priv;
494 r128_do_cleanup_cce( dev );
495 return -EINVAL;
496 }
497
498 DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
499 if(!dev_priv->fb) {
500 DRM_ERROR("could not find framebuffer!\n");
501 dev->dev_private = (void *)dev_priv;
502 r128_do_cleanup_cce( dev );
503 return -EINVAL;
504 }
505 DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
506 if(!dev_priv->mmio) {
507 DRM_ERROR("could not find mmio region!\n");
508 dev->dev_private = (void *)dev_priv;
509 r128_do_cleanup_cce( dev );
510 return -EINVAL;
511 }
512 DRM_FIND_MAP( dev_priv->cce_ring, init->ring_offset );
513 if(!dev_priv->cce_ring) {
514 DRM_ERROR("could not find cce ring region!\n");
515 dev->dev_private = (void *)dev_priv;
516 r128_do_cleanup_cce( dev );
517 return -EINVAL;
518 }
519 DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
520 if(!dev_priv->ring_rptr) {
521 DRM_ERROR("could not find ring read pointer!\n");
522 dev->dev_private = (void *)dev_priv;
523 r128_do_cleanup_cce( dev );
524 return -EINVAL;
525 }
526 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
527 if(!dev_priv->buffers) {
528 DRM_ERROR("could not find dma buffer region!\n");
529 dev->dev_private = (void *)dev_priv;
530 r128_do_cleanup_cce( dev );
531 return -EINVAL;
532 }
533
534 if ( !dev_priv->is_pci ) {
535 DRM_FIND_MAP( dev_priv->agp_textures,
536 init->agp_textures_offset );
537 if(!dev_priv->agp_textures) {
538 DRM_ERROR("could not find agp texture region!\n");
539 dev->dev_private = (void *)dev_priv;
540 r128_do_cleanup_cce( dev );
541 return -EINVAL;
542 }
543 }
544
545 dev_priv->sarea_priv =
546 (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle +
547 init->sarea_priv_offset);
548
549 if ( !dev_priv->is_pci ) {
550 DRM_IOREMAP( dev_priv->cce_ring, dev );
551 DRM_IOREMAP( dev_priv->ring_rptr, dev );
552 DRM_IOREMAP( dev_priv->buffers, dev );
553 if(!dev_priv->cce_ring->handle ||
554 !dev_priv->ring_rptr->handle ||
555 !dev_priv->buffers->handle) {
556 DRM_ERROR("Could not ioremap agp regions!\n");
557 dev->dev_private = (void *)dev_priv;
558 r128_do_cleanup_cce( dev );
559 return -ENOMEM;
560 }
561 } else {
562 dev_priv->cce_ring->handle =
563 (void *)dev_priv->cce_ring->offset;
564 dev_priv->ring_rptr->handle =
565 (void *)dev_priv->ring_rptr->offset;
566 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
567 }
568
569 #if __REALLY_HAVE_AGP
570 if ( !dev_priv->is_pci )
571 dev_priv->cce_buffers_offset = dev->agp->base;
572 else
573 #endif
574 dev_priv->cce_buffers_offset = dev->sg->handle;
575
576 dev_priv->ring.head = ((__volatile__ u32 *)
577 dev_priv->ring_rptr->handle);
578
579 dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle;
580 dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle
581 + init->ring_size / sizeof(u32));
582 dev_priv->ring.size = init->ring_size;
583 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
584
585 dev_priv->ring.tail_mask =
586 (dev_priv->ring.size / sizeof(u32)) - 1;
587
588 dev_priv->ring.high_mark = 128;
589
590 dev_priv->sarea_priv->last_frame = 0;
591 R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame );
592
593 dev_priv->sarea_priv->last_dispatch = 0;
594 R128_WRITE( R128_LAST_DISPATCH_REG,
595 dev_priv->sarea_priv->last_dispatch );
596
597 if ( dev_priv->is_pci ) {
598 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
599 &dev_priv->bus_pci_gart) ) {
600 DRM_ERROR( "failed to init PCI GART!\n" );
601 dev->dev_private = (void *)dev_priv;
602 r128_do_cleanup_cce( dev );
603 return -ENOMEM;
604 }
605 R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart );
606 }
607
608 r128_cce_init_ring_buffer( dev, dev_priv );
609 r128_cce_load_microcode( dev_priv );
610
611 dev->dev_private = (void *)dev_priv;
612
613 r128_do_engine_reset( dev );
614
615 return 0;
616 }
617
r128_do_cleanup_cce(drm_device_t * dev)618 int r128_do_cleanup_cce( drm_device_t *dev )
619 {
620 if ( dev->dev_private ) {
621 drm_r128_private_t *dev_priv = dev->dev_private;
622
623 #if __REALLY_HAVE_SG
624 if ( !dev_priv->is_pci ) {
625 #endif
626 DRM_IOREMAPFREE( dev_priv->cce_ring, dev );
627 DRM_IOREMAPFREE( dev_priv->ring_rptr, dev );
628 DRM_IOREMAPFREE( dev_priv->buffers, dev );
629 #if __REALLY_HAVE_SG
630 } else {
631 if (!DRM(ati_pcigart_cleanup)( dev,
632 dev_priv->phys_pci_gart,
633 dev_priv->bus_pci_gart ))
634 DRM_ERROR( "failed to cleanup PCI GART!\n" );
635 }
636 #endif
637
638 DRM(free)( dev->dev_private, sizeof(drm_r128_private_t),
639 DRM_MEM_DRIVER );
640 dev->dev_private = NULL;
641 }
642
643 return 0;
644 }
645
r128_cce_init(struct inode * inode,struct file * filp,unsigned int cmd,unsigned long arg)646 int r128_cce_init( struct inode *inode, struct file *filp,
647 unsigned int cmd, unsigned long arg )
648 {
649 drm_file_t *priv = filp->private_data;
650 drm_device_t *dev = priv->dev;
651 drm_r128_init_t init;
652
653 DRM_DEBUG( "%s\n", __FUNCTION__ );
654
655 if ( copy_from_user( &init, (drm_r128_init_t *)arg, sizeof(init) ) )
656 return -EFAULT;
657
658 switch ( init.func ) {
659 case R128_INIT_CCE:
660 return r128_do_init_cce( dev, &init );
661 case R128_CLEANUP_CCE:
662 return r128_do_cleanup_cce( dev );
663 }
664
665 return -EINVAL;
666 }
667
r128_cce_start(struct inode * inode,struct file * filp,unsigned int cmd,unsigned long arg)668 int r128_cce_start( struct inode *inode, struct file *filp,
669 unsigned int cmd, unsigned long arg )
670 {
671 drm_file_t *priv = filp->private_data;
672 drm_device_t *dev = priv->dev;
673 drm_r128_private_t *dev_priv = dev->dev_private;
674 DRM_DEBUG( "%s\n", __FUNCTION__ );
675
676 LOCK_TEST_WITH_RETURN( dev );
677
678 DEV_INIT_TEST_WITH_RETURN(dev_priv);
679
680 if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) {
681 DRM_DEBUG( "%s while CCE running\n", __FUNCTION__ );
682 return 0;
683 }
684
685 r128_do_cce_start( dev_priv );
686
687 return 0;
688 }
689
690 /* Stop the CCE. The engine must have been idled before calling this
691 * routine.
692 */
r128_cce_stop(struct inode * inode,struct file * filp,unsigned int cmd,unsigned long arg)693 int r128_cce_stop( struct inode *inode, struct file *filp,
694 unsigned int cmd, unsigned long arg )
695 {
696 drm_file_t *priv = filp->private_data;
697 drm_device_t *dev = priv->dev;
698 drm_r128_private_t *dev_priv = dev->dev_private;
699 drm_r128_cce_stop_t stop;
700 int ret;
701 DRM_DEBUG( "%s\n", __FUNCTION__ );
702
703 LOCK_TEST_WITH_RETURN( dev );
704
705 DEV_INIT_TEST_WITH_RETURN(dev_priv);
706
707 if ( copy_from_user( &stop, (drm_r128_init_t *)arg, sizeof(stop) ) )
708 return -EFAULT;
709
710 /* Flush any pending CCE commands. This ensures any outstanding
711 * commands are exectuted by the engine before we turn it off.
712 */
713 if ( stop.flush ) {
714 r128_do_cce_flush( dev_priv );
715 }
716
717 /* If we fail to make the engine go idle, we return an error
718 * code so that the DRM ioctl wrapper can try again.
719 */
720 if ( stop.idle ) {
721 ret = r128_do_cce_idle( dev_priv );
722 if ( ret ) return ret;
723 }
724
725 /* Finally, we can turn off the CCE. If the engine isn't idle,
726 * we will get some dropped triangles as they won't be fully
727 * rendered before the CCE is shut down.
728 */
729 r128_do_cce_stop( dev_priv );
730
731 /* Reset the engine */
732 r128_do_engine_reset( dev );
733
734 return 0;
735 }
736
737 /* Just reset the CCE ring. Called as part of an X Server engine reset.
738 */
r128_cce_reset(struct inode * inode,struct file * filp,unsigned int cmd,unsigned long arg)739 int r128_cce_reset( struct inode *inode, struct file *filp,
740 unsigned int cmd, unsigned long arg )
741 {
742 drm_file_t *priv = filp->private_data;
743 drm_device_t *dev = priv->dev;
744 drm_r128_private_t *dev_priv = dev->dev_private;
745 DRM_DEBUG( "%s\n", __FUNCTION__ );
746
747 LOCK_TEST_WITH_RETURN( dev );
748
749 DEV_INIT_TEST_WITH_RETURN(dev_priv);
750
751 r128_do_cce_reset( dev_priv );
752
753 /* The CCE is no longer running after an engine reset */
754 dev_priv->cce_running = 0;
755
756 return 0;
757 }
758
r128_cce_idle(struct inode * inode,struct file * filp,unsigned int cmd,unsigned long arg)759 int r128_cce_idle( struct inode *inode, struct file *filp,
760 unsigned int cmd, unsigned long arg )
761 {
762 drm_file_t *priv = filp->private_data;
763 drm_device_t *dev = priv->dev;
764 drm_r128_private_t *dev_priv = dev->dev_private;
765 DRM_DEBUG( "%s\n", __FUNCTION__ );
766
767 LOCK_TEST_WITH_RETURN( dev );
768
769 DEV_INIT_TEST_WITH_RETURN(dev_priv);
770
771 if ( dev_priv->cce_running ) {
772 r128_do_cce_flush( dev_priv );
773 }
774
775 return r128_do_cce_idle( dev_priv );
776 }
777
r128_engine_reset(struct inode * inode,struct file * filp,unsigned int cmd,unsigned long arg)778 int r128_engine_reset( struct inode *inode, struct file *filp,
779 unsigned int cmd, unsigned long arg )
780 {
781 drm_file_t *priv = filp->private_data;
782 drm_device_t *dev = priv->dev;
783 DRM_DEBUG( "%s\n", __FUNCTION__ );
784
785 LOCK_TEST_WITH_RETURN( dev );
786
787 DEV_INIT_TEST_WITH_RETURN(dev->dev_private);
788
789 return r128_do_engine_reset( dev );
790 }
791
792
793 /* ================================================================
794 * Fullscreen mode
795 */
796
r128_do_init_pageflip(drm_device_t * dev)797 static int r128_do_init_pageflip( drm_device_t *dev )
798 {
799 drm_r128_private_t *dev_priv = dev->dev_private;
800 DRM_DEBUG( "\n" );
801
802 dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET );
803 dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL );
804
805 R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset );
806 R128_WRITE( R128_CRTC_OFFSET_CNTL,
807 dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL );
808
809 dev_priv->page_flipping = 1;
810 dev_priv->current_page = 0;
811
812 return 0;
813 }
814
r128_do_cleanup_pageflip(drm_device_t * dev)815 int r128_do_cleanup_pageflip( drm_device_t *dev )
816 {
817 drm_r128_private_t *dev_priv = dev->dev_private;
818 DRM_DEBUG( "\n" );
819
820 R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset );
821 R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl );
822
823 dev_priv->page_flipping = 0;
824 dev_priv->current_page = 0;
825
826 return 0;
827 }
828
r128_fullscreen(struct inode * inode,struct file * filp,unsigned int cmd,unsigned long arg)829 int r128_fullscreen( struct inode *inode, struct file *filp,
830 unsigned int cmd, unsigned long arg )
831 {
832 drm_file_t *priv = filp->private_data;
833 drm_device_t *dev = priv->dev;
834 drm_r128_fullscreen_t fs;
835
836 LOCK_TEST_WITH_RETURN( dev );
837
838 if ( copy_from_user( &fs, (drm_r128_fullscreen_t *)arg, sizeof(fs) ) )
839 return -EFAULT;
840
841 switch ( fs.func ) {
842 case R128_INIT_FULLSCREEN:
843 return r128_do_init_pageflip( dev );
844 case R128_CLEANUP_FULLSCREEN:
845 return r128_do_cleanup_pageflip( dev );
846 }
847
848 return -EINVAL;
849 }
850
851
852 /* ================================================================
853 * Freelist management
854 */
855 #define R128_BUFFER_USED 0xffffffff
856 #define R128_BUFFER_FREE 0
857
858 #if 0
859 static int r128_freelist_init( drm_device_t *dev )
860 {
861 drm_device_dma_t *dma = dev->dma;
862 drm_r128_private_t *dev_priv = dev->dev_private;
863 drm_buf_t *buf;
864 drm_r128_buf_priv_t *buf_priv;
865 drm_r128_freelist_t *entry;
866 int i;
867
868 dev_priv->head = DRM(alloc)( sizeof(drm_r128_freelist_t),
869 DRM_MEM_DRIVER );
870 if ( dev_priv->head == NULL )
871 return -ENOMEM;
872
873 memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) );
874 dev_priv->head->age = R128_BUFFER_USED;
875
876 for ( i = 0 ; i < dma->buf_count ; i++ ) {
877 buf = dma->buflist[i];
878 buf_priv = buf->dev_private;
879
880 entry = DRM(alloc)( sizeof(drm_r128_freelist_t),
881 DRM_MEM_DRIVER );
882 if ( !entry ) return -ENOMEM;
883
884 entry->age = R128_BUFFER_FREE;
885 entry->buf = buf;
886 entry->prev = dev_priv->head;
887 entry->next = dev_priv->head->next;
888 if ( !entry->next )
889 dev_priv->tail = entry;
890
891 buf_priv->discard = 0;
892 buf_priv->dispatched = 0;
893 buf_priv->list_entry = entry;
894
895 dev_priv->head->next = entry;
896
897 if ( dev_priv->head->next )
898 dev_priv->head->next->prev = entry;
899 }
900
901 return 0;
902
903 }
904 #endif
905
r128_freelist_get(drm_device_t * dev)906 drm_buf_t *r128_freelist_get( drm_device_t *dev )
907 {
908 drm_device_dma_t *dma = dev->dma;
909 drm_r128_private_t *dev_priv = dev->dev_private;
910 drm_r128_buf_priv_t *buf_priv;
911 drm_buf_t *buf;
912 int i, t;
913
914 /* FIXME: Optimize -- use freelist code */
915
916 for ( i = 0 ; i < dma->buf_count ; i++ ) {
917 buf = dma->buflist[i];
918 buf_priv = buf->dev_private;
919 if ( buf->pid == 0 )
920 return buf;
921 }
922
923 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
924 u32 done_age = R128_READ( R128_LAST_DISPATCH_REG );
925
926 for ( i = 0 ; i < dma->buf_count ; i++ ) {
927 buf = dma->buflist[i];
928 buf_priv = buf->dev_private;
929 if ( buf->pending && buf_priv->age <= done_age ) {
930 /* The buffer has been processed, so it
931 * can now be used.
932 */
933 buf->pending = 0;
934 return buf;
935 }
936 }
937 udelay( 1 );
938 }
939
940 DRM_ERROR( "returning NULL!\n" );
941 return NULL;
942 }
943
r128_freelist_reset(drm_device_t * dev)944 void r128_freelist_reset( drm_device_t *dev )
945 {
946 drm_device_dma_t *dma = dev->dma;
947 int i;
948
949 for ( i = 0 ; i < dma->buf_count ; i++ ) {
950 drm_buf_t *buf = dma->buflist[i];
951 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
952 buf_priv->age = 0;
953 }
954 }
955
956
957 /* ================================================================
958 * CCE command submission
959 */
960
r128_wait_ring(drm_r128_private_t * dev_priv,int n)961 int r128_wait_ring( drm_r128_private_t *dev_priv, int n )
962 {
963 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
964 int i;
965
966 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
967 r128_update_ring_snapshot( ring );
968 if ( ring->space >= n )
969 return 0;
970 udelay( 1 );
971 }
972
973 /* FIXME: This is being ignored... */
974 DRM_ERROR( "failed!\n" );
975 return -EBUSY;
976 }
977
r128_cce_get_buffers(drm_device_t * dev,drm_dma_t * d)978 static int r128_cce_get_buffers( drm_device_t *dev, drm_dma_t *d )
979 {
980 int i;
981 drm_buf_t *buf;
982
983 for ( i = d->granted_count ; i < d->request_count ; i++ ) {
984 buf = r128_freelist_get( dev );
985 if ( !buf ) return -EAGAIN;
986
987 buf->pid = current->pid;
988
989 if ( copy_to_user( &d->request_indices[i], &buf->idx,
990 sizeof(buf->idx) ) )
991 return -EFAULT;
992 if ( copy_to_user( &d->request_sizes[i], &buf->total,
993 sizeof(buf->total) ) )
994 return -EFAULT;
995
996 d->granted_count++;
997 }
998 return 0;
999 }
1000
r128_cce_buffers(struct inode * inode,struct file * filp,unsigned int cmd,unsigned long arg)1001 int r128_cce_buffers( struct inode *inode, struct file *filp,
1002 unsigned int cmd, unsigned long arg )
1003 {
1004 drm_file_t *priv = filp->private_data;
1005 drm_device_t *dev = priv->dev;
1006 drm_device_dma_t *dma = dev->dma;
1007 int ret = 0;
1008 drm_dma_t d;
1009
1010 LOCK_TEST_WITH_RETURN( dev );
1011
1012 if ( copy_from_user( &d, (drm_dma_t *) arg, sizeof(d) ) )
1013 return -EFAULT;
1014
1015 /* Please don't send us buffers.
1016 */
1017 if ( d.send_count != 0 ) {
1018 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1019 current->pid, d.send_count );
1020 return -EINVAL;
1021 }
1022
1023 /* We'll send you buffers.
1024 */
1025 if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1026 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1027 current->pid, d.request_count, dma->buf_count );
1028 return -EINVAL;
1029 }
1030
1031 d.granted_count = 0;
1032
1033 if ( d.request_count ) {
1034 ret = r128_cce_get_buffers( dev, &d );
1035 }
1036
1037 if ( copy_to_user( (drm_dma_t *) arg, &d, sizeof(d) ) )
1038 return -EFAULT;
1039
1040 return ret;
1041 }
1042