1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "r100d.h"
37 #include "rs100d.h"
38 #include "rv200d.h"
39 #include "rv250d.h"
40 #include "atom.h"
41
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
44 #include <linux/module.h>
45
46 #include "r100_reg_safe.h"
47 #include "rn50_reg_safe.h"
48
49 /* Firmware Names */
50 #define FIRMWARE_R100 "radeon/R100_cp.bin"
51 #define FIRMWARE_R200 "radeon/R200_cp.bin"
52 #define FIRMWARE_R300 "radeon/R300_cp.bin"
53 #define FIRMWARE_R420 "radeon/R420_cp.bin"
54 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
55 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
56 #define FIRMWARE_R520 "radeon/R520_cp.bin"
57
58 MODULE_FIRMWARE(FIRMWARE_R100);
59 MODULE_FIRMWARE(FIRMWARE_R200);
60 MODULE_FIRMWARE(FIRMWARE_R300);
61 MODULE_FIRMWARE(FIRMWARE_R420);
62 MODULE_FIRMWARE(FIRMWARE_RS690);
63 MODULE_FIRMWARE(FIRMWARE_RS600);
64 MODULE_FIRMWARE(FIRMWARE_R520);
65
66 #include "r100_track.h"
67
r100_wait_for_vblank(struct radeon_device * rdev,int crtc)68 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
69 {
70 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
71 int i;
72
73 if (radeon_crtc->crtc_id == 0) {
74 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
75 for (i = 0; i < rdev->usec_timeout; i++) {
76 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
77 break;
78 udelay(1);
79 }
80 for (i = 0; i < rdev->usec_timeout; i++) {
81 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
82 break;
83 udelay(1);
84 }
85 }
86 } else {
87 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
88 for (i = 0; i < rdev->usec_timeout; i++) {
89 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
90 break;
91 udelay(1);
92 }
93 for (i = 0; i < rdev->usec_timeout; i++) {
94 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
95 break;
96 udelay(1);
97 }
98 }
99 }
100 }
101
102 /* This files gather functions specifics to:
103 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
104 */
105
r100_reloc_pitch_offset(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx,unsigned reg)106 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
107 struct radeon_cs_packet *pkt,
108 unsigned idx,
109 unsigned reg)
110 {
111 int r;
112 u32 tile_flags = 0;
113 u32 tmp;
114 struct radeon_cs_reloc *reloc;
115 u32 value;
116
117 r = r100_cs_packet_next_reloc(p, &reloc);
118 if (r) {
119 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
120 idx, reg);
121 r100_cs_dump_packet(p, pkt);
122 return r;
123 }
124
125 value = radeon_get_ib_value(p, idx);
126 tmp = value & 0x003fffff;
127 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
128
129 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
130 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
131 tile_flags |= RADEON_DST_TILE_MACRO;
132 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
133 if (reg == RADEON_SRC_PITCH_OFFSET) {
134 DRM_ERROR("Cannot src blit from microtiled surface\n");
135 r100_cs_dump_packet(p, pkt);
136 return -EINVAL;
137 }
138 tile_flags |= RADEON_DST_TILE_MICRO;
139 }
140
141 tmp |= tile_flags;
142 p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
143 } else
144 p->ib->ptr[idx] = (value & 0xffc00000) | tmp;
145 return 0;
146 }
147
r100_packet3_load_vbpntr(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,int idx)148 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
149 struct radeon_cs_packet *pkt,
150 int idx)
151 {
152 unsigned c, i;
153 struct radeon_cs_reloc *reloc;
154 struct r100_cs_track *track;
155 int r = 0;
156 volatile uint32_t *ib;
157 u32 idx_value;
158
159 ib = p->ib->ptr;
160 track = (struct r100_cs_track *)p->track;
161 c = radeon_get_ib_value(p, idx++) & 0x1F;
162 if (c > 16) {
163 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
164 pkt->opcode);
165 r100_cs_dump_packet(p, pkt);
166 return -EINVAL;
167 }
168 track->num_arrays = c;
169 for (i = 0; i < (c - 1); i+=2, idx+=3) {
170 r = r100_cs_packet_next_reloc(p, &reloc);
171 if (r) {
172 DRM_ERROR("No reloc for packet3 %d\n",
173 pkt->opcode);
174 r100_cs_dump_packet(p, pkt);
175 return r;
176 }
177 idx_value = radeon_get_ib_value(p, idx);
178 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
179
180 track->arrays[i + 0].esize = idx_value >> 8;
181 track->arrays[i + 0].robj = reloc->robj;
182 track->arrays[i + 0].esize &= 0x7F;
183 r = r100_cs_packet_next_reloc(p, &reloc);
184 if (r) {
185 DRM_ERROR("No reloc for packet3 %d\n",
186 pkt->opcode);
187 r100_cs_dump_packet(p, pkt);
188 return r;
189 }
190 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
191 track->arrays[i + 1].robj = reloc->robj;
192 track->arrays[i + 1].esize = idx_value >> 24;
193 track->arrays[i + 1].esize &= 0x7F;
194 }
195 if (c & 1) {
196 r = r100_cs_packet_next_reloc(p, &reloc);
197 if (r) {
198 DRM_ERROR("No reloc for packet3 %d\n",
199 pkt->opcode);
200 r100_cs_dump_packet(p, pkt);
201 return r;
202 }
203 idx_value = radeon_get_ib_value(p, idx);
204 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
205 track->arrays[i + 0].robj = reloc->robj;
206 track->arrays[i + 0].esize = idx_value >> 8;
207 track->arrays[i + 0].esize &= 0x7F;
208 }
209 return r;
210 }
211
r100_pre_page_flip(struct radeon_device * rdev,int crtc)212 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
213 {
214 /* enable the pflip int */
215 radeon_irq_kms_pflip_irq_get(rdev, crtc);
216 }
217
r100_post_page_flip(struct radeon_device * rdev,int crtc)218 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
219 {
220 /* disable the pflip int */
221 radeon_irq_kms_pflip_irq_put(rdev, crtc);
222 }
223
r100_page_flip(struct radeon_device * rdev,int crtc_id,u64 crtc_base)224 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
225 {
226 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
227 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
228 int i;
229
230 /* Lock the graphics update lock */
231 /* update the scanout addresses */
232 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
233
234 /* Wait for update_pending to go high. */
235 for (i = 0; i < rdev->usec_timeout; i++) {
236 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
237 break;
238 udelay(1);
239 }
240 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
241
242 /* Unlock the lock, so double-buffering can take place inside vblank */
243 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
244 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
245
246 /* Return current update_pending status: */
247 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
248 }
249
r100_pm_get_dynpm_state(struct radeon_device * rdev)250 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
251 {
252 int i;
253 rdev->pm.dynpm_can_upclock = true;
254 rdev->pm.dynpm_can_downclock = true;
255
256 switch (rdev->pm.dynpm_planned_action) {
257 case DYNPM_ACTION_MINIMUM:
258 rdev->pm.requested_power_state_index = 0;
259 rdev->pm.dynpm_can_downclock = false;
260 break;
261 case DYNPM_ACTION_DOWNCLOCK:
262 if (rdev->pm.current_power_state_index == 0) {
263 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
264 rdev->pm.dynpm_can_downclock = false;
265 } else {
266 if (rdev->pm.active_crtc_count > 1) {
267 for (i = 0; i < rdev->pm.num_power_states; i++) {
268 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
269 continue;
270 else if (i >= rdev->pm.current_power_state_index) {
271 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
272 break;
273 } else {
274 rdev->pm.requested_power_state_index = i;
275 break;
276 }
277 }
278 } else
279 rdev->pm.requested_power_state_index =
280 rdev->pm.current_power_state_index - 1;
281 }
282 /* don't use the power state if crtcs are active and no display flag is set */
283 if ((rdev->pm.active_crtc_count > 0) &&
284 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
285 RADEON_PM_MODE_NO_DISPLAY)) {
286 rdev->pm.requested_power_state_index++;
287 }
288 break;
289 case DYNPM_ACTION_UPCLOCK:
290 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
291 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
292 rdev->pm.dynpm_can_upclock = false;
293 } else {
294 if (rdev->pm.active_crtc_count > 1) {
295 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
296 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
297 continue;
298 else if (i <= rdev->pm.current_power_state_index) {
299 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
300 break;
301 } else {
302 rdev->pm.requested_power_state_index = i;
303 break;
304 }
305 }
306 } else
307 rdev->pm.requested_power_state_index =
308 rdev->pm.current_power_state_index + 1;
309 }
310 break;
311 case DYNPM_ACTION_DEFAULT:
312 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
313 rdev->pm.dynpm_can_upclock = false;
314 break;
315 case DYNPM_ACTION_NONE:
316 default:
317 DRM_ERROR("Requested mode for not defined action\n");
318 return;
319 }
320 /* only one clock mode per power state */
321 rdev->pm.requested_clock_mode_index = 0;
322
323 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
324 rdev->pm.power_state[rdev->pm.requested_power_state_index].
325 clock_info[rdev->pm.requested_clock_mode_index].sclk,
326 rdev->pm.power_state[rdev->pm.requested_power_state_index].
327 clock_info[rdev->pm.requested_clock_mode_index].mclk,
328 rdev->pm.power_state[rdev->pm.requested_power_state_index].
329 pcie_lanes);
330 }
331
r100_pm_init_profile(struct radeon_device * rdev)332 void r100_pm_init_profile(struct radeon_device *rdev)
333 {
334 /* default */
335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
336 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
337 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
339 /* low sh */
340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
342 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
344 /* mid sh */
345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
346 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
347 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
348 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
349 /* high sh */
350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
351 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
352 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
353 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
354 /* low mh */
355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
356 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
357 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
358 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
359 /* mid mh */
360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
361 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
362 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
363 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
364 /* high mh */
365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
366 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
367 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
368 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
369 }
370
r100_pm_misc(struct radeon_device * rdev)371 void r100_pm_misc(struct radeon_device *rdev)
372 {
373 int requested_index = rdev->pm.requested_power_state_index;
374 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
375 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
376 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
377
378 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
379 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
380 tmp = RREG32(voltage->gpio.reg);
381 if (voltage->active_high)
382 tmp |= voltage->gpio.mask;
383 else
384 tmp &= ~(voltage->gpio.mask);
385 WREG32(voltage->gpio.reg, tmp);
386 if (voltage->delay)
387 udelay(voltage->delay);
388 } else {
389 tmp = RREG32(voltage->gpio.reg);
390 if (voltage->active_high)
391 tmp &= ~voltage->gpio.mask;
392 else
393 tmp |= voltage->gpio.mask;
394 WREG32(voltage->gpio.reg, tmp);
395 if (voltage->delay)
396 udelay(voltage->delay);
397 }
398 }
399
400 sclk_cntl = RREG32_PLL(SCLK_CNTL);
401 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
402 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
403 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
404 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
405 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
406 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
407 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
408 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
409 else
410 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
411 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
412 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
413 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
414 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
415 } else
416 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
417
418 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
419 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
420 if (voltage->delay) {
421 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
422 switch (voltage->delay) {
423 case 33:
424 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
425 break;
426 case 66:
427 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
428 break;
429 case 99:
430 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
431 break;
432 case 132:
433 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
434 break;
435 }
436 } else
437 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
438 } else
439 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
440
441 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
442 sclk_cntl &= ~FORCE_HDP;
443 else
444 sclk_cntl |= FORCE_HDP;
445
446 WREG32_PLL(SCLK_CNTL, sclk_cntl);
447 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
448 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
449
450 /* set pcie lanes */
451 if ((rdev->flags & RADEON_IS_PCIE) &&
452 !(rdev->flags & RADEON_IS_IGP) &&
453 rdev->asic->pm.set_pcie_lanes &&
454 (ps->pcie_lanes !=
455 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
456 radeon_set_pcie_lanes(rdev,
457 ps->pcie_lanes);
458 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
459 }
460 }
461
r100_pm_prepare(struct radeon_device * rdev)462 void r100_pm_prepare(struct radeon_device *rdev)
463 {
464 struct drm_device *ddev = rdev->ddev;
465 struct drm_crtc *crtc;
466 struct radeon_crtc *radeon_crtc;
467 u32 tmp;
468
469 /* disable any active CRTCs */
470 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
471 radeon_crtc = to_radeon_crtc(crtc);
472 if (radeon_crtc->enabled) {
473 if (radeon_crtc->crtc_id) {
474 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
475 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
476 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
477 } else {
478 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
479 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
480 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
481 }
482 }
483 }
484 }
485
r100_pm_finish(struct radeon_device * rdev)486 void r100_pm_finish(struct radeon_device *rdev)
487 {
488 struct drm_device *ddev = rdev->ddev;
489 struct drm_crtc *crtc;
490 struct radeon_crtc *radeon_crtc;
491 u32 tmp;
492
493 /* enable any active CRTCs */
494 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
495 radeon_crtc = to_radeon_crtc(crtc);
496 if (radeon_crtc->enabled) {
497 if (radeon_crtc->crtc_id) {
498 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
499 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
500 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
501 } else {
502 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
503 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
504 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
505 }
506 }
507 }
508 }
509
r100_gui_idle(struct radeon_device * rdev)510 bool r100_gui_idle(struct radeon_device *rdev)
511 {
512 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
513 return false;
514 else
515 return true;
516 }
517
518 /* hpd for digital panel detect/disconnect */
r100_hpd_sense(struct radeon_device * rdev,enum radeon_hpd_id hpd)519 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
520 {
521 bool connected = false;
522
523 switch (hpd) {
524 case RADEON_HPD_1:
525 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
526 connected = true;
527 break;
528 case RADEON_HPD_2:
529 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
530 connected = true;
531 break;
532 default:
533 break;
534 }
535 return connected;
536 }
537
r100_hpd_set_polarity(struct radeon_device * rdev,enum radeon_hpd_id hpd)538 void r100_hpd_set_polarity(struct radeon_device *rdev,
539 enum radeon_hpd_id hpd)
540 {
541 u32 tmp;
542 bool connected = r100_hpd_sense(rdev, hpd);
543
544 switch (hpd) {
545 case RADEON_HPD_1:
546 tmp = RREG32(RADEON_FP_GEN_CNTL);
547 if (connected)
548 tmp &= ~RADEON_FP_DETECT_INT_POL;
549 else
550 tmp |= RADEON_FP_DETECT_INT_POL;
551 WREG32(RADEON_FP_GEN_CNTL, tmp);
552 break;
553 case RADEON_HPD_2:
554 tmp = RREG32(RADEON_FP2_GEN_CNTL);
555 if (connected)
556 tmp &= ~RADEON_FP2_DETECT_INT_POL;
557 else
558 tmp |= RADEON_FP2_DETECT_INT_POL;
559 WREG32(RADEON_FP2_GEN_CNTL, tmp);
560 break;
561 default:
562 break;
563 }
564 }
565
r100_hpd_init(struct radeon_device * rdev)566 void r100_hpd_init(struct radeon_device *rdev)
567 {
568 struct drm_device *dev = rdev->ddev;
569 struct drm_connector *connector;
570
571 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
572 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
573 switch (radeon_connector->hpd.hpd) {
574 case RADEON_HPD_1:
575 rdev->irq.hpd[0] = true;
576 break;
577 case RADEON_HPD_2:
578 rdev->irq.hpd[1] = true;
579 break;
580 default:
581 break;
582 }
583 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
584 }
585 if (rdev->irq.installed)
586 r100_irq_set(rdev);
587 }
588
r100_hpd_fini(struct radeon_device * rdev)589 void r100_hpd_fini(struct radeon_device *rdev)
590 {
591 struct drm_device *dev = rdev->ddev;
592 struct drm_connector *connector;
593
594 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
595 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
596 switch (radeon_connector->hpd.hpd) {
597 case RADEON_HPD_1:
598 rdev->irq.hpd[0] = false;
599 break;
600 case RADEON_HPD_2:
601 rdev->irq.hpd[1] = false;
602 break;
603 default:
604 break;
605 }
606 }
607 }
608
609 /*
610 * PCI GART
611 */
r100_pci_gart_tlb_flush(struct radeon_device * rdev)612 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
613 {
614 /* TODO: can we do somethings here ? */
615 /* It seems hw only cache one entry so we should discard this
616 * entry otherwise if first GPU GART read hit this entry it
617 * could end up in wrong address. */
618 }
619
r100_pci_gart_init(struct radeon_device * rdev)620 int r100_pci_gart_init(struct radeon_device *rdev)
621 {
622 int r;
623
624 if (rdev->gart.ptr) {
625 WARN(1, "R100 PCI GART already initialized\n");
626 return 0;
627 }
628 /* Initialize common gart structure */
629 r = radeon_gart_init(rdev);
630 if (r)
631 return r;
632 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
633 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
634 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
635 return radeon_gart_table_ram_alloc(rdev);
636 }
637
638 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
r100_enable_bm(struct radeon_device * rdev)639 void r100_enable_bm(struct radeon_device *rdev)
640 {
641 uint32_t tmp;
642 /* Enable bus mastering */
643 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
644 WREG32(RADEON_BUS_CNTL, tmp);
645 }
646
r100_pci_gart_enable(struct radeon_device * rdev)647 int r100_pci_gart_enable(struct radeon_device *rdev)
648 {
649 uint32_t tmp;
650
651 radeon_gart_restore(rdev);
652 /* discard memory request outside of configured range */
653 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
654 WREG32(RADEON_AIC_CNTL, tmp);
655 /* set address range for PCI address translate */
656 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
657 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
658 /* set PCI GART page-table base address */
659 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
660 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
661 WREG32(RADEON_AIC_CNTL, tmp);
662 r100_pci_gart_tlb_flush(rdev);
663 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
664 (unsigned)(rdev->mc.gtt_size >> 20),
665 (unsigned long long)rdev->gart.table_addr);
666 rdev->gart.ready = true;
667 return 0;
668 }
669
r100_pci_gart_disable(struct radeon_device * rdev)670 void r100_pci_gart_disable(struct radeon_device *rdev)
671 {
672 uint32_t tmp;
673
674 /* discard memory request outside of configured range */
675 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
676 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
677 WREG32(RADEON_AIC_LO_ADDR, 0);
678 WREG32(RADEON_AIC_HI_ADDR, 0);
679 }
680
r100_pci_gart_set_page(struct radeon_device * rdev,int i,uint64_t addr)681 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
682 {
683 u32 *gtt = rdev->gart.ptr;
684
685 if (i < 0 || i > rdev->gart.num_gpu_pages) {
686 return -EINVAL;
687 }
688 gtt[i] = cpu_to_le32(lower_32_bits(addr));
689 return 0;
690 }
691
r100_pci_gart_fini(struct radeon_device * rdev)692 void r100_pci_gart_fini(struct radeon_device *rdev)
693 {
694 radeon_gart_fini(rdev);
695 r100_pci_gart_disable(rdev);
696 radeon_gart_table_ram_free(rdev);
697 }
698
r100_irq_set(struct radeon_device * rdev)699 int r100_irq_set(struct radeon_device *rdev)
700 {
701 uint32_t tmp = 0;
702
703 if (!rdev->irq.installed) {
704 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
705 WREG32(R_000040_GEN_INT_CNTL, 0);
706 return -EINVAL;
707 }
708 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
709 tmp |= RADEON_SW_INT_ENABLE;
710 }
711 if (rdev->irq.gui_idle) {
712 tmp |= RADEON_GUI_IDLE_MASK;
713 }
714 if (rdev->irq.crtc_vblank_int[0] ||
715 rdev->irq.pflip[0]) {
716 tmp |= RADEON_CRTC_VBLANK_MASK;
717 }
718 if (rdev->irq.crtc_vblank_int[1] ||
719 rdev->irq.pflip[1]) {
720 tmp |= RADEON_CRTC2_VBLANK_MASK;
721 }
722 if (rdev->irq.hpd[0]) {
723 tmp |= RADEON_FP_DETECT_MASK;
724 }
725 if (rdev->irq.hpd[1]) {
726 tmp |= RADEON_FP2_DETECT_MASK;
727 }
728 WREG32(RADEON_GEN_INT_CNTL, tmp);
729 return 0;
730 }
731
r100_irq_disable(struct radeon_device * rdev)732 void r100_irq_disable(struct radeon_device *rdev)
733 {
734 u32 tmp;
735
736 WREG32(R_000040_GEN_INT_CNTL, 0);
737 /* Wait and acknowledge irq */
738 mdelay(1);
739 tmp = RREG32(R_000044_GEN_INT_STATUS);
740 WREG32(R_000044_GEN_INT_STATUS, tmp);
741 }
742
r100_irq_ack(struct radeon_device * rdev)743 static uint32_t r100_irq_ack(struct radeon_device *rdev)
744 {
745 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
746 uint32_t irq_mask = RADEON_SW_INT_TEST |
747 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
748 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
749
750 /* the interrupt works, but the status bit is permanently asserted */
751 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
752 if (!rdev->irq.gui_idle_acked)
753 irq_mask |= RADEON_GUI_IDLE_STAT;
754 }
755
756 if (irqs) {
757 WREG32(RADEON_GEN_INT_STATUS, irqs);
758 }
759 return irqs & irq_mask;
760 }
761
r100_irq_process(struct radeon_device * rdev)762 int r100_irq_process(struct radeon_device *rdev)
763 {
764 uint32_t status, msi_rearm;
765 bool queue_hotplug = false;
766
767 /* reset gui idle ack. the status bit is broken */
768 rdev->irq.gui_idle_acked = false;
769
770 status = r100_irq_ack(rdev);
771 if (!status) {
772 return IRQ_NONE;
773 }
774 if (rdev->shutdown) {
775 return IRQ_NONE;
776 }
777 while (status) {
778 /* SW interrupt */
779 if (status & RADEON_SW_INT_TEST) {
780 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
781 }
782 /* gui idle interrupt */
783 if (status & RADEON_GUI_IDLE_STAT) {
784 rdev->irq.gui_idle_acked = true;
785 rdev->pm.gui_idle = true;
786 wake_up(&rdev->irq.idle_queue);
787 }
788 /* Vertical blank interrupts */
789 if (status & RADEON_CRTC_VBLANK_STAT) {
790 if (rdev->irq.crtc_vblank_int[0]) {
791 drm_handle_vblank(rdev->ddev, 0);
792 rdev->pm.vblank_sync = true;
793 wake_up(&rdev->irq.vblank_queue);
794 }
795 if (rdev->irq.pflip[0])
796 radeon_crtc_handle_flip(rdev, 0);
797 }
798 if (status & RADEON_CRTC2_VBLANK_STAT) {
799 if (rdev->irq.crtc_vblank_int[1]) {
800 drm_handle_vblank(rdev->ddev, 1);
801 rdev->pm.vblank_sync = true;
802 wake_up(&rdev->irq.vblank_queue);
803 }
804 if (rdev->irq.pflip[1])
805 radeon_crtc_handle_flip(rdev, 1);
806 }
807 if (status & RADEON_FP_DETECT_STAT) {
808 queue_hotplug = true;
809 DRM_DEBUG("HPD1\n");
810 }
811 if (status & RADEON_FP2_DETECT_STAT) {
812 queue_hotplug = true;
813 DRM_DEBUG("HPD2\n");
814 }
815 status = r100_irq_ack(rdev);
816 }
817 /* reset gui idle ack. the status bit is broken */
818 rdev->irq.gui_idle_acked = false;
819 if (queue_hotplug)
820 schedule_work(&rdev->hotplug_work);
821 if (rdev->msi_enabled) {
822 switch (rdev->family) {
823 case CHIP_RS400:
824 case CHIP_RS480:
825 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
826 WREG32(RADEON_AIC_CNTL, msi_rearm);
827 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
828 break;
829 default:
830 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
831 break;
832 }
833 }
834 return IRQ_HANDLED;
835 }
836
r100_get_vblank_counter(struct radeon_device * rdev,int crtc)837 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
838 {
839 if (crtc == 0)
840 return RREG32(RADEON_CRTC_CRNT_FRAME);
841 else
842 return RREG32(RADEON_CRTC2_CRNT_FRAME);
843 }
844
845 /* Who ever call radeon_fence_emit should call ring_lock and ask
846 * for enough space (today caller are ib schedule and buffer move) */
r100_fence_ring_emit(struct radeon_device * rdev,struct radeon_fence * fence)847 void r100_fence_ring_emit(struct radeon_device *rdev,
848 struct radeon_fence *fence)
849 {
850 struct radeon_ring *ring = &rdev->ring[fence->ring];
851
852 /* We have to make sure that caches are flushed before
853 * CPU might read something from VRAM. */
854 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
855 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
856 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
857 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
858 /* Wait until IDLE & CLEAN */
859 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
860 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
861 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
862 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
863 RADEON_HDP_READ_BUFFER_INVALIDATE);
864 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
865 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
866 /* Emit fence sequence & fire IRQ */
867 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
868 radeon_ring_write(ring, fence->seq);
869 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
870 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
871 }
872
r100_semaphore_ring_emit(struct radeon_device * rdev,struct radeon_ring * ring,struct radeon_semaphore * semaphore,bool emit_wait)873 void r100_semaphore_ring_emit(struct radeon_device *rdev,
874 struct radeon_ring *ring,
875 struct radeon_semaphore *semaphore,
876 bool emit_wait)
877 {
878 /* Unused on older asics, since we don't have semaphores or multiple rings */
879 BUG();
880 }
881
r100_copy_blit(struct radeon_device * rdev,uint64_t src_offset,uint64_t dst_offset,unsigned num_gpu_pages,struct radeon_fence * fence)882 int r100_copy_blit(struct radeon_device *rdev,
883 uint64_t src_offset,
884 uint64_t dst_offset,
885 unsigned num_gpu_pages,
886 struct radeon_fence *fence)
887 {
888 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
889 uint32_t cur_pages;
890 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
891 uint32_t pitch;
892 uint32_t stride_pixels;
893 unsigned ndw;
894 int num_loops;
895 int r = 0;
896
897 /* radeon limited to 16k stride */
898 stride_bytes &= 0x3fff;
899 /* radeon pitch is /64 */
900 pitch = stride_bytes / 64;
901 stride_pixels = stride_bytes / 4;
902 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
903
904 /* Ask for enough room for blit + flush + fence */
905 ndw = 64 + (10 * num_loops);
906 r = radeon_ring_lock(rdev, ring, ndw);
907 if (r) {
908 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
909 return -EINVAL;
910 }
911 while (num_gpu_pages > 0) {
912 cur_pages = num_gpu_pages;
913 if (cur_pages > 8191) {
914 cur_pages = 8191;
915 }
916 num_gpu_pages -= cur_pages;
917
918 /* pages are in Y direction - height
919 page width in X direction - width */
920 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
921 radeon_ring_write(ring,
922 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
923 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
924 RADEON_GMC_SRC_CLIPPING |
925 RADEON_GMC_DST_CLIPPING |
926 RADEON_GMC_BRUSH_NONE |
927 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
928 RADEON_GMC_SRC_DATATYPE_COLOR |
929 RADEON_ROP3_S |
930 RADEON_DP_SRC_SOURCE_MEMORY |
931 RADEON_GMC_CLR_CMP_CNTL_DIS |
932 RADEON_GMC_WR_MSK_DIS);
933 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
934 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
935 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
936 radeon_ring_write(ring, 0);
937 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
938 radeon_ring_write(ring, num_gpu_pages);
939 radeon_ring_write(ring, num_gpu_pages);
940 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
941 }
942 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
943 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
944 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
945 radeon_ring_write(ring,
946 RADEON_WAIT_2D_IDLECLEAN |
947 RADEON_WAIT_HOST_IDLECLEAN |
948 RADEON_WAIT_DMA_GUI_IDLE);
949 if (fence) {
950 r = radeon_fence_emit(rdev, fence);
951 }
952 radeon_ring_unlock_commit(rdev, ring);
953 return r;
954 }
955
r100_cp_wait_for_idle(struct radeon_device * rdev)956 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
957 {
958 unsigned i;
959 u32 tmp;
960
961 for (i = 0; i < rdev->usec_timeout; i++) {
962 tmp = RREG32(R_000E40_RBBM_STATUS);
963 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
964 return 0;
965 }
966 udelay(1);
967 }
968 return -1;
969 }
970
r100_ring_start(struct radeon_device * rdev,struct radeon_ring * ring)971 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
972 {
973 int r;
974
975 r = radeon_ring_lock(rdev, ring, 2);
976 if (r) {
977 return;
978 }
979 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
980 radeon_ring_write(ring,
981 RADEON_ISYNC_ANY2D_IDLE3D |
982 RADEON_ISYNC_ANY3D_IDLE2D |
983 RADEON_ISYNC_WAIT_IDLEGUI |
984 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
985 radeon_ring_unlock_commit(rdev, ring);
986 }
987
988
989 /* Load the microcode for the CP */
r100_cp_init_microcode(struct radeon_device * rdev)990 static int r100_cp_init_microcode(struct radeon_device *rdev)
991 {
992 struct platform_device *pdev;
993 const char *fw_name = NULL;
994 int err;
995
996 DRM_DEBUG_KMS("\n");
997
998 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
999 err = IS_ERR(pdev);
1000 if (err) {
1001 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1002 return -EINVAL;
1003 }
1004 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
1005 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
1006 (rdev->family == CHIP_RS200)) {
1007 DRM_INFO("Loading R100 Microcode\n");
1008 fw_name = FIRMWARE_R100;
1009 } else if ((rdev->family == CHIP_R200) ||
1010 (rdev->family == CHIP_RV250) ||
1011 (rdev->family == CHIP_RV280) ||
1012 (rdev->family == CHIP_RS300)) {
1013 DRM_INFO("Loading R200 Microcode\n");
1014 fw_name = FIRMWARE_R200;
1015 } else if ((rdev->family == CHIP_R300) ||
1016 (rdev->family == CHIP_R350) ||
1017 (rdev->family == CHIP_RV350) ||
1018 (rdev->family == CHIP_RV380) ||
1019 (rdev->family == CHIP_RS400) ||
1020 (rdev->family == CHIP_RS480)) {
1021 DRM_INFO("Loading R300 Microcode\n");
1022 fw_name = FIRMWARE_R300;
1023 } else if ((rdev->family == CHIP_R420) ||
1024 (rdev->family == CHIP_R423) ||
1025 (rdev->family == CHIP_RV410)) {
1026 DRM_INFO("Loading R400 Microcode\n");
1027 fw_name = FIRMWARE_R420;
1028 } else if ((rdev->family == CHIP_RS690) ||
1029 (rdev->family == CHIP_RS740)) {
1030 DRM_INFO("Loading RS690/RS740 Microcode\n");
1031 fw_name = FIRMWARE_RS690;
1032 } else if (rdev->family == CHIP_RS600) {
1033 DRM_INFO("Loading RS600 Microcode\n");
1034 fw_name = FIRMWARE_RS600;
1035 } else if ((rdev->family == CHIP_RV515) ||
1036 (rdev->family == CHIP_R520) ||
1037 (rdev->family == CHIP_RV530) ||
1038 (rdev->family == CHIP_R580) ||
1039 (rdev->family == CHIP_RV560) ||
1040 (rdev->family == CHIP_RV570)) {
1041 DRM_INFO("Loading R500 Microcode\n");
1042 fw_name = FIRMWARE_R520;
1043 }
1044
1045 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1046 platform_device_unregister(pdev);
1047 if (err) {
1048 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1049 fw_name);
1050 } else if (rdev->me_fw->size % 8) {
1051 printk(KERN_ERR
1052 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1053 rdev->me_fw->size, fw_name);
1054 err = -EINVAL;
1055 release_firmware(rdev->me_fw);
1056 rdev->me_fw = NULL;
1057 }
1058 return err;
1059 }
1060
r100_cp_load_microcode(struct radeon_device * rdev)1061 static void r100_cp_load_microcode(struct radeon_device *rdev)
1062 {
1063 const __be32 *fw_data;
1064 int i, size;
1065
1066 if (r100_gui_wait_for_idle(rdev)) {
1067 printk(KERN_WARNING "Failed to wait GUI idle while "
1068 "programming pipes. Bad things might happen.\n");
1069 }
1070
1071 if (rdev->me_fw) {
1072 size = rdev->me_fw->size / 4;
1073 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1074 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1075 for (i = 0; i < size; i += 2) {
1076 WREG32(RADEON_CP_ME_RAM_DATAH,
1077 be32_to_cpup(&fw_data[i]));
1078 WREG32(RADEON_CP_ME_RAM_DATAL,
1079 be32_to_cpup(&fw_data[i + 1]));
1080 }
1081 }
1082 }
1083
r100_cp_init(struct radeon_device * rdev,unsigned ring_size)1084 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1085 {
1086 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1087 unsigned rb_bufsz;
1088 unsigned rb_blksz;
1089 unsigned max_fetch;
1090 unsigned pre_write_timer;
1091 unsigned pre_write_limit;
1092 unsigned indirect2_start;
1093 unsigned indirect1_start;
1094 uint32_t tmp;
1095 int r;
1096
1097 if (r100_debugfs_cp_init(rdev)) {
1098 DRM_ERROR("Failed to register debugfs file for CP !\n");
1099 }
1100 if (!rdev->me_fw) {
1101 r = r100_cp_init_microcode(rdev);
1102 if (r) {
1103 DRM_ERROR("Failed to load firmware!\n");
1104 return r;
1105 }
1106 }
1107
1108 /* Align ring size */
1109 rb_bufsz = drm_order(ring_size / 8);
1110 ring_size = (1 << (rb_bufsz + 1)) * 4;
1111 r100_cp_load_microcode(rdev);
1112 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1113 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1114 0, 0x7fffff, RADEON_CP_PACKET2);
1115 if (r) {
1116 return r;
1117 }
1118 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1119 * the rptr copy in system ram */
1120 rb_blksz = 9;
1121 /* cp will read 128bytes at a time (4 dwords) */
1122 max_fetch = 1;
1123 ring->align_mask = 16 - 1;
1124 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1125 pre_write_timer = 64;
1126 /* Force CP_RB_WPTR write if written more than one time before the
1127 * delay expire
1128 */
1129 pre_write_limit = 0;
1130 /* Setup the cp cache like this (cache size is 96 dwords) :
1131 * RING 0 to 15
1132 * INDIRECT1 16 to 79
1133 * INDIRECT2 80 to 95
1134 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1135 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1136 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1137 * Idea being that most of the gpu cmd will be through indirect1 buffer
1138 * so it gets the bigger cache.
1139 */
1140 indirect2_start = 80;
1141 indirect1_start = 16;
1142 /* cp setup */
1143 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1144 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1145 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1146 REG_SET(RADEON_MAX_FETCH, max_fetch));
1147 #ifdef __BIG_ENDIAN
1148 tmp |= RADEON_BUF_SWAP_32BIT;
1149 #endif
1150 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1151
1152 /* Set ring address */
1153 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1154 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1155 /* Force read & write ptr to 0 */
1156 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1157 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1158 ring->wptr = 0;
1159 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1160
1161 /* set the wb address whether it's enabled or not */
1162 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1163 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1164 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1165
1166 if (rdev->wb.enabled)
1167 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1168 else {
1169 tmp |= RADEON_RB_NO_UPDATE;
1170 WREG32(R_000770_SCRATCH_UMSK, 0);
1171 }
1172
1173 WREG32(RADEON_CP_RB_CNTL, tmp);
1174 udelay(10);
1175 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1176 /* Set cp mode to bus mastering & enable cp*/
1177 WREG32(RADEON_CP_CSQ_MODE,
1178 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1179 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1180 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1181 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1182 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1183 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1184 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1185 if (r) {
1186 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1187 return r;
1188 }
1189 ring->ready = true;
1190 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1191 return 0;
1192 }
1193
r100_cp_fini(struct radeon_device * rdev)1194 void r100_cp_fini(struct radeon_device *rdev)
1195 {
1196 if (r100_cp_wait_for_idle(rdev)) {
1197 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1198 }
1199 /* Disable ring */
1200 r100_cp_disable(rdev);
1201 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1202 DRM_INFO("radeon: cp finalized\n");
1203 }
1204
r100_cp_disable(struct radeon_device * rdev)1205 void r100_cp_disable(struct radeon_device *rdev)
1206 {
1207 /* Disable ring */
1208 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1209 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1210 WREG32(RADEON_CP_CSQ_MODE, 0);
1211 WREG32(RADEON_CP_CSQ_CNTL, 0);
1212 WREG32(R_000770_SCRATCH_UMSK, 0);
1213 if (r100_gui_wait_for_idle(rdev)) {
1214 printk(KERN_WARNING "Failed to wait GUI idle while "
1215 "programming pipes. Bad things might happen.\n");
1216 }
1217 }
1218
1219 /*
1220 * CS functions
1221 */
r100_cs_parse_packet0(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,const unsigned * auth,unsigned n,radeon_packet0_check_t check)1222 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1223 struct radeon_cs_packet *pkt,
1224 const unsigned *auth, unsigned n,
1225 radeon_packet0_check_t check)
1226 {
1227 unsigned reg;
1228 unsigned i, j, m;
1229 unsigned idx;
1230 int r;
1231
1232 idx = pkt->idx + 1;
1233 reg = pkt->reg;
1234 /* Check that register fall into register range
1235 * determined by the number of entry (n) in the
1236 * safe register bitmap.
1237 */
1238 if (pkt->one_reg_wr) {
1239 if ((reg >> 7) > n) {
1240 return -EINVAL;
1241 }
1242 } else {
1243 if (((reg + (pkt->count << 2)) >> 7) > n) {
1244 return -EINVAL;
1245 }
1246 }
1247 for (i = 0; i <= pkt->count; i++, idx++) {
1248 j = (reg >> 7);
1249 m = 1 << ((reg >> 2) & 31);
1250 if (auth[j] & m) {
1251 r = check(p, pkt, idx, reg);
1252 if (r) {
1253 return r;
1254 }
1255 }
1256 if (pkt->one_reg_wr) {
1257 if (!(auth[j] & m)) {
1258 break;
1259 }
1260 } else {
1261 reg += 4;
1262 }
1263 }
1264 return 0;
1265 }
1266
r100_cs_dump_packet(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt)1267 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1268 struct radeon_cs_packet *pkt)
1269 {
1270 volatile uint32_t *ib;
1271 unsigned i;
1272 unsigned idx;
1273
1274 ib = p->ib->ptr;
1275 idx = pkt->idx;
1276 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1277 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1278 }
1279 }
1280
1281 /**
1282 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1283 * @parser: parser structure holding parsing context.
1284 * @pkt: where to store packet informations
1285 *
1286 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1287 * if packet is bigger than remaining ib size. or if packets is unknown.
1288 **/
r100_cs_packet_parse(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx)1289 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1290 struct radeon_cs_packet *pkt,
1291 unsigned idx)
1292 {
1293 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1294 uint32_t header;
1295
1296 if (idx >= ib_chunk->length_dw) {
1297 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1298 idx, ib_chunk->length_dw);
1299 return -EINVAL;
1300 }
1301 header = radeon_get_ib_value(p, idx);
1302 pkt->idx = idx;
1303 pkt->type = CP_PACKET_GET_TYPE(header);
1304 pkt->count = CP_PACKET_GET_COUNT(header);
1305 switch (pkt->type) {
1306 case PACKET_TYPE0:
1307 pkt->reg = CP_PACKET0_GET_REG(header);
1308 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1309 break;
1310 case PACKET_TYPE3:
1311 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1312 break;
1313 case PACKET_TYPE2:
1314 pkt->count = -1;
1315 break;
1316 default:
1317 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1318 return -EINVAL;
1319 }
1320 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1321 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1322 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1323 return -EINVAL;
1324 }
1325 return 0;
1326 }
1327
1328 /**
1329 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1330 * @parser: parser structure holding parsing context.
1331 *
1332 * Userspace sends a special sequence for VLINE waits.
1333 * PACKET0 - VLINE_START_END + value
1334 * PACKET0 - WAIT_UNTIL +_value
1335 * RELOC (P3) - crtc_id in reloc.
1336 *
1337 * This function parses this and relocates the VLINE START END
1338 * and WAIT UNTIL packets to the correct crtc.
1339 * It also detects a switched off crtc and nulls out the
1340 * wait in that case.
1341 */
r100_cs_packet_parse_vline(struct radeon_cs_parser * p)1342 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1343 {
1344 struct drm_mode_object *obj;
1345 struct drm_crtc *crtc;
1346 struct radeon_crtc *radeon_crtc;
1347 struct radeon_cs_packet p3reloc, waitreloc;
1348 int crtc_id;
1349 int r;
1350 uint32_t header, h_idx, reg;
1351 volatile uint32_t *ib;
1352
1353 ib = p->ib->ptr;
1354
1355 /* parse the wait until */
1356 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1357 if (r)
1358 return r;
1359
1360 /* check its a wait until and only 1 count */
1361 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1362 waitreloc.count != 0) {
1363 DRM_ERROR("vline wait had illegal wait until segment\n");
1364 return -EINVAL;
1365 }
1366
1367 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1368 DRM_ERROR("vline wait had illegal wait until\n");
1369 return -EINVAL;
1370 }
1371
1372 /* jump over the NOP */
1373 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1374 if (r)
1375 return r;
1376
1377 h_idx = p->idx - 2;
1378 p->idx += waitreloc.count + 2;
1379 p->idx += p3reloc.count + 2;
1380
1381 header = radeon_get_ib_value(p, h_idx);
1382 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1383 reg = CP_PACKET0_GET_REG(header);
1384 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1385 if (!obj) {
1386 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1387 return -EINVAL;
1388 }
1389 crtc = obj_to_crtc(obj);
1390 radeon_crtc = to_radeon_crtc(crtc);
1391 crtc_id = radeon_crtc->crtc_id;
1392
1393 if (!crtc->enabled) {
1394 /* if the CRTC isn't enabled - we need to nop out the wait until */
1395 ib[h_idx + 2] = PACKET2(0);
1396 ib[h_idx + 3] = PACKET2(0);
1397 } else if (crtc_id == 1) {
1398 switch (reg) {
1399 case AVIVO_D1MODE_VLINE_START_END:
1400 header &= ~R300_CP_PACKET0_REG_MASK;
1401 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1402 break;
1403 case RADEON_CRTC_GUI_TRIG_VLINE:
1404 header &= ~R300_CP_PACKET0_REG_MASK;
1405 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1406 break;
1407 default:
1408 DRM_ERROR("unknown crtc reloc\n");
1409 return -EINVAL;
1410 }
1411 ib[h_idx] = header;
1412 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1413 }
1414
1415 return 0;
1416 }
1417
1418 /**
1419 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1420 * @parser: parser structure holding parsing context.
1421 * @data: pointer to relocation data
1422 * @offset_start: starting offset
1423 * @offset_mask: offset mask (to align start offset on)
1424 * @reloc: reloc informations
1425 *
1426 * Check next packet is relocation packet3, do bo validation and compute
1427 * GPU offset using the provided start.
1428 **/
r100_cs_packet_next_reloc(struct radeon_cs_parser * p,struct radeon_cs_reloc ** cs_reloc)1429 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1430 struct radeon_cs_reloc **cs_reloc)
1431 {
1432 struct radeon_cs_chunk *relocs_chunk;
1433 struct radeon_cs_packet p3reloc;
1434 unsigned idx;
1435 int r;
1436
1437 if (p->chunk_relocs_idx == -1) {
1438 DRM_ERROR("No relocation chunk !\n");
1439 return -EINVAL;
1440 }
1441 *cs_reloc = NULL;
1442 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1443 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1444 if (r) {
1445 return r;
1446 }
1447 p->idx += p3reloc.count + 2;
1448 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1449 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1450 p3reloc.idx);
1451 r100_cs_dump_packet(p, &p3reloc);
1452 return -EINVAL;
1453 }
1454 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1455 if (idx >= relocs_chunk->length_dw) {
1456 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1457 idx, relocs_chunk->length_dw);
1458 r100_cs_dump_packet(p, &p3reloc);
1459 return -EINVAL;
1460 }
1461 /* FIXME: we assume reloc size is 4 dwords */
1462 *cs_reloc = p->relocs_ptr[(idx / 4)];
1463 return 0;
1464 }
1465
r100_get_vtx_size(uint32_t vtx_fmt)1466 static int r100_get_vtx_size(uint32_t vtx_fmt)
1467 {
1468 int vtx_size;
1469 vtx_size = 2;
1470 /* ordered according to bits in spec */
1471 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1472 vtx_size++;
1473 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1474 vtx_size += 3;
1475 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1476 vtx_size++;
1477 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1478 vtx_size++;
1479 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1480 vtx_size += 3;
1481 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1482 vtx_size++;
1483 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1484 vtx_size++;
1485 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1486 vtx_size += 2;
1487 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1488 vtx_size += 2;
1489 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1490 vtx_size++;
1491 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1492 vtx_size += 2;
1493 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1494 vtx_size++;
1495 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1496 vtx_size += 2;
1497 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1498 vtx_size++;
1499 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1500 vtx_size++;
1501 /* blend weight */
1502 if (vtx_fmt & (0x7 << 15))
1503 vtx_size += (vtx_fmt >> 15) & 0x7;
1504 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1505 vtx_size += 3;
1506 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1507 vtx_size += 2;
1508 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1509 vtx_size++;
1510 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1511 vtx_size++;
1512 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1513 vtx_size++;
1514 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1515 vtx_size++;
1516 return vtx_size;
1517 }
1518
r100_packet0_check(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,unsigned idx,unsigned reg)1519 static int r100_packet0_check(struct radeon_cs_parser *p,
1520 struct radeon_cs_packet *pkt,
1521 unsigned idx, unsigned reg)
1522 {
1523 struct radeon_cs_reloc *reloc;
1524 struct r100_cs_track *track;
1525 volatile uint32_t *ib;
1526 uint32_t tmp;
1527 int r;
1528 int i, face;
1529 u32 tile_flags = 0;
1530 u32 idx_value;
1531
1532 ib = p->ib->ptr;
1533 track = (struct r100_cs_track *)p->track;
1534
1535 idx_value = radeon_get_ib_value(p, idx);
1536
1537 switch (reg) {
1538 case RADEON_CRTC_GUI_TRIG_VLINE:
1539 r = r100_cs_packet_parse_vline(p);
1540 if (r) {
1541 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1542 idx, reg);
1543 r100_cs_dump_packet(p, pkt);
1544 return r;
1545 }
1546 break;
1547 /* FIXME: only allow PACKET3 blit? easier to check for out of
1548 * range access */
1549 case RADEON_DST_PITCH_OFFSET:
1550 case RADEON_SRC_PITCH_OFFSET:
1551 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1552 if (r)
1553 return r;
1554 break;
1555 case RADEON_RB3D_DEPTHOFFSET:
1556 r = r100_cs_packet_next_reloc(p, &reloc);
1557 if (r) {
1558 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1559 idx, reg);
1560 r100_cs_dump_packet(p, pkt);
1561 return r;
1562 }
1563 track->zb.robj = reloc->robj;
1564 track->zb.offset = idx_value;
1565 track->zb_dirty = true;
1566 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1567 break;
1568 case RADEON_RB3D_COLOROFFSET:
1569 r = r100_cs_packet_next_reloc(p, &reloc);
1570 if (r) {
1571 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1572 idx, reg);
1573 r100_cs_dump_packet(p, pkt);
1574 return r;
1575 }
1576 track->cb[0].robj = reloc->robj;
1577 track->cb[0].offset = idx_value;
1578 track->cb_dirty = true;
1579 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1580 break;
1581 case RADEON_PP_TXOFFSET_0:
1582 case RADEON_PP_TXOFFSET_1:
1583 case RADEON_PP_TXOFFSET_2:
1584 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1585 r = r100_cs_packet_next_reloc(p, &reloc);
1586 if (r) {
1587 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1588 idx, reg);
1589 r100_cs_dump_packet(p, pkt);
1590 return r;
1591 }
1592 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1593 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1594 tile_flags |= RADEON_TXO_MACRO_TILE;
1595 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1596 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1597
1598 tmp = idx_value & ~(0x7 << 2);
1599 tmp |= tile_flags;
1600 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1601 } else
1602 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1603 track->textures[i].robj = reloc->robj;
1604 track->tex_dirty = true;
1605 break;
1606 case RADEON_PP_CUBIC_OFFSET_T0_0:
1607 case RADEON_PP_CUBIC_OFFSET_T0_1:
1608 case RADEON_PP_CUBIC_OFFSET_T0_2:
1609 case RADEON_PP_CUBIC_OFFSET_T0_3:
1610 case RADEON_PP_CUBIC_OFFSET_T0_4:
1611 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1612 r = r100_cs_packet_next_reloc(p, &reloc);
1613 if (r) {
1614 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1615 idx, reg);
1616 r100_cs_dump_packet(p, pkt);
1617 return r;
1618 }
1619 track->textures[0].cube_info[i].offset = idx_value;
1620 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1621 track->textures[0].cube_info[i].robj = reloc->robj;
1622 track->tex_dirty = true;
1623 break;
1624 case RADEON_PP_CUBIC_OFFSET_T1_0:
1625 case RADEON_PP_CUBIC_OFFSET_T1_1:
1626 case RADEON_PP_CUBIC_OFFSET_T1_2:
1627 case RADEON_PP_CUBIC_OFFSET_T1_3:
1628 case RADEON_PP_CUBIC_OFFSET_T1_4:
1629 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1630 r = r100_cs_packet_next_reloc(p, &reloc);
1631 if (r) {
1632 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1633 idx, reg);
1634 r100_cs_dump_packet(p, pkt);
1635 return r;
1636 }
1637 track->textures[1].cube_info[i].offset = idx_value;
1638 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1639 track->textures[1].cube_info[i].robj = reloc->robj;
1640 track->tex_dirty = true;
1641 break;
1642 case RADEON_PP_CUBIC_OFFSET_T2_0:
1643 case RADEON_PP_CUBIC_OFFSET_T2_1:
1644 case RADEON_PP_CUBIC_OFFSET_T2_2:
1645 case RADEON_PP_CUBIC_OFFSET_T2_3:
1646 case RADEON_PP_CUBIC_OFFSET_T2_4:
1647 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1648 r = r100_cs_packet_next_reloc(p, &reloc);
1649 if (r) {
1650 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1651 idx, reg);
1652 r100_cs_dump_packet(p, pkt);
1653 return r;
1654 }
1655 track->textures[2].cube_info[i].offset = idx_value;
1656 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1657 track->textures[2].cube_info[i].robj = reloc->robj;
1658 track->tex_dirty = true;
1659 break;
1660 case RADEON_RE_WIDTH_HEIGHT:
1661 track->maxy = ((idx_value >> 16) & 0x7FF);
1662 track->cb_dirty = true;
1663 track->zb_dirty = true;
1664 break;
1665 case RADEON_RB3D_COLORPITCH:
1666 r = r100_cs_packet_next_reloc(p, &reloc);
1667 if (r) {
1668 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1669 idx, reg);
1670 r100_cs_dump_packet(p, pkt);
1671 return r;
1672 }
1673 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1674 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1675 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1676 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1677 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1678
1679 tmp = idx_value & ~(0x7 << 16);
1680 tmp |= tile_flags;
1681 ib[idx] = tmp;
1682 } else
1683 ib[idx] = idx_value;
1684
1685 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1686 track->cb_dirty = true;
1687 break;
1688 case RADEON_RB3D_DEPTHPITCH:
1689 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1690 track->zb_dirty = true;
1691 break;
1692 case RADEON_RB3D_CNTL:
1693 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1694 case 7:
1695 case 8:
1696 case 9:
1697 case 11:
1698 case 12:
1699 track->cb[0].cpp = 1;
1700 break;
1701 case 3:
1702 case 4:
1703 case 15:
1704 track->cb[0].cpp = 2;
1705 break;
1706 case 6:
1707 track->cb[0].cpp = 4;
1708 break;
1709 default:
1710 DRM_ERROR("Invalid color buffer format (%d) !\n",
1711 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1712 return -EINVAL;
1713 }
1714 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1715 track->cb_dirty = true;
1716 track->zb_dirty = true;
1717 break;
1718 case RADEON_RB3D_ZSTENCILCNTL:
1719 switch (idx_value & 0xf) {
1720 case 0:
1721 track->zb.cpp = 2;
1722 break;
1723 case 2:
1724 case 3:
1725 case 4:
1726 case 5:
1727 case 9:
1728 case 11:
1729 track->zb.cpp = 4;
1730 break;
1731 default:
1732 break;
1733 }
1734 track->zb_dirty = true;
1735 break;
1736 case RADEON_RB3D_ZPASS_ADDR:
1737 r = r100_cs_packet_next_reloc(p, &reloc);
1738 if (r) {
1739 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1740 idx, reg);
1741 r100_cs_dump_packet(p, pkt);
1742 return r;
1743 }
1744 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1745 break;
1746 case RADEON_PP_CNTL:
1747 {
1748 uint32_t temp = idx_value >> 4;
1749 for (i = 0; i < track->num_texture; i++)
1750 track->textures[i].enabled = !!(temp & (1 << i));
1751 track->tex_dirty = true;
1752 }
1753 break;
1754 case RADEON_SE_VF_CNTL:
1755 track->vap_vf_cntl = idx_value;
1756 break;
1757 case RADEON_SE_VTX_FMT:
1758 track->vtx_size = r100_get_vtx_size(idx_value);
1759 break;
1760 case RADEON_PP_TEX_SIZE_0:
1761 case RADEON_PP_TEX_SIZE_1:
1762 case RADEON_PP_TEX_SIZE_2:
1763 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1764 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1765 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1766 track->tex_dirty = true;
1767 break;
1768 case RADEON_PP_TEX_PITCH_0:
1769 case RADEON_PP_TEX_PITCH_1:
1770 case RADEON_PP_TEX_PITCH_2:
1771 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1772 track->textures[i].pitch = idx_value + 32;
1773 track->tex_dirty = true;
1774 break;
1775 case RADEON_PP_TXFILTER_0:
1776 case RADEON_PP_TXFILTER_1:
1777 case RADEON_PP_TXFILTER_2:
1778 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1779 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1780 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1781 tmp = (idx_value >> 23) & 0x7;
1782 if (tmp == 2 || tmp == 6)
1783 track->textures[i].roundup_w = false;
1784 tmp = (idx_value >> 27) & 0x7;
1785 if (tmp == 2 || tmp == 6)
1786 track->textures[i].roundup_h = false;
1787 track->tex_dirty = true;
1788 break;
1789 case RADEON_PP_TXFORMAT_0:
1790 case RADEON_PP_TXFORMAT_1:
1791 case RADEON_PP_TXFORMAT_2:
1792 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1793 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1794 track->textures[i].use_pitch = 1;
1795 } else {
1796 track->textures[i].use_pitch = 0;
1797 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1798 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1799 }
1800 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1801 track->textures[i].tex_coord_type = 2;
1802 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1803 case RADEON_TXFORMAT_I8:
1804 case RADEON_TXFORMAT_RGB332:
1805 case RADEON_TXFORMAT_Y8:
1806 track->textures[i].cpp = 1;
1807 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1808 break;
1809 case RADEON_TXFORMAT_AI88:
1810 case RADEON_TXFORMAT_ARGB1555:
1811 case RADEON_TXFORMAT_RGB565:
1812 case RADEON_TXFORMAT_ARGB4444:
1813 case RADEON_TXFORMAT_VYUY422:
1814 case RADEON_TXFORMAT_YVYU422:
1815 case RADEON_TXFORMAT_SHADOW16:
1816 case RADEON_TXFORMAT_LDUDV655:
1817 case RADEON_TXFORMAT_DUDV88:
1818 track->textures[i].cpp = 2;
1819 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1820 break;
1821 case RADEON_TXFORMAT_ARGB8888:
1822 case RADEON_TXFORMAT_RGBA8888:
1823 case RADEON_TXFORMAT_SHADOW32:
1824 case RADEON_TXFORMAT_LDUDUV8888:
1825 track->textures[i].cpp = 4;
1826 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1827 break;
1828 case RADEON_TXFORMAT_DXT1:
1829 track->textures[i].cpp = 1;
1830 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1831 break;
1832 case RADEON_TXFORMAT_DXT23:
1833 case RADEON_TXFORMAT_DXT45:
1834 track->textures[i].cpp = 1;
1835 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1836 break;
1837 }
1838 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1839 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1840 track->tex_dirty = true;
1841 break;
1842 case RADEON_PP_CUBIC_FACES_0:
1843 case RADEON_PP_CUBIC_FACES_1:
1844 case RADEON_PP_CUBIC_FACES_2:
1845 tmp = idx_value;
1846 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1847 for (face = 0; face < 4; face++) {
1848 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1849 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1850 }
1851 track->tex_dirty = true;
1852 break;
1853 default:
1854 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1855 reg, idx);
1856 return -EINVAL;
1857 }
1858 return 0;
1859 }
1860
r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt,struct radeon_bo * robj)1861 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1862 struct radeon_cs_packet *pkt,
1863 struct radeon_bo *robj)
1864 {
1865 unsigned idx;
1866 u32 value;
1867 idx = pkt->idx + 1;
1868 value = radeon_get_ib_value(p, idx + 2);
1869 if ((value + 1) > radeon_bo_size(robj)) {
1870 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1871 "(need %u have %lu) !\n",
1872 value + 1,
1873 radeon_bo_size(robj));
1874 return -EINVAL;
1875 }
1876 return 0;
1877 }
1878
r100_packet3_check(struct radeon_cs_parser * p,struct radeon_cs_packet * pkt)1879 static int r100_packet3_check(struct radeon_cs_parser *p,
1880 struct radeon_cs_packet *pkt)
1881 {
1882 struct radeon_cs_reloc *reloc;
1883 struct r100_cs_track *track;
1884 unsigned idx;
1885 volatile uint32_t *ib;
1886 int r;
1887
1888 ib = p->ib->ptr;
1889 idx = pkt->idx + 1;
1890 track = (struct r100_cs_track *)p->track;
1891 switch (pkt->opcode) {
1892 case PACKET3_3D_LOAD_VBPNTR:
1893 r = r100_packet3_load_vbpntr(p, pkt, idx);
1894 if (r)
1895 return r;
1896 break;
1897 case PACKET3_INDX_BUFFER:
1898 r = r100_cs_packet_next_reloc(p, &reloc);
1899 if (r) {
1900 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1901 r100_cs_dump_packet(p, pkt);
1902 return r;
1903 }
1904 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1905 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1906 if (r) {
1907 return r;
1908 }
1909 break;
1910 case 0x23:
1911 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1912 r = r100_cs_packet_next_reloc(p, &reloc);
1913 if (r) {
1914 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1915 r100_cs_dump_packet(p, pkt);
1916 return r;
1917 }
1918 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1919 track->num_arrays = 1;
1920 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1921
1922 track->arrays[0].robj = reloc->robj;
1923 track->arrays[0].esize = track->vtx_size;
1924
1925 track->max_indx = radeon_get_ib_value(p, idx+1);
1926
1927 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1928 track->immd_dwords = pkt->count - 1;
1929 r = r100_cs_track_check(p->rdev, track);
1930 if (r)
1931 return r;
1932 break;
1933 case PACKET3_3D_DRAW_IMMD:
1934 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1935 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1936 return -EINVAL;
1937 }
1938 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1939 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1940 track->immd_dwords = pkt->count - 1;
1941 r = r100_cs_track_check(p->rdev, track);
1942 if (r)
1943 return r;
1944 break;
1945 /* triggers drawing using in-packet vertex data */
1946 case PACKET3_3D_DRAW_IMMD_2:
1947 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1948 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1949 return -EINVAL;
1950 }
1951 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1952 track->immd_dwords = pkt->count;
1953 r = r100_cs_track_check(p->rdev, track);
1954 if (r)
1955 return r;
1956 break;
1957 /* triggers drawing using in-packet vertex data */
1958 case PACKET3_3D_DRAW_VBUF_2:
1959 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1960 r = r100_cs_track_check(p->rdev, track);
1961 if (r)
1962 return r;
1963 break;
1964 /* triggers drawing of vertex buffers setup elsewhere */
1965 case PACKET3_3D_DRAW_INDX_2:
1966 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1967 r = r100_cs_track_check(p->rdev, track);
1968 if (r)
1969 return r;
1970 break;
1971 /* triggers drawing using indices to vertex buffer */
1972 case PACKET3_3D_DRAW_VBUF:
1973 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1974 r = r100_cs_track_check(p->rdev, track);
1975 if (r)
1976 return r;
1977 break;
1978 /* triggers drawing of vertex buffers setup elsewhere */
1979 case PACKET3_3D_DRAW_INDX:
1980 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1981 r = r100_cs_track_check(p->rdev, track);
1982 if (r)
1983 return r;
1984 break;
1985 /* triggers drawing using indices to vertex buffer */
1986 case PACKET3_3D_CLEAR_HIZ:
1987 case PACKET3_3D_CLEAR_ZMASK:
1988 if (p->rdev->hyperz_filp != p->filp)
1989 return -EINVAL;
1990 break;
1991 case PACKET3_NOP:
1992 break;
1993 default:
1994 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1995 return -EINVAL;
1996 }
1997 return 0;
1998 }
1999
r100_cs_parse(struct radeon_cs_parser * p)2000 int r100_cs_parse(struct radeon_cs_parser *p)
2001 {
2002 struct radeon_cs_packet pkt;
2003 struct r100_cs_track *track;
2004 int r;
2005
2006 track = kzalloc(sizeof(*track), GFP_KERNEL);
2007 r100_cs_track_clear(p->rdev, track);
2008 p->track = track;
2009 do {
2010 r = r100_cs_packet_parse(p, &pkt, p->idx);
2011 if (r) {
2012 return r;
2013 }
2014 p->idx += pkt.count + 2;
2015 switch (pkt.type) {
2016 case PACKET_TYPE0:
2017 if (p->rdev->family >= CHIP_R200)
2018 r = r100_cs_parse_packet0(p, &pkt,
2019 p->rdev->config.r100.reg_safe_bm,
2020 p->rdev->config.r100.reg_safe_bm_size,
2021 &r200_packet0_check);
2022 else
2023 r = r100_cs_parse_packet0(p, &pkt,
2024 p->rdev->config.r100.reg_safe_bm,
2025 p->rdev->config.r100.reg_safe_bm_size,
2026 &r100_packet0_check);
2027 break;
2028 case PACKET_TYPE2:
2029 break;
2030 case PACKET_TYPE3:
2031 r = r100_packet3_check(p, &pkt);
2032 break;
2033 default:
2034 DRM_ERROR("Unknown packet type %d !\n",
2035 pkt.type);
2036 return -EINVAL;
2037 }
2038 if (r) {
2039 return r;
2040 }
2041 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2042 return 0;
2043 }
2044
2045
2046 /*
2047 * Global GPU functions
2048 */
r100_errata(struct radeon_device * rdev)2049 void r100_errata(struct radeon_device *rdev)
2050 {
2051 rdev->pll_errata = 0;
2052
2053 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2054 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2055 }
2056
2057 if (rdev->family == CHIP_RV100 ||
2058 rdev->family == CHIP_RS100 ||
2059 rdev->family == CHIP_RS200) {
2060 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2061 }
2062 }
2063
2064 /* Wait for vertical sync on primary CRTC */
r100_gpu_wait_for_vsync(struct radeon_device * rdev)2065 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2066 {
2067 uint32_t crtc_gen_cntl, tmp;
2068 int i;
2069
2070 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2071 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2072 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2073 return;
2074 }
2075 /* Clear the CRTC_VBLANK_SAVE bit */
2076 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2077 for (i = 0; i < rdev->usec_timeout; i++) {
2078 tmp = RREG32(RADEON_CRTC_STATUS);
2079 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2080 return;
2081 }
2082 DRM_UDELAY(1);
2083 }
2084 }
2085
2086 /* Wait for vertical sync on secondary CRTC */
r100_gpu_wait_for_vsync2(struct radeon_device * rdev)2087 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2088 {
2089 uint32_t crtc2_gen_cntl, tmp;
2090 int i;
2091
2092 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2093 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2094 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2095 return;
2096
2097 /* Clear the CRTC_VBLANK_SAVE bit */
2098 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2099 for (i = 0; i < rdev->usec_timeout; i++) {
2100 tmp = RREG32(RADEON_CRTC2_STATUS);
2101 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2102 return;
2103 }
2104 DRM_UDELAY(1);
2105 }
2106 }
2107
r100_rbbm_fifo_wait_for_entry(struct radeon_device * rdev,unsigned n)2108 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2109 {
2110 unsigned i;
2111 uint32_t tmp;
2112
2113 for (i = 0; i < rdev->usec_timeout; i++) {
2114 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2115 if (tmp >= n) {
2116 return 0;
2117 }
2118 DRM_UDELAY(1);
2119 }
2120 return -1;
2121 }
2122
r100_gui_wait_for_idle(struct radeon_device * rdev)2123 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2124 {
2125 unsigned i;
2126 uint32_t tmp;
2127
2128 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2129 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2130 " Bad things might happen.\n");
2131 }
2132 for (i = 0; i < rdev->usec_timeout; i++) {
2133 tmp = RREG32(RADEON_RBBM_STATUS);
2134 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2135 return 0;
2136 }
2137 DRM_UDELAY(1);
2138 }
2139 return -1;
2140 }
2141
r100_mc_wait_for_idle(struct radeon_device * rdev)2142 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2143 {
2144 unsigned i;
2145 uint32_t tmp;
2146
2147 for (i = 0; i < rdev->usec_timeout; i++) {
2148 /* read MC_STATUS */
2149 tmp = RREG32(RADEON_MC_STATUS);
2150 if (tmp & RADEON_MC_IDLE) {
2151 return 0;
2152 }
2153 DRM_UDELAY(1);
2154 }
2155 return -1;
2156 }
2157
r100_gpu_lockup_update(struct r100_gpu_lockup * lockup,struct radeon_ring * ring)2158 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_ring *ring)
2159 {
2160 lockup->last_cp_rptr = ring->rptr;
2161 lockup->last_jiffies = jiffies;
2162 }
2163
2164 /**
2165 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2166 * @rdev: radeon device structure
2167 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
2168 * @cp: radeon_cp structure holding CP information
2169 *
2170 * We don't need to initialize the lockup tracking information as we will either
2171 * have CP rptr to a different value of jiffies wrap around which will force
2172 * initialization of the lockup tracking informations.
2173 *
2174 * A possible false positivie is if we get call after while and last_cp_rptr ==
2175 * the current CP rptr, even if it's unlikely it might happen. To avoid this
2176 * if the elapsed time since last call is bigger than 2 second than we return
2177 * false and update the tracking information. Due to this the caller must call
2178 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2179 * the fencing code should be cautious about that.
2180 *
2181 * Caller should write to the ring to force CP to do something so we don't get
2182 * false positive when CP is just gived nothing to do.
2183 *
2184 **/
r100_gpu_cp_is_lockup(struct radeon_device * rdev,struct r100_gpu_lockup * lockup,struct radeon_ring * ring)2185 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_ring *ring)
2186 {
2187 unsigned long cjiffies, elapsed;
2188
2189 cjiffies = jiffies;
2190 if (!time_after(cjiffies, lockup->last_jiffies)) {
2191 /* likely a wrap around */
2192 lockup->last_cp_rptr = ring->rptr;
2193 lockup->last_jiffies = jiffies;
2194 return false;
2195 }
2196 if (ring->rptr != lockup->last_cp_rptr) {
2197 /* CP is still working no lockup */
2198 lockup->last_cp_rptr = ring->rptr;
2199 lockup->last_jiffies = jiffies;
2200 return false;
2201 }
2202 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2203 if (elapsed >= 10000) {
2204 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2205 return true;
2206 }
2207 /* give a chance to the GPU ... */
2208 return false;
2209 }
2210
r100_gpu_is_lockup(struct radeon_device * rdev,struct radeon_ring * ring)2211 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2212 {
2213 u32 rbbm_status;
2214 int r;
2215
2216 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2217 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2218 r100_gpu_lockup_update(&rdev->config.r100.lockup, ring);
2219 return false;
2220 }
2221 /* force CP activities */
2222 r = radeon_ring_lock(rdev, ring, 2);
2223 if (!r) {
2224 /* PACKET2 NOP */
2225 radeon_ring_write(ring, 0x80000000);
2226 radeon_ring_write(ring, 0x80000000);
2227 radeon_ring_unlock_commit(rdev, ring);
2228 }
2229 ring->rptr = RREG32(ring->rptr_reg);
2230 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, ring);
2231 }
2232
r100_bm_disable(struct radeon_device * rdev)2233 void r100_bm_disable(struct radeon_device *rdev)
2234 {
2235 u32 tmp;
2236
2237 /* disable bus mastering */
2238 tmp = RREG32(R_000030_BUS_CNTL);
2239 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2240 mdelay(1);
2241 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2242 mdelay(1);
2243 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2244 tmp = RREG32(RADEON_BUS_CNTL);
2245 mdelay(1);
2246 pci_clear_master(rdev->pdev);
2247 mdelay(1);
2248 }
2249
r100_asic_reset(struct radeon_device * rdev)2250 int r100_asic_reset(struct radeon_device *rdev)
2251 {
2252 struct r100_mc_save save;
2253 u32 status, tmp;
2254 int ret = 0;
2255
2256 status = RREG32(R_000E40_RBBM_STATUS);
2257 if (!G_000E40_GUI_ACTIVE(status)) {
2258 return 0;
2259 }
2260 r100_mc_stop(rdev, &save);
2261 status = RREG32(R_000E40_RBBM_STATUS);
2262 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2263 /* stop CP */
2264 WREG32(RADEON_CP_CSQ_CNTL, 0);
2265 tmp = RREG32(RADEON_CP_RB_CNTL);
2266 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2267 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2268 WREG32(RADEON_CP_RB_WPTR, 0);
2269 WREG32(RADEON_CP_RB_CNTL, tmp);
2270 /* save PCI state */
2271 pci_save_state(rdev->pdev);
2272 /* disable bus mastering */
2273 r100_bm_disable(rdev);
2274 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2275 S_0000F0_SOFT_RESET_RE(1) |
2276 S_0000F0_SOFT_RESET_PP(1) |
2277 S_0000F0_SOFT_RESET_RB(1));
2278 RREG32(R_0000F0_RBBM_SOFT_RESET);
2279 mdelay(500);
2280 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2281 mdelay(1);
2282 status = RREG32(R_000E40_RBBM_STATUS);
2283 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2284 /* reset CP */
2285 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2286 RREG32(R_0000F0_RBBM_SOFT_RESET);
2287 mdelay(500);
2288 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2289 mdelay(1);
2290 status = RREG32(R_000E40_RBBM_STATUS);
2291 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2292 /* restore PCI & busmastering */
2293 pci_restore_state(rdev->pdev);
2294 r100_enable_bm(rdev);
2295 /* Check if GPU is idle */
2296 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2297 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2298 dev_err(rdev->dev, "failed to reset GPU\n");
2299 rdev->gpu_lockup = true;
2300 ret = -1;
2301 } else
2302 dev_info(rdev->dev, "GPU reset succeed\n");
2303 r100_mc_resume(rdev, &save);
2304 return ret;
2305 }
2306
r100_set_common_regs(struct radeon_device * rdev)2307 void r100_set_common_regs(struct radeon_device *rdev)
2308 {
2309 struct drm_device *dev = rdev->ddev;
2310 bool force_dac2 = false;
2311 u32 tmp;
2312
2313 /* set these so they don't interfere with anything */
2314 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2315 WREG32(RADEON_SUBPIC_CNTL, 0);
2316 WREG32(RADEON_VIPH_CONTROL, 0);
2317 WREG32(RADEON_I2C_CNTL_1, 0);
2318 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2319 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2320 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2321
2322 /* always set up dac2 on rn50 and some rv100 as lots
2323 * of servers seem to wire it up to a VGA port but
2324 * don't report it in the bios connector
2325 * table.
2326 */
2327 switch (dev->pdev->device) {
2328 /* RN50 */
2329 case 0x515e:
2330 case 0x5969:
2331 force_dac2 = true;
2332 break;
2333 /* RV100*/
2334 case 0x5159:
2335 case 0x515a:
2336 /* DELL triple head servers */
2337 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2338 ((dev->pdev->subsystem_device == 0x016c) ||
2339 (dev->pdev->subsystem_device == 0x016d) ||
2340 (dev->pdev->subsystem_device == 0x016e) ||
2341 (dev->pdev->subsystem_device == 0x016f) ||
2342 (dev->pdev->subsystem_device == 0x0170) ||
2343 (dev->pdev->subsystem_device == 0x017d) ||
2344 (dev->pdev->subsystem_device == 0x017e) ||
2345 (dev->pdev->subsystem_device == 0x0183) ||
2346 (dev->pdev->subsystem_device == 0x018a) ||
2347 (dev->pdev->subsystem_device == 0x019a)))
2348 force_dac2 = true;
2349 break;
2350 }
2351
2352 if (force_dac2) {
2353 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2354 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2355 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2356
2357 /* For CRT on DAC2, don't turn it on if BIOS didn't
2358 enable it, even it's detected.
2359 */
2360
2361 /* force it to crtc0 */
2362 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2363 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2364 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2365
2366 /* set up the TV DAC */
2367 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2368 RADEON_TV_DAC_STD_MASK |
2369 RADEON_TV_DAC_RDACPD |
2370 RADEON_TV_DAC_GDACPD |
2371 RADEON_TV_DAC_BDACPD |
2372 RADEON_TV_DAC_BGADJ_MASK |
2373 RADEON_TV_DAC_DACADJ_MASK);
2374 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2375 RADEON_TV_DAC_NHOLD |
2376 RADEON_TV_DAC_STD_PS2 |
2377 (0x58 << 16));
2378
2379 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2380 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2381 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2382 }
2383
2384 /* switch PM block to ACPI mode */
2385 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2386 tmp &= ~RADEON_PM_MODE_SEL;
2387 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2388
2389 }
2390
2391 /*
2392 * VRAM info
2393 */
r100_vram_get_type(struct radeon_device * rdev)2394 static void r100_vram_get_type(struct radeon_device *rdev)
2395 {
2396 uint32_t tmp;
2397
2398 rdev->mc.vram_is_ddr = false;
2399 if (rdev->flags & RADEON_IS_IGP)
2400 rdev->mc.vram_is_ddr = true;
2401 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2402 rdev->mc.vram_is_ddr = true;
2403 if ((rdev->family == CHIP_RV100) ||
2404 (rdev->family == CHIP_RS100) ||
2405 (rdev->family == CHIP_RS200)) {
2406 tmp = RREG32(RADEON_MEM_CNTL);
2407 if (tmp & RV100_HALF_MODE) {
2408 rdev->mc.vram_width = 32;
2409 } else {
2410 rdev->mc.vram_width = 64;
2411 }
2412 if (rdev->flags & RADEON_SINGLE_CRTC) {
2413 rdev->mc.vram_width /= 4;
2414 rdev->mc.vram_is_ddr = true;
2415 }
2416 } else if (rdev->family <= CHIP_RV280) {
2417 tmp = RREG32(RADEON_MEM_CNTL);
2418 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2419 rdev->mc.vram_width = 128;
2420 } else {
2421 rdev->mc.vram_width = 64;
2422 }
2423 } else {
2424 /* newer IGPs */
2425 rdev->mc.vram_width = 128;
2426 }
2427 }
2428
r100_get_accessible_vram(struct radeon_device * rdev)2429 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2430 {
2431 u32 aper_size;
2432 u8 byte;
2433
2434 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2435
2436 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2437 * that is has the 2nd generation multifunction PCI interface
2438 */
2439 if (rdev->family == CHIP_RV280 ||
2440 rdev->family >= CHIP_RV350) {
2441 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2442 ~RADEON_HDP_APER_CNTL);
2443 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2444 return aper_size * 2;
2445 }
2446
2447 /* Older cards have all sorts of funny issues to deal with. First
2448 * check if it's a multifunction card by reading the PCI config
2449 * header type... Limit those to one aperture size
2450 */
2451 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2452 if (byte & 0x80) {
2453 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2454 DRM_INFO("Limiting VRAM to one aperture\n");
2455 return aper_size;
2456 }
2457
2458 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2459 * have set it up. We don't write this as it's broken on some ASICs but
2460 * we expect the BIOS to have done the right thing (might be too optimistic...)
2461 */
2462 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2463 return aper_size * 2;
2464 return aper_size;
2465 }
2466
r100_vram_init_sizes(struct radeon_device * rdev)2467 void r100_vram_init_sizes(struct radeon_device *rdev)
2468 {
2469 u64 config_aper_size;
2470
2471 /* work out accessible VRAM */
2472 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2473 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2474 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2475 /* FIXME we don't use the second aperture yet when we could use it */
2476 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2477 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2478 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2479 if (rdev->flags & RADEON_IS_IGP) {
2480 uint32_t tom;
2481 /* read NB_TOM to get the amount of ram stolen for the GPU */
2482 tom = RREG32(RADEON_NB_TOM);
2483 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2484 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2485 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2486 } else {
2487 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2488 /* Some production boards of m6 will report 0
2489 * if it's 8 MB
2490 */
2491 if (rdev->mc.real_vram_size == 0) {
2492 rdev->mc.real_vram_size = 8192 * 1024;
2493 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2494 }
2495 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2496 * Novell bug 204882 + along with lots of ubuntu ones
2497 */
2498 if (rdev->mc.aper_size > config_aper_size)
2499 config_aper_size = rdev->mc.aper_size;
2500
2501 if (config_aper_size > rdev->mc.real_vram_size)
2502 rdev->mc.mc_vram_size = config_aper_size;
2503 else
2504 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2505 }
2506 }
2507
r100_vga_set_state(struct radeon_device * rdev,bool state)2508 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2509 {
2510 uint32_t temp;
2511
2512 temp = RREG32(RADEON_CONFIG_CNTL);
2513 if (state == false) {
2514 temp &= ~RADEON_CFG_VGA_RAM_EN;
2515 temp |= RADEON_CFG_VGA_IO_DIS;
2516 } else {
2517 temp &= ~RADEON_CFG_VGA_IO_DIS;
2518 }
2519 WREG32(RADEON_CONFIG_CNTL, temp);
2520 }
2521
r100_mc_init(struct radeon_device * rdev)2522 void r100_mc_init(struct radeon_device *rdev)
2523 {
2524 u64 base;
2525
2526 r100_vram_get_type(rdev);
2527 r100_vram_init_sizes(rdev);
2528 base = rdev->mc.aper_base;
2529 if (rdev->flags & RADEON_IS_IGP)
2530 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2531 radeon_vram_location(rdev, &rdev->mc, base);
2532 rdev->mc.gtt_base_align = 0;
2533 if (!(rdev->flags & RADEON_IS_AGP))
2534 radeon_gtt_location(rdev, &rdev->mc);
2535 radeon_update_bandwidth_info(rdev);
2536 }
2537
2538
2539 /*
2540 * Indirect registers accessor
2541 */
r100_pll_errata_after_index(struct radeon_device * rdev)2542 void r100_pll_errata_after_index(struct radeon_device *rdev)
2543 {
2544 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2545 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2546 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2547 }
2548 }
2549
r100_pll_errata_after_data(struct radeon_device * rdev)2550 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2551 {
2552 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2553 * or the chip could hang on a subsequent access
2554 */
2555 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2556 mdelay(5);
2557 }
2558
2559 /* This function is required to workaround a hardware bug in some (all?)
2560 * revisions of the R300. This workaround should be called after every
2561 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2562 * may not be correct.
2563 */
2564 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2565 uint32_t save, tmp;
2566
2567 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2568 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2569 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2570 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2571 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2572 }
2573 }
2574
r100_pll_rreg(struct radeon_device * rdev,uint32_t reg)2575 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2576 {
2577 uint32_t data;
2578
2579 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2580 r100_pll_errata_after_index(rdev);
2581 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2582 r100_pll_errata_after_data(rdev);
2583 return data;
2584 }
2585
r100_pll_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)2586 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2587 {
2588 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2589 r100_pll_errata_after_index(rdev);
2590 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2591 r100_pll_errata_after_data(rdev);
2592 }
2593
r100_set_safe_registers(struct radeon_device * rdev)2594 void r100_set_safe_registers(struct radeon_device *rdev)
2595 {
2596 if (ASIC_IS_RN50(rdev)) {
2597 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2598 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2599 } else if (rdev->family < CHIP_R200) {
2600 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2601 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2602 } else {
2603 r200_set_safe_registers(rdev);
2604 }
2605 }
2606
2607 /*
2608 * Debugfs info
2609 */
2610 #if defined(CONFIG_DEBUG_FS)
r100_debugfs_rbbm_info(struct seq_file * m,void * data)2611 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2612 {
2613 struct drm_info_node *node = (struct drm_info_node *) m->private;
2614 struct drm_device *dev = node->minor->dev;
2615 struct radeon_device *rdev = dev->dev_private;
2616 uint32_t reg, value;
2617 unsigned i;
2618
2619 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2620 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2621 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2622 for (i = 0; i < 64; i++) {
2623 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2624 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2625 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2626 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2627 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2628 }
2629 return 0;
2630 }
2631
r100_debugfs_cp_ring_info(struct seq_file * m,void * data)2632 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2633 {
2634 struct drm_info_node *node = (struct drm_info_node *) m->private;
2635 struct drm_device *dev = node->minor->dev;
2636 struct radeon_device *rdev = dev->dev_private;
2637 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2638 uint32_t rdp, wdp;
2639 unsigned count, i, j;
2640
2641 radeon_ring_free_size(rdev, ring);
2642 rdp = RREG32(RADEON_CP_RB_RPTR);
2643 wdp = RREG32(RADEON_CP_RB_WPTR);
2644 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2645 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2646 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2647 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2648 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2649 seq_printf(m, "%u dwords in ring\n", count);
2650 for (j = 0; j <= count; j++) {
2651 i = (rdp + j) & ring->ptr_mask;
2652 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2653 }
2654 return 0;
2655 }
2656
2657
r100_debugfs_cp_csq_fifo(struct seq_file * m,void * data)2658 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2659 {
2660 struct drm_info_node *node = (struct drm_info_node *) m->private;
2661 struct drm_device *dev = node->minor->dev;
2662 struct radeon_device *rdev = dev->dev_private;
2663 uint32_t csq_stat, csq2_stat, tmp;
2664 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2665 unsigned i;
2666
2667 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2668 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2669 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2670 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2671 r_rptr = (csq_stat >> 0) & 0x3ff;
2672 r_wptr = (csq_stat >> 10) & 0x3ff;
2673 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2674 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2675 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2676 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2677 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2678 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2679 seq_printf(m, "Ring rptr %u\n", r_rptr);
2680 seq_printf(m, "Ring wptr %u\n", r_wptr);
2681 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2682 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2683 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2684 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2685 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2686 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2687 seq_printf(m, "Ring fifo:\n");
2688 for (i = 0; i < 256; i++) {
2689 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2690 tmp = RREG32(RADEON_CP_CSQ_DATA);
2691 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2692 }
2693 seq_printf(m, "Indirect1 fifo:\n");
2694 for (i = 256; i <= 512; i++) {
2695 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2696 tmp = RREG32(RADEON_CP_CSQ_DATA);
2697 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2698 }
2699 seq_printf(m, "Indirect2 fifo:\n");
2700 for (i = 640; i < ib1_wptr; i++) {
2701 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2702 tmp = RREG32(RADEON_CP_CSQ_DATA);
2703 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2704 }
2705 return 0;
2706 }
2707
r100_debugfs_mc_info(struct seq_file * m,void * data)2708 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2709 {
2710 struct drm_info_node *node = (struct drm_info_node *) m->private;
2711 struct drm_device *dev = node->minor->dev;
2712 struct radeon_device *rdev = dev->dev_private;
2713 uint32_t tmp;
2714
2715 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2716 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2717 tmp = RREG32(RADEON_MC_FB_LOCATION);
2718 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2719 tmp = RREG32(RADEON_BUS_CNTL);
2720 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2721 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2722 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2723 tmp = RREG32(RADEON_AGP_BASE);
2724 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2725 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2726 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2727 tmp = RREG32(0x01D0);
2728 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2729 tmp = RREG32(RADEON_AIC_LO_ADDR);
2730 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2731 tmp = RREG32(RADEON_AIC_HI_ADDR);
2732 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2733 tmp = RREG32(0x01E4);
2734 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2735 return 0;
2736 }
2737
2738 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2739 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2740 };
2741
2742 static struct drm_info_list r100_debugfs_cp_list[] = {
2743 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2744 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2745 };
2746
2747 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2748 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2749 };
2750 #endif
2751
r100_debugfs_rbbm_init(struct radeon_device * rdev)2752 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2753 {
2754 #if defined(CONFIG_DEBUG_FS)
2755 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2756 #else
2757 return 0;
2758 #endif
2759 }
2760
r100_debugfs_cp_init(struct radeon_device * rdev)2761 int r100_debugfs_cp_init(struct radeon_device *rdev)
2762 {
2763 #if defined(CONFIG_DEBUG_FS)
2764 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2765 #else
2766 return 0;
2767 #endif
2768 }
2769
r100_debugfs_mc_info_init(struct radeon_device * rdev)2770 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2771 {
2772 #if defined(CONFIG_DEBUG_FS)
2773 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2774 #else
2775 return 0;
2776 #endif
2777 }
2778
r100_set_surface_reg(struct radeon_device * rdev,int reg,uint32_t tiling_flags,uint32_t pitch,uint32_t offset,uint32_t obj_size)2779 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2780 uint32_t tiling_flags, uint32_t pitch,
2781 uint32_t offset, uint32_t obj_size)
2782 {
2783 int surf_index = reg * 16;
2784 int flags = 0;
2785
2786 if (rdev->family <= CHIP_RS200) {
2787 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2788 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2789 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2790 if (tiling_flags & RADEON_TILING_MACRO)
2791 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2792 } else if (rdev->family <= CHIP_RV280) {
2793 if (tiling_flags & (RADEON_TILING_MACRO))
2794 flags |= R200_SURF_TILE_COLOR_MACRO;
2795 if (tiling_flags & RADEON_TILING_MICRO)
2796 flags |= R200_SURF_TILE_COLOR_MICRO;
2797 } else {
2798 if (tiling_flags & RADEON_TILING_MACRO)
2799 flags |= R300_SURF_TILE_MACRO;
2800 if (tiling_flags & RADEON_TILING_MICRO)
2801 flags |= R300_SURF_TILE_MICRO;
2802 }
2803
2804 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2805 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2806 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2807 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2808
2809 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2810 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2811 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2812 if (ASIC_IS_RN50(rdev))
2813 pitch /= 16;
2814 }
2815
2816 /* r100/r200 divide by 16 */
2817 if (rdev->family < CHIP_R300)
2818 flags |= pitch / 16;
2819 else
2820 flags |= pitch / 8;
2821
2822
2823 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2824 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2825 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2826 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2827 return 0;
2828 }
2829
r100_clear_surface_reg(struct radeon_device * rdev,int reg)2830 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2831 {
2832 int surf_index = reg * 16;
2833 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2834 }
2835
r100_bandwidth_update(struct radeon_device * rdev)2836 void r100_bandwidth_update(struct radeon_device *rdev)
2837 {
2838 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2839 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2840 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2841 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2842 fixed20_12 memtcas_ff[8] = {
2843 dfixed_init(1),
2844 dfixed_init(2),
2845 dfixed_init(3),
2846 dfixed_init(0),
2847 dfixed_init_half(1),
2848 dfixed_init_half(2),
2849 dfixed_init(0),
2850 };
2851 fixed20_12 memtcas_rs480_ff[8] = {
2852 dfixed_init(0),
2853 dfixed_init(1),
2854 dfixed_init(2),
2855 dfixed_init(3),
2856 dfixed_init(0),
2857 dfixed_init_half(1),
2858 dfixed_init_half(2),
2859 dfixed_init_half(3),
2860 };
2861 fixed20_12 memtcas2_ff[8] = {
2862 dfixed_init(0),
2863 dfixed_init(1),
2864 dfixed_init(2),
2865 dfixed_init(3),
2866 dfixed_init(4),
2867 dfixed_init(5),
2868 dfixed_init(6),
2869 dfixed_init(7),
2870 };
2871 fixed20_12 memtrbs[8] = {
2872 dfixed_init(1),
2873 dfixed_init_half(1),
2874 dfixed_init(2),
2875 dfixed_init_half(2),
2876 dfixed_init(3),
2877 dfixed_init_half(3),
2878 dfixed_init(4),
2879 dfixed_init_half(4)
2880 };
2881 fixed20_12 memtrbs_r4xx[8] = {
2882 dfixed_init(4),
2883 dfixed_init(5),
2884 dfixed_init(6),
2885 dfixed_init(7),
2886 dfixed_init(8),
2887 dfixed_init(9),
2888 dfixed_init(10),
2889 dfixed_init(11)
2890 };
2891 fixed20_12 min_mem_eff;
2892 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2893 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2894 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2895 disp_drain_rate2, read_return_rate;
2896 fixed20_12 time_disp1_drop_priority;
2897 int c;
2898 int cur_size = 16; /* in octawords */
2899 int critical_point = 0, critical_point2;
2900 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2901 int stop_req, max_stop_req;
2902 struct drm_display_mode *mode1 = NULL;
2903 struct drm_display_mode *mode2 = NULL;
2904 uint32_t pixel_bytes1 = 0;
2905 uint32_t pixel_bytes2 = 0;
2906
2907 radeon_update_display_priority(rdev);
2908
2909 if (rdev->mode_info.crtcs[0]->base.enabled) {
2910 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2911 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2912 }
2913 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2914 if (rdev->mode_info.crtcs[1]->base.enabled) {
2915 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2916 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2917 }
2918 }
2919
2920 min_mem_eff.full = dfixed_const_8(0);
2921 /* get modes */
2922 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2923 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2924 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2925 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2926 /* check crtc enables */
2927 if (mode2)
2928 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2929 if (mode1)
2930 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2931 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2932 }
2933
2934 /*
2935 * determine is there is enough bw for current mode
2936 */
2937 sclk_ff = rdev->pm.sclk;
2938 mclk_ff = rdev->pm.mclk;
2939
2940 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2941 temp_ff.full = dfixed_const(temp);
2942 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2943
2944 pix_clk.full = 0;
2945 pix_clk2.full = 0;
2946 peak_disp_bw.full = 0;
2947 if (mode1) {
2948 temp_ff.full = dfixed_const(1000);
2949 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2950 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2951 temp_ff.full = dfixed_const(pixel_bytes1);
2952 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2953 }
2954 if (mode2) {
2955 temp_ff.full = dfixed_const(1000);
2956 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2957 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2958 temp_ff.full = dfixed_const(pixel_bytes2);
2959 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2960 }
2961
2962 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2963 if (peak_disp_bw.full >= mem_bw.full) {
2964 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2965 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2966 }
2967
2968 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2969 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2970 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2971 mem_trcd = ((temp >> 2) & 0x3) + 1;
2972 mem_trp = ((temp & 0x3)) + 1;
2973 mem_tras = ((temp & 0x70) >> 4) + 1;
2974 } else if (rdev->family == CHIP_R300 ||
2975 rdev->family == CHIP_R350) { /* r300, r350 */
2976 mem_trcd = (temp & 0x7) + 1;
2977 mem_trp = ((temp >> 8) & 0x7) + 1;
2978 mem_tras = ((temp >> 11) & 0xf) + 4;
2979 } else if (rdev->family == CHIP_RV350 ||
2980 rdev->family <= CHIP_RV380) {
2981 /* rv3x0 */
2982 mem_trcd = (temp & 0x7) + 3;
2983 mem_trp = ((temp >> 8) & 0x7) + 3;
2984 mem_tras = ((temp >> 11) & 0xf) + 6;
2985 } else if (rdev->family == CHIP_R420 ||
2986 rdev->family == CHIP_R423 ||
2987 rdev->family == CHIP_RV410) {
2988 /* r4xx */
2989 mem_trcd = (temp & 0xf) + 3;
2990 if (mem_trcd > 15)
2991 mem_trcd = 15;
2992 mem_trp = ((temp >> 8) & 0xf) + 3;
2993 if (mem_trp > 15)
2994 mem_trp = 15;
2995 mem_tras = ((temp >> 12) & 0x1f) + 6;
2996 if (mem_tras > 31)
2997 mem_tras = 31;
2998 } else { /* RV200, R200 */
2999 mem_trcd = (temp & 0x7) + 1;
3000 mem_trp = ((temp >> 8) & 0x7) + 1;
3001 mem_tras = ((temp >> 12) & 0xf) + 4;
3002 }
3003 /* convert to FF */
3004 trcd_ff.full = dfixed_const(mem_trcd);
3005 trp_ff.full = dfixed_const(mem_trp);
3006 tras_ff.full = dfixed_const(mem_tras);
3007
3008 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3009 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3010 data = (temp & (7 << 20)) >> 20;
3011 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3012 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3013 tcas_ff = memtcas_rs480_ff[data];
3014 else
3015 tcas_ff = memtcas_ff[data];
3016 } else
3017 tcas_ff = memtcas2_ff[data];
3018
3019 if (rdev->family == CHIP_RS400 ||
3020 rdev->family == CHIP_RS480) {
3021 /* extra cas latency stored in bits 23-25 0-4 clocks */
3022 data = (temp >> 23) & 0x7;
3023 if (data < 5)
3024 tcas_ff.full += dfixed_const(data);
3025 }
3026
3027 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3028 /* on the R300, Tcas is included in Trbs.
3029 */
3030 temp = RREG32(RADEON_MEM_CNTL);
3031 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3032 if (data == 1) {
3033 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3034 temp = RREG32(R300_MC_IND_INDEX);
3035 temp &= ~R300_MC_IND_ADDR_MASK;
3036 temp |= R300_MC_READ_CNTL_CD_mcind;
3037 WREG32(R300_MC_IND_INDEX, temp);
3038 temp = RREG32(R300_MC_IND_DATA);
3039 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3040 } else {
3041 temp = RREG32(R300_MC_READ_CNTL_AB);
3042 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3043 }
3044 } else {
3045 temp = RREG32(R300_MC_READ_CNTL_AB);
3046 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3047 }
3048 if (rdev->family == CHIP_RV410 ||
3049 rdev->family == CHIP_R420 ||
3050 rdev->family == CHIP_R423)
3051 trbs_ff = memtrbs_r4xx[data];
3052 else
3053 trbs_ff = memtrbs[data];
3054 tcas_ff.full += trbs_ff.full;
3055 }
3056
3057 sclk_eff_ff.full = sclk_ff.full;
3058
3059 if (rdev->flags & RADEON_IS_AGP) {
3060 fixed20_12 agpmode_ff;
3061 agpmode_ff.full = dfixed_const(radeon_agpmode);
3062 temp_ff.full = dfixed_const_666(16);
3063 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3064 }
3065 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3066
3067 if (ASIC_IS_R300(rdev)) {
3068 sclk_delay_ff.full = dfixed_const(250);
3069 } else {
3070 if ((rdev->family == CHIP_RV100) ||
3071 rdev->flags & RADEON_IS_IGP) {
3072 if (rdev->mc.vram_is_ddr)
3073 sclk_delay_ff.full = dfixed_const(41);
3074 else
3075 sclk_delay_ff.full = dfixed_const(33);
3076 } else {
3077 if (rdev->mc.vram_width == 128)
3078 sclk_delay_ff.full = dfixed_const(57);
3079 else
3080 sclk_delay_ff.full = dfixed_const(41);
3081 }
3082 }
3083
3084 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3085
3086 if (rdev->mc.vram_is_ddr) {
3087 if (rdev->mc.vram_width == 32) {
3088 k1.full = dfixed_const(40);
3089 c = 3;
3090 } else {
3091 k1.full = dfixed_const(20);
3092 c = 1;
3093 }
3094 } else {
3095 k1.full = dfixed_const(40);
3096 c = 3;
3097 }
3098
3099 temp_ff.full = dfixed_const(2);
3100 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3101 temp_ff.full = dfixed_const(c);
3102 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3103 temp_ff.full = dfixed_const(4);
3104 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3105 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3106 mc_latency_mclk.full += k1.full;
3107
3108 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3109 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3110
3111 /*
3112 HW cursor time assuming worst case of full size colour cursor.
3113 */
3114 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3115 temp_ff.full += trcd_ff.full;
3116 if (temp_ff.full < tras_ff.full)
3117 temp_ff.full = tras_ff.full;
3118 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3119
3120 temp_ff.full = dfixed_const(cur_size);
3121 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3122 /*
3123 Find the total latency for the display data.
3124 */
3125 disp_latency_overhead.full = dfixed_const(8);
3126 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3127 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3128 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3129
3130 if (mc_latency_mclk.full > mc_latency_sclk.full)
3131 disp_latency.full = mc_latency_mclk.full;
3132 else
3133 disp_latency.full = mc_latency_sclk.full;
3134
3135 /* setup Max GRPH_STOP_REQ default value */
3136 if (ASIC_IS_RV100(rdev))
3137 max_stop_req = 0x5c;
3138 else
3139 max_stop_req = 0x7c;
3140
3141 if (mode1) {
3142 /* CRTC1
3143 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3144 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3145 */
3146 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3147
3148 if (stop_req > max_stop_req)
3149 stop_req = max_stop_req;
3150
3151 /*
3152 Find the drain rate of the display buffer.
3153 */
3154 temp_ff.full = dfixed_const((16/pixel_bytes1));
3155 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3156
3157 /*
3158 Find the critical point of the display buffer.
3159 */
3160 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3161 crit_point_ff.full += dfixed_const_half(0);
3162
3163 critical_point = dfixed_trunc(crit_point_ff);
3164
3165 if (rdev->disp_priority == 2) {
3166 critical_point = 0;
3167 }
3168
3169 /*
3170 The critical point should never be above max_stop_req-4. Setting
3171 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3172 */
3173 if (max_stop_req - critical_point < 4)
3174 critical_point = 0;
3175
3176 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3177 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3178 critical_point = 0x10;
3179 }
3180
3181 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3182 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3183 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3184 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3185 if ((rdev->family == CHIP_R350) &&
3186 (stop_req > 0x15)) {
3187 stop_req -= 0x10;
3188 }
3189 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3190 temp |= RADEON_GRPH_BUFFER_SIZE;
3191 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3192 RADEON_GRPH_CRITICAL_AT_SOF |
3193 RADEON_GRPH_STOP_CNTL);
3194 /*
3195 Write the result into the register.
3196 */
3197 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3198 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3199
3200 #if 0
3201 if ((rdev->family == CHIP_RS400) ||
3202 (rdev->family == CHIP_RS480)) {
3203 /* attempt to program RS400 disp regs correctly ??? */
3204 temp = RREG32(RS400_DISP1_REG_CNTL);
3205 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3206 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3207 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3208 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3209 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3210 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3211 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3212 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3213 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3214 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3215 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3216 }
3217 #endif
3218
3219 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3220 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3221 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3222 }
3223
3224 if (mode2) {
3225 u32 grph2_cntl;
3226 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3227
3228 if (stop_req > max_stop_req)
3229 stop_req = max_stop_req;
3230
3231 /*
3232 Find the drain rate of the display buffer.
3233 */
3234 temp_ff.full = dfixed_const((16/pixel_bytes2));
3235 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3236
3237 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3238 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3239 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3240 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3241 if ((rdev->family == CHIP_R350) &&
3242 (stop_req > 0x15)) {
3243 stop_req -= 0x10;
3244 }
3245 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3246 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3247 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3248 RADEON_GRPH_CRITICAL_AT_SOF |
3249 RADEON_GRPH_STOP_CNTL);
3250
3251 if ((rdev->family == CHIP_RS100) ||
3252 (rdev->family == CHIP_RS200))
3253 critical_point2 = 0;
3254 else {
3255 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3256 temp_ff.full = dfixed_const(temp);
3257 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3258 if (sclk_ff.full < temp_ff.full)
3259 temp_ff.full = sclk_ff.full;
3260
3261 read_return_rate.full = temp_ff.full;
3262
3263 if (mode1) {
3264 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3265 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3266 } else {
3267 time_disp1_drop_priority.full = 0;
3268 }
3269 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3270 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3271 crit_point_ff.full += dfixed_const_half(0);
3272
3273 critical_point2 = dfixed_trunc(crit_point_ff);
3274
3275 if (rdev->disp_priority == 2) {
3276 critical_point2 = 0;
3277 }
3278
3279 if (max_stop_req - critical_point2 < 4)
3280 critical_point2 = 0;
3281
3282 }
3283
3284 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3285 /* some R300 cards have problem with this set to 0 */
3286 critical_point2 = 0x10;
3287 }
3288
3289 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3290 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3291
3292 if ((rdev->family == CHIP_RS400) ||
3293 (rdev->family == CHIP_RS480)) {
3294 #if 0
3295 /* attempt to program RS400 disp2 regs correctly ??? */
3296 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3297 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3298 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3299 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3300 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3301 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3302 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3303 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3304 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3305 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3306 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3307 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3308 #endif
3309 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3310 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3311 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3312 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3313 }
3314
3315 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3316 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3317 }
3318 }
3319
r100_cs_track_texture_print(struct r100_cs_track_texture * t)3320 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3321 {
3322 DRM_ERROR("pitch %d\n", t->pitch);
3323 DRM_ERROR("use_pitch %d\n", t->use_pitch);
3324 DRM_ERROR("width %d\n", t->width);
3325 DRM_ERROR("width_11 %d\n", t->width_11);
3326 DRM_ERROR("height %d\n", t->height);
3327 DRM_ERROR("height_11 %d\n", t->height_11);
3328 DRM_ERROR("num levels %d\n", t->num_levels);
3329 DRM_ERROR("depth %d\n", t->txdepth);
3330 DRM_ERROR("bpp %d\n", t->cpp);
3331 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3332 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3333 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3334 DRM_ERROR("compress format %d\n", t->compress_format);
3335 }
3336
r100_track_compress_size(int compress_format,int w,int h)3337 static int r100_track_compress_size(int compress_format, int w, int h)
3338 {
3339 int block_width, block_height, block_bytes;
3340 int wblocks, hblocks;
3341 int min_wblocks;
3342 int sz;
3343
3344 block_width = 4;
3345 block_height = 4;
3346
3347 switch (compress_format) {
3348 case R100_TRACK_COMP_DXT1:
3349 block_bytes = 8;
3350 min_wblocks = 4;
3351 break;
3352 default:
3353 case R100_TRACK_COMP_DXT35:
3354 block_bytes = 16;
3355 min_wblocks = 2;
3356 break;
3357 }
3358
3359 hblocks = (h + block_height - 1) / block_height;
3360 wblocks = (w + block_width - 1) / block_width;
3361 if (wblocks < min_wblocks)
3362 wblocks = min_wblocks;
3363 sz = wblocks * hblocks * block_bytes;
3364 return sz;
3365 }
3366
r100_cs_track_cube(struct radeon_device * rdev,struct r100_cs_track * track,unsigned idx)3367 static int r100_cs_track_cube(struct radeon_device *rdev,
3368 struct r100_cs_track *track, unsigned idx)
3369 {
3370 unsigned face, w, h;
3371 struct radeon_bo *cube_robj;
3372 unsigned long size;
3373 unsigned compress_format = track->textures[idx].compress_format;
3374
3375 for (face = 0; face < 5; face++) {
3376 cube_robj = track->textures[idx].cube_info[face].robj;
3377 w = track->textures[idx].cube_info[face].width;
3378 h = track->textures[idx].cube_info[face].height;
3379
3380 if (compress_format) {
3381 size = r100_track_compress_size(compress_format, w, h);
3382 } else
3383 size = w * h;
3384 size *= track->textures[idx].cpp;
3385
3386 size += track->textures[idx].cube_info[face].offset;
3387
3388 if (size > radeon_bo_size(cube_robj)) {
3389 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3390 size, radeon_bo_size(cube_robj));
3391 r100_cs_track_texture_print(&track->textures[idx]);
3392 return -1;
3393 }
3394 }
3395 return 0;
3396 }
3397
r100_cs_track_texture_check(struct radeon_device * rdev,struct r100_cs_track * track)3398 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3399 struct r100_cs_track *track)
3400 {
3401 struct radeon_bo *robj;
3402 unsigned long size;
3403 unsigned u, i, w, h, d;
3404 int ret;
3405
3406 for (u = 0; u < track->num_texture; u++) {
3407 if (!track->textures[u].enabled)
3408 continue;
3409 if (track->textures[u].lookup_disable)
3410 continue;
3411 robj = track->textures[u].robj;
3412 if (robj == NULL) {
3413 DRM_ERROR("No texture bound to unit %u\n", u);
3414 return -EINVAL;
3415 }
3416 size = 0;
3417 for (i = 0; i <= track->textures[u].num_levels; i++) {
3418 if (track->textures[u].use_pitch) {
3419 if (rdev->family < CHIP_R300)
3420 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3421 else
3422 w = track->textures[u].pitch / (1 << i);
3423 } else {
3424 w = track->textures[u].width;
3425 if (rdev->family >= CHIP_RV515)
3426 w |= track->textures[u].width_11;
3427 w = w / (1 << i);
3428 if (track->textures[u].roundup_w)
3429 w = roundup_pow_of_two(w);
3430 }
3431 h = track->textures[u].height;
3432 if (rdev->family >= CHIP_RV515)
3433 h |= track->textures[u].height_11;
3434 h = h / (1 << i);
3435 if (track->textures[u].roundup_h)
3436 h = roundup_pow_of_two(h);
3437 if (track->textures[u].tex_coord_type == 1) {
3438 d = (1 << track->textures[u].txdepth) / (1 << i);
3439 if (!d)
3440 d = 1;
3441 } else {
3442 d = 1;
3443 }
3444 if (track->textures[u].compress_format) {
3445
3446 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3447 /* compressed textures are block based */
3448 } else
3449 size += w * h * d;
3450 }
3451 size *= track->textures[u].cpp;
3452
3453 switch (track->textures[u].tex_coord_type) {
3454 case 0:
3455 case 1:
3456 break;
3457 case 2:
3458 if (track->separate_cube) {
3459 ret = r100_cs_track_cube(rdev, track, u);
3460 if (ret)
3461 return ret;
3462 } else
3463 size *= 6;
3464 break;
3465 default:
3466 DRM_ERROR("Invalid texture coordinate type %u for unit "
3467 "%u\n", track->textures[u].tex_coord_type, u);
3468 return -EINVAL;
3469 }
3470 if (size > radeon_bo_size(robj)) {
3471 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3472 "%lu\n", u, size, radeon_bo_size(robj));
3473 r100_cs_track_texture_print(&track->textures[u]);
3474 return -EINVAL;
3475 }
3476 }
3477 return 0;
3478 }
3479
r100_cs_track_check(struct radeon_device * rdev,struct r100_cs_track * track)3480 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3481 {
3482 unsigned i;
3483 unsigned long size;
3484 unsigned prim_walk;
3485 unsigned nverts;
3486 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3487
3488 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3489 !track->blend_read_enable)
3490 num_cb = 0;
3491
3492 for (i = 0; i < num_cb; i++) {
3493 if (track->cb[i].robj == NULL) {
3494 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3495 return -EINVAL;
3496 }
3497 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3498 size += track->cb[i].offset;
3499 if (size > radeon_bo_size(track->cb[i].robj)) {
3500 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3501 "(need %lu have %lu) !\n", i, size,
3502 radeon_bo_size(track->cb[i].robj));
3503 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3504 i, track->cb[i].pitch, track->cb[i].cpp,
3505 track->cb[i].offset, track->maxy);
3506 return -EINVAL;
3507 }
3508 }
3509 track->cb_dirty = false;
3510
3511 if (track->zb_dirty && track->z_enabled) {
3512 if (track->zb.robj == NULL) {
3513 DRM_ERROR("[drm] No buffer for z buffer !\n");
3514 return -EINVAL;
3515 }
3516 size = track->zb.pitch * track->zb.cpp * track->maxy;
3517 size += track->zb.offset;
3518 if (size > radeon_bo_size(track->zb.robj)) {
3519 DRM_ERROR("[drm] Buffer too small for z buffer "
3520 "(need %lu have %lu) !\n", size,
3521 radeon_bo_size(track->zb.robj));
3522 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3523 track->zb.pitch, track->zb.cpp,
3524 track->zb.offset, track->maxy);
3525 return -EINVAL;
3526 }
3527 }
3528 track->zb_dirty = false;
3529
3530 if (track->aa_dirty && track->aaresolve) {
3531 if (track->aa.robj == NULL) {
3532 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3533 return -EINVAL;
3534 }
3535 /* I believe the format comes from colorbuffer0. */
3536 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3537 size += track->aa.offset;
3538 if (size > radeon_bo_size(track->aa.robj)) {
3539 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3540 "(need %lu have %lu) !\n", i, size,
3541 radeon_bo_size(track->aa.robj));
3542 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3543 i, track->aa.pitch, track->cb[0].cpp,
3544 track->aa.offset, track->maxy);
3545 return -EINVAL;
3546 }
3547 }
3548 track->aa_dirty = false;
3549
3550 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3551 if (track->vap_vf_cntl & (1 << 14)) {
3552 nverts = track->vap_alt_nverts;
3553 } else {
3554 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3555 }
3556 switch (prim_walk) {
3557 case 1:
3558 for (i = 0; i < track->num_arrays; i++) {
3559 size = track->arrays[i].esize * track->max_indx * 4;
3560 if (track->arrays[i].robj == NULL) {
3561 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3562 "bound\n", prim_walk, i);
3563 return -EINVAL;
3564 }
3565 if (size > radeon_bo_size(track->arrays[i].robj)) {
3566 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3567 "need %lu dwords have %lu dwords\n",
3568 prim_walk, i, size >> 2,
3569 radeon_bo_size(track->arrays[i].robj)
3570 >> 2);
3571 DRM_ERROR("Max indices %u\n", track->max_indx);
3572 return -EINVAL;
3573 }
3574 }
3575 break;
3576 case 2:
3577 for (i = 0; i < track->num_arrays; i++) {
3578 size = track->arrays[i].esize * (nverts - 1) * 4;
3579 if (track->arrays[i].robj == NULL) {
3580 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3581 "bound\n", prim_walk, i);
3582 return -EINVAL;
3583 }
3584 if (size > radeon_bo_size(track->arrays[i].robj)) {
3585 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3586 "need %lu dwords have %lu dwords\n",
3587 prim_walk, i, size >> 2,
3588 radeon_bo_size(track->arrays[i].robj)
3589 >> 2);
3590 return -EINVAL;
3591 }
3592 }
3593 break;
3594 case 3:
3595 size = track->vtx_size * nverts;
3596 if (size != track->immd_dwords) {
3597 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3598 track->immd_dwords, size);
3599 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3600 nverts, track->vtx_size);
3601 return -EINVAL;
3602 }
3603 break;
3604 default:
3605 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3606 prim_walk);
3607 return -EINVAL;
3608 }
3609
3610 if (track->tex_dirty) {
3611 track->tex_dirty = false;
3612 return r100_cs_track_texture_check(rdev, track);
3613 }
3614 return 0;
3615 }
3616
r100_cs_track_clear(struct radeon_device * rdev,struct r100_cs_track * track)3617 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3618 {
3619 unsigned i, face;
3620
3621 track->cb_dirty = true;
3622 track->zb_dirty = true;
3623 track->tex_dirty = true;
3624 track->aa_dirty = true;
3625
3626 if (rdev->family < CHIP_R300) {
3627 track->num_cb = 1;
3628 if (rdev->family <= CHIP_RS200)
3629 track->num_texture = 3;
3630 else
3631 track->num_texture = 6;
3632 track->maxy = 2048;
3633 track->separate_cube = 1;
3634 } else {
3635 track->num_cb = 4;
3636 track->num_texture = 16;
3637 track->maxy = 4096;
3638 track->separate_cube = 0;
3639 track->aaresolve = false;
3640 track->aa.robj = NULL;
3641 }
3642
3643 for (i = 0; i < track->num_cb; i++) {
3644 track->cb[i].robj = NULL;
3645 track->cb[i].pitch = 8192;
3646 track->cb[i].cpp = 16;
3647 track->cb[i].offset = 0;
3648 }
3649 track->z_enabled = true;
3650 track->zb.robj = NULL;
3651 track->zb.pitch = 8192;
3652 track->zb.cpp = 4;
3653 track->zb.offset = 0;
3654 track->vtx_size = 0x7F;
3655 track->immd_dwords = 0xFFFFFFFFUL;
3656 track->num_arrays = 11;
3657 track->max_indx = 0x00FFFFFFUL;
3658 for (i = 0; i < track->num_arrays; i++) {
3659 track->arrays[i].robj = NULL;
3660 track->arrays[i].esize = 0x7F;
3661 }
3662 for (i = 0; i < track->num_texture; i++) {
3663 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3664 track->textures[i].pitch = 16536;
3665 track->textures[i].width = 16536;
3666 track->textures[i].height = 16536;
3667 track->textures[i].width_11 = 1 << 11;
3668 track->textures[i].height_11 = 1 << 11;
3669 track->textures[i].num_levels = 12;
3670 if (rdev->family <= CHIP_RS200) {
3671 track->textures[i].tex_coord_type = 0;
3672 track->textures[i].txdepth = 0;
3673 } else {
3674 track->textures[i].txdepth = 16;
3675 track->textures[i].tex_coord_type = 1;
3676 }
3677 track->textures[i].cpp = 64;
3678 track->textures[i].robj = NULL;
3679 /* CS IB emission code makes sure texture unit are disabled */
3680 track->textures[i].enabled = false;
3681 track->textures[i].lookup_disable = false;
3682 track->textures[i].roundup_w = true;
3683 track->textures[i].roundup_h = true;
3684 if (track->separate_cube)
3685 for (face = 0; face < 5; face++) {
3686 track->textures[i].cube_info[face].robj = NULL;
3687 track->textures[i].cube_info[face].width = 16536;
3688 track->textures[i].cube_info[face].height = 16536;
3689 track->textures[i].cube_info[face].offset = 0;
3690 }
3691 }
3692 }
3693
r100_ring_test(struct radeon_device * rdev,struct radeon_ring * ring)3694 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3695 {
3696 uint32_t scratch;
3697 uint32_t tmp = 0;
3698 unsigned i;
3699 int r;
3700
3701 r = radeon_scratch_get(rdev, &scratch);
3702 if (r) {
3703 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3704 return r;
3705 }
3706 WREG32(scratch, 0xCAFEDEAD);
3707 r = radeon_ring_lock(rdev, ring, 2);
3708 if (r) {
3709 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3710 radeon_scratch_free(rdev, scratch);
3711 return r;
3712 }
3713 radeon_ring_write(ring, PACKET0(scratch, 0));
3714 radeon_ring_write(ring, 0xDEADBEEF);
3715 radeon_ring_unlock_commit(rdev, ring);
3716 for (i = 0; i < rdev->usec_timeout; i++) {
3717 tmp = RREG32(scratch);
3718 if (tmp == 0xDEADBEEF) {
3719 break;
3720 }
3721 DRM_UDELAY(1);
3722 }
3723 if (i < rdev->usec_timeout) {
3724 DRM_INFO("ring test succeeded in %d usecs\n", i);
3725 } else {
3726 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3727 scratch, tmp);
3728 r = -EINVAL;
3729 }
3730 radeon_scratch_free(rdev, scratch);
3731 return r;
3732 }
3733
r100_ring_ib_execute(struct radeon_device * rdev,struct radeon_ib * ib)3734 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3735 {
3736 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3737
3738 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3739 radeon_ring_write(ring, ib->gpu_addr);
3740 radeon_ring_write(ring, ib->length_dw);
3741 }
3742
r100_ib_test(struct radeon_device * rdev,struct radeon_ring * ring)3743 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3744 {
3745 struct radeon_ib *ib;
3746 uint32_t scratch;
3747 uint32_t tmp = 0;
3748 unsigned i;
3749 int r;
3750
3751 r = radeon_scratch_get(rdev, &scratch);
3752 if (r) {
3753 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3754 return r;
3755 }
3756 WREG32(scratch, 0xCAFEDEAD);
3757 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256);
3758 if (r) {
3759 return r;
3760 }
3761 ib->ptr[0] = PACKET0(scratch, 0);
3762 ib->ptr[1] = 0xDEADBEEF;
3763 ib->ptr[2] = PACKET2(0);
3764 ib->ptr[3] = PACKET2(0);
3765 ib->ptr[4] = PACKET2(0);
3766 ib->ptr[5] = PACKET2(0);
3767 ib->ptr[6] = PACKET2(0);
3768 ib->ptr[7] = PACKET2(0);
3769 ib->length_dw = 8;
3770 r = radeon_ib_schedule(rdev, ib);
3771 if (r) {
3772 radeon_scratch_free(rdev, scratch);
3773 radeon_ib_free(rdev, &ib);
3774 return r;
3775 }
3776 r = radeon_fence_wait(ib->fence, false);
3777 if (r) {
3778 return r;
3779 }
3780 for (i = 0; i < rdev->usec_timeout; i++) {
3781 tmp = RREG32(scratch);
3782 if (tmp == 0xDEADBEEF) {
3783 break;
3784 }
3785 DRM_UDELAY(1);
3786 }
3787 if (i < rdev->usec_timeout) {
3788 DRM_INFO("ib test succeeded in %u usecs\n", i);
3789 } else {
3790 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3791 scratch, tmp);
3792 r = -EINVAL;
3793 }
3794 radeon_scratch_free(rdev, scratch);
3795 radeon_ib_free(rdev, &ib);
3796 return r;
3797 }
3798
r100_ib_fini(struct radeon_device * rdev)3799 void r100_ib_fini(struct radeon_device *rdev)
3800 {
3801 radeon_ib_pool_suspend(rdev);
3802 radeon_ib_pool_fini(rdev);
3803 }
3804
r100_mc_stop(struct radeon_device * rdev,struct r100_mc_save * save)3805 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3806 {
3807 /* Shutdown CP we shouldn't need to do that but better be safe than
3808 * sorry
3809 */
3810 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3811 WREG32(R_000740_CP_CSQ_CNTL, 0);
3812
3813 /* Save few CRTC registers */
3814 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3815 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3816 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3817 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3818 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3819 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3820 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3821 }
3822
3823 /* Disable VGA aperture access */
3824 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3825 /* Disable cursor, overlay, crtc */
3826 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3827 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3828 S_000054_CRTC_DISPLAY_DIS(1));
3829 WREG32(R_000050_CRTC_GEN_CNTL,
3830 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3831 S_000050_CRTC_DISP_REQ_EN_B(1));
3832 WREG32(R_000420_OV0_SCALE_CNTL,
3833 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3834 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3835 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3836 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3837 S_000360_CUR2_LOCK(1));
3838 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3839 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3840 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3841 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3842 WREG32(R_000360_CUR2_OFFSET,
3843 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3844 }
3845 }
3846
r100_mc_resume(struct radeon_device * rdev,struct r100_mc_save * save)3847 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3848 {
3849 /* Update base address for crtc */
3850 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3851 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3852 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3853 }
3854 /* Restore CRTC registers */
3855 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3856 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3857 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3858 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3859 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3860 }
3861 }
3862
r100_vga_render_disable(struct radeon_device * rdev)3863 void r100_vga_render_disable(struct radeon_device *rdev)
3864 {
3865 u32 tmp;
3866
3867 tmp = RREG8(R_0003C2_GENMO_WT);
3868 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3869 }
3870
r100_debugfs(struct radeon_device * rdev)3871 static void r100_debugfs(struct radeon_device *rdev)
3872 {
3873 int r;
3874
3875 r = r100_debugfs_mc_info_init(rdev);
3876 if (r)
3877 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3878 }
3879
r100_mc_program(struct radeon_device * rdev)3880 static void r100_mc_program(struct radeon_device *rdev)
3881 {
3882 struct r100_mc_save save;
3883
3884 /* Stops all mc clients */
3885 r100_mc_stop(rdev, &save);
3886 if (rdev->flags & RADEON_IS_AGP) {
3887 WREG32(R_00014C_MC_AGP_LOCATION,
3888 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3889 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3890 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3891 if (rdev->family > CHIP_RV200)
3892 WREG32(R_00015C_AGP_BASE_2,
3893 upper_32_bits(rdev->mc.agp_base) & 0xff);
3894 } else {
3895 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3896 WREG32(R_000170_AGP_BASE, 0);
3897 if (rdev->family > CHIP_RV200)
3898 WREG32(R_00015C_AGP_BASE_2, 0);
3899 }
3900 /* Wait for mc idle */
3901 if (r100_mc_wait_for_idle(rdev))
3902 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3903 /* Program MC, should be a 32bits limited address space */
3904 WREG32(R_000148_MC_FB_LOCATION,
3905 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3906 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3907 r100_mc_resume(rdev, &save);
3908 }
3909
r100_clock_startup(struct radeon_device * rdev)3910 void r100_clock_startup(struct radeon_device *rdev)
3911 {
3912 u32 tmp;
3913
3914 if (radeon_dynclks != -1 && radeon_dynclks)
3915 radeon_legacy_set_clock_gating(rdev, 1);
3916 /* We need to force on some of the block */
3917 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3918 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3919 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3920 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3921 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3922 }
3923
r100_startup(struct radeon_device * rdev)3924 static int r100_startup(struct radeon_device *rdev)
3925 {
3926 int r;
3927
3928 /* set common regs */
3929 r100_set_common_regs(rdev);
3930 /* program mc */
3931 r100_mc_program(rdev);
3932 /* Resume clock */
3933 r100_clock_startup(rdev);
3934 /* Initialize GART (initialize after TTM so we can allocate
3935 * memory through TTM but finalize after TTM) */
3936 r100_enable_bm(rdev);
3937 if (rdev->flags & RADEON_IS_PCI) {
3938 r = r100_pci_gart_enable(rdev);
3939 if (r)
3940 return r;
3941 }
3942
3943 /* allocate wb buffer */
3944 r = radeon_wb_init(rdev);
3945 if (r)
3946 return r;
3947
3948 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3949 if (r) {
3950 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3951 return r;
3952 }
3953
3954 /* Enable IRQ */
3955 if (!rdev->irq.installed) {
3956 r = radeon_irq_kms_init(rdev);
3957 if (r)
3958 return r;
3959 }
3960
3961 r100_irq_set(rdev);
3962 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3963 /* 1M ring buffer */
3964 r = r100_cp_init(rdev, 1024 * 1024);
3965 if (r) {
3966 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3967 return r;
3968 }
3969
3970 r = radeon_ib_pool_start(rdev);
3971 if (r)
3972 return r;
3973
3974 r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3975 if (r) {
3976 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3977 rdev->accel_working = false;
3978 return r;
3979 }
3980
3981 return 0;
3982 }
3983
r100_resume(struct radeon_device * rdev)3984 int r100_resume(struct radeon_device *rdev)
3985 {
3986 int r;
3987
3988 /* Make sur GART are not working */
3989 if (rdev->flags & RADEON_IS_PCI)
3990 r100_pci_gart_disable(rdev);
3991 /* Resume clock before doing reset */
3992 r100_clock_startup(rdev);
3993 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3994 if (radeon_asic_reset(rdev)) {
3995 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3996 RREG32(R_000E40_RBBM_STATUS),
3997 RREG32(R_0007C0_CP_STAT));
3998 }
3999 /* post */
4000 radeon_combios_asic_init(rdev->ddev);
4001 /* Resume clock after posting */
4002 r100_clock_startup(rdev);
4003 /* Initialize surface registers */
4004 radeon_surface_init(rdev);
4005
4006 rdev->accel_working = true;
4007 r = r100_startup(rdev);
4008 if (r) {
4009 rdev->accel_working = false;
4010 }
4011 return r;
4012 }
4013
r100_suspend(struct radeon_device * rdev)4014 int r100_suspend(struct radeon_device *rdev)
4015 {
4016 radeon_ib_pool_suspend(rdev);
4017 r100_cp_disable(rdev);
4018 radeon_wb_disable(rdev);
4019 r100_irq_disable(rdev);
4020 if (rdev->flags & RADEON_IS_PCI)
4021 r100_pci_gart_disable(rdev);
4022 return 0;
4023 }
4024
r100_fini(struct radeon_device * rdev)4025 void r100_fini(struct radeon_device *rdev)
4026 {
4027 r100_cp_fini(rdev);
4028 radeon_wb_fini(rdev);
4029 r100_ib_fini(rdev);
4030 radeon_gem_fini(rdev);
4031 if (rdev->flags & RADEON_IS_PCI)
4032 r100_pci_gart_fini(rdev);
4033 radeon_agp_fini(rdev);
4034 radeon_irq_kms_fini(rdev);
4035 radeon_fence_driver_fini(rdev);
4036 radeon_bo_fini(rdev);
4037 radeon_atombios_fini(rdev);
4038 kfree(rdev->bios);
4039 rdev->bios = NULL;
4040 }
4041
4042 /*
4043 * Due to how kexec works, it can leave the hw fully initialised when it
4044 * boots the new kernel. However doing our init sequence with the CP and
4045 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
4046 * do some quick sanity checks and restore sane values to avoid this
4047 * problem.
4048 */
r100_restore_sanity(struct radeon_device * rdev)4049 void r100_restore_sanity(struct radeon_device *rdev)
4050 {
4051 u32 tmp;
4052
4053 tmp = RREG32(RADEON_CP_CSQ_CNTL);
4054 if (tmp) {
4055 WREG32(RADEON_CP_CSQ_CNTL, 0);
4056 }
4057 tmp = RREG32(RADEON_CP_RB_CNTL);
4058 if (tmp) {
4059 WREG32(RADEON_CP_RB_CNTL, 0);
4060 }
4061 tmp = RREG32(RADEON_SCRATCH_UMSK);
4062 if (tmp) {
4063 WREG32(RADEON_SCRATCH_UMSK, 0);
4064 }
4065 }
4066
r100_init(struct radeon_device * rdev)4067 int r100_init(struct radeon_device *rdev)
4068 {
4069 int r;
4070
4071 /* Register debugfs file specific to this group of asics */
4072 r100_debugfs(rdev);
4073 /* Disable VGA */
4074 r100_vga_render_disable(rdev);
4075 /* Initialize scratch registers */
4076 radeon_scratch_init(rdev);
4077 /* Initialize surface registers */
4078 radeon_surface_init(rdev);
4079 /* sanity check some register to avoid hangs like after kexec */
4080 r100_restore_sanity(rdev);
4081 /* TODO: disable VGA need to use VGA request */
4082 /* BIOS*/
4083 if (!radeon_get_bios(rdev)) {
4084 if (ASIC_IS_AVIVO(rdev))
4085 return -EINVAL;
4086 }
4087 if (rdev->is_atom_bios) {
4088 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4089 return -EINVAL;
4090 } else {
4091 r = radeon_combios_init(rdev);
4092 if (r)
4093 return r;
4094 }
4095 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4096 if (radeon_asic_reset(rdev)) {
4097 dev_warn(rdev->dev,
4098 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4099 RREG32(R_000E40_RBBM_STATUS),
4100 RREG32(R_0007C0_CP_STAT));
4101 }
4102 /* check if cards are posted or not */
4103 if (radeon_boot_test_post_card(rdev) == false)
4104 return -EINVAL;
4105 /* Set asic errata */
4106 r100_errata(rdev);
4107 /* Initialize clocks */
4108 radeon_get_clock_info(rdev->ddev);
4109 /* initialize AGP */
4110 if (rdev->flags & RADEON_IS_AGP) {
4111 r = radeon_agp_init(rdev);
4112 if (r) {
4113 radeon_agp_disable(rdev);
4114 }
4115 }
4116 /* initialize VRAM */
4117 r100_mc_init(rdev);
4118 /* Fence driver */
4119 r = radeon_fence_driver_init(rdev);
4120 if (r)
4121 return r;
4122 /* Memory manager */
4123 r = radeon_bo_init(rdev);
4124 if (r)
4125 return r;
4126 if (rdev->flags & RADEON_IS_PCI) {
4127 r = r100_pci_gart_init(rdev);
4128 if (r)
4129 return r;
4130 }
4131 r100_set_safe_registers(rdev);
4132
4133 r = radeon_ib_pool_init(rdev);
4134 rdev->accel_working = true;
4135 if (r) {
4136 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4137 rdev->accel_working = false;
4138 }
4139
4140 r = r100_startup(rdev);
4141 if (r) {
4142 /* Somethings want wront with the accel init stop accel */
4143 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4144 r100_cp_fini(rdev);
4145 radeon_wb_fini(rdev);
4146 r100_ib_fini(rdev);
4147 radeon_irq_kms_fini(rdev);
4148 if (rdev->flags & RADEON_IS_PCI)
4149 r100_pci_gart_fini(rdev);
4150 rdev->accel_working = false;
4151 }
4152 return 0;
4153 }
4154
r100_mm_rreg(struct radeon_device * rdev,uint32_t reg)4155 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4156 {
4157 if (reg < rdev->rmmio_size)
4158 return readl(((void __iomem *)rdev->rmmio) + reg);
4159 else {
4160 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4161 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4162 }
4163 }
4164
r100_mm_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)4165 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4166 {
4167 if (reg < rdev->rmmio_size)
4168 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4169 else {
4170 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4171 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4172 }
4173 }
4174
r100_io_rreg(struct radeon_device * rdev,u32 reg)4175 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4176 {
4177 if (reg < rdev->rio_mem_size)
4178 return ioread32(rdev->rio_mem + reg);
4179 else {
4180 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4181 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4182 }
4183 }
4184
r100_io_wreg(struct radeon_device * rdev,u32 reg,u32 v)4185 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4186 {
4187 if (reg < rdev->rio_mem_size)
4188 iowrite32(v, rdev->rio_mem + reg);
4189 else {
4190 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4191 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4192 }
4193 }
4194