1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2019 HiSilicon Limited. */
3 #ifndef HISI_ACC_QM_H
4 #define HISI_ACC_QM_H
5
6 #include <linux/bitfield.h>
7 #include <linux/debugfs.h>
8 #include <linux/iopoll.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11
12 #define QM_QNUM_V1 4096
13 #define QM_QNUM_V2 1024
14 #define QM_MAX_VFS_NUM_V2 63
15
16 /* qm user domain */
17 #define QM_ARUSER_M_CFG_1 0x100088
18 #define AXUSER_SNOOP_ENABLE BIT(30)
19 #define AXUSER_CMD_TYPE GENMASK(14, 12)
20 #define AXUSER_CMD_SMMU_NORMAL 1
21 #define AXUSER_NS BIT(6)
22 #define AXUSER_NO BIT(5)
23 #define AXUSER_FP BIT(4)
24 #define AXUSER_SSV BIT(0)
25 #define AXUSER_BASE (AXUSER_SNOOP_ENABLE | \
26 FIELD_PREP(AXUSER_CMD_TYPE, \
27 AXUSER_CMD_SMMU_NORMAL) | \
28 AXUSER_NS | AXUSER_NO | AXUSER_FP)
29 #define QM_ARUSER_M_CFG_ENABLE 0x100090
30 #define ARUSER_M_CFG_ENABLE 0xfffffffe
31 #define QM_AWUSER_M_CFG_1 0x100098
32 #define QM_AWUSER_M_CFG_ENABLE 0x1000a0
33 #define AWUSER_M_CFG_ENABLE 0xfffffffe
34 #define QM_WUSER_M_CFG_ENABLE 0x1000a8
35 #define WUSER_M_CFG_ENABLE 0xffffffff
36
37 /* mailbox */
38 #define QM_MB_CMD_SQC 0x0
39 #define QM_MB_CMD_CQC 0x1
40 #define QM_MB_CMD_EQC 0x2
41 #define QM_MB_CMD_AEQC 0x3
42 #define QM_MB_CMD_SQC_BT 0x4
43 #define QM_MB_CMD_CQC_BT 0x5
44 #define QM_MB_CMD_SQC_VFT_V2 0x6
45 #define QM_MB_CMD_STOP_QP 0x8
46 #define QM_MB_CMD_SRC 0xc
47 #define QM_MB_CMD_DST 0xd
48
49 #define QM_MB_CMD_SEND_BASE 0x300
50 #define QM_MB_EVENT_SHIFT 8
51 #define QM_MB_BUSY_SHIFT 13
52 #define QM_MB_OP_SHIFT 14
53 #define QM_MB_CMD_DATA_ADDR_L 0x304
54 #define QM_MB_CMD_DATA_ADDR_H 0x308
55 #define QM_MB_MAX_WAIT_CNT 6000
56
57 /* doorbell */
58 #define QM_DOORBELL_CMD_SQ 0
59 #define QM_DOORBELL_CMD_CQ 1
60 #define QM_DOORBELL_CMD_EQ 2
61 #define QM_DOORBELL_CMD_AEQ 3
62
63 #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
64 #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
65 #define QM_QP_MAX_NUM_SHIFT 11
66 #define QM_DB_CMD_SHIFT_V2 12
67 #define QM_DB_RAND_SHIFT_V2 16
68 #define QM_DB_INDEX_SHIFT_V2 32
69 #define QM_DB_PRIORITY_SHIFT_V2 48
70 #define QM_VF_STATE 0x60
71
72 /* qm cache */
73 #define QM_CACHE_CTL 0x100050
74 #define SQC_CACHE_ENABLE BIT(0)
75 #define CQC_CACHE_ENABLE BIT(1)
76 #define SQC_CACHE_WB_ENABLE BIT(4)
77 #define SQC_CACHE_WB_THRD GENMASK(10, 5)
78 #define CQC_CACHE_WB_ENABLE BIT(11)
79 #define CQC_CACHE_WB_THRD GENMASK(17, 12)
80 #define QM_AXI_M_CFG 0x1000ac
81 #define AXI_M_CFG 0xffff
82 #define QM_AXI_M_CFG_ENABLE 0x1000b0
83 #define AM_CFG_SINGLE_PORT_MAX_TRANS 0x300014
84 #define AXI_M_CFG_ENABLE 0xffffffff
85 #define QM_PEH_AXUSER_CFG 0x1000cc
86 #define QM_PEH_AXUSER_CFG_ENABLE 0x1000d0
87 #define PEH_AXUSER_CFG 0x401001
88 #define PEH_AXUSER_CFG_ENABLE 0xffffffff
89
90 #define QM_MIN_QNUM 2
91 #define HISI_ACC_SGL_SGE_NR_MAX 255
92 #define QM_SHAPER_CFG 0x100164
93 #define QM_SHAPER_ENABLE BIT(30)
94 #define QM_SHAPER_TYPE1_OFFSET 10
95
96 /* page number for queue file region */
97 #define QM_DOORBELL_PAGE_NR 1
98
99 /* uacce mode of the driver */
100 #define UACCE_MODE_NOUACCE 0 /* don't use uacce */
101 #define UACCE_MODE_SVA 1 /* use uacce sva mode */
102 #define UACCE_MODE_DESC "0(default) means only register to crypto, 1 means both register to crypto and uacce"
103
104 enum qm_stop_reason {
105 QM_NORMAL,
106 QM_SOFT_RESET,
107 QM_DOWN,
108 };
109
110 enum qm_state {
111 QM_INIT = 0,
112 QM_START,
113 QM_CLOSE,
114 QM_STOP,
115 };
116
117 enum qp_state {
118 QP_INIT = 1,
119 QP_START,
120 QP_STOP,
121 QP_CLOSE,
122 };
123
124 enum qm_hw_ver {
125 QM_HW_V1 = 0x20,
126 QM_HW_V2 = 0x21,
127 QM_HW_V3 = 0x30,
128 };
129
130 enum qm_fun_type {
131 QM_HW_PF,
132 QM_HW_VF,
133 };
134
135 enum qm_debug_file {
136 CURRENT_QM,
137 CURRENT_Q,
138 CLEAR_ENABLE,
139 DEBUG_FILE_NUM,
140 };
141
142 enum qm_vf_state {
143 QM_READY = 0,
144 QM_NOT_READY,
145 };
146
147 enum qm_misc_ctl_bits {
148 QM_DRIVER_REMOVING = 0x0,
149 QM_RST_SCHED,
150 QM_RESETTING,
151 QM_MODULE_PARAM,
152 };
153
154 enum qm_cap_bits {
155 QM_SUPPORT_DB_ISOLATION = 0x0,
156 QM_SUPPORT_FUNC_QOS,
157 QM_SUPPORT_STOP_QP,
158 QM_SUPPORT_MB_COMMAND,
159 QM_SUPPORT_SVA_PREFETCH,
160 QM_SUPPORT_RPM,
161 };
162
163 struct qm_dev_alg {
164 u64 alg_msk;
165 const char *alg;
166 };
167
168 struct dfx_diff_registers {
169 u32 *regs;
170 u32 reg_offset;
171 u32 reg_len;
172 };
173
174 struct qm_dfx {
175 atomic64_t err_irq_cnt;
176 atomic64_t aeq_irq_cnt;
177 atomic64_t abnormal_irq_cnt;
178 atomic64_t create_qp_err_cnt;
179 atomic64_t mb_err_cnt;
180 };
181
182 struct debugfs_file {
183 enum qm_debug_file index;
184 struct mutex lock;
185 struct qm_debug *debug;
186 };
187
188 struct qm_debug {
189 u32 curr_qm_qp_num;
190 u32 sqe_mask_offset;
191 u32 sqe_mask_len;
192 struct qm_dfx dfx;
193 struct dentry *debug_root;
194 struct dentry *qm_d;
195 struct debugfs_file files[DEBUG_FILE_NUM];
196 unsigned int *qm_last_words;
197 /* ACC engines recoreding last regs */
198 unsigned int *last_words;
199 struct dfx_diff_registers *qm_diff_regs;
200 struct dfx_diff_registers *acc_diff_regs;
201 };
202
203 struct qm_shaper_factor {
204 u32 func_qos;
205 u64 cir_b;
206 u64 cir_u;
207 u64 cir_s;
208 u64 cbs_s;
209 };
210
211 struct qm_dma {
212 void *va;
213 dma_addr_t dma;
214 size_t size;
215 };
216
217 struct hisi_qm_status {
218 u32 eq_head;
219 bool eqc_phase;
220 u32 aeq_head;
221 bool aeqc_phase;
222 atomic_t flags;
223 int stop_reason;
224 };
225
226 struct hisi_qm;
227
228 struct hisi_qm_err_info {
229 char *acpi_rst;
230 u32 msi_wr_port;
231 u32 ecc_2bits_mask;
232 u32 qm_shutdown_mask;
233 u32 dev_shutdown_mask;
234 u32 qm_reset_mask;
235 u32 dev_reset_mask;
236 u32 ce;
237 u32 nfe;
238 u32 fe;
239 };
240
241 struct hisi_qm_err_status {
242 u32 is_qm_ecc_mbit;
243 u32 is_dev_ecc_mbit;
244 };
245
246 struct hisi_qm_err_ini {
247 int (*hw_init)(struct hisi_qm *qm);
248 void (*hw_err_enable)(struct hisi_qm *qm);
249 void (*hw_err_disable)(struct hisi_qm *qm);
250 u32 (*get_dev_hw_err_status)(struct hisi_qm *qm);
251 void (*clear_dev_hw_err_status)(struct hisi_qm *qm, u32 err_sts);
252 void (*open_axi_master_ooo)(struct hisi_qm *qm);
253 void (*close_axi_master_ooo)(struct hisi_qm *qm);
254 void (*open_sva_prefetch)(struct hisi_qm *qm);
255 void (*close_sva_prefetch)(struct hisi_qm *qm);
256 void (*log_dev_hw_err)(struct hisi_qm *qm, u32 err_sts);
257 void (*show_last_dfx_regs)(struct hisi_qm *qm);
258 void (*err_info_init)(struct hisi_qm *qm);
259 };
260
261 struct hisi_qm_cap_info {
262 u32 type;
263 /* Register offset */
264 u32 offset;
265 /* Bit offset in register */
266 u32 shift;
267 u32 mask;
268 u32 v1_val;
269 u32 v2_val;
270 u32 v3_val;
271 };
272
273 struct hisi_qm_cap_record {
274 u32 type;
275 u32 cap_val;
276 };
277
278 struct hisi_qm_cap_tables {
279 struct hisi_qm_cap_record *qm_cap_table;
280 struct hisi_qm_cap_record *dev_cap_table;
281 };
282
283 struct hisi_qm_list {
284 struct mutex lock;
285 struct list_head list;
286 int (*register_to_crypto)(struct hisi_qm *qm);
287 void (*unregister_from_crypto)(struct hisi_qm *qm);
288 };
289
290 struct hisi_qm_poll_data {
291 struct hisi_qm *qm;
292 struct work_struct work;
293 u16 *qp_finish_id;
294 u16 eqe_num;
295 };
296
297 /**
298 * struct qm_err_isolate
299 * @isolate_lock: protects device error log
300 * @err_threshold: user config error threshold which triggers isolation
301 * @is_isolate: device isolation state
302 * @uacce_hw_errs: index into qm device error list
303 */
304 struct qm_err_isolate {
305 struct mutex isolate_lock;
306 u32 err_threshold;
307 bool is_isolate;
308 struct list_head qm_hw_errs;
309 };
310
311 struct hisi_qm {
312 enum qm_hw_ver ver;
313 enum qm_fun_type fun_type;
314 const char *dev_name;
315 struct pci_dev *pdev;
316 void __iomem *io_base;
317 void __iomem *db_io_base;
318
319 /* Capbility version, 0: not supports */
320 u32 cap_ver;
321 u32 sqe_size;
322 u32 qp_base;
323 u32 qp_num;
324 u32 qp_in_used;
325 u32 ctrl_qp_num;
326 u32 max_qp_num;
327 u32 vfs_num;
328 u32 db_interval;
329 u16 eq_depth;
330 u16 aeq_depth;
331 struct list_head list;
332 struct hisi_qm_list *qm_list;
333
334 struct qm_dma qdma;
335 struct qm_sqc *sqc;
336 struct qm_cqc *cqc;
337 struct qm_eqe *eqe;
338 struct qm_aeqe *aeqe;
339 dma_addr_t sqc_dma;
340 dma_addr_t cqc_dma;
341 dma_addr_t eqe_dma;
342 dma_addr_t aeqe_dma;
343
344 struct hisi_qm_status status;
345 const struct hisi_qm_err_ini *err_ini;
346 struct hisi_qm_err_info err_info;
347 struct hisi_qm_err_status err_status;
348 /* driver removing and reset sched */
349 unsigned long misc_ctl;
350 /* Device capability bit */
351 unsigned long caps;
352
353 struct rw_semaphore qps_lock;
354 struct idr qp_idr;
355 struct hisi_qp *qp_array;
356 struct hisi_qm_poll_data *poll_data;
357
358 struct mutex mailbox_lock;
359
360 const struct hisi_qm_hw_ops *ops;
361
362 struct qm_debug debug;
363
364 u32 error_mask;
365
366 struct workqueue_struct *wq;
367 struct work_struct rst_work;
368 struct work_struct cmd_process;
369
370 bool use_sva;
371
372 resource_size_t phys_base;
373 resource_size_t db_phys_base;
374 struct uacce_device *uacce;
375 int mode;
376 struct qm_shaper_factor *factor;
377 u32 mb_qos;
378 u32 type_rate;
379 struct qm_err_isolate isolate_data;
380
381 struct hisi_qm_cap_tables cap_tables;
382 };
383
384 struct hisi_qp_status {
385 atomic_t used;
386 u16 sq_tail;
387 u16 cq_head;
388 bool cqc_phase;
389 atomic_t flags;
390 };
391
392 struct hisi_qp_ops {
393 int (*fill_sqe)(void *sqe, void *q_parm, void *d_parm);
394 };
395
396 struct hisi_qp {
397 u32 qp_id;
398 u16 sq_depth;
399 u16 cq_depth;
400 u8 alg_type;
401 u8 req_type;
402
403 struct qm_dma qdma;
404 void *sqe;
405 struct qm_cqe *cqe;
406 dma_addr_t sqe_dma;
407 dma_addr_t cqe_dma;
408
409 struct hisi_qp_status qp_status;
410 struct hisi_qp_ops *hw_ops;
411 void *qp_ctx;
412 void (*req_cb)(struct hisi_qp *qp, void *data);
413 void (*event_cb)(struct hisi_qp *qp);
414
415 struct hisi_qm *qm;
416 bool is_resetting;
417 bool is_in_kernel;
418 u16 pasid;
419 struct uacce_queue *uacce_q;
420 };
421
q_num_set(const char * val,const struct kernel_param * kp,unsigned int device)422 static inline int q_num_set(const char *val, const struct kernel_param *kp,
423 unsigned int device)
424 {
425 struct pci_dev *pdev;
426 u32 n, q_num;
427 int ret;
428
429 if (!val)
430 return -EINVAL;
431
432 pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI, device, NULL);
433 if (!pdev) {
434 q_num = min_t(u32, QM_QNUM_V1, QM_QNUM_V2);
435 pr_info("No device found currently, suppose queue number is %u\n",
436 q_num);
437 } else {
438 if (pdev->revision == QM_HW_V1)
439 q_num = QM_QNUM_V1;
440 else
441 q_num = QM_QNUM_V2;
442
443 pci_dev_put(pdev);
444 }
445
446 ret = kstrtou32(val, 10, &n);
447 if (ret || n < QM_MIN_QNUM || n > q_num)
448 return -EINVAL;
449
450 return param_set_int(val, kp);
451 }
452
vfs_num_set(const char * val,const struct kernel_param * kp)453 static inline int vfs_num_set(const char *val, const struct kernel_param *kp)
454 {
455 u32 n;
456 int ret;
457
458 if (!val)
459 return -EINVAL;
460
461 ret = kstrtou32(val, 10, &n);
462 if (ret < 0)
463 return ret;
464
465 if (n > QM_MAX_VFS_NUM_V2)
466 return -EINVAL;
467
468 return param_set_int(val, kp);
469 }
470
mode_set(const char * val,const struct kernel_param * kp)471 static inline int mode_set(const char *val, const struct kernel_param *kp)
472 {
473 u32 n;
474 int ret;
475
476 if (!val)
477 return -EINVAL;
478
479 ret = kstrtou32(val, 10, &n);
480 if (ret != 0 || (n != UACCE_MODE_SVA &&
481 n != UACCE_MODE_NOUACCE))
482 return -EINVAL;
483
484 return param_set_int(val, kp);
485 }
486
uacce_mode_set(const char * val,const struct kernel_param * kp)487 static inline int uacce_mode_set(const char *val, const struct kernel_param *kp)
488 {
489 return mode_set(val, kp);
490 }
491
hisi_qm_init_list(struct hisi_qm_list * qm_list)492 static inline void hisi_qm_init_list(struct hisi_qm_list *qm_list)
493 {
494 INIT_LIST_HEAD(&qm_list->list);
495 mutex_init(&qm_list->lock);
496 }
497
498 int hisi_qm_init(struct hisi_qm *qm);
499 void hisi_qm_uninit(struct hisi_qm *qm);
500 int hisi_qm_start(struct hisi_qm *qm);
501 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r);
502 int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg);
503 int hisi_qm_stop_qp(struct hisi_qp *qp);
504 int hisi_qp_send(struct hisi_qp *qp, const void *msg);
505 void hisi_qm_debug_init(struct hisi_qm *qm);
506 void hisi_qm_debug_regs_clear(struct hisi_qm *qm);
507 int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs);
508 int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen);
509 int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs);
510 void hisi_qm_dev_err_init(struct hisi_qm *qm);
511 void hisi_qm_dev_err_uninit(struct hisi_qm *qm);
512 int hisi_qm_regs_debugfs_init(struct hisi_qm *qm,
513 struct dfx_diff_registers *dregs, u32 reg_len);
514 void hisi_qm_regs_debugfs_uninit(struct hisi_qm *qm, u32 reg_len);
515 void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s,
516 struct dfx_diff_registers *dregs, u32 regs_len);
517
518 pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
519 pci_channel_state_t state);
520 pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev);
521 void hisi_qm_reset_prepare(struct pci_dev *pdev);
522 void hisi_qm_reset_done(struct pci_dev *pdev);
523
524 int hisi_qm_wait_mb_ready(struct hisi_qm *qm);
525 int hisi_qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
526 bool op);
527
528 struct hisi_acc_sgl_pool;
529 struct hisi_acc_hw_sgl *hisi_acc_sg_buf_map_to_hw_sgl(struct device *dev,
530 struct scatterlist *sgl, struct hisi_acc_sgl_pool *pool,
531 u32 index, dma_addr_t *hw_sgl_dma);
532 void hisi_acc_sg_buf_unmap(struct device *dev, struct scatterlist *sgl,
533 struct hisi_acc_hw_sgl *hw_sgl);
534 struct hisi_acc_sgl_pool *hisi_acc_create_sgl_pool(struct device *dev,
535 u32 count, u32 sge_nr);
536 void hisi_acc_free_sgl_pool(struct device *dev,
537 struct hisi_acc_sgl_pool *pool);
538 int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
539 u8 alg_type, int node, struct hisi_qp **qps);
540 void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num);
541 void hisi_qm_dev_shutdown(struct pci_dev *pdev);
542 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
543 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
544 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list);
545 int hisi_qm_resume(struct device *dev);
546 int hisi_qm_suspend(struct device *dev);
547 void hisi_qm_pm_uninit(struct hisi_qm *qm);
548 void hisi_qm_pm_init(struct hisi_qm *qm);
549 int hisi_qm_get_dfx_access(struct hisi_qm *qm);
550 void hisi_qm_put_dfx_access(struct hisi_qm *qm);
551 void hisi_qm_regs_dump(struct seq_file *s, struct debugfs_regset32 *regset);
552 u32 hisi_qm_get_hw_info(struct hisi_qm *qm,
553 const struct hisi_qm_cap_info *info_table,
554 u32 index, bool is_read);
555 int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs,
556 u32 dev_algs_size);
557
558 /* Used by VFIO ACC live migration driver */
559 struct pci_driver *hisi_sec_get_pf_driver(void);
560 struct pci_driver *hisi_hpre_get_pf_driver(void);
561 struct pci_driver *hisi_zip_get_pf_driver(void);
562 #endif
563