1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #include "qlcnic.h"
9
10 #include <linux/slab.h>
11 #include <net/ip.h>
12
13 #define MASK(n) ((1ULL<<(n))-1)
14 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
15
16 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
17
18 #define CRB_BLK(off) ((off >> 20) & 0x3f)
19 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
20 #define CRB_WINDOW_2M (0x130060)
21 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
22 #define CRB_INDIRECT_2M (0x1e0000UL)
23
24
25 #ifndef readq
readq(void __iomem * addr)26 static inline u64 readq(void __iomem *addr)
27 {
28 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
29 }
30 #endif
31
32 #ifndef writeq
writeq(u64 val,void __iomem * addr)33 static inline void writeq(u64 val, void __iomem *addr)
34 {
35 writel(((u32) (val)), (addr));
36 writel(((u32) (val >> 32)), (addr + 4));
37 }
38 #endif
39
40 static const struct crb_128M_2M_block_map
41 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
42 {{{0, 0, 0, 0} } }, /* 0: PCI */
43 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
44 {1, 0x0110000, 0x0120000, 0x130000},
45 {1, 0x0120000, 0x0122000, 0x124000},
46 {1, 0x0130000, 0x0132000, 0x126000},
47 {1, 0x0140000, 0x0142000, 0x128000},
48 {1, 0x0150000, 0x0152000, 0x12a000},
49 {1, 0x0160000, 0x0170000, 0x110000},
50 {1, 0x0170000, 0x0172000, 0x12e000},
51 {0, 0x0000000, 0x0000000, 0x000000},
52 {0, 0x0000000, 0x0000000, 0x000000},
53 {0, 0x0000000, 0x0000000, 0x000000},
54 {0, 0x0000000, 0x0000000, 0x000000},
55 {0, 0x0000000, 0x0000000, 0x000000},
56 {0, 0x0000000, 0x0000000, 0x000000},
57 {1, 0x01e0000, 0x01e0800, 0x122000},
58 {0, 0x0000000, 0x0000000, 0x000000} } },
59 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
60 {{{0, 0, 0, 0} } }, /* 3: */
61 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
62 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
63 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
64 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
65 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {0, 0x0000000, 0x0000000, 0x000000},
72 {0, 0x0000000, 0x0000000, 0x000000},
73 {0, 0x0000000, 0x0000000, 0x000000},
74 {0, 0x0000000, 0x0000000, 0x000000},
75 {0, 0x0000000, 0x0000000, 0x000000},
76 {0, 0x0000000, 0x0000000, 0x000000},
77 {0, 0x0000000, 0x0000000, 0x000000},
78 {0, 0x0000000, 0x0000000, 0x000000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {1, 0x08f0000, 0x08f2000, 0x172000} } },
81 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {1, 0x09f0000, 0x09f2000, 0x176000} } },
97 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
113 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
129 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
130 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
131 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
132 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
133 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
134 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
135 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
136 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
137 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
138 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
139 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
140 {{{0, 0, 0, 0} } }, /* 23: */
141 {{{0, 0, 0, 0} } }, /* 24: */
142 {{{0, 0, 0, 0} } }, /* 25: */
143 {{{0, 0, 0, 0} } }, /* 26: */
144 {{{0, 0, 0, 0} } }, /* 27: */
145 {{{0, 0, 0, 0} } }, /* 28: */
146 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
147 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
148 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
149 {{{0} } }, /* 32: PCI */
150 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
151 {1, 0x2110000, 0x2120000, 0x130000},
152 {1, 0x2120000, 0x2122000, 0x124000},
153 {1, 0x2130000, 0x2132000, 0x126000},
154 {1, 0x2140000, 0x2142000, 0x128000},
155 {1, 0x2150000, 0x2152000, 0x12a000},
156 {1, 0x2160000, 0x2170000, 0x110000},
157 {1, 0x2170000, 0x2172000, 0x12e000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000} } },
166 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
167 {{{0} } }, /* 35: */
168 {{{0} } }, /* 36: */
169 {{{0} } }, /* 37: */
170 {{{0} } }, /* 38: */
171 {{{0} } }, /* 39: */
172 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
173 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
174 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
175 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
176 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
177 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
178 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
179 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
180 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
181 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
182 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
183 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
184 {{{0} } }, /* 52: */
185 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
186 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
187 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
188 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
189 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
190 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
191 {{{0} } }, /* 59: I2C0 */
192 {{{0} } }, /* 60: I2C1 */
193 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
194 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
195 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
196 };
197
198 /*
199 * top 12 bits of crb internal address (hub, agent)
200 */
201 static const unsigned crb_hub_agt[64] = {
202 0,
203 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
204 QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
205 QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
206 0,
207 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
208 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
209 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
210 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
211 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
212 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
213 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
214 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
215 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
216 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
217 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
218 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
219 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
220 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
221 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
222 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
223 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
224 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
225 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
226 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
227 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
228 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
229 0,
230 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
232 0,
233 QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
234 0,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
237 0,
238 0,
239 0,
240 0,
241 0,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
243 0,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
245 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
246 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
248 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
249 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
250 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
251 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
252 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
254 0,
255 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
256 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
257 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
258 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
259 0,
260 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
263 0,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
265 0,
266 };
267
268 /* PCI Windowing for DDR regions. */
269
270 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
271
272 int
qlcnic_pcie_sem_lock(struct qlcnic_adapter * adapter,int sem,u32 id_reg)273 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
274 {
275 int done = 0, timeout = 0;
276
277 while (!done) {
278 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
279 if (done == 1)
280 break;
281 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
282 dev_err(&adapter->pdev->dev,
283 "Failed to acquire sem=%d lock; holdby=%d\n",
284 sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
285 return -EIO;
286 }
287 msleep(1);
288 }
289
290 if (id_reg)
291 QLCWR32(adapter, id_reg, adapter->portnum);
292
293 return 0;
294 }
295
296 void
qlcnic_pcie_sem_unlock(struct qlcnic_adapter * adapter,int sem)297 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
298 {
299 QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
300 }
301
302 static int
qlcnic_send_cmd_descs(struct qlcnic_adapter * adapter,struct cmd_desc_type0 * cmd_desc_arr,int nr_desc)303 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
304 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
305 {
306 u32 i, producer, consumer;
307 struct qlcnic_cmd_buffer *pbuf;
308 struct cmd_desc_type0 *cmd_desc;
309 struct qlcnic_host_tx_ring *tx_ring;
310
311 i = 0;
312
313 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
314 return -EIO;
315
316 tx_ring = adapter->tx_ring;
317 __netif_tx_lock_bh(tx_ring->txq);
318
319 producer = tx_ring->producer;
320 consumer = tx_ring->sw_consumer;
321
322 if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
323 netif_tx_stop_queue(tx_ring->txq);
324 smp_mb();
325 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
326 if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
327 netif_tx_wake_queue(tx_ring->txq);
328 } else {
329 adapter->stats.xmit_off++;
330 __netif_tx_unlock_bh(tx_ring->txq);
331 return -EBUSY;
332 }
333 }
334
335 do {
336 cmd_desc = &cmd_desc_arr[i];
337
338 pbuf = &tx_ring->cmd_buf_arr[producer];
339 pbuf->skb = NULL;
340 pbuf->frag_count = 0;
341
342 memcpy(&tx_ring->desc_head[producer],
343 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
344
345 producer = get_next_index(producer, tx_ring->num_desc);
346 i++;
347
348 } while (i != nr_desc);
349
350 tx_ring->producer = producer;
351
352 qlcnic_update_cmd_producer(adapter, tx_ring);
353
354 __netif_tx_unlock_bh(tx_ring->txq);
355
356 return 0;
357 }
358
359 static int
qlcnic_sre_macaddr_change(struct qlcnic_adapter * adapter,u8 * addr,__le16 vlan_id,unsigned op)360 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
361 __le16 vlan_id, unsigned op)
362 {
363 struct qlcnic_nic_req req;
364 struct qlcnic_mac_req *mac_req;
365 struct qlcnic_vlan_req *vlan_req;
366 u64 word;
367
368 memset(&req, 0, sizeof(struct qlcnic_nic_req));
369 req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
370
371 word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
372 req.req_hdr = cpu_to_le64(word);
373
374 mac_req = (struct qlcnic_mac_req *)&req.words[0];
375 mac_req->op = op;
376 memcpy(mac_req->mac_addr, addr, 6);
377
378 vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
379 vlan_req->vlan_id = vlan_id;
380
381 return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
382 }
383
qlcnic_nic_add_mac(struct qlcnic_adapter * adapter,const u8 * addr)384 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr)
385 {
386 struct list_head *head;
387 struct qlcnic_mac_list_s *cur;
388
389 /* look up if already exists */
390 list_for_each(head, &adapter->mac_list) {
391 cur = list_entry(head, struct qlcnic_mac_list_s, list);
392 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
393 return 0;
394 }
395
396 cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
397 if (cur == NULL) {
398 dev_err(&adapter->netdev->dev,
399 "failed to add mac address filter\n");
400 return -ENOMEM;
401 }
402 memcpy(cur->mac_addr, addr, ETH_ALEN);
403
404 if (qlcnic_sre_macaddr_change(adapter,
405 cur->mac_addr, 0, QLCNIC_MAC_ADD)) {
406 kfree(cur);
407 return -EIO;
408 }
409
410 list_add_tail(&cur->list, &adapter->mac_list);
411 return 0;
412 }
413
qlcnic_set_multi(struct net_device * netdev)414 void qlcnic_set_multi(struct net_device *netdev)
415 {
416 struct qlcnic_adapter *adapter = netdev_priv(netdev);
417 struct netdev_hw_addr *ha;
418 static const u8 bcast_addr[ETH_ALEN] = {
419 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
420 };
421 u32 mode = VPORT_MISS_MODE_DROP;
422
423 if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
424 return;
425
426 qlcnic_nic_add_mac(adapter, adapter->mac_addr);
427 qlcnic_nic_add_mac(adapter, bcast_addr);
428
429 if (netdev->flags & IFF_PROMISC) {
430 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
431 mode = VPORT_MISS_MODE_ACCEPT_ALL;
432 goto send_fw_cmd;
433 }
434
435 if ((netdev->flags & IFF_ALLMULTI) ||
436 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
437 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
438 goto send_fw_cmd;
439 }
440
441 if (!netdev_mc_empty(netdev)) {
442 netdev_for_each_mc_addr(ha, netdev) {
443 qlcnic_nic_add_mac(adapter, ha->addr);
444 }
445 }
446
447 send_fw_cmd:
448 qlcnic_nic_set_promisc(adapter, mode);
449 }
450
qlcnic_nic_set_promisc(struct qlcnic_adapter * adapter,u32 mode)451 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
452 {
453 struct qlcnic_nic_req req;
454 u64 word;
455
456 memset(&req, 0, sizeof(struct qlcnic_nic_req));
457
458 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
459
460 word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
461 ((u64)adapter->portnum << 16);
462 req.req_hdr = cpu_to_le64(word);
463
464 req.words[0] = cpu_to_le64(mode);
465
466 return qlcnic_send_cmd_descs(adapter,
467 (struct cmd_desc_type0 *)&req, 1);
468 }
469
qlcnic_free_mac_list(struct qlcnic_adapter * adapter)470 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
471 {
472 struct qlcnic_mac_list_s *cur;
473 struct list_head *head = &adapter->mac_list;
474
475 while (!list_empty(head)) {
476 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
477 qlcnic_sre_macaddr_change(adapter,
478 cur->mac_addr, 0, QLCNIC_MAC_DEL);
479 list_del(&cur->list);
480 kfree(cur);
481 }
482 }
483
qlcnic_prune_lb_filters(struct qlcnic_adapter * adapter)484 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
485 {
486 struct qlcnic_filter *tmp_fil;
487 struct hlist_node *tmp_hnode, *n;
488 struct hlist_head *head;
489 int i;
490
491 for (i = 0; i < adapter->fhash.fmax; i++) {
492 head = &(adapter->fhash.fhead[i]);
493
494 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode)
495 {
496 if (jiffies >
497 (QLCNIC_FILTER_AGE * HZ + tmp_fil->ftime)) {
498 qlcnic_sre_macaddr_change(adapter,
499 tmp_fil->faddr, tmp_fil->vlan_id,
500 tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
501 QLCNIC_MAC_DEL);
502 spin_lock_bh(&adapter->mac_learn_lock);
503 adapter->fhash.fnum--;
504 hlist_del(&tmp_fil->fnode);
505 spin_unlock_bh(&adapter->mac_learn_lock);
506 kfree(tmp_fil);
507 }
508 }
509 }
510 }
511
qlcnic_delete_lb_filters(struct qlcnic_adapter * adapter)512 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
513 {
514 struct qlcnic_filter *tmp_fil;
515 struct hlist_node *tmp_hnode, *n;
516 struct hlist_head *head;
517 int i;
518
519 for (i = 0; i < adapter->fhash.fmax; i++) {
520 head = &(adapter->fhash.fhead[i]);
521
522 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
523 qlcnic_sre_macaddr_change(adapter, tmp_fil->faddr,
524 tmp_fil->vlan_id, tmp_fil->vlan_id ?
525 QLCNIC_MAC_VLAN_DEL : QLCNIC_MAC_DEL);
526 spin_lock_bh(&adapter->mac_learn_lock);
527 adapter->fhash.fnum--;
528 hlist_del(&tmp_fil->fnode);
529 spin_unlock_bh(&adapter->mac_learn_lock);
530 kfree(tmp_fil);
531 }
532 }
533 }
534
535 #define QLCNIC_CONFIG_INTR_COALESCE 3
536
537 /*
538 * Send the interrupt coalescing parameter set by ethtool to the card.
539 */
qlcnic_config_intr_coalesce(struct qlcnic_adapter * adapter)540 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
541 {
542 struct qlcnic_nic_req req;
543 u64 word[6];
544 int rv, i;
545
546 memset(&req, 0, sizeof(struct qlcnic_nic_req));
547
548 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
549
550 word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
551 req.req_hdr = cpu_to_le64(word[0]);
552
553 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
554 for (i = 0; i < 6; i++)
555 req.words[i] = cpu_to_le64(word[i]);
556
557 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
558 if (rv != 0)
559 dev_err(&adapter->netdev->dev,
560 "Could not send interrupt coalescing parameters\n");
561
562 return rv;
563 }
564
qlcnic_config_hw_lro(struct qlcnic_adapter * adapter,int enable)565 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
566 {
567 struct qlcnic_nic_req req;
568 u64 word;
569 int rv;
570
571 memset(&req, 0, sizeof(struct qlcnic_nic_req));
572
573 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
574
575 word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
576 req.req_hdr = cpu_to_le64(word);
577
578 req.words[0] = cpu_to_le64(enable);
579
580 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
581 if (rv != 0)
582 dev_err(&adapter->netdev->dev,
583 "Could not send configure hw lro request\n");
584
585 return rv;
586 }
587
qlcnic_config_bridged_mode(struct qlcnic_adapter * adapter,u32 enable)588 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
589 {
590 struct qlcnic_nic_req req;
591 u64 word;
592 int rv;
593
594 if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
595 return 0;
596
597 memset(&req, 0, sizeof(struct qlcnic_nic_req));
598
599 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
600
601 word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
602 ((u64)adapter->portnum << 16);
603 req.req_hdr = cpu_to_le64(word);
604
605 req.words[0] = cpu_to_le64(enable);
606
607 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
608 if (rv != 0)
609 dev_err(&adapter->netdev->dev,
610 "Could not send configure bridge mode request\n");
611
612 adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
613
614 return rv;
615 }
616
617
618 #define RSS_HASHTYPE_IP_TCP 0x3
619
qlcnic_config_rss(struct qlcnic_adapter * adapter,int enable)620 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
621 {
622 struct qlcnic_nic_req req;
623 u64 word;
624 int i, rv;
625
626 static const u64 key[] = {
627 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
628 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
629 0x255b0ec26d5a56daULL
630 };
631
632 memset(&req, 0, sizeof(struct qlcnic_nic_req));
633 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
634
635 word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
636 req.req_hdr = cpu_to_le64(word);
637
638 /*
639 * RSS request:
640 * bits 3-0: hash_method
641 * 5-4: hash_type_ipv4
642 * 7-6: hash_type_ipv6
643 * 8: enable
644 * 9: use indirection table
645 * 47-10: reserved
646 * 63-48: indirection table mask
647 */
648 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
649 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
650 ((u64)(enable & 0x1) << 8) |
651 ((0x7ULL) << 48);
652 req.words[0] = cpu_to_le64(word);
653 for (i = 0; i < 5; i++)
654 req.words[i+1] = cpu_to_le64(key[i]);
655
656 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
657 if (rv != 0)
658 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
659
660 return rv;
661 }
662
qlcnic_config_ipaddr(struct qlcnic_adapter * adapter,__be32 ip,int cmd)663 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd)
664 {
665 struct qlcnic_nic_req req;
666 struct qlcnic_ipaddr *ipa;
667 u64 word;
668 int rv;
669
670 memset(&req, 0, sizeof(struct qlcnic_nic_req));
671 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
672
673 word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
674 req.req_hdr = cpu_to_le64(word);
675
676 req.words[0] = cpu_to_le64(cmd);
677 ipa = (struct qlcnic_ipaddr *)&req.words[1];
678 ipa->ipv4 = ip;
679
680 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
681 if (rv != 0)
682 dev_err(&adapter->netdev->dev,
683 "could not notify %s IP 0x%x reuqest\n",
684 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
685
686 return rv;
687 }
688
qlcnic_linkevent_request(struct qlcnic_adapter * adapter,int enable)689 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
690 {
691 struct qlcnic_nic_req req;
692 u64 word;
693 int rv;
694
695 memset(&req, 0, sizeof(struct qlcnic_nic_req));
696 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
697
698 word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
699 req.req_hdr = cpu_to_le64(word);
700 req.words[0] = cpu_to_le64(enable | (enable << 8));
701
702 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
703 if (rv != 0)
704 dev_err(&adapter->netdev->dev,
705 "could not configure link notification\n");
706
707 return rv;
708 }
709
qlcnic_send_lro_cleanup(struct qlcnic_adapter * adapter)710 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
711 {
712 struct qlcnic_nic_req req;
713 u64 word;
714 int rv;
715
716 memset(&req, 0, sizeof(struct qlcnic_nic_req));
717 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
718
719 word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
720 ((u64)adapter->portnum << 16) |
721 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
722
723 req.req_hdr = cpu_to_le64(word);
724
725 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
726 if (rv != 0)
727 dev_err(&adapter->netdev->dev,
728 "could not cleanup lro flows\n");
729
730 return rv;
731 }
732
733 /*
734 * qlcnic_change_mtu - Change the Maximum Transfer Unit
735 * @returns 0 on success, negative on failure
736 */
737
qlcnic_change_mtu(struct net_device * netdev,int mtu)738 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
739 {
740 struct qlcnic_adapter *adapter = netdev_priv(netdev);
741 int rc = 0;
742
743 if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
744 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
745 " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
746 return -EINVAL;
747 }
748
749 rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
750
751 if (!rc)
752 netdev->mtu = mtu;
753
754 return rc;
755 }
756
757 /*
758 * Changes the CRB window to the specified window.
759 */
760 /* Returns < 0 if off is not valid,
761 * 1 if window access is needed. 'off' is set to offset from
762 * CRB space in 128M pci map
763 * 0 if no window access is needed. 'off' is set to 2M addr
764 * In: 'off' is offset from base in 128M pci map
765 */
766 static int
qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter * adapter,ulong off,void __iomem ** addr)767 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
768 ulong off, void __iomem **addr)
769 {
770 const struct crb_128M_2M_sub_block_map *m;
771
772 if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
773 return -EINVAL;
774
775 off -= QLCNIC_PCI_CRBSPACE;
776
777 /*
778 * Try direct map
779 */
780 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
781
782 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
783 *addr = adapter->ahw.pci_base0 + m->start_2M +
784 (off - m->start_128M);
785 return 0;
786 }
787
788 /*
789 * Not in direct map, use crb window
790 */
791 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
792 return 1;
793 }
794
795 /*
796 * In: 'off' is offset from CRB space in 128M pci map
797 * Out: 'off' is 2M pci map addr
798 * side effect: lock crb window
799 */
800 static int
qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter * adapter,ulong off)801 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
802 {
803 u32 window;
804 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
805
806 off -= QLCNIC_PCI_CRBSPACE;
807
808 window = CRB_HI(off);
809 if (window == 0) {
810 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
811 return -EIO;
812 }
813
814 writel(window, addr);
815 if (readl(addr) != window) {
816 if (printk_ratelimit())
817 dev_warn(&adapter->pdev->dev,
818 "failed to set CRB window to %d off 0x%lx\n",
819 window, off);
820 return -EIO;
821 }
822 return 0;
823 }
824
825 int
qlcnic_hw_write_wx_2M(struct qlcnic_adapter * adapter,ulong off,u32 data)826 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
827 {
828 unsigned long flags;
829 int rv;
830 void __iomem *addr = NULL;
831
832 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
833
834 if (rv == 0) {
835 writel(data, addr);
836 return 0;
837 }
838
839 if (rv > 0) {
840 /* indirect access */
841 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
842 crb_win_lock(adapter);
843 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
844 if (!rv)
845 writel(data, addr);
846 crb_win_unlock(adapter);
847 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
848 return rv;
849 }
850
851 dev_err(&adapter->pdev->dev,
852 "%s: invalid offset: 0x%016lx\n", __func__, off);
853 dump_stack();
854 return -EIO;
855 }
856
857 u32
qlcnic_hw_read_wx_2M(struct qlcnic_adapter * adapter,ulong off)858 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
859 {
860 unsigned long flags;
861 int rv;
862 u32 data = -1;
863 void __iomem *addr = NULL;
864
865 rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
866
867 if (rv == 0)
868 return readl(addr);
869
870 if (rv > 0) {
871 /* indirect access */
872 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
873 crb_win_lock(adapter);
874 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
875 data = readl(addr);
876 crb_win_unlock(adapter);
877 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
878 return data;
879 }
880
881 dev_err(&adapter->pdev->dev,
882 "%s: invalid offset: 0x%016lx\n", __func__, off);
883 dump_stack();
884 return -1;
885 }
886
887
888 void __iomem *
qlcnic_get_ioaddr(struct qlcnic_adapter * adapter,u32 offset)889 qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
890 {
891 void __iomem *addr = NULL;
892
893 WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
894
895 return addr;
896 }
897
898
899 static int
qlcnic_pci_set_window_2M(struct qlcnic_adapter * adapter,u64 addr,u32 * start)900 qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
901 u64 addr, u32 *start)
902 {
903 u32 window;
904
905 window = OCM_WIN_P3P(addr);
906
907 writel(window, adapter->ahw.ocm_win_crb);
908 /* read back to flush */
909 readl(adapter->ahw.ocm_win_crb);
910
911 *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
912 return 0;
913 }
914
915 static int
qlcnic_pci_mem_access_direct(struct qlcnic_adapter * adapter,u64 off,u64 * data,int op)916 qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
917 u64 *data, int op)
918 {
919 void __iomem *addr;
920 int ret;
921 u32 start;
922
923 mutex_lock(&adapter->ahw.mem_lock);
924
925 ret = qlcnic_pci_set_window_2M(adapter, off, &start);
926 if (ret != 0)
927 goto unlock;
928
929 addr = adapter->ahw.pci_base0 + start;
930
931 if (op == 0) /* read */
932 *data = readq(addr);
933 else /* write */
934 writeq(*data, addr);
935
936 unlock:
937 mutex_unlock(&adapter->ahw.mem_lock);
938
939 return ret;
940 }
941
942 void
qlcnic_pci_camqm_read_2M(struct qlcnic_adapter * adapter,u64 off,u64 * data)943 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
944 {
945 void __iomem *addr = adapter->ahw.pci_base0 +
946 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
947
948 mutex_lock(&adapter->ahw.mem_lock);
949 *data = readq(addr);
950 mutex_unlock(&adapter->ahw.mem_lock);
951 }
952
953 void
qlcnic_pci_camqm_write_2M(struct qlcnic_adapter * adapter,u64 off,u64 data)954 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
955 {
956 void __iomem *addr = adapter->ahw.pci_base0 +
957 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
958
959 mutex_lock(&adapter->ahw.mem_lock);
960 writeq(data, addr);
961 mutex_unlock(&adapter->ahw.mem_lock);
962 }
963
964 #define MAX_CTL_CHECK 1000
965
966 int
qlcnic_pci_mem_write_2M(struct qlcnic_adapter * adapter,u64 off,u64 data)967 qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
968 u64 off, u64 data)
969 {
970 int i, j, ret;
971 u32 temp, off8;
972 void __iomem *mem_crb;
973
974 /* Only 64-bit aligned access */
975 if (off & 7)
976 return -EIO;
977
978 /* P3 onward, test agent base for MIU and SIU is same */
979 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
980 QLCNIC_ADDR_QDR_NET_MAX)) {
981 mem_crb = qlcnic_get_ioaddr(adapter,
982 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
983 goto correct;
984 }
985
986 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
987 mem_crb = qlcnic_get_ioaddr(adapter,
988 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
989 goto correct;
990 }
991
992 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
993 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
994
995 return -EIO;
996
997 correct:
998 off8 = off & ~0xf;
999
1000 mutex_lock(&adapter->ahw.mem_lock);
1001
1002 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1003 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1004
1005 i = 0;
1006 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1007 writel((TA_CTL_START | TA_CTL_ENABLE),
1008 (mem_crb + TEST_AGT_CTRL));
1009
1010 for (j = 0; j < MAX_CTL_CHECK; j++) {
1011 temp = readl(mem_crb + TEST_AGT_CTRL);
1012 if ((temp & TA_CTL_BUSY) == 0)
1013 break;
1014 }
1015
1016 if (j >= MAX_CTL_CHECK) {
1017 ret = -EIO;
1018 goto done;
1019 }
1020
1021 i = (off & 0xf) ? 0 : 2;
1022 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1023 mem_crb + MIU_TEST_AGT_WRDATA(i));
1024 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1025 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1026 i = (off & 0xf) ? 2 : 0;
1027
1028 writel(data & 0xffffffff,
1029 mem_crb + MIU_TEST_AGT_WRDATA(i));
1030 writel((data >> 32) & 0xffffffff,
1031 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1032
1033 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1034 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1035 (mem_crb + TEST_AGT_CTRL));
1036
1037 for (j = 0; j < MAX_CTL_CHECK; j++) {
1038 temp = readl(mem_crb + TEST_AGT_CTRL);
1039 if ((temp & TA_CTL_BUSY) == 0)
1040 break;
1041 }
1042
1043 if (j >= MAX_CTL_CHECK) {
1044 if (printk_ratelimit())
1045 dev_err(&adapter->pdev->dev,
1046 "failed to write through agent\n");
1047 ret = -EIO;
1048 } else
1049 ret = 0;
1050
1051 done:
1052 mutex_unlock(&adapter->ahw.mem_lock);
1053
1054 return ret;
1055 }
1056
1057 int
qlcnic_pci_mem_read_2M(struct qlcnic_adapter * adapter,u64 off,u64 * data)1058 qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1059 u64 off, u64 *data)
1060 {
1061 int j, ret;
1062 u32 temp, off8;
1063 u64 val;
1064 void __iomem *mem_crb;
1065
1066 /* Only 64-bit aligned access */
1067 if (off & 7)
1068 return -EIO;
1069
1070 /* P3 onward, test agent base for MIU and SIU is same */
1071 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1072 QLCNIC_ADDR_QDR_NET_MAX)) {
1073 mem_crb = qlcnic_get_ioaddr(adapter,
1074 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1075 goto correct;
1076 }
1077
1078 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1079 mem_crb = qlcnic_get_ioaddr(adapter,
1080 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1081 goto correct;
1082 }
1083
1084 if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1085 return qlcnic_pci_mem_access_direct(adapter,
1086 off, data, 0);
1087 }
1088
1089 return -EIO;
1090
1091 correct:
1092 off8 = off & ~0xf;
1093
1094 mutex_lock(&adapter->ahw.mem_lock);
1095
1096 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1097 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1098 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1099 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1100
1101 for (j = 0; j < MAX_CTL_CHECK; j++) {
1102 temp = readl(mem_crb + TEST_AGT_CTRL);
1103 if ((temp & TA_CTL_BUSY) == 0)
1104 break;
1105 }
1106
1107 if (j >= MAX_CTL_CHECK) {
1108 if (printk_ratelimit())
1109 dev_err(&adapter->pdev->dev,
1110 "failed to read through agent\n");
1111 ret = -EIO;
1112 } else {
1113 off8 = MIU_TEST_AGT_RDDATA_LO;
1114 if (off & 0xf)
1115 off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1116
1117 temp = readl(mem_crb + off8 + 4);
1118 val = (u64)temp << 32;
1119 val |= readl(mem_crb + off8);
1120 *data = val;
1121 ret = 0;
1122 }
1123
1124 mutex_unlock(&adapter->ahw.mem_lock);
1125
1126 return ret;
1127 }
1128
qlcnic_get_board_info(struct qlcnic_adapter * adapter)1129 int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1130 {
1131 int offset, board_type, magic;
1132 struct pci_dev *pdev = adapter->pdev;
1133
1134 offset = QLCNIC_FW_MAGIC_OFFSET;
1135 if (qlcnic_rom_fast_read(adapter, offset, &magic))
1136 return -EIO;
1137
1138 if (magic != QLCNIC_BDINFO_MAGIC) {
1139 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1140 magic);
1141 return -EIO;
1142 }
1143
1144 offset = QLCNIC_BRDTYPE_OFFSET;
1145 if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1146 return -EIO;
1147
1148 adapter->ahw.board_type = board_type;
1149
1150 if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
1151 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1152 if ((gpio & 0x8000) == 0)
1153 board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
1154 }
1155
1156 switch (board_type) {
1157 case QLCNIC_BRDTYPE_P3P_HMEZ:
1158 case QLCNIC_BRDTYPE_P3P_XG_LOM:
1159 case QLCNIC_BRDTYPE_P3P_10G_CX4:
1160 case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1161 case QLCNIC_BRDTYPE_P3P_IMEZ:
1162 case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1163 case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1164 case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1165 case QLCNIC_BRDTYPE_P3P_10G_XFP:
1166 case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
1167 adapter->ahw.port_type = QLCNIC_XGBE;
1168 break;
1169 case QLCNIC_BRDTYPE_P3P_REF_QG:
1170 case QLCNIC_BRDTYPE_P3P_4_GB:
1171 case QLCNIC_BRDTYPE_P3P_4_GB_MM:
1172 adapter->ahw.port_type = QLCNIC_GBE;
1173 break;
1174 case QLCNIC_BRDTYPE_P3P_10G_TP:
1175 adapter->ahw.port_type = (adapter->portnum < 2) ?
1176 QLCNIC_XGBE : QLCNIC_GBE;
1177 break;
1178 default:
1179 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1180 adapter->ahw.port_type = QLCNIC_XGBE;
1181 break;
1182 }
1183
1184 return 0;
1185 }
1186
1187 int
qlcnic_wol_supported(struct qlcnic_adapter * adapter)1188 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1189 {
1190 u32 wol_cfg;
1191
1192 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1193 if (wol_cfg & (1UL << adapter->portnum)) {
1194 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1195 if (wol_cfg & (1 << adapter->portnum))
1196 return 1;
1197 }
1198
1199 return 0;
1200 }
1201
qlcnic_config_led(struct qlcnic_adapter * adapter,u32 state,u32 rate)1202 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1203 {
1204 struct qlcnic_nic_req req;
1205 int rv;
1206 u64 word;
1207
1208 memset(&req, 0, sizeof(struct qlcnic_nic_req));
1209 req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1210
1211 word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1212 req.req_hdr = cpu_to_le64(word);
1213
1214 req.words[0] = cpu_to_le64((u64)rate << 32);
1215 req.words[1] = cpu_to_le64(state);
1216
1217 rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1218 if (rv)
1219 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1220
1221 return rv;
1222 }
1223