1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #include "qla_def.h"
7
8 #include <linux/moduleparam.h>
9 #include <linux/vmalloc.h>
10 #include <linux/delay.h>
11 #include <linux/kthread.h>
12 #include <linux/mutex.h>
13 #include <linux/kobject.h>
14 #include <linux/slab.h>
15 #include <linux/blk-mq-pci.h>
16 #include <linux/refcount.h>
17 #include <linux/crash_dump.h>
18
19 #include <scsi/scsi_tcq.h>
20 #include <scsi/scsicam.h>
21 #include <scsi/scsi_transport.h>
22 #include <scsi/scsi_transport_fc.h>
23
24 #include "qla_target.h"
25
26 /*
27 * Driver version
28 */
29 char qla2x00_version_str[40];
30
31 static int apidev_major;
32
33 /*
34 * SRB allocation cache
35 */
36 struct kmem_cache *srb_cachep;
37
38 int ql2xfulldump_on_mpifail;
39 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
40 MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
41 "Set this to take full dump on MPI hang.");
42
43 int ql2xenforce_iocb_limit = 1;
44 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR);
45 MODULE_PARM_DESC(ql2xenforce_iocb_limit,
46 "Enforce IOCB throttling, to avoid FW congestion. (default: 1)");
47
48 /*
49 * CT6 CTX allocation cache
50 */
51 static struct kmem_cache *ctx_cachep;
52 /*
53 * error level for logging
54 */
55 uint ql_errlev = 0x8001;
56
57 int ql2xsecenable;
58 module_param(ql2xsecenable, int, S_IRUGO);
59 MODULE_PARM_DESC(ql2xsecenable,
60 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled.");
61
62 static int ql2xenableclass2;
63 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
64 MODULE_PARM_DESC(ql2xenableclass2,
65 "Specify if Class 2 operations are supported from the very "
66 "beginning. Default is 0 - class 2 not supported.");
67
68
69 int ql2xlogintimeout = 20;
70 module_param(ql2xlogintimeout, int, S_IRUGO);
71 MODULE_PARM_DESC(ql2xlogintimeout,
72 "Login timeout value in seconds.");
73
74 int qlport_down_retry;
75 module_param(qlport_down_retry, int, S_IRUGO);
76 MODULE_PARM_DESC(qlport_down_retry,
77 "Maximum number of command retries to a port that returns "
78 "a PORT-DOWN status.");
79
80 int ql2xplogiabsentdevice;
81 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
82 MODULE_PARM_DESC(ql2xplogiabsentdevice,
83 "Option to enable PLOGI to devices that are not present after "
84 "a Fabric scan. This is needed for several broken switches. "
85 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
86
87 int ql2xloginretrycount;
88 module_param(ql2xloginretrycount, int, S_IRUGO);
89 MODULE_PARM_DESC(ql2xloginretrycount,
90 "Specify an alternate value for the NVRAM login retry count.");
91
92 int ql2xallocfwdump = 1;
93 module_param(ql2xallocfwdump, int, S_IRUGO);
94 MODULE_PARM_DESC(ql2xallocfwdump,
95 "Option to enable allocation of memory for a firmware dump "
96 "during HBA initialization. Memory allocation requirements "
97 "vary by ISP type. Default is 1 - allocate memory.");
98
99 int ql2xextended_error_logging;
100 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
101 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
102 MODULE_PARM_DESC(ql2xextended_error_logging,
103 "Option to enable extended error logging,\n"
104 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
105 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
106 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
107 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
108 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
109 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
110 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
111 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
112 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
113 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
114 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
115 "\t\t0x1e400000 - Preferred value for capturing essential "
116 "debug information (equivalent to old "
117 "ql2xextended_error_logging=1).\n"
118 "\t\tDo LOGICAL OR of the value to enable more than one level");
119
120 int ql2xshiftctondsd = 6;
121 module_param(ql2xshiftctondsd, int, S_IRUGO);
122 MODULE_PARM_DESC(ql2xshiftctondsd,
123 "Set to control shifting of command type processing "
124 "based on total number of SG elements.");
125
126 int ql2xfdmienable = 1;
127 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
128 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
129 MODULE_PARM_DESC(ql2xfdmienable,
130 "Enables FDMI registrations. "
131 "0 - no FDMI registrations. "
132 "1 - provide FDMI registrations (default).");
133
134 #define MAX_Q_DEPTH 64
135 static int ql2xmaxqdepth = MAX_Q_DEPTH;
136 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
137 MODULE_PARM_DESC(ql2xmaxqdepth,
138 "Maximum queue depth to set for each LUN. "
139 "Default is 64.");
140
141 int ql2xenabledif = 2;
142 module_param(ql2xenabledif, int, S_IRUGO);
143 MODULE_PARM_DESC(ql2xenabledif,
144 " Enable T10-CRC-DIF:\n"
145 " Default is 2.\n"
146 " 0 -- No DIF Support\n"
147 " 1 -- Enable DIF for all types\n"
148 " 2 -- Enable DIF for all types, except Type 0.\n");
149
150 #if (IS_ENABLED(CONFIG_NVME_FC))
151 int ql2xnvmeenable = 1;
152 #else
153 int ql2xnvmeenable;
154 #endif
155 module_param(ql2xnvmeenable, int, 0644);
156 MODULE_PARM_DESC(ql2xnvmeenable,
157 "Enables NVME support. "
158 "0 - no NVMe. Default is Y");
159
160 int ql2xenablehba_err_chk = 2;
161 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
162 MODULE_PARM_DESC(ql2xenablehba_err_chk,
163 " Enable T10-CRC-DIF Error isolation by HBA:\n"
164 " Default is 2.\n"
165 " 0 -- Error isolation disabled\n"
166 " 1 -- Error isolation enabled only for DIX Type 0\n"
167 " 2 -- Error isolation enabled for all Types\n");
168
169 int ql2xiidmaenable = 1;
170 module_param(ql2xiidmaenable, int, S_IRUGO);
171 MODULE_PARM_DESC(ql2xiidmaenable,
172 "Enables iIDMA settings "
173 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
174
175 int ql2xmqsupport = 1;
176 module_param(ql2xmqsupport, int, S_IRUGO);
177 MODULE_PARM_DESC(ql2xmqsupport,
178 "Enable on demand multiple queue pairs support "
179 "Default is 1 for supported. "
180 "Set it to 0 to turn off mq qpair support.");
181
182 int ql2xfwloadbin;
183 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
184 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
185 MODULE_PARM_DESC(ql2xfwloadbin,
186 "Option to specify location from which to load ISP firmware:.\n"
187 " 2 -- load firmware via the request_firmware() (hotplug).\n"
188 " interface.\n"
189 " 1 -- load firmware from flash.\n"
190 " 0 -- use default semantics.\n");
191
192 int ql2xetsenable;
193 module_param(ql2xetsenable, int, S_IRUGO);
194 MODULE_PARM_DESC(ql2xetsenable,
195 "Enables firmware ETS burst."
196 "Default is 0 - skip ETS enablement.");
197
198 int ql2xdbwr = 1;
199 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
200 MODULE_PARM_DESC(ql2xdbwr,
201 "Option to specify scheme for request queue posting.\n"
202 " 0 -- Regular doorbell.\n"
203 " 1 -- CAMRAM doorbell (faster).\n");
204
205 int ql2xgffidenable;
206 module_param(ql2xgffidenable, int, S_IRUGO);
207 MODULE_PARM_DESC(ql2xgffidenable,
208 "Enables GFF_ID checks of port type. "
209 "Default is 0 - Do not use GFF_ID information.");
210
211 int ql2xasynctmfenable = 1;
212 module_param(ql2xasynctmfenable, int, S_IRUGO);
213 MODULE_PARM_DESC(ql2xasynctmfenable,
214 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
215 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
216
217 int ql2xdontresethba;
218 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
219 MODULE_PARM_DESC(ql2xdontresethba,
220 "Option to specify reset behaviour.\n"
221 " 0 (Default) -- Reset on failure.\n"
222 " 1 -- Do not reset on failure.\n");
223
224 uint64_t ql2xmaxlun = MAX_LUNS;
225 module_param(ql2xmaxlun, ullong, S_IRUGO);
226 MODULE_PARM_DESC(ql2xmaxlun,
227 "Defines the maximum LU number to register with the SCSI "
228 "midlayer. Default is 65535.");
229
230 int ql2xmdcapmask = 0x1F;
231 module_param(ql2xmdcapmask, int, S_IRUGO);
232 MODULE_PARM_DESC(ql2xmdcapmask,
233 "Set the Minidump driver capture mask level. "
234 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
235
236 int ql2xmdenable = 1;
237 module_param(ql2xmdenable, int, S_IRUGO);
238 MODULE_PARM_DESC(ql2xmdenable,
239 "Enable/disable MiniDump. "
240 "0 - MiniDump disabled. "
241 "1 (Default) - MiniDump enabled.");
242
243 int ql2xexlogins;
244 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
245 MODULE_PARM_DESC(ql2xexlogins,
246 "Number of extended Logins. "
247 "0 (Default)- Disabled.");
248
249 int ql2xexchoffld = 1024;
250 module_param(ql2xexchoffld, uint, 0644);
251 MODULE_PARM_DESC(ql2xexchoffld,
252 "Number of target exchanges.");
253
254 int ql2xiniexchg = 1024;
255 module_param(ql2xiniexchg, uint, 0644);
256 MODULE_PARM_DESC(ql2xiniexchg,
257 "Number of initiator exchanges.");
258
259 int ql2xfwholdabts;
260 module_param(ql2xfwholdabts, int, S_IRUGO);
261 MODULE_PARM_DESC(ql2xfwholdabts,
262 "Allow FW to hold status IOCB until ABTS rsp received. "
263 "0 (Default) Do not set fw option. "
264 "1 - Set fw option to hold ABTS.");
265
266 int ql2xmvasynctoatio = 1;
267 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
268 MODULE_PARM_DESC(ql2xmvasynctoatio,
269 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
270 "0 (Default). Do not move IOCBs"
271 "1 - Move IOCBs.");
272
273 int ql2xautodetectsfp = 1;
274 module_param(ql2xautodetectsfp, int, 0444);
275 MODULE_PARM_DESC(ql2xautodetectsfp,
276 "Detect SFP range and set appropriate distance.\n"
277 "1 (Default): Enable\n");
278
279 int ql2xenablemsix = 1;
280 module_param(ql2xenablemsix, int, 0444);
281 MODULE_PARM_DESC(ql2xenablemsix,
282 "Set to enable MSI or MSI-X interrupt mechanism.\n"
283 " Default is 1, enable MSI-X interrupt mechanism.\n"
284 " 0 -- enable traditional pin-based mechanism.\n"
285 " 1 -- enable MSI-X interrupt mechanism.\n"
286 " 2 -- enable MSI interrupt mechanism.\n");
287
288 int qla2xuseresexchforels;
289 module_param(qla2xuseresexchforels, int, 0444);
290 MODULE_PARM_DESC(qla2xuseresexchforels,
291 "Reserve 1/2 of emergency exchanges for ELS.\n"
292 " 0 (default): disabled");
293
294 static int ql2xprotmask;
295 module_param(ql2xprotmask, int, 0644);
296 MODULE_PARM_DESC(ql2xprotmask,
297 "Override DIF/DIX protection capabilities mask\n"
298 "Default is 0 which sets protection mask based on "
299 "capabilities reported by HBA firmware.\n");
300
301 static int ql2xprotguard;
302 module_param(ql2xprotguard, int, 0644);
303 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
304 " 0 -- Let HBA firmware decide\n"
305 " 1 -- Force T10 CRC\n"
306 " 2 -- Force IP checksum\n");
307
308 int ql2xdifbundlinginternalbuffers;
309 module_param(ql2xdifbundlinginternalbuffers, int, 0644);
310 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
311 "Force using internal buffers for DIF information\n"
312 "0 (Default). Based on check.\n"
313 "1 Force using internal buffers\n");
314
315 int ql2xsmartsan;
316 module_param(ql2xsmartsan, int, 0444);
317 module_param_named(smartsan, ql2xsmartsan, int, 0444);
318 MODULE_PARM_DESC(ql2xsmartsan,
319 "Send SmartSAN Management Attributes for FDMI Registration."
320 " Default is 0 - No SmartSAN registration,"
321 " 1 - Register SmartSAN Management Attributes.");
322
323 int ql2xrdpenable;
324 module_param(ql2xrdpenable, int, 0444);
325 module_param_named(rdpenable, ql2xrdpenable, int, 0444);
326 MODULE_PARM_DESC(ql2xrdpenable,
327 "Enables RDP responses. "
328 "0 - no RDP responses (default). "
329 "1 - provide RDP responses.");
330 int ql2xabts_wait_nvme = 1;
331 module_param(ql2xabts_wait_nvme, int, 0444);
332 MODULE_PARM_DESC(ql2xabts_wait_nvme,
333 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)");
334
335
336 u32 ql2xdelay_before_pci_error_handling = 5;
337 module_param(ql2xdelay_before_pci_error_handling, uint, 0644);
338 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling,
339 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n");
340
341 static void qla2x00_clear_drv_active(struct qla_hw_data *);
342 static void qla2x00_free_device(scsi_qla_host_t *);
343 static int qla2xxx_map_queues(struct Scsi_Host *shost);
344 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
345
346 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES;
347 module_param(ql2xnvme_queues, uint, S_IRUGO);
348 MODULE_PARM_DESC(ql2xnvme_queues,
349 "Number of NVMe Queues that can be configured.\n"
350 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n"
351 "1 - Minimum number of queues supported\n"
352 "8 - Default value");
353
354 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
355 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
356
357 /* TODO Convert to inlines
358 *
359 * Timer routines
360 */
361
362 __inline__ void
qla2x00_start_timer(scsi_qla_host_t * vha,unsigned long interval)363 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
364 {
365 timer_setup(&vha->timer, qla2x00_timer, 0);
366 vha->timer.expires = jiffies + interval * HZ;
367 add_timer(&vha->timer);
368 vha->timer_active = 1;
369 }
370
371 static inline void
qla2x00_restart_timer(scsi_qla_host_t * vha,unsigned long interval)372 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
373 {
374 /* Currently used for 82XX only. */
375 if (vha->device_flags & DFLG_DEV_FAILED) {
376 ql_dbg(ql_dbg_timer, vha, 0x600d,
377 "Device in a failed state, returning.\n");
378 return;
379 }
380
381 mod_timer(&vha->timer, jiffies + interval * HZ);
382 }
383
384 static __inline__ void
qla2x00_stop_timer(scsi_qla_host_t * vha)385 qla2x00_stop_timer(scsi_qla_host_t *vha)
386 {
387 del_timer_sync(&vha->timer);
388 vha->timer_active = 0;
389 }
390
391 static int qla2x00_do_dpc(void *data);
392
393 static void qla2x00_rst_aen(scsi_qla_host_t *);
394
395 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
396 struct req_que **, struct rsp_que **);
397 static void qla2x00_free_fw_dump(struct qla_hw_data *);
398 static void qla2x00_mem_free(struct qla_hw_data *);
399 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
400 struct qla_qpair *qpair);
401
402 /* -------------------------------------------------------------------------- */
qla_init_base_qpair(struct scsi_qla_host * vha,struct req_que * req,struct rsp_que * rsp)403 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
404 struct rsp_que *rsp)
405 {
406 struct qla_hw_data *ha = vha->hw;
407
408 rsp->qpair = ha->base_qpair;
409 rsp->req = req;
410 ha->base_qpair->hw = ha;
411 ha->base_qpair->req = req;
412 ha->base_qpair->rsp = rsp;
413 ha->base_qpair->vha = vha;
414 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
415 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
416 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
417 ha->base_qpair->srb_mempool = ha->srb_mempool;
418 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
419 ha->base_qpair->enable_class_2 = ql2xenableclass2;
420 /* init qpair to this cpu. Will adjust at run time. */
421 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
422 ha->base_qpair->pdev = ha->pdev;
423
424 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
425 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
426 }
427
qla2x00_alloc_queues(struct qla_hw_data * ha,struct req_que * req,struct rsp_que * rsp)428 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
429 struct rsp_que *rsp)
430 {
431 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
432
433 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
434 GFP_KERNEL);
435 if (!ha->req_q_map) {
436 ql_log(ql_log_fatal, vha, 0x003b,
437 "Unable to allocate memory for request queue ptrs.\n");
438 goto fail_req_map;
439 }
440
441 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
442 GFP_KERNEL);
443 if (!ha->rsp_q_map) {
444 ql_log(ql_log_fatal, vha, 0x003c,
445 "Unable to allocate memory for response queue ptrs.\n");
446 goto fail_rsp_map;
447 }
448
449 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
450 if (ha->base_qpair == NULL) {
451 ql_log(ql_log_warn, vha, 0x00e0,
452 "Failed to allocate base queue pair memory.\n");
453 goto fail_base_qpair;
454 }
455
456 qla_init_base_qpair(vha, req, rsp);
457
458 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
459 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
460 GFP_KERNEL);
461 if (!ha->queue_pair_map) {
462 ql_log(ql_log_fatal, vha, 0x0180,
463 "Unable to allocate memory for queue pair ptrs.\n");
464 goto fail_qpair_map;
465 }
466 }
467
468 /*
469 * Make sure we record at least the request and response queue zero in
470 * case we need to free them if part of the probe fails.
471 */
472 ha->rsp_q_map[0] = rsp;
473 ha->req_q_map[0] = req;
474 set_bit(0, ha->rsp_qid_map);
475 set_bit(0, ha->req_qid_map);
476 return 0;
477
478 fail_qpair_map:
479 kfree(ha->base_qpair);
480 ha->base_qpair = NULL;
481 fail_base_qpair:
482 kfree(ha->rsp_q_map);
483 ha->rsp_q_map = NULL;
484 fail_rsp_map:
485 kfree(ha->req_q_map);
486 ha->req_q_map = NULL;
487 fail_req_map:
488 return -ENOMEM;
489 }
490
qla2x00_free_req_que(struct qla_hw_data * ha,struct req_que * req)491 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
492 {
493 if (IS_QLAFX00(ha)) {
494 if (req && req->ring_fx00)
495 dma_free_coherent(&ha->pdev->dev,
496 (req->length_fx00 + 1) * sizeof(request_t),
497 req->ring_fx00, req->dma_fx00);
498 } else if (req && req->ring)
499 dma_free_coherent(&ha->pdev->dev,
500 (req->length + 1) * sizeof(request_t),
501 req->ring, req->dma);
502
503 if (req)
504 kfree(req->outstanding_cmds);
505
506 kfree(req);
507 }
508
qla2x00_free_rsp_que(struct qla_hw_data * ha,struct rsp_que * rsp)509 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
510 {
511 if (IS_QLAFX00(ha)) {
512 if (rsp && rsp->ring_fx00)
513 dma_free_coherent(&ha->pdev->dev,
514 (rsp->length_fx00 + 1) * sizeof(request_t),
515 rsp->ring_fx00, rsp->dma_fx00);
516 } else if (rsp && rsp->ring) {
517 dma_free_coherent(&ha->pdev->dev,
518 (rsp->length + 1) * sizeof(response_t),
519 rsp->ring, rsp->dma);
520 }
521 kfree(rsp);
522 }
523
qla2x00_free_queues(struct qla_hw_data * ha)524 static void qla2x00_free_queues(struct qla_hw_data *ha)
525 {
526 struct req_que *req;
527 struct rsp_que *rsp;
528 int cnt;
529 unsigned long flags;
530
531 if (ha->queue_pair_map) {
532 kfree(ha->queue_pair_map);
533 ha->queue_pair_map = NULL;
534 }
535 if (ha->base_qpair) {
536 kfree(ha->base_qpair);
537 ha->base_qpair = NULL;
538 }
539
540 spin_lock_irqsave(&ha->hardware_lock, flags);
541 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
542 if (!test_bit(cnt, ha->req_qid_map))
543 continue;
544
545 req = ha->req_q_map[cnt];
546 clear_bit(cnt, ha->req_qid_map);
547 ha->req_q_map[cnt] = NULL;
548
549 spin_unlock_irqrestore(&ha->hardware_lock, flags);
550 qla2x00_free_req_que(ha, req);
551 spin_lock_irqsave(&ha->hardware_lock, flags);
552 }
553 spin_unlock_irqrestore(&ha->hardware_lock, flags);
554
555 kfree(ha->req_q_map);
556 ha->req_q_map = NULL;
557
558
559 spin_lock_irqsave(&ha->hardware_lock, flags);
560 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
561 if (!test_bit(cnt, ha->rsp_qid_map))
562 continue;
563
564 rsp = ha->rsp_q_map[cnt];
565 clear_bit(cnt, ha->rsp_qid_map);
566 ha->rsp_q_map[cnt] = NULL;
567 spin_unlock_irqrestore(&ha->hardware_lock, flags);
568 qla2x00_free_rsp_que(ha, rsp);
569 spin_lock_irqsave(&ha->hardware_lock, flags);
570 }
571 spin_unlock_irqrestore(&ha->hardware_lock, flags);
572
573 kfree(ha->rsp_q_map);
574 ha->rsp_q_map = NULL;
575 }
576
577 static char *
qla2x00_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)578 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
579 {
580 struct qla_hw_data *ha = vha->hw;
581 static const char *const pci_bus_modes[] = {
582 "33", "66", "100", "133",
583 };
584 uint16_t pci_bus;
585
586 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
587 if (pci_bus) {
588 snprintf(str, str_len, "PCI-X (%s MHz)",
589 pci_bus_modes[pci_bus]);
590 } else {
591 pci_bus = (ha->pci_attr & BIT_8) >> 8;
592 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
593 }
594
595 return str;
596 }
597
598 static char *
qla24xx_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)599 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
600 {
601 static const char *const pci_bus_modes[] = {
602 "33", "66", "100", "133",
603 };
604 struct qla_hw_data *ha = vha->hw;
605 uint32_t pci_bus;
606
607 if (pci_is_pcie(ha->pdev)) {
608 uint32_t lstat, lspeed, lwidth;
609 const char *speed_str;
610
611 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
612 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
613 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
614
615 switch (lspeed) {
616 case 1:
617 speed_str = "2.5GT/s";
618 break;
619 case 2:
620 speed_str = "5.0GT/s";
621 break;
622 case 3:
623 speed_str = "8.0GT/s";
624 break;
625 case 4:
626 speed_str = "16.0GT/s";
627 break;
628 default:
629 speed_str = "<unknown>";
630 break;
631 }
632 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
633
634 return str;
635 }
636
637 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
638 if (pci_bus == 0 || pci_bus == 8)
639 snprintf(str, str_len, "PCI (%s MHz)",
640 pci_bus_modes[pci_bus >> 3]);
641 else
642 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
643 pci_bus & 4 ? 2 : 1,
644 pci_bus_modes[pci_bus & 3]);
645
646 return str;
647 }
648
649 static char *
qla2x00_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)650 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
651 {
652 char un_str[10];
653 struct qla_hw_data *ha = vha->hw;
654
655 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
656 ha->fw_minor_version, ha->fw_subminor_version);
657
658 if (ha->fw_attributes & BIT_9) {
659 strcat(str, "FLX");
660 return (str);
661 }
662
663 switch (ha->fw_attributes & 0xFF) {
664 case 0x7:
665 strcat(str, "EF");
666 break;
667 case 0x17:
668 strcat(str, "TP");
669 break;
670 case 0x37:
671 strcat(str, "IP");
672 break;
673 case 0x77:
674 strcat(str, "VI");
675 break;
676 default:
677 sprintf(un_str, "(%x)", ha->fw_attributes);
678 strcat(str, un_str);
679 break;
680 }
681 if (ha->fw_attributes & 0x100)
682 strcat(str, "X");
683
684 return (str);
685 }
686
687 static char *
qla24xx_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)688 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
689 {
690 struct qla_hw_data *ha = vha->hw;
691
692 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
693 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
694 return str;
695 }
696
qla2x00_sp_free_dma(srb_t * sp)697 void qla2x00_sp_free_dma(srb_t *sp)
698 {
699 struct qla_hw_data *ha = sp->vha->hw;
700 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
701
702 if (sp->flags & SRB_DMA_VALID) {
703 scsi_dma_unmap(cmd);
704 sp->flags &= ~SRB_DMA_VALID;
705 }
706
707 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
708 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
709 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
710 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
711 }
712
713 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
714 /* List assured to be having elements */
715 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
716 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
717 }
718
719 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
720 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
721
722 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
723 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
724 }
725
726 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
727 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
728
729 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
730 ctx1->fcp_cmnd_dma);
731 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
732 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
733 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
734 mempool_free(ctx1, ha->ctx_mempool);
735 }
736 }
737
qla2x00_sp_compl(srb_t * sp,int res)738 void qla2x00_sp_compl(srb_t *sp, int res)
739 {
740 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
741 struct completion *comp = sp->comp;
742
743 /* kref: INIT */
744 kref_put(&sp->cmd_kref, qla2x00_sp_release);
745 cmd->result = res;
746 sp->type = 0;
747 scsi_done(cmd);
748 if (comp)
749 complete(comp);
750 }
751
qla2xxx_qpair_sp_free_dma(srb_t * sp)752 void qla2xxx_qpair_sp_free_dma(srb_t *sp)
753 {
754 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
755 struct qla_hw_data *ha = sp->fcport->vha->hw;
756
757 if (sp->flags & SRB_DMA_VALID) {
758 scsi_dma_unmap(cmd);
759 sp->flags &= ~SRB_DMA_VALID;
760 }
761
762 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
763 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
764 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
765 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
766 }
767
768 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
769 /* List assured to be having elements */
770 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
771 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
772 }
773
774 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
775 struct crc_context *difctx = sp->u.scmd.crc_ctx;
776 struct dsd_dma *dif_dsd, *nxt_dsd;
777
778 list_for_each_entry_safe(dif_dsd, nxt_dsd,
779 &difctx->ldif_dma_hndl_list, list) {
780 list_del(&dif_dsd->list);
781 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
782 dif_dsd->dsd_list_dma);
783 kfree(dif_dsd);
784 difctx->no_dif_bundl--;
785 }
786
787 list_for_each_entry_safe(dif_dsd, nxt_dsd,
788 &difctx->ldif_dsd_list, list) {
789 list_del(&dif_dsd->list);
790 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
791 dif_dsd->dsd_list_dma);
792 kfree(dif_dsd);
793 difctx->no_ldif_dsd--;
794 }
795
796 if (difctx->no_ldif_dsd) {
797 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
798 "%s: difctx->no_ldif_dsd=%x\n",
799 __func__, difctx->no_ldif_dsd);
800 }
801
802 if (difctx->no_dif_bundl) {
803 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
804 "%s: difctx->no_dif_bundl=%x\n",
805 __func__, difctx->no_dif_bundl);
806 }
807 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
808 }
809
810 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
811 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
812
813 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
814 ctx1->fcp_cmnd_dma);
815 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
816 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
817 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
818 mempool_free(ctx1, ha->ctx_mempool);
819 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
820 }
821
822 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
823 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
824
825 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
826 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
827 }
828 }
829
qla2xxx_qpair_sp_compl(srb_t * sp,int res)830 void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
831 {
832 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
833 struct completion *comp = sp->comp;
834
835 /* ref: INIT */
836 kref_put(&sp->cmd_kref, qla2x00_sp_release);
837 cmd->result = res;
838 sp->type = 0;
839 scsi_done(cmd);
840 if (comp)
841 complete(comp);
842 }
843
844 static int
qla2xxx_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)845 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
846 {
847 scsi_qla_host_t *vha = shost_priv(host);
848 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
849 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
850 struct qla_hw_data *ha = vha->hw;
851 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
852 srb_t *sp;
853 int rval;
854
855 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
856 WARN_ON_ONCE(!rport)) {
857 cmd->result = DID_NO_CONNECT << 16;
858 goto qc24_fail_command;
859 }
860
861 if (ha->mqenable) {
862 uint32_t tag;
863 uint16_t hwq;
864 struct qla_qpair *qpair = NULL;
865
866 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd));
867 hwq = blk_mq_unique_tag_to_hwq(tag);
868 qpair = ha->queue_pair_map[hwq];
869
870 if (qpair)
871 return qla2xxx_mqueuecommand(host, cmd, qpair);
872 }
873
874 if (ha->flags.eeh_busy) {
875 if (ha->flags.pci_channel_io_perm_failure) {
876 ql_dbg(ql_dbg_aer, vha, 0x9010,
877 "PCI Channel IO permanent failure, exiting "
878 "cmd=%p.\n", cmd);
879 cmd->result = DID_NO_CONNECT << 16;
880 } else {
881 ql_dbg(ql_dbg_aer, vha, 0x9011,
882 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
883 cmd->result = DID_REQUEUE << 16;
884 }
885 goto qc24_fail_command;
886 }
887
888 rval = fc_remote_port_chkready(rport);
889 if (rval) {
890 cmd->result = rval;
891 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
892 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
893 cmd, rval);
894 goto qc24_fail_command;
895 }
896
897 if (!vha->flags.difdix_supported &&
898 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
899 ql_dbg(ql_dbg_io, vha, 0x3004,
900 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
901 cmd);
902 cmd->result = DID_NO_CONNECT << 16;
903 goto qc24_fail_command;
904 }
905
906 if (!fcport || fcport->deleted) {
907 cmd->result = DID_IMM_RETRY << 16;
908 goto qc24_fail_command;
909 }
910
911 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
912 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
913 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
914 ql_dbg(ql_dbg_io, vha, 0x3005,
915 "Returning DNC, fcport_state=%d loop_state=%d.\n",
916 atomic_read(&fcport->state),
917 atomic_read(&base_vha->loop_state));
918 cmd->result = DID_NO_CONNECT << 16;
919 goto qc24_fail_command;
920 }
921 goto qc24_target_busy;
922 }
923
924 /*
925 * Return target busy if we've received a non-zero retry_delay_timer
926 * in a FCP_RSP.
927 */
928 if (fcport->retry_delay_timestamp == 0) {
929 /* retry delay not set */
930 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
931 fcport->retry_delay_timestamp = 0;
932 else
933 goto qc24_target_busy;
934
935 sp = scsi_cmd_priv(cmd);
936 /* ref: INIT */
937 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
938
939 sp->u.scmd.cmd = cmd;
940 sp->type = SRB_SCSI_CMD;
941 sp->free = qla2x00_sp_free_dma;
942 sp->done = qla2x00_sp_compl;
943
944 rval = ha->isp_ops->start_scsi(sp);
945 if (rval != QLA_SUCCESS) {
946 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
947 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
948 goto qc24_host_busy_free_sp;
949 }
950
951 return 0;
952
953 qc24_host_busy_free_sp:
954 /* ref: INIT */
955 kref_put(&sp->cmd_kref, qla2x00_sp_release);
956
957 qc24_target_busy:
958 return SCSI_MLQUEUE_TARGET_BUSY;
959
960 qc24_fail_command:
961 scsi_done(cmd);
962
963 return 0;
964 }
965
966 /* For MQ supported I/O */
967 int
qla2xxx_mqueuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd,struct qla_qpair * qpair)968 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
969 struct qla_qpair *qpair)
970 {
971 scsi_qla_host_t *vha = shost_priv(host);
972 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
973 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
974 struct qla_hw_data *ha = vha->hw;
975 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
976 srb_t *sp;
977 int rval;
978
979 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16);
980 if (rval) {
981 cmd->result = rval;
982 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
983 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
984 cmd, rval);
985 goto qc24_fail_command;
986 }
987
988 if (!qpair->online) {
989 ql_dbg(ql_dbg_io, vha, 0x3077,
990 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy);
991 cmd->result = DID_NO_CONNECT << 16;
992 goto qc24_fail_command;
993 }
994
995 if (!fcport || fcport->deleted) {
996 cmd->result = DID_IMM_RETRY << 16;
997 goto qc24_fail_command;
998 }
999
1000 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
1001 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
1002 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
1003 ql_dbg(ql_dbg_io, vha, 0x3077,
1004 "Returning DNC, fcport_state=%d loop_state=%d.\n",
1005 atomic_read(&fcport->state),
1006 atomic_read(&base_vha->loop_state));
1007 cmd->result = DID_NO_CONNECT << 16;
1008 goto qc24_fail_command;
1009 }
1010 goto qc24_target_busy;
1011 }
1012
1013 /*
1014 * Return target busy if we've received a non-zero retry_delay_timer
1015 * in a FCP_RSP.
1016 */
1017 if (fcport->retry_delay_timestamp == 0) {
1018 /* retry delay not set */
1019 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1020 fcport->retry_delay_timestamp = 0;
1021 else
1022 goto qc24_target_busy;
1023
1024 sp = scsi_cmd_priv(cmd);
1025 /* ref: INIT */
1026 qla2xxx_init_sp(sp, vha, qpair, fcport);
1027
1028 sp->u.scmd.cmd = cmd;
1029 sp->type = SRB_SCSI_CMD;
1030 sp->free = qla2xxx_qpair_sp_free_dma;
1031 sp->done = qla2xxx_qpair_sp_compl;
1032
1033 rval = ha->isp_ops->start_scsi_mq(sp);
1034 if (rval != QLA_SUCCESS) {
1035 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1036 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1037 goto qc24_host_busy_free_sp;
1038 }
1039
1040 return 0;
1041
1042 qc24_host_busy_free_sp:
1043 /* ref: INIT */
1044 kref_put(&sp->cmd_kref, qla2x00_sp_release);
1045
1046 qc24_target_busy:
1047 return SCSI_MLQUEUE_TARGET_BUSY;
1048
1049 qc24_fail_command:
1050 scsi_done(cmd);
1051
1052 return 0;
1053 }
1054
1055 /*
1056 * qla2x00_eh_wait_on_command
1057 * Waits for the command to be returned by the Firmware for some
1058 * max time.
1059 *
1060 * Input:
1061 * cmd = Scsi Command to wait on.
1062 *
1063 * Return:
1064 * Completed in time : QLA_SUCCESS
1065 * Did not complete in time : QLA_FUNCTION_FAILED
1066 */
1067 static int
qla2x00_eh_wait_on_command(struct scsi_cmnd * cmd)1068 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1069 {
1070 #define ABORT_POLLING_PERIOD 1000
1071 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
1072 unsigned long wait_iter = ABORT_WAIT_ITER;
1073 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1074 struct qla_hw_data *ha = vha->hw;
1075 srb_t *sp = scsi_cmd_priv(cmd);
1076 int ret = QLA_SUCCESS;
1077
1078 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
1079 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1080 "Return:eh_wait.\n");
1081 return ret;
1082 }
1083
1084 while (sp->type && wait_iter--)
1085 msleep(ABORT_POLLING_PERIOD);
1086 if (sp->type)
1087 ret = QLA_FUNCTION_FAILED;
1088
1089 return ret;
1090 }
1091
1092 /*
1093 * qla2x00_wait_for_hba_online
1094 * Wait till the HBA is online after going through
1095 * <= MAX_RETRIES_OF_ISP_ABORT or
1096 * finally HBA is disabled ie marked offline
1097 *
1098 * Input:
1099 * ha - pointer to host adapter structure
1100 *
1101 * Note:
1102 * Does context switching-Release SPIN_LOCK
1103 * (if any) before calling this routine.
1104 *
1105 * Return:
1106 * Success (Adapter is online) : 0
1107 * Failed (Adapter is offline/disabled) : 1
1108 */
1109 int
qla2x00_wait_for_hba_online(scsi_qla_host_t * vha)1110 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1111 {
1112 int return_status;
1113 unsigned long wait_online;
1114 struct qla_hw_data *ha = vha->hw;
1115 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1116
1117 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1118 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1119 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1120 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1121 ha->dpc_active) && time_before(jiffies, wait_online)) {
1122
1123 msleep(1000);
1124 }
1125 if (base_vha->flags.online)
1126 return_status = QLA_SUCCESS;
1127 else
1128 return_status = QLA_FUNCTION_FAILED;
1129
1130 return (return_status);
1131 }
1132
test_fcport_count(scsi_qla_host_t * vha)1133 static inline int test_fcport_count(scsi_qla_host_t *vha)
1134 {
1135 struct qla_hw_data *ha = vha->hw;
1136 unsigned long flags;
1137 int res;
1138 /* Return 0 = sleep, x=wake */
1139
1140 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1141 ql_dbg(ql_dbg_init, vha, 0x00ec,
1142 "tgt %p, fcport_count=%d\n",
1143 vha, vha->fcport_count);
1144 res = (vha->fcport_count == 0);
1145 if (res) {
1146 struct fc_port *fcport;
1147
1148 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1149 if (fcport->deleted != QLA_SESS_DELETED) {
1150 /* session(s) may not be fully logged in
1151 * (ie fcport_count=0), but session
1152 * deletion thread(s) may be inflight.
1153 */
1154
1155 res = 0;
1156 break;
1157 }
1158 }
1159 }
1160 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1161
1162 return res;
1163 }
1164
1165 /*
1166 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1167 * it has dependency on UNLOADING flag to stop device discovery
1168 */
1169 void
qla2x00_wait_for_sess_deletion(scsi_qla_host_t * vha)1170 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1171 {
1172 u8 i;
1173
1174 qla2x00_mark_all_devices_lost(vha);
1175
1176 for (i = 0; i < 10; i++) {
1177 if (wait_event_timeout(vha->fcport_waitQ,
1178 test_fcport_count(vha), HZ) > 0)
1179 break;
1180 }
1181
1182 flush_workqueue(vha->hw->wq);
1183 }
1184
1185 /*
1186 * qla2x00_wait_for_hba_ready
1187 * Wait till the HBA is ready before doing driver unload
1188 *
1189 * Input:
1190 * ha - pointer to host adapter structure
1191 *
1192 * Note:
1193 * Does context switching-Release SPIN_LOCK
1194 * (if any) before calling this routine.
1195 *
1196 */
1197 static void
qla2x00_wait_for_hba_ready(scsi_qla_host_t * vha)1198 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1199 {
1200 struct qla_hw_data *ha = vha->hw;
1201 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1202
1203 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1204 ha->flags.mbox_busy) ||
1205 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1206 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1207 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1208 break;
1209 msleep(1000);
1210 }
1211 }
1212
1213 int
qla2x00_wait_for_chip_reset(scsi_qla_host_t * vha)1214 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1215 {
1216 int return_status;
1217 unsigned long wait_reset;
1218 struct qla_hw_data *ha = vha->hw;
1219 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1220
1221 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1222 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1223 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1224 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1225 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1226
1227 msleep(1000);
1228
1229 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1230 ha->flags.chip_reset_done)
1231 break;
1232 }
1233 if (ha->flags.chip_reset_done)
1234 return_status = QLA_SUCCESS;
1235 else
1236 return_status = QLA_FUNCTION_FAILED;
1237
1238 return return_status;
1239 }
1240
1241 /**************************************************************************
1242 * qla2xxx_eh_abort
1243 *
1244 * Description:
1245 * The abort function will abort the specified command.
1246 *
1247 * Input:
1248 * cmd = Linux SCSI command packet to be aborted.
1249 *
1250 * Returns:
1251 * Either SUCCESS or FAILED.
1252 *
1253 * Note:
1254 * Only return FAILED if command not returned by firmware.
1255 **************************************************************************/
1256 static int
qla2xxx_eh_abort(struct scsi_cmnd * cmd)1257 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1258 {
1259 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1260 DECLARE_COMPLETION_ONSTACK(comp);
1261 srb_t *sp;
1262 int ret;
1263 unsigned int id;
1264 uint64_t lun;
1265 int rval;
1266 struct qla_hw_data *ha = vha->hw;
1267 uint32_t ratov_j;
1268 struct qla_qpair *qpair;
1269 unsigned long flags;
1270 int fast_fail_status = SUCCESS;
1271
1272 if (qla2x00_isp_reg_stat(ha)) {
1273 ql_log(ql_log_info, vha, 0x8042,
1274 "PCI/Register disconnect, exiting.\n");
1275 qla_pci_set_eeh_busy(vha);
1276 return FAILED;
1277 }
1278
1279 /* Save any FAST_IO_FAIL value to return later if abort succeeds */
1280 ret = fc_block_scsi_eh(cmd);
1281 if (ret != 0)
1282 fast_fail_status = ret;
1283
1284 sp = scsi_cmd_priv(cmd);
1285 qpair = sp->qpair;
1286
1287 vha->cmd_timeout_cnt++;
1288
1289 if ((sp->fcport && sp->fcport->deleted) || !qpair)
1290 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED;
1291
1292 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1293 sp->comp = ∁
1294 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1295
1296
1297 id = cmd->device->id;
1298 lun = cmd->device->lun;
1299
1300 ql_dbg(ql_dbg_taskm, vha, 0x8002,
1301 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1302 vha->host_no, id, lun, sp, cmd, sp->handle);
1303
1304 /*
1305 * Abort will release the original Command/sp from FW. Let the
1306 * original command call scsi_done. In return, he will wakeup
1307 * this sleeping thread.
1308 */
1309 rval = ha->isp_ops->abort_command(sp);
1310
1311 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1312 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1313
1314 /* Wait for the command completion. */
1315 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1316 ratov_j = msecs_to_jiffies(ratov_j);
1317 switch (rval) {
1318 case QLA_SUCCESS:
1319 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1320 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1321 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1322 __func__, ha->r_a_tov/10);
1323 ret = FAILED;
1324 } else {
1325 ret = fast_fail_status;
1326 }
1327 break;
1328 default:
1329 ret = FAILED;
1330 break;
1331 }
1332
1333 sp->comp = NULL;
1334
1335 ql_log(ql_log_info, vha, 0x801c,
1336 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1337 vha->host_no, id, lun, ret);
1338
1339 return ret;
1340 }
1341
1342 /*
1343 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1344 */
1345 static int
__qla2x00_eh_wait_for_pending_commands(struct qla_qpair * qpair,unsigned int t,uint64_t l,enum nexus_wait_type type)1346 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t,
1347 uint64_t l, enum nexus_wait_type type)
1348 {
1349 int cnt, match, status;
1350 unsigned long flags;
1351 scsi_qla_host_t *vha = qpair->vha;
1352 struct req_que *req = qpair->req;
1353 srb_t *sp;
1354 struct scsi_cmnd *cmd;
1355
1356 status = QLA_SUCCESS;
1357
1358 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1359 for (cnt = 1; status == QLA_SUCCESS &&
1360 cnt < req->num_outstanding_cmds; cnt++) {
1361 sp = req->outstanding_cmds[cnt];
1362 if (!sp)
1363 continue;
1364 if (sp->type != SRB_SCSI_CMD)
1365 continue;
1366 if (vha->vp_idx != sp->vha->vp_idx)
1367 continue;
1368 match = 0;
1369 cmd = GET_CMD_SP(sp);
1370 switch (type) {
1371 case WAIT_HOST:
1372 match = 1;
1373 break;
1374 case WAIT_TARGET:
1375 match = cmd->device->id == t;
1376 break;
1377 case WAIT_LUN:
1378 match = (cmd->device->id == t &&
1379 cmd->device->lun == l);
1380 break;
1381 }
1382 if (!match)
1383 continue;
1384
1385 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1386 status = qla2x00_eh_wait_on_command(cmd);
1387 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1388 }
1389 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1390
1391 return status;
1392 }
1393
1394 int
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t * vha,unsigned int t,uint64_t l,enum nexus_wait_type type)1395 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1396 uint64_t l, enum nexus_wait_type type)
1397 {
1398 struct qla_qpair *qpair;
1399 struct qla_hw_data *ha = vha->hw;
1400 int i, status = QLA_SUCCESS;
1401
1402 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l,
1403 type);
1404 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) {
1405 qpair = ha->queue_pair_map[i];
1406 if (!qpair)
1407 continue;
1408 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l,
1409 type);
1410 }
1411 return status;
1412 }
1413
1414 static char *reset_errors[] = {
1415 "HBA not online",
1416 "HBA not ready",
1417 "Task management failed",
1418 "Waiting for command completions",
1419 };
1420
1421 static int
qla2xxx_eh_device_reset(struct scsi_cmnd * cmd)1422 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1423 {
1424 struct scsi_device *sdev = cmd->device;
1425 scsi_qla_host_t *vha = shost_priv(sdev->host);
1426 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1427 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1428 struct qla_hw_data *ha = vha->hw;
1429 int err;
1430
1431 if (qla2x00_isp_reg_stat(ha)) {
1432 ql_log(ql_log_info, vha, 0x803e,
1433 "PCI/Register disconnect, exiting.\n");
1434 qla_pci_set_eeh_busy(vha);
1435 return FAILED;
1436 }
1437
1438 if (!fcport) {
1439 return FAILED;
1440 }
1441
1442 err = fc_block_rport(rport);
1443 if (err != 0)
1444 return err;
1445
1446 if (fcport->deleted)
1447 return FAILED;
1448
1449 ql_log(ql_log_info, vha, 0x8009,
1450 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no,
1451 sdev->id, sdev->lun, cmd);
1452
1453 err = 0;
1454 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1455 ql_log(ql_log_warn, vha, 0x800a,
1456 "Wait for hba online failed for cmd=%p.\n", cmd);
1457 goto eh_reset_failed;
1458 }
1459 err = 2;
1460 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1)
1461 != QLA_SUCCESS) {
1462 ql_log(ql_log_warn, vha, 0x800c,
1463 "do_reset failed for cmd=%p.\n", cmd);
1464 goto eh_reset_failed;
1465 }
1466 err = 3;
1467 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id,
1468 sdev->lun, WAIT_LUN) != QLA_SUCCESS) {
1469 ql_log(ql_log_warn, vha, 0x800d,
1470 "wait for pending cmds failed for cmd=%p.\n", cmd);
1471 goto eh_reset_failed;
1472 }
1473
1474 ql_log(ql_log_info, vha, 0x800e,
1475 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n",
1476 vha->host_no, sdev->id, sdev->lun, cmd);
1477
1478 return SUCCESS;
1479
1480 eh_reset_failed:
1481 ql_log(ql_log_info, vha, 0x800f,
1482 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1483 reset_errors[err], vha->host_no, sdev->id, sdev->lun,
1484 cmd);
1485 vha->reset_cmd_err_cnt++;
1486 return FAILED;
1487 }
1488
1489 static int
qla2xxx_eh_target_reset(struct scsi_cmnd * cmd)1490 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1491 {
1492 struct scsi_device *sdev = cmd->device;
1493 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1494 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport));
1495 struct qla_hw_data *ha = vha->hw;
1496 fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
1497 int err;
1498
1499 if (qla2x00_isp_reg_stat(ha)) {
1500 ql_log(ql_log_info, vha, 0x803f,
1501 "PCI/Register disconnect, exiting.\n");
1502 qla_pci_set_eeh_busy(vha);
1503 return FAILED;
1504 }
1505
1506 if (!fcport) {
1507 return FAILED;
1508 }
1509
1510 err = fc_block_rport(rport);
1511 if (err != 0)
1512 return err;
1513
1514 if (fcport->deleted)
1515 return FAILED;
1516
1517 ql_log(ql_log_info, vha, 0x8009,
1518 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no,
1519 sdev->id, cmd);
1520
1521 err = 0;
1522 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1523 ql_log(ql_log_warn, vha, 0x800a,
1524 "Wait for hba online failed for cmd=%p.\n", cmd);
1525 goto eh_reset_failed;
1526 }
1527 err = 2;
1528 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) {
1529 ql_log(ql_log_warn, vha, 0x800c,
1530 "target_reset failed for cmd=%p.\n", cmd);
1531 goto eh_reset_failed;
1532 }
1533 err = 3;
1534 if (qla2x00_eh_wait_for_pending_commands(vha, sdev->id,
1535 0, WAIT_TARGET) != QLA_SUCCESS) {
1536 ql_log(ql_log_warn, vha, 0x800d,
1537 "wait for pending cmds failed for cmd=%p.\n", cmd);
1538 goto eh_reset_failed;
1539 }
1540
1541 ql_log(ql_log_info, vha, 0x800e,
1542 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n",
1543 vha->host_no, sdev->id, cmd);
1544
1545 return SUCCESS;
1546
1547 eh_reset_failed:
1548 ql_log(ql_log_info, vha, 0x800f,
1549 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1550 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1551 cmd);
1552 vha->reset_cmd_err_cnt++;
1553 return FAILED;
1554 }
1555
1556 /**************************************************************************
1557 * qla2xxx_eh_bus_reset
1558 *
1559 * Description:
1560 * The bus reset function will reset the bus and abort any executing
1561 * commands.
1562 *
1563 * Input:
1564 * cmd = Linux SCSI command packet of the command that cause the
1565 * bus reset.
1566 *
1567 * Returns:
1568 * SUCCESS/FAILURE (defined as macro in scsi.h).
1569 *
1570 **************************************************************************/
1571 static int
qla2xxx_eh_bus_reset(struct scsi_cmnd * cmd)1572 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1573 {
1574 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1575 int ret = FAILED;
1576 unsigned int id;
1577 uint64_t lun;
1578 struct qla_hw_data *ha = vha->hw;
1579
1580 if (qla2x00_isp_reg_stat(ha)) {
1581 ql_log(ql_log_info, vha, 0x8040,
1582 "PCI/Register disconnect, exiting.\n");
1583 qla_pci_set_eeh_busy(vha);
1584 return FAILED;
1585 }
1586
1587 id = cmd->device->id;
1588 lun = cmd->device->lun;
1589
1590 if (qla2x00_chip_is_down(vha))
1591 return ret;
1592
1593 ql_log(ql_log_info, vha, 0x8012,
1594 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1595
1596 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1597 ql_log(ql_log_fatal, vha, 0x8013,
1598 "Wait for hba online failed board disabled.\n");
1599 goto eh_bus_reset_done;
1600 }
1601
1602 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1603 ret = SUCCESS;
1604
1605 if (ret == FAILED)
1606 goto eh_bus_reset_done;
1607
1608 /* Flush outstanding commands. */
1609 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1610 QLA_SUCCESS) {
1611 ql_log(ql_log_warn, vha, 0x8014,
1612 "Wait for pending commands failed.\n");
1613 ret = FAILED;
1614 }
1615
1616 eh_bus_reset_done:
1617 ql_log(ql_log_warn, vha, 0x802b,
1618 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1619 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1620
1621 return ret;
1622 }
1623
1624 /**************************************************************************
1625 * qla2xxx_eh_host_reset
1626 *
1627 * Description:
1628 * The reset function will reset the Adapter.
1629 *
1630 * Input:
1631 * cmd = Linux SCSI command packet of the command that cause the
1632 * adapter reset.
1633 *
1634 * Returns:
1635 * Either SUCCESS or FAILED.
1636 *
1637 * Note:
1638 **************************************************************************/
1639 static int
qla2xxx_eh_host_reset(struct scsi_cmnd * cmd)1640 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1641 {
1642 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1643 struct qla_hw_data *ha = vha->hw;
1644 int ret = FAILED;
1645 unsigned int id;
1646 uint64_t lun;
1647 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1648
1649 if (qla2x00_isp_reg_stat(ha)) {
1650 ql_log(ql_log_info, vha, 0x8041,
1651 "PCI/Register disconnect, exiting.\n");
1652 qla_pci_set_eeh_busy(vha);
1653 return SUCCESS;
1654 }
1655
1656 id = cmd->device->id;
1657 lun = cmd->device->lun;
1658
1659 ql_log(ql_log_info, vha, 0x8018,
1660 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1661
1662 /*
1663 * No point in issuing another reset if one is active. Also do not
1664 * attempt a reset if we are updating flash.
1665 */
1666 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1667 goto eh_host_reset_lock;
1668
1669 if (vha != base_vha) {
1670 if (qla2x00_vp_abort_isp(vha))
1671 goto eh_host_reset_lock;
1672 } else {
1673 if (IS_P3P_TYPE(vha->hw)) {
1674 if (!qla82xx_fcoe_ctx_reset(vha)) {
1675 /* Ctx reset success */
1676 ret = SUCCESS;
1677 goto eh_host_reset_lock;
1678 }
1679 /* fall thru if ctx reset failed */
1680 }
1681 if (ha->wq)
1682 flush_workqueue(ha->wq);
1683
1684 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1685 if (ha->isp_ops->abort_isp(base_vha)) {
1686 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1687 /* failed. schedule dpc to try */
1688 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1689
1690 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1691 ql_log(ql_log_warn, vha, 0x802a,
1692 "wait for hba online failed.\n");
1693 goto eh_host_reset_lock;
1694 }
1695 }
1696 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1697 }
1698
1699 /* Waiting for command to be returned to OS.*/
1700 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1701 QLA_SUCCESS)
1702 ret = SUCCESS;
1703
1704 eh_host_reset_lock:
1705 ql_log(ql_log_info, vha, 0x8017,
1706 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1707 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1708
1709 return ret;
1710 }
1711
1712 /*
1713 * qla2x00_loop_reset
1714 * Issue loop reset.
1715 *
1716 * Input:
1717 * ha = adapter block pointer.
1718 *
1719 * Returns:
1720 * 0 = success
1721 */
1722 int
qla2x00_loop_reset(scsi_qla_host_t * vha)1723 qla2x00_loop_reset(scsi_qla_host_t *vha)
1724 {
1725 int ret;
1726 struct qla_hw_data *ha = vha->hw;
1727
1728 if (IS_QLAFX00(ha))
1729 return QLA_SUCCESS;
1730
1731 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1732 atomic_set(&vha->loop_state, LOOP_DOWN);
1733 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1734 qla2x00_mark_all_devices_lost(vha);
1735 ret = qla2x00_full_login_lip(vha);
1736 if (ret != QLA_SUCCESS) {
1737 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1738 "full_login_lip=%d.\n", ret);
1739 }
1740 }
1741
1742 if (ha->flags.enable_lip_reset) {
1743 ret = qla2x00_lip_reset(vha);
1744 if (ret != QLA_SUCCESS)
1745 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1746 "lip_reset failed (%d).\n", ret);
1747 }
1748
1749 /* Issue marker command only when we are going to start the I/O */
1750 vha->marker_needed = 1;
1751
1752 return QLA_SUCCESS;
1753 }
1754
1755 /*
1756 * The caller must ensure that no completion interrupts will happen
1757 * while this function is in progress.
1758 */
qla2x00_abort_srb(struct qla_qpair * qp,srb_t * sp,const int res,unsigned long * flags)1759 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1760 unsigned long *flags)
1761 __releases(qp->qp_lock_ptr)
1762 __acquires(qp->qp_lock_ptr)
1763 {
1764 DECLARE_COMPLETION_ONSTACK(comp);
1765 scsi_qla_host_t *vha = qp->vha;
1766 struct qla_hw_data *ha = vha->hw;
1767 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1768 int rval;
1769 bool ret_cmd;
1770 uint32_t ratov_j;
1771
1772 lockdep_assert_held(qp->qp_lock_ptr);
1773
1774 if (qla2x00_chip_is_down(vha)) {
1775 sp->done(sp, res);
1776 return;
1777 }
1778
1779 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1780 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1781 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1782 !qla2x00_isp_reg_stat(ha))) {
1783 if (sp->comp) {
1784 sp->done(sp, res);
1785 return;
1786 }
1787
1788 sp->comp = ∁
1789 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1790
1791 rval = ha->isp_ops->abort_command(sp);
1792 /* Wait for command completion. */
1793 ret_cmd = false;
1794 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1795 ratov_j = msecs_to_jiffies(ratov_j);
1796 switch (rval) {
1797 case QLA_SUCCESS:
1798 if (wait_for_completion_timeout(&comp, ratov_j)) {
1799 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1800 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1801 __func__, ha->r_a_tov/10);
1802 ret_cmd = true;
1803 }
1804 /* else FW return SP to driver */
1805 break;
1806 default:
1807 ret_cmd = true;
1808 break;
1809 }
1810
1811 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1812 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd)))
1813 sp->done(sp, res);
1814 } else {
1815 sp->done(sp, res);
1816 }
1817 }
1818
1819 /*
1820 * The caller must ensure that no completion interrupts will happen
1821 * while this function is in progress.
1822 */
1823 static void
__qla2x00_abort_all_cmds(struct qla_qpair * qp,int res)1824 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1825 {
1826 int cnt;
1827 unsigned long flags;
1828 srb_t *sp;
1829 scsi_qla_host_t *vha = qp->vha;
1830 struct qla_hw_data *ha = vha->hw;
1831 struct req_que *req;
1832 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1833 struct qla_tgt_cmd *cmd;
1834
1835 if (!ha->req_q_map)
1836 return;
1837 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1838 req = qp->req;
1839 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1840 sp = req->outstanding_cmds[cnt];
1841 if (sp) {
1842 switch (sp->cmd_type) {
1843 case TYPE_SRB:
1844 qla2x00_abort_srb(qp, sp, res, &flags);
1845 break;
1846 case TYPE_TGT_CMD:
1847 if (!vha->hw->tgt.tgt_ops || !tgt ||
1848 qla_ini_mode_enabled(vha)) {
1849 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1850 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1851 vha->dpc_flags);
1852 continue;
1853 }
1854 cmd = (struct qla_tgt_cmd *)sp;
1855 cmd->aborted = 1;
1856 break;
1857 case TYPE_TGT_TMCMD:
1858 /* Skip task management functions. */
1859 break;
1860 default:
1861 break;
1862 }
1863 req->outstanding_cmds[cnt] = NULL;
1864 }
1865 }
1866 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1867 }
1868
1869 /*
1870 * The caller must ensure that no completion interrupts will happen
1871 * while this function is in progress.
1872 */
1873 void
qla2x00_abort_all_cmds(scsi_qla_host_t * vha,int res)1874 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1875 {
1876 int que;
1877 struct qla_hw_data *ha = vha->hw;
1878
1879 /* Continue only if initialization complete. */
1880 if (!ha->base_qpair)
1881 return;
1882 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1883
1884 if (!ha->queue_pair_map)
1885 return;
1886 for (que = 0; que < ha->max_qpairs; que++) {
1887 if (!ha->queue_pair_map[que])
1888 continue;
1889
1890 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1891 }
1892 }
1893
1894 static int
qla2xxx_slave_alloc(struct scsi_device * sdev)1895 qla2xxx_slave_alloc(struct scsi_device *sdev)
1896 {
1897 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1898
1899 if (!rport || fc_remote_port_chkready(rport))
1900 return -ENXIO;
1901
1902 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1903
1904 return 0;
1905 }
1906
1907 static int
qla2xxx_slave_configure(struct scsi_device * sdev)1908 qla2xxx_slave_configure(struct scsi_device *sdev)
1909 {
1910 scsi_qla_host_t *vha = shost_priv(sdev->host);
1911 struct req_que *req = vha->req;
1912
1913 if (IS_T10_PI_CAPABLE(vha->hw))
1914 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1915
1916 scsi_change_queue_depth(sdev, req->max_q_depth);
1917 return 0;
1918 }
1919
1920 static void
qla2xxx_slave_destroy(struct scsi_device * sdev)1921 qla2xxx_slave_destroy(struct scsi_device *sdev)
1922 {
1923 sdev->hostdata = NULL;
1924 }
1925
1926 /**
1927 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1928 * @ha: HA context
1929 *
1930 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1931 * supported addressing method.
1932 */
1933 static void
qla2x00_config_dma_addressing(struct qla_hw_data * ha)1934 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1935 {
1936 /* Assume a 32bit DMA mask. */
1937 ha->flags.enable_64bit_addressing = 0;
1938
1939 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1940 /* Any upper-dword bits set? */
1941 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1942 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1943 /* Ok, a 64bit DMA mask is applicable. */
1944 ha->flags.enable_64bit_addressing = 1;
1945 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1946 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1947 return;
1948 }
1949 }
1950
1951 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1952 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1953 }
1954
1955 static void
qla2x00_enable_intrs(struct qla_hw_data * ha)1956 qla2x00_enable_intrs(struct qla_hw_data *ha)
1957 {
1958 unsigned long flags = 0;
1959 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1960
1961 spin_lock_irqsave(&ha->hardware_lock, flags);
1962 ha->interrupts_on = 1;
1963 /* enable risc and host interrupts */
1964 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
1965 rd_reg_word(®->ictrl);
1966 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1967
1968 }
1969
1970 static void
qla2x00_disable_intrs(struct qla_hw_data * ha)1971 qla2x00_disable_intrs(struct qla_hw_data *ha)
1972 {
1973 unsigned long flags = 0;
1974 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1975
1976 spin_lock_irqsave(&ha->hardware_lock, flags);
1977 ha->interrupts_on = 0;
1978 /* disable risc and host interrupts */
1979 wrt_reg_word(®->ictrl, 0);
1980 rd_reg_word(®->ictrl);
1981 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1982 }
1983
1984 static void
qla24xx_enable_intrs(struct qla_hw_data * ha)1985 qla24xx_enable_intrs(struct qla_hw_data *ha)
1986 {
1987 unsigned long flags = 0;
1988 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1989
1990 spin_lock_irqsave(&ha->hardware_lock, flags);
1991 ha->interrupts_on = 1;
1992 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT);
1993 rd_reg_dword(®->ictrl);
1994 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1995 }
1996
1997 static void
qla24xx_disable_intrs(struct qla_hw_data * ha)1998 qla24xx_disable_intrs(struct qla_hw_data *ha)
1999 {
2000 unsigned long flags = 0;
2001 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2002
2003 if (IS_NOPOLLING_TYPE(ha))
2004 return;
2005 spin_lock_irqsave(&ha->hardware_lock, flags);
2006 ha->interrupts_on = 0;
2007 wrt_reg_dword(®->ictrl, 0);
2008 rd_reg_dword(®->ictrl);
2009 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2010 }
2011
2012 static int
qla2x00_iospace_config(struct qla_hw_data * ha)2013 qla2x00_iospace_config(struct qla_hw_data *ha)
2014 {
2015 resource_size_t pio;
2016 uint16_t msix;
2017
2018 if (pci_request_selected_regions(ha->pdev, ha->bars,
2019 QLA2XXX_DRIVER_NAME)) {
2020 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
2021 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2022 pci_name(ha->pdev));
2023 goto iospace_error_exit;
2024 }
2025 if (!(ha->bars & 1))
2026 goto skip_pio;
2027
2028 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
2029 pio = pci_resource_start(ha->pdev, 0);
2030 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
2031 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2032 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
2033 "Invalid pci I/O region size (%s).\n",
2034 pci_name(ha->pdev));
2035 pio = 0;
2036 }
2037 } else {
2038 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
2039 "Region #0 no a PIO resource (%s).\n",
2040 pci_name(ha->pdev));
2041 pio = 0;
2042 }
2043 ha->pio_address = pio;
2044 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2045 "PIO address=%llu.\n",
2046 (unsigned long long)ha->pio_address);
2047
2048 skip_pio:
2049 /* Use MMIO operations for all accesses. */
2050 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2051 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2052 "Region #1 not an MMIO resource (%s), aborting.\n",
2053 pci_name(ha->pdev));
2054 goto iospace_error_exit;
2055 }
2056 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2057 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2058 "Invalid PCI mem region size (%s), aborting.\n",
2059 pci_name(ha->pdev));
2060 goto iospace_error_exit;
2061 }
2062
2063 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2064 if (!ha->iobase) {
2065 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2066 "Cannot remap MMIO (%s), aborting.\n",
2067 pci_name(ha->pdev));
2068 goto iospace_error_exit;
2069 }
2070
2071 /* Determine queue resources */
2072 ha->max_req_queues = ha->max_rsp_queues = 1;
2073 ha->msix_count = QLA_BASE_VECTORS;
2074
2075 /* Check if FW supports MQ or not */
2076 if (!(ha->fw_attributes & BIT_6))
2077 goto mqiobase_exit;
2078
2079 if (!ql2xmqsupport || !ql2xnvmeenable ||
2080 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2081 goto mqiobase_exit;
2082
2083 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2084 pci_resource_len(ha->pdev, 3));
2085 if (ha->mqiobase) {
2086 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2087 "MQIO Base=%p.\n", ha->mqiobase);
2088 /* Read MSIX vector size of the board */
2089 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2090 ha->msix_count = msix + 1;
2091 /* Max queues are bounded by available msix vectors */
2092 /* MB interrupt uses 1 vector */
2093 ha->max_req_queues = ha->msix_count - 1;
2094 ha->max_rsp_queues = ha->max_req_queues;
2095 /* Queue pairs is the max value minus the base queue pair */
2096 ha->max_qpairs = ha->max_rsp_queues - 1;
2097 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2098 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2099
2100 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2101 "MSI-X vector count: %d.\n", ha->msix_count);
2102 } else
2103 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2104 "BAR 3 not enabled.\n");
2105
2106 mqiobase_exit:
2107 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2108 "MSIX Count: %d.\n", ha->msix_count);
2109 return (0);
2110
2111 iospace_error_exit:
2112 return (-ENOMEM);
2113 }
2114
2115
2116 static int
qla83xx_iospace_config(struct qla_hw_data * ha)2117 qla83xx_iospace_config(struct qla_hw_data *ha)
2118 {
2119 uint16_t msix;
2120
2121 if (pci_request_selected_regions(ha->pdev, ha->bars,
2122 QLA2XXX_DRIVER_NAME)) {
2123 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2124 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2125 pci_name(ha->pdev));
2126
2127 goto iospace_error_exit;
2128 }
2129
2130 /* Use MMIO operations for all accesses. */
2131 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2132 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2133 "Invalid pci I/O region size (%s).\n",
2134 pci_name(ha->pdev));
2135 goto iospace_error_exit;
2136 }
2137 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2138 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2139 "Invalid PCI mem region size (%s), aborting\n",
2140 pci_name(ha->pdev));
2141 goto iospace_error_exit;
2142 }
2143
2144 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2145 if (!ha->iobase) {
2146 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2147 "Cannot remap MMIO (%s), aborting.\n",
2148 pci_name(ha->pdev));
2149 goto iospace_error_exit;
2150 }
2151
2152 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2153 /* 83XX 26XX always use MQ type access for queues
2154 * - mbar 2, a.k.a region 4 */
2155 ha->max_req_queues = ha->max_rsp_queues = 1;
2156 ha->msix_count = QLA_BASE_VECTORS;
2157 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2158 pci_resource_len(ha->pdev, 4));
2159
2160 if (!ha->mqiobase) {
2161 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2162 "BAR2/region4 not enabled\n");
2163 goto mqiobase_exit;
2164 }
2165
2166 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2167 pci_resource_len(ha->pdev, 2));
2168 if (ha->msixbase) {
2169 /* Read MSIX vector size of the board */
2170 pci_read_config_word(ha->pdev,
2171 QLA_83XX_PCI_MSIX_CONTROL, &msix);
2172 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
2173 /*
2174 * By default, driver uses at least two msix vectors
2175 * (default & rspq)
2176 */
2177 if (ql2xmqsupport || ql2xnvmeenable) {
2178 /* MB interrupt uses 1 vector */
2179 ha->max_req_queues = ha->msix_count - 1;
2180
2181 /* ATIOQ needs 1 vector. That's 1 less QPair */
2182 if (QLA_TGT_MODE_ENABLED())
2183 ha->max_req_queues--;
2184
2185 ha->max_rsp_queues = ha->max_req_queues;
2186
2187 /* Queue pairs is the max value minus
2188 * the base queue pair */
2189 ha->max_qpairs = ha->max_req_queues - 1;
2190 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2191 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2192 }
2193 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2194 "MSI-X vector count: %d.\n", ha->msix_count);
2195 } else
2196 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2197 "BAR 1 not enabled.\n");
2198
2199 mqiobase_exit:
2200 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2201 "MSIX Count: %d.\n", ha->msix_count);
2202 return 0;
2203
2204 iospace_error_exit:
2205 return -ENOMEM;
2206 }
2207
2208 static struct isp_operations qla2100_isp_ops = {
2209 .pci_config = qla2100_pci_config,
2210 .reset_chip = qla2x00_reset_chip,
2211 .chip_diag = qla2x00_chip_diag,
2212 .config_rings = qla2x00_config_rings,
2213 .reset_adapter = qla2x00_reset_adapter,
2214 .nvram_config = qla2x00_nvram_config,
2215 .update_fw_options = qla2x00_update_fw_options,
2216 .load_risc = qla2x00_load_risc,
2217 .pci_info_str = qla2x00_pci_info_str,
2218 .fw_version_str = qla2x00_fw_version_str,
2219 .intr_handler = qla2100_intr_handler,
2220 .enable_intrs = qla2x00_enable_intrs,
2221 .disable_intrs = qla2x00_disable_intrs,
2222 .abort_command = qla2x00_abort_command,
2223 .target_reset = qla2x00_abort_target,
2224 .lun_reset = qla2x00_lun_reset,
2225 .fabric_login = qla2x00_login_fabric,
2226 .fabric_logout = qla2x00_fabric_logout,
2227 .calc_req_entries = qla2x00_calc_iocbs_32,
2228 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2229 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2230 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2231 .read_nvram = qla2x00_read_nvram_data,
2232 .write_nvram = qla2x00_write_nvram_data,
2233 .fw_dump = qla2100_fw_dump,
2234 .beacon_on = NULL,
2235 .beacon_off = NULL,
2236 .beacon_blink = NULL,
2237 .read_optrom = qla2x00_read_optrom_data,
2238 .write_optrom = qla2x00_write_optrom_data,
2239 .get_flash_version = qla2x00_get_flash_version,
2240 .start_scsi = qla2x00_start_scsi,
2241 .start_scsi_mq = NULL,
2242 .abort_isp = qla2x00_abort_isp,
2243 .iospace_config = qla2x00_iospace_config,
2244 .initialize_adapter = qla2x00_initialize_adapter,
2245 };
2246
2247 static struct isp_operations qla2300_isp_ops = {
2248 .pci_config = qla2300_pci_config,
2249 .reset_chip = qla2x00_reset_chip,
2250 .chip_diag = qla2x00_chip_diag,
2251 .config_rings = qla2x00_config_rings,
2252 .reset_adapter = qla2x00_reset_adapter,
2253 .nvram_config = qla2x00_nvram_config,
2254 .update_fw_options = qla2x00_update_fw_options,
2255 .load_risc = qla2x00_load_risc,
2256 .pci_info_str = qla2x00_pci_info_str,
2257 .fw_version_str = qla2x00_fw_version_str,
2258 .intr_handler = qla2300_intr_handler,
2259 .enable_intrs = qla2x00_enable_intrs,
2260 .disable_intrs = qla2x00_disable_intrs,
2261 .abort_command = qla2x00_abort_command,
2262 .target_reset = qla2x00_abort_target,
2263 .lun_reset = qla2x00_lun_reset,
2264 .fabric_login = qla2x00_login_fabric,
2265 .fabric_logout = qla2x00_fabric_logout,
2266 .calc_req_entries = qla2x00_calc_iocbs_32,
2267 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2268 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2269 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2270 .read_nvram = qla2x00_read_nvram_data,
2271 .write_nvram = qla2x00_write_nvram_data,
2272 .fw_dump = qla2300_fw_dump,
2273 .beacon_on = qla2x00_beacon_on,
2274 .beacon_off = qla2x00_beacon_off,
2275 .beacon_blink = qla2x00_beacon_blink,
2276 .read_optrom = qla2x00_read_optrom_data,
2277 .write_optrom = qla2x00_write_optrom_data,
2278 .get_flash_version = qla2x00_get_flash_version,
2279 .start_scsi = qla2x00_start_scsi,
2280 .start_scsi_mq = NULL,
2281 .abort_isp = qla2x00_abort_isp,
2282 .iospace_config = qla2x00_iospace_config,
2283 .initialize_adapter = qla2x00_initialize_adapter,
2284 };
2285
2286 static struct isp_operations qla24xx_isp_ops = {
2287 .pci_config = qla24xx_pci_config,
2288 .reset_chip = qla24xx_reset_chip,
2289 .chip_diag = qla24xx_chip_diag,
2290 .config_rings = qla24xx_config_rings,
2291 .reset_adapter = qla24xx_reset_adapter,
2292 .nvram_config = qla24xx_nvram_config,
2293 .update_fw_options = qla24xx_update_fw_options,
2294 .load_risc = qla24xx_load_risc,
2295 .pci_info_str = qla24xx_pci_info_str,
2296 .fw_version_str = qla24xx_fw_version_str,
2297 .intr_handler = qla24xx_intr_handler,
2298 .enable_intrs = qla24xx_enable_intrs,
2299 .disable_intrs = qla24xx_disable_intrs,
2300 .abort_command = qla24xx_abort_command,
2301 .target_reset = qla24xx_abort_target,
2302 .lun_reset = qla24xx_lun_reset,
2303 .fabric_login = qla24xx_login_fabric,
2304 .fabric_logout = qla24xx_fabric_logout,
2305 .calc_req_entries = NULL,
2306 .build_iocbs = NULL,
2307 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2308 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2309 .read_nvram = qla24xx_read_nvram_data,
2310 .write_nvram = qla24xx_write_nvram_data,
2311 .fw_dump = qla24xx_fw_dump,
2312 .beacon_on = qla24xx_beacon_on,
2313 .beacon_off = qla24xx_beacon_off,
2314 .beacon_blink = qla24xx_beacon_blink,
2315 .read_optrom = qla24xx_read_optrom_data,
2316 .write_optrom = qla24xx_write_optrom_data,
2317 .get_flash_version = qla24xx_get_flash_version,
2318 .start_scsi = qla24xx_start_scsi,
2319 .start_scsi_mq = NULL,
2320 .abort_isp = qla2x00_abort_isp,
2321 .iospace_config = qla2x00_iospace_config,
2322 .initialize_adapter = qla2x00_initialize_adapter,
2323 };
2324
2325 static struct isp_operations qla25xx_isp_ops = {
2326 .pci_config = qla25xx_pci_config,
2327 .reset_chip = qla24xx_reset_chip,
2328 .chip_diag = qla24xx_chip_diag,
2329 .config_rings = qla24xx_config_rings,
2330 .reset_adapter = qla24xx_reset_adapter,
2331 .nvram_config = qla24xx_nvram_config,
2332 .update_fw_options = qla24xx_update_fw_options,
2333 .load_risc = qla24xx_load_risc,
2334 .pci_info_str = qla24xx_pci_info_str,
2335 .fw_version_str = qla24xx_fw_version_str,
2336 .intr_handler = qla24xx_intr_handler,
2337 .enable_intrs = qla24xx_enable_intrs,
2338 .disable_intrs = qla24xx_disable_intrs,
2339 .abort_command = qla24xx_abort_command,
2340 .target_reset = qla24xx_abort_target,
2341 .lun_reset = qla24xx_lun_reset,
2342 .fabric_login = qla24xx_login_fabric,
2343 .fabric_logout = qla24xx_fabric_logout,
2344 .calc_req_entries = NULL,
2345 .build_iocbs = NULL,
2346 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2347 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2348 .read_nvram = qla25xx_read_nvram_data,
2349 .write_nvram = qla25xx_write_nvram_data,
2350 .fw_dump = qla25xx_fw_dump,
2351 .beacon_on = qla24xx_beacon_on,
2352 .beacon_off = qla24xx_beacon_off,
2353 .beacon_blink = qla24xx_beacon_blink,
2354 .read_optrom = qla25xx_read_optrom_data,
2355 .write_optrom = qla24xx_write_optrom_data,
2356 .get_flash_version = qla24xx_get_flash_version,
2357 .start_scsi = qla24xx_dif_start_scsi,
2358 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2359 .abort_isp = qla2x00_abort_isp,
2360 .iospace_config = qla2x00_iospace_config,
2361 .initialize_adapter = qla2x00_initialize_adapter,
2362 };
2363
2364 static struct isp_operations qla81xx_isp_ops = {
2365 .pci_config = qla25xx_pci_config,
2366 .reset_chip = qla24xx_reset_chip,
2367 .chip_diag = qla24xx_chip_diag,
2368 .config_rings = qla24xx_config_rings,
2369 .reset_adapter = qla24xx_reset_adapter,
2370 .nvram_config = qla81xx_nvram_config,
2371 .update_fw_options = qla24xx_update_fw_options,
2372 .load_risc = qla81xx_load_risc,
2373 .pci_info_str = qla24xx_pci_info_str,
2374 .fw_version_str = qla24xx_fw_version_str,
2375 .intr_handler = qla24xx_intr_handler,
2376 .enable_intrs = qla24xx_enable_intrs,
2377 .disable_intrs = qla24xx_disable_intrs,
2378 .abort_command = qla24xx_abort_command,
2379 .target_reset = qla24xx_abort_target,
2380 .lun_reset = qla24xx_lun_reset,
2381 .fabric_login = qla24xx_login_fabric,
2382 .fabric_logout = qla24xx_fabric_logout,
2383 .calc_req_entries = NULL,
2384 .build_iocbs = NULL,
2385 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2386 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2387 .read_nvram = NULL,
2388 .write_nvram = NULL,
2389 .fw_dump = qla81xx_fw_dump,
2390 .beacon_on = qla24xx_beacon_on,
2391 .beacon_off = qla24xx_beacon_off,
2392 .beacon_blink = qla83xx_beacon_blink,
2393 .read_optrom = qla25xx_read_optrom_data,
2394 .write_optrom = qla24xx_write_optrom_data,
2395 .get_flash_version = qla24xx_get_flash_version,
2396 .start_scsi = qla24xx_dif_start_scsi,
2397 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2398 .abort_isp = qla2x00_abort_isp,
2399 .iospace_config = qla2x00_iospace_config,
2400 .initialize_adapter = qla2x00_initialize_adapter,
2401 };
2402
2403 static struct isp_operations qla82xx_isp_ops = {
2404 .pci_config = qla82xx_pci_config,
2405 .reset_chip = qla82xx_reset_chip,
2406 .chip_diag = qla24xx_chip_diag,
2407 .config_rings = qla82xx_config_rings,
2408 .reset_adapter = qla24xx_reset_adapter,
2409 .nvram_config = qla81xx_nvram_config,
2410 .update_fw_options = qla24xx_update_fw_options,
2411 .load_risc = qla82xx_load_risc,
2412 .pci_info_str = qla24xx_pci_info_str,
2413 .fw_version_str = qla24xx_fw_version_str,
2414 .intr_handler = qla82xx_intr_handler,
2415 .enable_intrs = qla82xx_enable_intrs,
2416 .disable_intrs = qla82xx_disable_intrs,
2417 .abort_command = qla24xx_abort_command,
2418 .target_reset = qla24xx_abort_target,
2419 .lun_reset = qla24xx_lun_reset,
2420 .fabric_login = qla24xx_login_fabric,
2421 .fabric_logout = qla24xx_fabric_logout,
2422 .calc_req_entries = NULL,
2423 .build_iocbs = NULL,
2424 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2425 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2426 .read_nvram = qla24xx_read_nvram_data,
2427 .write_nvram = qla24xx_write_nvram_data,
2428 .fw_dump = qla82xx_fw_dump,
2429 .beacon_on = qla82xx_beacon_on,
2430 .beacon_off = qla82xx_beacon_off,
2431 .beacon_blink = NULL,
2432 .read_optrom = qla82xx_read_optrom_data,
2433 .write_optrom = qla82xx_write_optrom_data,
2434 .get_flash_version = qla82xx_get_flash_version,
2435 .start_scsi = qla82xx_start_scsi,
2436 .start_scsi_mq = NULL,
2437 .abort_isp = qla82xx_abort_isp,
2438 .iospace_config = qla82xx_iospace_config,
2439 .initialize_adapter = qla2x00_initialize_adapter,
2440 };
2441
2442 static struct isp_operations qla8044_isp_ops = {
2443 .pci_config = qla82xx_pci_config,
2444 .reset_chip = qla82xx_reset_chip,
2445 .chip_diag = qla24xx_chip_diag,
2446 .config_rings = qla82xx_config_rings,
2447 .reset_adapter = qla24xx_reset_adapter,
2448 .nvram_config = qla81xx_nvram_config,
2449 .update_fw_options = qla24xx_update_fw_options,
2450 .load_risc = qla82xx_load_risc,
2451 .pci_info_str = qla24xx_pci_info_str,
2452 .fw_version_str = qla24xx_fw_version_str,
2453 .intr_handler = qla8044_intr_handler,
2454 .enable_intrs = qla82xx_enable_intrs,
2455 .disable_intrs = qla82xx_disable_intrs,
2456 .abort_command = qla24xx_abort_command,
2457 .target_reset = qla24xx_abort_target,
2458 .lun_reset = qla24xx_lun_reset,
2459 .fabric_login = qla24xx_login_fabric,
2460 .fabric_logout = qla24xx_fabric_logout,
2461 .calc_req_entries = NULL,
2462 .build_iocbs = NULL,
2463 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2464 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2465 .read_nvram = NULL,
2466 .write_nvram = NULL,
2467 .fw_dump = qla8044_fw_dump,
2468 .beacon_on = qla82xx_beacon_on,
2469 .beacon_off = qla82xx_beacon_off,
2470 .beacon_blink = NULL,
2471 .read_optrom = qla8044_read_optrom_data,
2472 .write_optrom = qla8044_write_optrom_data,
2473 .get_flash_version = qla82xx_get_flash_version,
2474 .start_scsi = qla82xx_start_scsi,
2475 .start_scsi_mq = NULL,
2476 .abort_isp = qla8044_abort_isp,
2477 .iospace_config = qla82xx_iospace_config,
2478 .initialize_adapter = qla2x00_initialize_adapter,
2479 };
2480
2481 static struct isp_operations qla83xx_isp_ops = {
2482 .pci_config = qla25xx_pci_config,
2483 .reset_chip = qla24xx_reset_chip,
2484 .chip_diag = qla24xx_chip_diag,
2485 .config_rings = qla24xx_config_rings,
2486 .reset_adapter = qla24xx_reset_adapter,
2487 .nvram_config = qla81xx_nvram_config,
2488 .update_fw_options = qla24xx_update_fw_options,
2489 .load_risc = qla81xx_load_risc,
2490 .pci_info_str = qla24xx_pci_info_str,
2491 .fw_version_str = qla24xx_fw_version_str,
2492 .intr_handler = qla24xx_intr_handler,
2493 .enable_intrs = qla24xx_enable_intrs,
2494 .disable_intrs = qla24xx_disable_intrs,
2495 .abort_command = qla24xx_abort_command,
2496 .target_reset = qla24xx_abort_target,
2497 .lun_reset = qla24xx_lun_reset,
2498 .fabric_login = qla24xx_login_fabric,
2499 .fabric_logout = qla24xx_fabric_logout,
2500 .calc_req_entries = NULL,
2501 .build_iocbs = NULL,
2502 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2503 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2504 .read_nvram = NULL,
2505 .write_nvram = NULL,
2506 .fw_dump = qla83xx_fw_dump,
2507 .beacon_on = qla24xx_beacon_on,
2508 .beacon_off = qla24xx_beacon_off,
2509 .beacon_blink = qla83xx_beacon_blink,
2510 .read_optrom = qla25xx_read_optrom_data,
2511 .write_optrom = qla24xx_write_optrom_data,
2512 .get_flash_version = qla24xx_get_flash_version,
2513 .start_scsi = qla24xx_dif_start_scsi,
2514 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2515 .abort_isp = qla2x00_abort_isp,
2516 .iospace_config = qla83xx_iospace_config,
2517 .initialize_adapter = qla2x00_initialize_adapter,
2518 };
2519
2520 static struct isp_operations qlafx00_isp_ops = {
2521 .pci_config = qlafx00_pci_config,
2522 .reset_chip = qlafx00_soft_reset,
2523 .chip_diag = qlafx00_chip_diag,
2524 .config_rings = qlafx00_config_rings,
2525 .reset_adapter = qlafx00_soft_reset,
2526 .nvram_config = NULL,
2527 .update_fw_options = NULL,
2528 .load_risc = NULL,
2529 .pci_info_str = qlafx00_pci_info_str,
2530 .fw_version_str = qlafx00_fw_version_str,
2531 .intr_handler = qlafx00_intr_handler,
2532 .enable_intrs = qlafx00_enable_intrs,
2533 .disable_intrs = qlafx00_disable_intrs,
2534 .abort_command = qla24xx_async_abort_command,
2535 .target_reset = qlafx00_abort_target,
2536 .lun_reset = qlafx00_lun_reset,
2537 .fabric_login = NULL,
2538 .fabric_logout = NULL,
2539 .calc_req_entries = NULL,
2540 .build_iocbs = NULL,
2541 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2542 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2543 .read_nvram = qla24xx_read_nvram_data,
2544 .write_nvram = qla24xx_write_nvram_data,
2545 .fw_dump = NULL,
2546 .beacon_on = qla24xx_beacon_on,
2547 .beacon_off = qla24xx_beacon_off,
2548 .beacon_blink = NULL,
2549 .read_optrom = qla24xx_read_optrom_data,
2550 .write_optrom = qla24xx_write_optrom_data,
2551 .get_flash_version = qla24xx_get_flash_version,
2552 .start_scsi = qlafx00_start_scsi,
2553 .start_scsi_mq = NULL,
2554 .abort_isp = qlafx00_abort_isp,
2555 .iospace_config = qlafx00_iospace_config,
2556 .initialize_adapter = qlafx00_initialize_adapter,
2557 };
2558
2559 static struct isp_operations qla27xx_isp_ops = {
2560 .pci_config = qla25xx_pci_config,
2561 .reset_chip = qla24xx_reset_chip,
2562 .chip_diag = qla24xx_chip_diag,
2563 .config_rings = qla24xx_config_rings,
2564 .reset_adapter = qla24xx_reset_adapter,
2565 .nvram_config = qla81xx_nvram_config,
2566 .update_fw_options = qla24xx_update_fw_options,
2567 .load_risc = qla81xx_load_risc,
2568 .pci_info_str = qla24xx_pci_info_str,
2569 .fw_version_str = qla24xx_fw_version_str,
2570 .intr_handler = qla24xx_intr_handler,
2571 .enable_intrs = qla24xx_enable_intrs,
2572 .disable_intrs = qla24xx_disable_intrs,
2573 .abort_command = qla24xx_abort_command,
2574 .target_reset = qla24xx_abort_target,
2575 .lun_reset = qla24xx_lun_reset,
2576 .fabric_login = qla24xx_login_fabric,
2577 .fabric_logout = qla24xx_fabric_logout,
2578 .calc_req_entries = NULL,
2579 .build_iocbs = NULL,
2580 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2581 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2582 .read_nvram = NULL,
2583 .write_nvram = NULL,
2584 .fw_dump = qla27xx_fwdump,
2585 .mpi_fw_dump = qla27xx_mpi_fwdump,
2586 .beacon_on = qla24xx_beacon_on,
2587 .beacon_off = qla24xx_beacon_off,
2588 .beacon_blink = qla83xx_beacon_blink,
2589 .read_optrom = qla25xx_read_optrom_data,
2590 .write_optrom = qla24xx_write_optrom_data,
2591 .get_flash_version = qla24xx_get_flash_version,
2592 .start_scsi = qla24xx_dif_start_scsi,
2593 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2594 .abort_isp = qla2x00_abort_isp,
2595 .iospace_config = qla83xx_iospace_config,
2596 .initialize_adapter = qla2x00_initialize_adapter,
2597 };
2598
2599 static inline void
qla2x00_set_isp_flags(struct qla_hw_data * ha)2600 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2601 {
2602 ha->device_type = DT_EXTENDED_IDS;
2603 switch (ha->pdev->device) {
2604 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2605 ha->isp_type |= DT_ISP2100;
2606 ha->device_type &= ~DT_EXTENDED_IDS;
2607 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2608 break;
2609 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2610 ha->isp_type |= DT_ISP2200;
2611 ha->device_type &= ~DT_EXTENDED_IDS;
2612 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2613 break;
2614 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2615 ha->isp_type |= DT_ISP2300;
2616 ha->device_type |= DT_ZIO_SUPPORTED;
2617 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2618 break;
2619 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2620 ha->isp_type |= DT_ISP2312;
2621 ha->device_type |= DT_ZIO_SUPPORTED;
2622 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2623 break;
2624 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2625 ha->isp_type |= DT_ISP2322;
2626 ha->device_type |= DT_ZIO_SUPPORTED;
2627 if (ha->pdev->subsystem_vendor == 0x1028 &&
2628 ha->pdev->subsystem_device == 0x0170)
2629 ha->device_type |= DT_OEM_001;
2630 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2631 break;
2632 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2633 ha->isp_type |= DT_ISP6312;
2634 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2635 break;
2636 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2637 ha->isp_type |= DT_ISP6322;
2638 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2639 break;
2640 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2641 ha->isp_type |= DT_ISP2422;
2642 ha->device_type |= DT_ZIO_SUPPORTED;
2643 ha->device_type |= DT_FWI2;
2644 ha->device_type |= DT_IIDMA;
2645 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2646 break;
2647 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2648 ha->isp_type |= DT_ISP2432;
2649 ha->device_type |= DT_ZIO_SUPPORTED;
2650 ha->device_type |= DT_FWI2;
2651 ha->device_type |= DT_IIDMA;
2652 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2653 break;
2654 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2655 ha->isp_type |= DT_ISP8432;
2656 ha->device_type |= DT_ZIO_SUPPORTED;
2657 ha->device_type |= DT_FWI2;
2658 ha->device_type |= DT_IIDMA;
2659 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2660 break;
2661 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2662 ha->isp_type |= DT_ISP5422;
2663 ha->device_type |= DT_FWI2;
2664 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2665 break;
2666 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2667 ha->isp_type |= DT_ISP5432;
2668 ha->device_type |= DT_FWI2;
2669 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2670 break;
2671 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2672 ha->isp_type |= DT_ISP2532;
2673 ha->device_type |= DT_ZIO_SUPPORTED;
2674 ha->device_type |= DT_FWI2;
2675 ha->device_type |= DT_IIDMA;
2676 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2677 break;
2678 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2679 ha->isp_type |= DT_ISP8001;
2680 ha->device_type |= DT_ZIO_SUPPORTED;
2681 ha->device_type |= DT_FWI2;
2682 ha->device_type |= DT_IIDMA;
2683 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2684 break;
2685 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2686 ha->isp_type |= DT_ISP8021;
2687 ha->device_type |= DT_ZIO_SUPPORTED;
2688 ha->device_type |= DT_FWI2;
2689 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2690 /* Initialize 82XX ISP flags */
2691 qla82xx_init_flags(ha);
2692 break;
2693 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2694 ha->isp_type |= DT_ISP8044;
2695 ha->device_type |= DT_ZIO_SUPPORTED;
2696 ha->device_type |= DT_FWI2;
2697 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2698 /* Initialize 82XX ISP flags */
2699 qla82xx_init_flags(ha);
2700 break;
2701 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2702 ha->isp_type |= DT_ISP2031;
2703 ha->device_type |= DT_ZIO_SUPPORTED;
2704 ha->device_type |= DT_FWI2;
2705 ha->device_type |= DT_IIDMA;
2706 ha->device_type |= DT_T10_PI;
2707 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2708 break;
2709 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2710 ha->isp_type |= DT_ISP8031;
2711 ha->device_type |= DT_ZIO_SUPPORTED;
2712 ha->device_type |= DT_FWI2;
2713 ha->device_type |= DT_IIDMA;
2714 ha->device_type |= DT_T10_PI;
2715 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2716 break;
2717 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2718 ha->isp_type |= DT_ISPFX00;
2719 break;
2720 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2721 ha->isp_type |= DT_ISP2071;
2722 ha->device_type |= DT_ZIO_SUPPORTED;
2723 ha->device_type |= DT_FWI2;
2724 ha->device_type |= DT_IIDMA;
2725 ha->device_type |= DT_T10_PI;
2726 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2727 break;
2728 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2729 ha->isp_type |= DT_ISP2271;
2730 ha->device_type |= DT_ZIO_SUPPORTED;
2731 ha->device_type |= DT_FWI2;
2732 ha->device_type |= DT_IIDMA;
2733 ha->device_type |= DT_T10_PI;
2734 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2735 break;
2736 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2737 ha->isp_type |= DT_ISP2261;
2738 ha->device_type |= DT_ZIO_SUPPORTED;
2739 ha->device_type |= DT_FWI2;
2740 ha->device_type |= DT_IIDMA;
2741 ha->device_type |= DT_T10_PI;
2742 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2743 break;
2744 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2745 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2746 ha->isp_type |= DT_ISP2081;
2747 ha->device_type |= DT_ZIO_SUPPORTED;
2748 ha->device_type |= DT_FWI2;
2749 ha->device_type |= DT_IIDMA;
2750 ha->device_type |= DT_T10_PI;
2751 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2752 break;
2753 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2754 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2755 ha->isp_type |= DT_ISP2281;
2756 ha->device_type |= DT_ZIO_SUPPORTED;
2757 ha->device_type |= DT_FWI2;
2758 ha->device_type |= DT_IIDMA;
2759 ha->device_type |= DT_T10_PI;
2760 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2761 break;
2762 }
2763
2764 if (IS_QLA82XX(ha))
2765 ha->port_no = ha->portnum & 1;
2766 else {
2767 /* Get adapter physical port no from interrupt pin register. */
2768 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2769 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2770 IS_QLA27XX(ha) || IS_QLA28XX(ha))
2771 ha->port_no--;
2772 else
2773 ha->port_no = !(ha->port_no & 1);
2774 }
2775
2776 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2777 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2778 ha->device_type, ha->port_no, ha->fw_srisc_address);
2779 }
2780
2781 static void
qla2xxx_scan_start(struct Scsi_Host * shost)2782 qla2xxx_scan_start(struct Scsi_Host *shost)
2783 {
2784 scsi_qla_host_t *vha = shost_priv(shost);
2785
2786 if (vha->hw->flags.running_gold_fw)
2787 return;
2788
2789 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2790 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2791 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2792 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2793 }
2794
2795 static int
qla2xxx_scan_finished(struct Scsi_Host * shost,unsigned long time)2796 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2797 {
2798 scsi_qla_host_t *vha = shost_priv(shost);
2799
2800 if (test_bit(UNLOADING, &vha->dpc_flags))
2801 return 1;
2802 if (!vha->host)
2803 return 1;
2804 if (time > vha->hw->loop_reset_delay * HZ)
2805 return 1;
2806
2807 return atomic_read(&vha->loop_state) == LOOP_READY;
2808 }
2809
qla_heartbeat_work_fn(struct work_struct * work)2810 static void qla_heartbeat_work_fn(struct work_struct *work)
2811 {
2812 struct qla_hw_data *ha = container_of(work,
2813 struct qla_hw_data, heartbeat_work);
2814 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2815
2816 if (!ha->flags.mbox_busy && base_vha->flags.init_done)
2817 qla_no_op_mb(base_vha);
2818 }
2819
qla2x00_iocb_work_fn(struct work_struct * work)2820 static void qla2x00_iocb_work_fn(struct work_struct *work)
2821 {
2822 struct scsi_qla_host *vha = container_of(work,
2823 struct scsi_qla_host, iocb_work);
2824 struct qla_hw_data *ha = vha->hw;
2825 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2826 int i = 2;
2827 unsigned long flags;
2828
2829 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2830 return;
2831
2832 while (!list_empty(&vha->work_list) && i > 0) {
2833 qla2x00_do_work(vha);
2834 i--;
2835 }
2836
2837 spin_lock_irqsave(&vha->work_lock, flags);
2838 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2839 spin_unlock_irqrestore(&vha->work_lock, flags);
2840 }
2841
2842 /*
2843 * PCI driver interface
2844 */
2845 static int
qla2x00_probe_one(struct pci_dev * pdev,const struct pci_device_id * id)2846 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2847 {
2848 int ret = -ENODEV;
2849 struct Scsi_Host *host;
2850 scsi_qla_host_t *base_vha = NULL;
2851 struct qla_hw_data *ha;
2852 char pci_info[30];
2853 char fw_str[30], wq_name[30];
2854 struct scsi_host_template *sht;
2855 int bars, mem_only = 0;
2856 uint16_t req_length = 0, rsp_length = 0;
2857 struct req_que *req = NULL;
2858 struct rsp_que *rsp = NULL;
2859 int i;
2860
2861 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2862 sht = &qla2xxx_driver_template;
2863 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2864 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2865 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2866 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2867 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2868 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2869 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2870 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2871 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2872 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2873 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2874 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2875 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2876 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2877 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2878 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2879 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2880 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2881 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2882 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2883 mem_only = 1;
2884 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2885 "Mem only adapter.\n");
2886 }
2887 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2888 "Bars=%d.\n", bars);
2889
2890 if (mem_only) {
2891 if (pci_enable_device_mem(pdev))
2892 return ret;
2893 } else {
2894 if (pci_enable_device(pdev))
2895 return ret;
2896 }
2897
2898 if (is_kdump_kernel()) {
2899 ql2xmqsupport = 0;
2900 ql2xallocfwdump = 0;
2901 }
2902
2903 /* This may fail but that's ok */
2904 pci_enable_pcie_error_reporting(pdev);
2905
2906 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2907 if (!ha) {
2908 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2909 "Unable to allocate memory for ha.\n");
2910 goto disable_device;
2911 }
2912 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2913 "Memory allocated for ha=%p.\n", ha);
2914 ha->pdev = pdev;
2915 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2916 spin_lock_init(&ha->tgt.q_full_lock);
2917 spin_lock_init(&ha->tgt.sess_lock);
2918 spin_lock_init(&ha->tgt.atio_lock);
2919
2920 spin_lock_init(&ha->sadb_lock);
2921 INIT_LIST_HEAD(&ha->sadb_tx_index_list);
2922 INIT_LIST_HEAD(&ha->sadb_rx_index_list);
2923
2924 spin_lock_init(&ha->sadb_fp_lock);
2925
2926 if (qla_edif_sadb_build_free_pool(ha)) {
2927 kfree(ha);
2928 goto disable_device;
2929 }
2930
2931 atomic_set(&ha->nvme_active_aen_cnt, 0);
2932
2933 /* Clear our data area */
2934 ha->bars = bars;
2935 ha->mem_only = mem_only;
2936 spin_lock_init(&ha->hardware_lock);
2937 spin_lock_init(&ha->vport_slock);
2938 mutex_init(&ha->selflogin_lock);
2939 mutex_init(&ha->optrom_mutex);
2940
2941 /* Set ISP-type information. */
2942 qla2x00_set_isp_flags(ha);
2943
2944 /* Set EEH reset type to fundamental if required by hba */
2945 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2946 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
2947 pdev->needs_freset = 1;
2948
2949 ha->prev_topology = 0;
2950 ha->init_cb_size = sizeof(init_cb_t);
2951 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2952 ha->optrom_size = OPTROM_SIZE_2300;
2953 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
2954 atomic_set(&ha->num_pend_mbx_stage1, 0);
2955 atomic_set(&ha->num_pend_mbx_stage2, 0);
2956 atomic_set(&ha->num_pend_mbx_stage3, 0);
2957 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2958 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
2959
2960 /* Assign ISP specific operations. */
2961 if (IS_QLA2100(ha)) {
2962 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2963 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2964 req_length = REQUEST_ENTRY_CNT_2100;
2965 rsp_length = RESPONSE_ENTRY_CNT_2100;
2966 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2967 ha->gid_list_info_size = 4;
2968 ha->flash_conf_off = ~0;
2969 ha->flash_data_off = ~0;
2970 ha->nvram_conf_off = ~0;
2971 ha->nvram_data_off = ~0;
2972 ha->isp_ops = &qla2100_isp_ops;
2973 } else if (IS_QLA2200(ha)) {
2974 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2975 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2976 req_length = REQUEST_ENTRY_CNT_2200;
2977 rsp_length = RESPONSE_ENTRY_CNT_2100;
2978 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2979 ha->gid_list_info_size = 4;
2980 ha->flash_conf_off = ~0;
2981 ha->flash_data_off = ~0;
2982 ha->nvram_conf_off = ~0;
2983 ha->nvram_data_off = ~0;
2984 ha->isp_ops = &qla2100_isp_ops;
2985 } else if (IS_QLA23XX(ha)) {
2986 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2987 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2988 req_length = REQUEST_ENTRY_CNT_2200;
2989 rsp_length = RESPONSE_ENTRY_CNT_2300;
2990 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2991 ha->gid_list_info_size = 6;
2992 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2993 ha->optrom_size = OPTROM_SIZE_2322;
2994 ha->flash_conf_off = ~0;
2995 ha->flash_data_off = ~0;
2996 ha->nvram_conf_off = ~0;
2997 ha->nvram_data_off = ~0;
2998 ha->isp_ops = &qla2300_isp_ops;
2999 } else if (IS_QLA24XX_TYPE(ha)) {
3000 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3001 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3002 req_length = REQUEST_ENTRY_CNT_24XX;
3003 rsp_length = RESPONSE_ENTRY_CNT_2300;
3004 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3005 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3006 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3007 ha->gid_list_info_size = 8;
3008 ha->optrom_size = OPTROM_SIZE_24XX;
3009 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
3010 ha->isp_ops = &qla24xx_isp_ops;
3011 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3012 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3013 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3014 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3015 } else if (IS_QLA25XX(ha)) {
3016 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3017 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3018 req_length = REQUEST_ENTRY_CNT_24XX;
3019 rsp_length = RESPONSE_ENTRY_CNT_2300;
3020 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3021 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3022 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3023 ha->gid_list_info_size = 8;
3024 ha->optrom_size = OPTROM_SIZE_25XX;
3025 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3026 ha->isp_ops = &qla25xx_isp_ops;
3027 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3028 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3029 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3030 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3031 } else if (IS_QLA81XX(ha)) {
3032 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3033 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3034 req_length = REQUEST_ENTRY_CNT_24XX;
3035 rsp_length = RESPONSE_ENTRY_CNT_2300;
3036 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3037 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3038 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3039 ha->gid_list_info_size = 8;
3040 ha->optrom_size = OPTROM_SIZE_81XX;
3041 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3042 ha->isp_ops = &qla81xx_isp_ops;
3043 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3044 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3045 ha->nvram_conf_off = ~0;
3046 ha->nvram_data_off = ~0;
3047 } else if (IS_QLA82XX(ha)) {
3048 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3049 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3050 req_length = REQUEST_ENTRY_CNT_82XX;
3051 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3052 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3053 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3054 ha->gid_list_info_size = 8;
3055 ha->optrom_size = OPTROM_SIZE_82XX;
3056 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3057 ha->isp_ops = &qla82xx_isp_ops;
3058 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3059 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3060 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3061 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3062 } else if (IS_QLA8044(ha)) {
3063 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3064 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3065 req_length = REQUEST_ENTRY_CNT_82XX;
3066 rsp_length = RESPONSE_ENTRY_CNT_82XX;
3067 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3068 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3069 ha->gid_list_info_size = 8;
3070 ha->optrom_size = OPTROM_SIZE_83XX;
3071 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3072 ha->isp_ops = &qla8044_isp_ops;
3073 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3074 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3075 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3076 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3077 } else if (IS_QLA83XX(ha)) {
3078 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3079 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3080 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3081 req_length = REQUEST_ENTRY_CNT_83XX;
3082 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3083 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3084 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3085 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3086 ha->gid_list_info_size = 8;
3087 ha->optrom_size = OPTROM_SIZE_83XX;
3088 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3089 ha->isp_ops = &qla83xx_isp_ops;
3090 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3091 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3092 ha->nvram_conf_off = ~0;
3093 ha->nvram_data_off = ~0;
3094 } else if (IS_QLAFX00(ha)) {
3095 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3096 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3097 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3098 req_length = REQUEST_ENTRY_CNT_FX00;
3099 rsp_length = RESPONSE_ENTRY_CNT_FX00;
3100 ha->isp_ops = &qlafx00_isp_ops;
3101 ha->port_down_retry_count = 30; /* default value */
3102 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3103 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3104 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3105 ha->mr.fw_hbt_en = 1;
3106 ha->mr.host_info_resend = false;
3107 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3108 } else if (IS_QLA27XX(ha)) {
3109 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3110 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3111 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3112 req_length = REQUEST_ENTRY_CNT_83XX;
3113 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3114 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3115 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3116 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3117 ha->gid_list_info_size = 8;
3118 ha->optrom_size = OPTROM_SIZE_83XX;
3119 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3120 ha->isp_ops = &qla27xx_isp_ops;
3121 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3122 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3123 ha->nvram_conf_off = ~0;
3124 ha->nvram_data_off = ~0;
3125 } else if (IS_QLA28XX(ha)) {
3126 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3127 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3128 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3129 req_length = REQUEST_ENTRY_CNT_83XX;
3130 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3131 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3132 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3133 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3134 ha->gid_list_info_size = 8;
3135 ha->optrom_size = OPTROM_SIZE_28XX;
3136 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3137 ha->isp_ops = &qla27xx_isp_ops;
3138 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3139 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3140 ha->nvram_conf_off = ~0;
3141 ha->nvram_data_off = ~0;
3142 }
3143
3144 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3145 "mbx_count=%d, req_length=%d, "
3146 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3147 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3148 "max_fibre_devices=%d.\n",
3149 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3150 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3151 ha->nvram_npiv_size, ha->max_fibre_devices);
3152 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3153 "isp_ops=%p, flash_conf_off=%d, "
3154 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3155 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3156 ha->nvram_conf_off, ha->nvram_data_off);
3157
3158 /* Configure PCI I/O space */
3159 ret = ha->isp_ops->iospace_config(ha);
3160 if (ret)
3161 goto iospace_config_failed;
3162
3163 ql_log_pci(ql_log_info, pdev, 0x001d,
3164 "Found an ISP%04X irq %d iobase 0x%p.\n",
3165 pdev->device, pdev->irq, ha->iobase);
3166 mutex_init(&ha->vport_lock);
3167 mutex_init(&ha->mq_lock);
3168 init_completion(&ha->mbx_cmd_comp);
3169 complete(&ha->mbx_cmd_comp);
3170 init_completion(&ha->mbx_intr_comp);
3171 init_completion(&ha->dcbx_comp);
3172 init_completion(&ha->lb_portup_comp);
3173
3174 set_bit(0, (unsigned long *) ha->vp_idx_map);
3175
3176 qla2x00_config_dma_addressing(ha);
3177 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3178 "64 Bit addressing is %s.\n",
3179 ha->flags.enable_64bit_addressing ? "enable" :
3180 "disable");
3181 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3182 if (ret) {
3183 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3184 "Failed to allocate memory for adapter, aborting.\n");
3185
3186 goto probe_hw_failed;
3187 }
3188
3189 req->max_q_depth = MAX_Q_DEPTH;
3190 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3191 req->max_q_depth = ql2xmaxqdepth;
3192
3193
3194 base_vha = qla2x00_create_host(sht, ha);
3195 if (!base_vha) {
3196 ret = -ENOMEM;
3197 goto probe_hw_failed;
3198 }
3199
3200 pci_set_drvdata(pdev, base_vha);
3201 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3202
3203 host = base_vha->host;
3204 base_vha->req = req;
3205 if (IS_QLA2XXX_MIDTYPE(ha))
3206 base_vha->mgmt_svr_loop_id =
3207 qla2x00_reserve_mgmt_server_loop_id(base_vha);
3208 else
3209 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3210 base_vha->vp_idx;
3211
3212 /* Setup fcport template structure. */
3213 ha->mr.fcport.vha = base_vha;
3214 ha->mr.fcport.port_type = FCT_UNKNOWN;
3215 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3216 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3217 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3218 ha->mr.fcport.scan_state = 1;
3219
3220 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN |
3221 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT |
3222 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN);
3223
3224 /* Set the SG table size based on ISP type */
3225 if (!IS_FWI2_CAPABLE(ha)) {
3226 if (IS_QLA2100(ha))
3227 host->sg_tablesize = 32;
3228 } else {
3229 if (!IS_QLA82XX(ha))
3230 host->sg_tablesize = QLA_SG_ALL;
3231 }
3232 host->max_id = ha->max_fibre_devices;
3233 host->cmd_per_lun = 3;
3234 host->unique_id = host->host_no;
3235 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3236 host->max_cmd_len = 32;
3237 else
3238 host->max_cmd_len = MAX_CMDSZ;
3239 host->max_channel = MAX_BUSES - 1;
3240 /* Older HBAs support only 16-bit LUNs */
3241 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3242 ql2xmaxlun > 0xffff)
3243 host->max_lun = 0xffff;
3244 else
3245 host->max_lun = ql2xmaxlun;
3246 host->transportt = qla2xxx_transport_template;
3247 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3248
3249 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3250 "max_id=%d this_id=%d "
3251 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3252 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3253 host->this_id, host->cmd_per_lun, host->unique_id,
3254 host->max_cmd_len, host->max_channel, host->max_lun,
3255 host->transportt, sht->vendor_id);
3256
3257 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3258 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn);
3259
3260 /* Set up the irqs */
3261 ret = qla2x00_request_irqs(ha, rsp);
3262 if (ret)
3263 goto probe_failed;
3264
3265 /* Alloc arrays of request and response ring ptrs */
3266 ret = qla2x00_alloc_queues(ha, req, rsp);
3267 if (ret) {
3268 ql_log(ql_log_fatal, base_vha, 0x003d,
3269 "Failed to allocate memory for queue pointers..."
3270 "aborting.\n");
3271 ret = -ENODEV;
3272 goto probe_failed;
3273 }
3274
3275 if (ha->mqenable) {
3276 /* number of hardware queues supported by blk/scsi-mq*/
3277 host->nr_hw_queues = ha->max_qpairs;
3278
3279 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3280 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3281 } else {
3282 if (ql2xnvmeenable) {
3283 host->nr_hw_queues = ha->max_qpairs;
3284 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3285 "FC-NVMe support is enabled, HW queues=%d\n",
3286 host->nr_hw_queues);
3287 } else {
3288 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3289 "blk/scsi-mq disabled.\n");
3290 }
3291 }
3292
3293 qlt_probe_one_stage1(base_vha, ha);
3294
3295 pci_save_state(pdev);
3296
3297 /* Assign back pointers */
3298 rsp->req = req;
3299 req->rsp = rsp;
3300
3301 if (IS_QLAFX00(ha)) {
3302 ha->rsp_q_map[0] = rsp;
3303 ha->req_q_map[0] = req;
3304 set_bit(0, ha->req_qid_map);
3305 set_bit(0, ha->rsp_qid_map);
3306 }
3307
3308 /* FWI2-capable only. */
3309 req->req_q_in = &ha->iobase->isp24.req_q_in;
3310 req->req_q_out = &ha->iobase->isp24.req_q_out;
3311 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3312 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3313 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3314 IS_QLA28XX(ha)) {
3315 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3316 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3317 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3318 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
3319 }
3320
3321 if (IS_QLAFX00(ha)) {
3322 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3323 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3324 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3325 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3326 }
3327
3328 if (IS_P3P_TYPE(ha)) {
3329 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3330 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3331 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3332 }
3333
3334 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3335 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3336 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3337 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3338 "req->req_q_in=%p req->req_q_out=%p "
3339 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3340 req->req_q_in, req->req_q_out,
3341 rsp->rsp_q_in, rsp->rsp_q_out);
3342 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3343 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3344 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3345 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3346 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3347 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3348
3349 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0);
3350 if (unlikely(!ha->wq)) {
3351 ret = -ENOMEM;
3352 goto probe_failed;
3353 }
3354
3355 if (ha->isp_ops->initialize_adapter(base_vha)) {
3356 ql_log(ql_log_fatal, base_vha, 0x00d6,
3357 "Failed to initialize adapter - Adapter flags %x.\n",
3358 base_vha->device_flags);
3359
3360 if (IS_QLA82XX(ha)) {
3361 qla82xx_idc_lock(ha);
3362 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3363 QLA8XXX_DEV_FAILED);
3364 qla82xx_idc_unlock(ha);
3365 ql_log(ql_log_fatal, base_vha, 0x00d7,
3366 "HW State: FAILED.\n");
3367 } else if (IS_QLA8044(ha)) {
3368 qla8044_idc_lock(ha);
3369 qla8044_wr_direct(base_vha,
3370 QLA8044_CRB_DEV_STATE_INDEX,
3371 QLA8XXX_DEV_FAILED);
3372 qla8044_idc_unlock(ha);
3373 ql_log(ql_log_fatal, base_vha, 0x0150,
3374 "HW State: FAILED.\n");
3375 }
3376
3377 ret = -ENODEV;
3378 goto probe_failed;
3379 }
3380
3381 if (IS_QLAFX00(ha))
3382 host->can_queue = QLAFX00_MAX_CANQUEUE;
3383 else
3384 host->can_queue = req->num_outstanding_cmds - 10;
3385
3386 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3387 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3388 host->can_queue, base_vha->req,
3389 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3390
3391 /* Check if FW supports MQ or not for ISP25xx */
3392 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6))
3393 ha->mqenable = 0;
3394
3395 if (ha->mqenable) {
3396 bool startit = false;
3397
3398 if (QLA_TGT_MODE_ENABLED())
3399 startit = false;
3400
3401 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
3402 startit = true;
3403
3404 /* Create start of day qpairs for Block MQ */
3405 for (i = 0; i < ha->max_qpairs; i++)
3406 qla2xxx_create_qpair(base_vha, 5, 0, startit);
3407 }
3408 qla_init_iocb_limit(base_vha);
3409
3410 if (ha->flags.running_gold_fw)
3411 goto skip_dpc;
3412
3413 /*
3414 * Startup the kernel thread for this host adapter
3415 */
3416 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3417 "%s_dpc", base_vha->host_str);
3418 if (IS_ERR(ha->dpc_thread)) {
3419 ql_log(ql_log_fatal, base_vha, 0x00ed,
3420 "Failed to start DPC thread.\n");
3421 ret = PTR_ERR(ha->dpc_thread);
3422 ha->dpc_thread = NULL;
3423 goto probe_failed;
3424 }
3425 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3426 "DPC thread started successfully.\n");
3427
3428 /*
3429 * If we're not coming up in initiator mode, we might sit for
3430 * a while without waking up the dpc thread, which leads to a
3431 * stuck process warning. So just kick the dpc once here and
3432 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3433 */
3434 qla2xxx_wake_dpc(base_vha);
3435
3436 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3437
3438 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3439 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3440 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3441 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3442
3443 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3444 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3445 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3446 INIT_WORK(&ha->idc_state_handler,
3447 qla83xx_idc_state_handler_work);
3448 INIT_WORK(&ha->nic_core_unrecoverable,
3449 qla83xx_nic_core_unrecoverable_work);
3450 }
3451
3452 skip_dpc:
3453 list_add_tail(&base_vha->list, &ha->vp_list);
3454 base_vha->host->irq = ha->pdev->irq;
3455
3456 /* Initialized the timer */
3457 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3458 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3459 "Started qla2x00_timer with "
3460 "interval=%d.\n", WATCH_INTERVAL);
3461 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3462 "Detected hba at address=%p.\n",
3463 ha);
3464
3465 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3466 if (ha->fw_attributes & BIT_4) {
3467 int prot = 0, guard;
3468
3469 base_vha->flags.difdix_supported = 1;
3470 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3471 "Registering for DIF/DIX type 1 and 3 protection.\n");
3472 if (ql2xenabledif == 1)
3473 prot = SHOST_DIX_TYPE0_PROTECTION;
3474 if (ql2xprotmask)
3475 scsi_host_set_prot(host, ql2xprotmask);
3476 else
3477 scsi_host_set_prot(host,
3478 prot | SHOST_DIF_TYPE1_PROTECTION
3479 | SHOST_DIF_TYPE2_PROTECTION
3480 | SHOST_DIF_TYPE3_PROTECTION
3481 | SHOST_DIX_TYPE1_PROTECTION
3482 | SHOST_DIX_TYPE2_PROTECTION
3483 | SHOST_DIX_TYPE3_PROTECTION);
3484
3485 guard = SHOST_DIX_GUARD_CRC;
3486
3487 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3488 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3489 guard |= SHOST_DIX_GUARD_IP;
3490
3491 if (ql2xprotguard)
3492 scsi_host_set_guard(host, ql2xprotguard);
3493 else
3494 scsi_host_set_guard(host, guard);
3495 } else
3496 base_vha->flags.difdix_supported = 0;
3497 }
3498
3499 ha->isp_ops->enable_intrs(ha);
3500
3501 if (IS_QLAFX00(ha)) {
3502 ret = qlafx00_fx_disc(base_vha,
3503 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3504 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3505 QLA_SG_ALL : 128;
3506 }
3507
3508 ret = scsi_add_host(host, &pdev->dev);
3509 if (ret)
3510 goto probe_failed;
3511
3512 base_vha->flags.init_done = 1;
3513 base_vha->flags.online = 1;
3514 ha->prev_minidump_failed = 0;
3515
3516 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3517 "Init done and hba is online.\n");
3518
3519 if (qla_ini_mode_enabled(base_vha) ||
3520 qla_dual_mode_enabled(base_vha))
3521 scsi_scan_host(host);
3522 else
3523 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3524 "skipping scsi_scan_host() for non-initiator port\n");
3525
3526 qla2x00_alloc_sysfs_attr(base_vha);
3527
3528 if (IS_QLAFX00(ha)) {
3529 ret = qlafx00_fx_disc(base_vha,
3530 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3531
3532 /* Register system information */
3533 ret = qlafx00_fx_disc(base_vha,
3534 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3535 }
3536
3537 qla2x00_init_host_attr(base_vha);
3538
3539 qla2x00_dfs_setup(base_vha);
3540
3541 ql_log(ql_log_info, base_vha, 0x00fb,
3542 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3543 ql_log(ql_log_info, base_vha, 0x00fc,
3544 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3545 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3546 sizeof(pci_info)),
3547 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3548 base_vha->host_no,
3549 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3550
3551 qlt_add_target(ha, base_vha);
3552
3553 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3554
3555 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3556 return -ENODEV;
3557
3558 return 0;
3559
3560 probe_failed:
3561 qla_enode_stop(base_vha);
3562 qla_edb_stop(base_vha);
3563 if (base_vha->gnl.l) {
3564 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3565 base_vha->gnl.l, base_vha->gnl.ldma);
3566 base_vha->gnl.l = NULL;
3567 }
3568
3569 if (base_vha->timer_active)
3570 qla2x00_stop_timer(base_vha);
3571 base_vha->flags.online = 0;
3572 if (ha->dpc_thread) {
3573 struct task_struct *t = ha->dpc_thread;
3574
3575 ha->dpc_thread = NULL;
3576 kthread_stop(t);
3577 }
3578
3579 qla2x00_free_device(base_vha);
3580 scsi_host_put(base_vha->host);
3581 /*
3582 * Need to NULL out local req/rsp after
3583 * qla2x00_free_device => qla2x00_free_queues frees
3584 * what these are pointing to. Or else we'll
3585 * fall over below in qla2x00_free_req/rsp_que.
3586 */
3587 req = NULL;
3588 rsp = NULL;
3589
3590 probe_hw_failed:
3591 qla2x00_mem_free(ha);
3592 qla2x00_free_req_que(ha, req);
3593 qla2x00_free_rsp_que(ha, rsp);
3594 qla2x00_clear_drv_active(ha);
3595
3596 iospace_config_failed:
3597 if (IS_P3P_TYPE(ha)) {
3598 if (!ha->nx_pcibase)
3599 iounmap((device_reg_t *)ha->nx_pcibase);
3600 if (!ql2xdbwr)
3601 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3602 } else {
3603 if (ha->iobase)
3604 iounmap(ha->iobase);
3605 if (ha->cregbase)
3606 iounmap(ha->cregbase);
3607 }
3608 pci_release_selected_regions(ha->pdev, ha->bars);
3609 kfree(ha);
3610
3611 disable_device:
3612 pci_disable_device(pdev);
3613 return ret;
3614 }
3615
__qla_set_remove_flag(scsi_qla_host_t * base_vha)3616 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3617 {
3618 scsi_qla_host_t *vp;
3619 unsigned long flags;
3620 struct qla_hw_data *ha;
3621
3622 if (!base_vha)
3623 return;
3624
3625 ha = base_vha->hw;
3626
3627 spin_lock_irqsave(&ha->vport_slock, flags);
3628 list_for_each_entry(vp, &ha->vp_list, list)
3629 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3630
3631 /*
3632 * Indicate device removal to prevent future board_disable
3633 * and wait until any pending board_disable has completed.
3634 */
3635 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3636 spin_unlock_irqrestore(&ha->vport_slock, flags);
3637 }
3638
3639 static void
qla2x00_shutdown(struct pci_dev * pdev)3640 qla2x00_shutdown(struct pci_dev *pdev)
3641 {
3642 scsi_qla_host_t *vha;
3643 struct qla_hw_data *ha;
3644
3645 vha = pci_get_drvdata(pdev);
3646 ha = vha->hw;
3647
3648 ql_log(ql_log_info, vha, 0xfffa,
3649 "Adapter shutdown\n");
3650
3651 /*
3652 * Prevent future board_disable and wait
3653 * until any pending board_disable has completed.
3654 */
3655 __qla_set_remove_flag(vha);
3656 cancel_work_sync(&ha->board_disable);
3657
3658 if (!atomic_read(&pdev->enable_cnt))
3659 return;
3660
3661 /* Notify ISPFX00 firmware */
3662 if (IS_QLAFX00(ha))
3663 qlafx00_driver_shutdown(vha, 20);
3664
3665 /* Turn-off FCE trace */
3666 if (ha->flags.fce_enabled) {
3667 qla2x00_disable_fce_trace(vha, NULL, NULL);
3668 ha->flags.fce_enabled = 0;
3669 }
3670
3671 /* Turn-off EFT trace */
3672 if (ha->eft)
3673 qla2x00_disable_eft_trace(vha);
3674
3675 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3676 IS_QLA28XX(ha)) {
3677 if (ha->flags.fw_started)
3678 qla2x00_abort_isp_cleanup(vha);
3679 } else {
3680 /* Stop currently executing firmware. */
3681 qla2x00_try_to_stop_firmware(vha);
3682 }
3683
3684 /* Disable timer */
3685 if (vha->timer_active)
3686 qla2x00_stop_timer(vha);
3687
3688 /* Turn adapter off line */
3689 vha->flags.online = 0;
3690
3691 /* turn-off interrupts on the card */
3692 if (ha->interrupts_on) {
3693 vha->flags.init_done = 0;
3694 ha->isp_ops->disable_intrs(ha);
3695 }
3696
3697 qla2x00_free_irqs(vha);
3698
3699 qla2x00_free_fw_dump(ha);
3700
3701 pci_disable_device(pdev);
3702 ql_log(ql_log_info, vha, 0xfffe,
3703 "Adapter shutdown successfully.\n");
3704 }
3705
3706 /* Deletes all the virtual ports for a given ha */
3707 static void
qla2x00_delete_all_vps(struct qla_hw_data * ha,scsi_qla_host_t * base_vha)3708 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3709 {
3710 scsi_qla_host_t *vha;
3711 unsigned long flags;
3712
3713 mutex_lock(&ha->vport_lock);
3714 while (ha->cur_vport_count) {
3715 spin_lock_irqsave(&ha->vport_slock, flags);
3716
3717 BUG_ON(base_vha->list.next == &ha->vp_list);
3718 /* This assumes first entry in ha->vp_list is always base vha */
3719 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3720 scsi_host_get(vha->host);
3721
3722 spin_unlock_irqrestore(&ha->vport_slock, flags);
3723 mutex_unlock(&ha->vport_lock);
3724
3725 qla_nvme_delete(vha);
3726
3727 fc_vport_terminate(vha->fc_vport);
3728 scsi_host_put(vha->host);
3729
3730 mutex_lock(&ha->vport_lock);
3731 }
3732 mutex_unlock(&ha->vport_lock);
3733 }
3734
3735 /* Stops all deferred work threads */
3736 static void
qla2x00_destroy_deferred_work(struct qla_hw_data * ha)3737 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3738 {
3739 /* Cancel all work and destroy DPC workqueues */
3740 if (ha->dpc_lp_wq) {
3741 cancel_work_sync(&ha->idc_aen);
3742 destroy_workqueue(ha->dpc_lp_wq);
3743 ha->dpc_lp_wq = NULL;
3744 }
3745
3746 if (ha->dpc_hp_wq) {
3747 cancel_work_sync(&ha->nic_core_reset);
3748 cancel_work_sync(&ha->idc_state_handler);
3749 cancel_work_sync(&ha->nic_core_unrecoverable);
3750 destroy_workqueue(ha->dpc_hp_wq);
3751 ha->dpc_hp_wq = NULL;
3752 }
3753
3754 /* Kill the kernel thread for this host */
3755 if (ha->dpc_thread) {
3756 struct task_struct *t = ha->dpc_thread;
3757
3758 /*
3759 * qla2xxx_wake_dpc checks for ->dpc_thread
3760 * so we need to zero it out.
3761 */
3762 ha->dpc_thread = NULL;
3763 kthread_stop(t);
3764 }
3765 }
3766
3767 static void
qla2x00_unmap_iobases(struct qla_hw_data * ha)3768 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3769 {
3770 if (IS_QLA82XX(ha)) {
3771
3772 iounmap((device_reg_t *)ha->nx_pcibase);
3773 if (!ql2xdbwr)
3774 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3775 } else {
3776 if (ha->iobase)
3777 iounmap(ha->iobase);
3778
3779 if (ha->cregbase)
3780 iounmap(ha->cregbase);
3781
3782 if (ha->mqiobase)
3783 iounmap(ha->mqiobase);
3784
3785 if (ha->msixbase)
3786 iounmap(ha->msixbase);
3787 }
3788 }
3789
3790 static void
qla2x00_clear_drv_active(struct qla_hw_data * ha)3791 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3792 {
3793 if (IS_QLA8044(ha)) {
3794 qla8044_idc_lock(ha);
3795 qla8044_clear_drv_active(ha);
3796 qla8044_idc_unlock(ha);
3797 } else if (IS_QLA82XX(ha)) {
3798 qla82xx_idc_lock(ha);
3799 qla82xx_clear_drv_active(ha);
3800 qla82xx_idc_unlock(ha);
3801 }
3802 }
3803
3804 static void
qla2x00_remove_one(struct pci_dev * pdev)3805 qla2x00_remove_one(struct pci_dev *pdev)
3806 {
3807 scsi_qla_host_t *base_vha;
3808 struct qla_hw_data *ha;
3809
3810 base_vha = pci_get_drvdata(pdev);
3811 ha = base_vha->hw;
3812 ql_log(ql_log_info, base_vha, 0xb079,
3813 "Removing driver\n");
3814 __qla_set_remove_flag(base_vha);
3815 cancel_work_sync(&ha->board_disable);
3816
3817 /*
3818 * If the PCI device is disabled then there was a PCI-disconnect and
3819 * qla2x00_disable_board_on_pci_error has taken care of most of the
3820 * resources.
3821 */
3822 if (!atomic_read(&pdev->enable_cnt)) {
3823 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3824 base_vha->gnl.l, base_vha->gnl.ldma);
3825 base_vha->gnl.l = NULL;
3826 scsi_host_put(base_vha->host);
3827 kfree(ha);
3828 pci_set_drvdata(pdev, NULL);
3829 return;
3830 }
3831 qla2x00_wait_for_hba_ready(base_vha);
3832
3833 /*
3834 * if UNLOADING flag is already set, then continue unload,
3835 * where it was set first.
3836 */
3837 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3838 return;
3839
3840 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3841 IS_QLA28XX(ha)) {
3842 if (ha->flags.fw_started)
3843 qla2x00_abort_isp_cleanup(base_vha);
3844 } else if (!IS_QLAFX00(ha)) {
3845 if (IS_QLA8031(ha)) {
3846 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3847 "Clearing fcoe driver presence.\n");
3848 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3849 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3850 "Error while clearing DRV-Presence.\n");
3851 }
3852
3853 qla2x00_try_to_stop_firmware(base_vha);
3854 }
3855
3856 qla2x00_wait_for_sess_deletion(base_vha);
3857
3858 qla_nvme_delete(base_vha);
3859
3860 dma_free_coherent(&ha->pdev->dev,
3861 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3862
3863 base_vha->gnl.l = NULL;
3864 qla_enode_stop(base_vha);
3865 qla_edb_stop(base_vha);
3866
3867 vfree(base_vha->scan.l);
3868
3869 if (IS_QLAFX00(ha))
3870 qlafx00_driver_shutdown(base_vha, 20);
3871
3872 qla2x00_delete_all_vps(ha, base_vha);
3873
3874 qla2x00_dfs_remove(base_vha);
3875
3876 qla84xx_put_chip(base_vha);
3877
3878 /* Disable timer */
3879 if (base_vha->timer_active)
3880 qla2x00_stop_timer(base_vha);
3881
3882 base_vha->flags.online = 0;
3883
3884 /* free DMA memory */
3885 if (ha->exlogin_buf)
3886 qla2x00_free_exlogin_buffer(ha);
3887
3888 /* free DMA memory */
3889 if (ha->exchoffld_buf)
3890 qla2x00_free_exchoffld_buffer(ha);
3891
3892 qla2x00_destroy_deferred_work(ha);
3893
3894 qlt_remove_target(ha, base_vha);
3895
3896 qla2x00_free_sysfs_attr(base_vha, true);
3897
3898 fc_remove_host(base_vha->host);
3899
3900 scsi_remove_host(base_vha->host);
3901
3902 qla2x00_free_device(base_vha);
3903
3904 qla2x00_clear_drv_active(ha);
3905
3906 scsi_host_put(base_vha->host);
3907
3908 qla2x00_unmap_iobases(ha);
3909
3910 pci_release_selected_regions(ha->pdev, ha->bars);
3911 kfree(ha);
3912
3913 pci_disable_pcie_error_reporting(pdev);
3914
3915 pci_disable_device(pdev);
3916 }
3917
3918 static inline void
qla24xx_free_purex_list(struct purex_list * list)3919 qla24xx_free_purex_list(struct purex_list *list)
3920 {
3921 struct purex_item *item, *next;
3922 ulong flags;
3923
3924 spin_lock_irqsave(&list->lock, flags);
3925 list_for_each_entry_safe(item, next, &list->head, list) {
3926 list_del(&item->list);
3927 if (item == &item->vha->default_item)
3928 continue;
3929 kfree(item);
3930 }
3931 spin_unlock_irqrestore(&list->lock, flags);
3932 }
3933
3934 static void
qla2x00_free_device(scsi_qla_host_t * vha)3935 qla2x00_free_device(scsi_qla_host_t *vha)
3936 {
3937 struct qla_hw_data *ha = vha->hw;
3938
3939 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3940
3941 /* Disable timer */
3942 if (vha->timer_active)
3943 qla2x00_stop_timer(vha);
3944
3945 qla25xx_delete_queues(vha);
3946 vha->flags.online = 0;
3947
3948 /* turn-off interrupts on the card */
3949 if (ha->interrupts_on) {
3950 vha->flags.init_done = 0;
3951 ha->isp_ops->disable_intrs(ha);
3952 }
3953
3954 qla2x00_free_fcports(vha);
3955
3956 qla2x00_free_irqs(vha);
3957
3958 /* Flush the work queue and remove it */
3959 if (ha->wq) {
3960 destroy_workqueue(ha->wq);
3961 ha->wq = NULL;
3962 }
3963
3964
3965 qla24xx_free_purex_list(&vha->purex_list);
3966
3967 qla2x00_mem_free(ha);
3968
3969 qla82xx_md_free(vha);
3970
3971 qla_edif_sadb_release_free_pool(ha);
3972 qla_edif_sadb_release(ha);
3973
3974 qla2x00_free_queues(ha);
3975 }
3976
qla2x00_free_fcports(struct scsi_qla_host * vha)3977 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3978 {
3979 fc_port_t *fcport, *tfcport;
3980
3981 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
3982 qla2x00_free_fcport(fcport);
3983 }
3984
3985 static inline void
qla2x00_schedule_rport_del(struct scsi_qla_host * vha,fc_port_t * fcport)3986 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
3987 {
3988 int now;
3989
3990 if (!fcport->rport)
3991 return;
3992
3993 if (fcport->rport) {
3994 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3995 "%s %8phN. rport %p roles %x\n",
3996 __func__, fcport->port_name, fcport->rport,
3997 fcport->rport->roles);
3998 fc_remote_port_delete(fcport->rport);
3999 }
4000 qlt_do_generation_tick(vha, &now);
4001 }
4002
4003 /*
4004 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
4005 *
4006 * Input: ha = adapter block pointer. fcport = port structure pointer.
4007 *
4008 * Return: None.
4009 *
4010 * Context:
4011 */
qla2x00_mark_device_lost(scsi_qla_host_t * vha,fc_port_t * fcport,int do_login)4012 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
4013 int do_login)
4014 {
4015 if (IS_QLAFX00(vha->hw)) {
4016 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4017 qla2x00_schedule_rport_del(vha, fcport);
4018 return;
4019 }
4020
4021 if (atomic_read(&fcport->state) == FCS_ONLINE &&
4022 vha->vp_idx == fcport->vha->vp_idx) {
4023 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4024 qla2x00_schedule_rport_del(vha, fcport);
4025 }
4026
4027 /*
4028 * We may need to retry the login, so don't change the state of the
4029 * port but do the retries.
4030 */
4031 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
4032 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4033
4034 if (!do_login)
4035 return;
4036
4037 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4038 }
4039
4040 void
qla2x00_mark_all_devices_lost(scsi_qla_host_t * vha)4041 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
4042 {
4043 fc_port_t *fcport;
4044
4045 ql_dbg(ql_dbg_disc, vha, 0x20f1,
4046 "Mark all dev lost\n");
4047
4048 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4049 if (fcport->loop_id != FC_NO_LOOP_ID &&
4050 (fcport->flags & FCF_FCP2_DEVICE) &&
4051 fcport->port_type == FCT_TARGET &&
4052 !qla2x00_reset_active(vha)) {
4053 ql_dbg(ql_dbg_disc, vha, 0x211a,
4054 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC",
4055 fcport->flags, fcport->port_type,
4056 fcport->d_id.b24, fcport->port_name);
4057 continue;
4058 }
4059 fcport->scan_state = 0;
4060 qlt_schedule_sess_for_deletion(fcport);
4061 }
4062 }
4063
qla2x00_set_reserved_loop_ids(struct qla_hw_data * ha)4064 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
4065 {
4066 int i;
4067
4068 if (IS_FWI2_CAPABLE(ha))
4069 return;
4070
4071 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
4072 set_bit(i, ha->loop_id_map);
4073 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
4074 set_bit(BROADCAST, ha->loop_id_map);
4075 }
4076
4077 /*
4078 * qla2x00_mem_alloc
4079 * Allocates adapter memory.
4080 *
4081 * Returns:
4082 * 0 = success.
4083 * !0 = failure.
4084 */
4085 static int
qla2x00_mem_alloc(struct qla_hw_data * ha,uint16_t req_len,uint16_t rsp_len,struct req_que ** req,struct rsp_que ** rsp)4086 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
4087 struct req_que **req, struct rsp_que **rsp)
4088 {
4089 char name[16];
4090 int rc;
4091
4092 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
4093 &ha->init_cb_dma, GFP_KERNEL);
4094 if (!ha->init_cb)
4095 goto fail;
4096
4097 rc = btree_init32(&ha->host_map);
4098 if (rc)
4099 goto fail_free_init_cb;
4100
4101 if (qlt_mem_alloc(ha) < 0)
4102 goto fail_free_btree;
4103
4104 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4105 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
4106 if (!ha->gid_list)
4107 goto fail_free_tgt_mem;
4108
4109 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4110 if (!ha->srb_mempool)
4111 goto fail_free_gid_list;
4112
4113 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) {
4114 /* Allocate cache for CT6 Ctx. */
4115 if (!ctx_cachep) {
4116 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4117 sizeof(struct ct6_dsd), 0,
4118 SLAB_HWCACHE_ALIGN, NULL);
4119 if (!ctx_cachep)
4120 goto fail_free_srb_mempool;
4121 }
4122 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4123 ctx_cachep);
4124 if (!ha->ctx_mempool)
4125 goto fail_free_srb_mempool;
4126 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4127 "ctx_cachep=%p ctx_mempool=%p.\n",
4128 ctx_cachep, ha->ctx_mempool);
4129 }
4130
4131 /* Get memory for cached NVRAM */
4132 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4133 if (!ha->nvram)
4134 goto fail_free_ctx_mempool;
4135
4136 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4137 ha->pdev->device);
4138 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4139 DMA_POOL_SIZE, 8, 0);
4140 if (!ha->s_dma_pool)
4141 goto fail_free_nvram;
4142
4143 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4144 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4145 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4146
4147 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) {
4148 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4149 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4150 if (!ha->dl_dma_pool) {
4151 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4152 "Failed to allocate memory for dl_dma_pool.\n");
4153 goto fail_s_dma_pool;
4154 }
4155
4156 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4157 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4158 if (!ha->fcp_cmnd_dma_pool) {
4159 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4160 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4161 goto fail_dl_dma_pool;
4162 }
4163
4164 if (ql2xenabledif) {
4165 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4166 struct dsd_dma *dsd, *nxt;
4167 uint i;
4168 /* Creata a DMA pool of buffers for DIF bundling */
4169 ha->dif_bundl_pool = dma_pool_create(name,
4170 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4171 if (!ha->dif_bundl_pool) {
4172 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4173 "%s: failed create dif_bundl_pool\n",
4174 __func__);
4175 goto fail_dif_bundl_dma_pool;
4176 }
4177
4178 INIT_LIST_HEAD(&ha->pool.good.head);
4179 INIT_LIST_HEAD(&ha->pool.unusable.head);
4180 ha->pool.good.count = 0;
4181 ha->pool.unusable.count = 0;
4182 for (i = 0; i < 128; i++) {
4183 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4184 if (!dsd) {
4185 ql_dbg_pci(ql_dbg_init, ha->pdev,
4186 0xe0ee, "%s: failed alloc dsd\n",
4187 __func__);
4188 return -ENOMEM;
4189 }
4190 ha->dif_bundle_kallocs++;
4191
4192 dsd->dsd_addr = dma_pool_alloc(
4193 ha->dif_bundl_pool, GFP_ATOMIC,
4194 &dsd->dsd_list_dma);
4195 if (!dsd->dsd_addr) {
4196 ql_dbg_pci(ql_dbg_init, ha->pdev,
4197 0xe0ee,
4198 "%s: failed alloc ->dsd_addr\n",
4199 __func__);
4200 kfree(dsd);
4201 ha->dif_bundle_kallocs--;
4202 continue;
4203 }
4204 ha->dif_bundle_dma_allocs++;
4205
4206 /*
4207 * if DMA buffer crosses 4G boundary,
4208 * put it on bad list
4209 */
4210 if (MSD(dsd->dsd_list_dma) ^
4211 MSD(dsd->dsd_list_dma + bufsize)) {
4212 list_add_tail(&dsd->list,
4213 &ha->pool.unusable.head);
4214 ha->pool.unusable.count++;
4215 } else {
4216 list_add_tail(&dsd->list,
4217 &ha->pool.good.head);
4218 ha->pool.good.count++;
4219 }
4220 }
4221
4222 /* return the good ones back to the pool */
4223 list_for_each_entry_safe(dsd, nxt,
4224 &ha->pool.good.head, list) {
4225 list_del(&dsd->list);
4226 dma_pool_free(ha->dif_bundl_pool,
4227 dsd->dsd_addr, dsd->dsd_list_dma);
4228 ha->dif_bundle_dma_allocs--;
4229 kfree(dsd);
4230 ha->dif_bundle_kallocs--;
4231 }
4232
4233 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4234 "%s: dif dma pool (good=%u unusable=%u)\n",
4235 __func__, ha->pool.good.count,
4236 ha->pool.unusable.count);
4237 }
4238
4239 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4240 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4241 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4242 ha->dif_bundl_pool);
4243 }
4244
4245 /* Allocate memory for SNS commands */
4246 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4247 /* Get consistent memory allocated for SNS commands */
4248 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4249 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4250 if (!ha->sns_cmd)
4251 goto fail_dma_pool;
4252 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4253 "sns_cmd: %p.\n", ha->sns_cmd);
4254 } else {
4255 /* Get consistent memory allocated for MS IOCB */
4256 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4257 &ha->ms_iocb_dma);
4258 if (!ha->ms_iocb)
4259 goto fail_dma_pool;
4260 /* Get consistent memory allocated for CT SNS commands */
4261 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4262 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4263 if (!ha->ct_sns)
4264 goto fail_free_ms_iocb;
4265 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4266 "ms_iocb=%p ct_sns=%p.\n",
4267 ha->ms_iocb, ha->ct_sns);
4268 }
4269
4270 /* Allocate memory for request ring */
4271 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4272 if (!*req) {
4273 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4274 "Failed to allocate memory for req.\n");
4275 goto fail_req;
4276 }
4277 (*req)->length = req_len;
4278 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4279 ((*req)->length + 1) * sizeof(request_t),
4280 &(*req)->dma, GFP_KERNEL);
4281 if (!(*req)->ring) {
4282 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4283 "Failed to allocate memory for req_ring.\n");
4284 goto fail_req_ring;
4285 }
4286 /* Allocate memory for response ring */
4287 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4288 if (!*rsp) {
4289 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4290 "Failed to allocate memory for rsp.\n");
4291 goto fail_rsp;
4292 }
4293 (*rsp)->hw = ha;
4294 (*rsp)->length = rsp_len;
4295 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4296 ((*rsp)->length + 1) * sizeof(response_t),
4297 &(*rsp)->dma, GFP_KERNEL);
4298 if (!(*rsp)->ring) {
4299 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4300 "Failed to allocate memory for rsp_ring.\n");
4301 goto fail_rsp_ring;
4302 }
4303 (*req)->rsp = *rsp;
4304 (*rsp)->req = *req;
4305 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4306 "req=%p req->length=%d req->ring=%p rsp=%p "
4307 "rsp->length=%d rsp->ring=%p.\n",
4308 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4309 (*rsp)->ring);
4310 /* Allocate memory for NVRAM data for vports */
4311 if (ha->nvram_npiv_size) {
4312 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4313 sizeof(struct qla_npiv_entry),
4314 GFP_KERNEL);
4315 if (!ha->npiv_info) {
4316 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4317 "Failed to allocate memory for npiv_info.\n");
4318 goto fail_npiv_info;
4319 }
4320 } else
4321 ha->npiv_info = NULL;
4322
4323 /* Get consistent memory allocated for EX-INIT-CB. */
4324 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4325 IS_QLA28XX(ha)) {
4326 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4327 &ha->ex_init_cb_dma);
4328 if (!ha->ex_init_cb)
4329 goto fail_ex_init_cb;
4330 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4331 "ex_init_cb=%p.\n", ha->ex_init_cb);
4332 }
4333
4334 /* Get consistent memory allocated for Special Features-CB. */
4335 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4336 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL,
4337 &ha->sf_init_cb_dma);
4338 if (!ha->sf_init_cb)
4339 goto fail_sf_init_cb;
4340 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4341 "sf_init_cb=%p.\n", ha->sf_init_cb);
4342 }
4343
4344 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4345
4346 /* Get consistent memory allocated for Async Port-Database. */
4347 if (!IS_FWI2_CAPABLE(ha)) {
4348 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4349 &ha->async_pd_dma);
4350 if (!ha->async_pd)
4351 goto fail_async_pd;
4352 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4353 "async_pd=%p.\n", ha->async_pd);
4354 }
4355
4356 INIT_LIST_HEAD(&ha->vp_list);
4357
4358 /* Allocate memory for our loop_id bitmap */
4359 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4360 sizeof(long),
4361 GFP_KERNEL);
4362 if (!ha->loop_id_map)
4363 goto fail_loop_id_map;
4364 else {
4365 qla2x00_set_reserved_loop_ids(ha);
4366 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4367 "loop_id_map=%p.\n", ha->loop_id_map);
4368 }
4369
4370 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4371 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4372 if (!ha->sfp_data) {
4373 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4374 "Unable to allocate memory for SFP read-data.\n");
4375 goto fail_sfp_data;
4376 }
4377
4378 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4379 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4380 GFP_KERNEL);
4381 if (!ha->flt) {
4382 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4383 "Unable to allocate memory for FLT.\n");
4384 goto fail_flt_buffer;
4385 }
4386
4387 /* allocate the purex dma pool */
4388 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4389 ELS_MAX_PAYLOAD, 8, 0);
4390
4391 if (!ha->purex_dma_pool) {
4392 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4393 "Unable to allocate purex_dma_pool.\n");
4394 goto fail_flt;
4395 }
4396
4397 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16;
4398 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev,
4399 ha->elsrej.size, &ha->elsrej.cdma, GFP_KERNEL);
4400
4401 if (!ha->elsrej.c) {
4402 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4403 "Alloc failed for els reject cmd.\n");
4404 goto fail_elsrej;
4405 }
4406 ha->elsrej.c->er_cmd = ELS_LS_RJT;
4407 ha->elsrej.c->er_reason = ELS_RJT_LOGIC;
4408 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA;
4409 return 0;
4410
4411 fail_elsrej:
4412 dma_pool_destroy(ha->purex_dma_pool);
4413 fail_flt:
4414 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4415 ha->flt, ha->flt_dma);
4416
4417 fail_flt_buffer:
4418 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4419 ha->sfp_data, ha->sfp_data_dma);
4420 fail_sfp_data:
4421 kfree(ha->loop_id_map);
4422 fail_loop_id_map:
4423 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4424 fail_async_pd:
4425 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4426 fail_sf_init_cb:
4427 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4428 fail_ex_init_cb:
4429 kfree(ha->npiv_info);
4430 fail_npiv_info:
4431 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4432 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4433 (*rsp)->ring = NULL;
4434 (*rsp)->dma = 0;
4435 fail_rsp_ring:
4436 kfree(*rsp);
4437 *rsp = NULL;
4438 fail_rsp:
4439 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4440 sizeof(request_t), (*req)->ring, (*req)->dma);
4441 (*req)->ring = NULL;
4442 (*req)->dma = 0;
4443 fail_req_ring:
4444 kfree(*req);
4445 *req = NULL;
4446 fail_req:
4447 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4448 ha->ct_sns, ha->ct_sns_dma);
4449 ha->ct_sns = NULL;
4450 ha->ct_sns_dma = 0;
4451 fail_free_ms_iocb:
4452 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4453 ha->ms_iocb = NULL;
4454 ha->ms_iocb_dma = 0;
4455
4456 if (ha->sns_cmd)
4457 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4458 ha->sns_cmd, ha->sns_cmd_dma);
4459 fail_dma_pool:
4460 if (ql2xenabledif) {
4461 struct dsd_dma *dsd, *nxt;
4462
4463 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4464 list) {
4465 list_del(&dsd->list);
4466 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4467 dsd->dsd_list_dma);
4468 ha->dif_bundle_dma_allocs--;
4469 kfree(dsd);
4470 ha->dif_bundle_kallocs--;
4471 ha->pool.unusable.count--;
4472 }
4473 dma_pool_destroy(ha->dif_bundl_pool);
4474 ha->dif_bundl_pool = NULL;
4475 }
4476
4477 fail_dif_bundl_dma_pool:
4478 if (IS_QLA82XX(ha) || ql2xenabledif) {
4479 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4480 ha->fcp_cmnd_dma_pool = NULL;
4481 }
4482 fail_dl_dma_pool:
4483 if (IS_QLA82XX(ha) || ql2xenabledif) {
4484 dma_pool_destroy(ha->dl_dma_pool);
4485 ha->dl_dma_pool = NULL;
4486 }
4487 fail_s_dma_pool:
4488 dma_pool_destroy(ha->s_dma_pool);
4489 ha->s_dma_pool = NULL;
4490 fail_free_nvram:
4491 kfree(ha->nvram);
4492 ha->nvram = NULL;
4493 fail_free_ctx_mempool:
4494 mempool_destroy(ha->ctx_mempool);
4495 ha->ctx_mempool = NULL;
4496 fail_free_srb_mempool:
4497 mempool_destroy(ha->srb_mempool);
4498 ha->srb_mempool = NULL;
4499 fail_free_gid_list:
4500 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4501 ha->gid_list,
4502 ha->gid_list_dma);
4503 ha->gid_list = NULL;
4504 ha->gid_list_dma = 0;
4505 fail_free_tgt_mem:
4506 qlt_mem_free(ha);
4507 fail_free_btree:
4508 btree_destroy32(&ha->host_map);
4509 fail_free_init_cb:
4510 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4511 ha->init_cb_dma);
4512 ha->init_cb = NULL;
4513 ha->init_cb_dma = 0;
4514 fail:
4515 ql_log(ql_log_fatal, NULL, 0x0030,
4516 "Memory allocation failure.\n");
4517 return -ENOMEM;
4518 }
4519
4520 int
qla2x00_set_exlogins_buffer(scsi_qla_host_t * vha)4521 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4522 {
4523 int rval;
4524 uint16_t size, max_cnt;
4525 uint32_t temp;
4526 struct qla_hw_data *ha = vha->hw;
4527
4528 /* Return if we don't need to alloacate any extended logins */
4529 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400)
4530 return QLA_SUCCESS;
4531
4532 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4533 return QLA_SUCCESS;
4534
4535 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4536 max_cnt = 0;
4537 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4538 if (rval != QLA_SUCCESS) {
4539 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4540 "Failed to get exlogin status.\n");
4541 return rval;
4542 }
4543
4544 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4545 temp *= size;
4546
4547 if (temp != ha->exlogin_size) {
4548 qla2x00_free_exlogin_buffer(ha);
4549 ha->exlogin_size = temp;
4550
4551 ql_log(ql_log_info, vha, 0xd024,
4552 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4553 max_cnt, size, temp);
4554
4555 ql_log(ql_log_info, vha, 0xd025,
4556 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4557
4558 /* Get consistent memory for extended logins */
4559 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4560 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4561 if (!ha->exlogin_buf) {
4562 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4563 "Failed to allocate memory for exlogin_buf_dma.\n");
4564 return -ENOMEM;
4565 }
4566 }
4567
4568 /* Now configure the dma buffer */
4569 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4570 if (rval) {
4571 ql_log(ql_log_fatal, vha, 0xd033,
4572 "Setup extended login buffer ****FAILED****.\n");
4573 qla2x00_free_exlogin_buffer(ha);
4574 }
4575
4576 return rval;
4577 }
4578
4579 /*
4580 * qla2x00_free_exlogin_buffer
4581 *
4582 * Input:
4583 * ha = adapter block pointer
4584 */
4585 void
qla2x00_free_exlogin_buffer(struct qla_hw_data * ha)4586 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4587 {
4588 if (ha->exlogin_buf) {
4589 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4590 ha->exlogin_buf, ha->exlogin_buf_dma);
4591 ha->exlogin_buf = NULL;
4592 ha->exlogin_size = 0;
4593 }
4594 }
4595
4596 static void
qla2x00_number_of_exch(scsi_qla_host_t * vha,u32 * ret_cnt,u16 max_cnt)4597 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4598 {
4599 u32 temp;
4600 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
4601 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4602
4603 if (max_cnt > vha->hw->max_exchg)
4604 max_cnt = vha->hw->max_exchg;
4605
4606 if (qla_ini_mode_enabled(vha)) {
4607 if (vha->ql2xiniexchg > max_cnt)
4608 vha->ql2xiniexchg = max_cnt;
4609
4610 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4611 *ret_cnt = vha->ql2xiniexchg;
4612
4613 } else if (qla_tgt_mode_enabled(vha)) {
4614 if (vha->ql2xexchoffld > max_cnt) {
4615 vha->ql2xexchoffld = max_cnt;
4616 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4617 }
4618
4619 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4620 *ret_cnt = vha->ql2xexchoffld;
4621 } else if (qla_dual_mode_enabled(vha)) {
4622 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4623 if (temp > max_cnt) {
4624 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4625 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4626 temp = max_cnt;
4627 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4628 }
4629
4630 if (temp > FW_DEF_EXCHANGES_CNT)
4631 *ret_cnt = temp;
4632 }
4633 }
4634
4635 int
qla2x00_set_exchoffld_buffer(scsi_qla_host_t * vha)4636 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4637 {
4638 int rval;
4639 u16 size, max_cnt;
4640 u32 actual_cnt, totsz;
4641 struct qla_hw_data *ha = vha->hw;
4642
4643 if (!ha->flags.exchoffld_enabled)
4644 return QLA_SUCCESS;
4645
4646 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4647 return QLA_SUCCESS;
4648
4649 max_cnt = 0;
4650 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4651 if (rval != QLA_SUCCESS) {
4652 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4653 "Failed to get exlogin status.\n");
4654 return rval;
4655 }
4656
4657 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4658 ql_log(ql_log_info, vha, 0xd014,
4659 "Actual exchange offload count: %d.\n", actual_cnt);
4660
4661 totsz = actual_cnt * size;
4662
4663 if (totsz != ha->exchoffld_size) {
4664 qla2x00_free_exchoffld_buffer(ha);
4665 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4666 ha->exchoffld_size = 0;
4667 ha->flags.exchoffld_enabled = 0;
4668 return QLA_SUCCESS;
4669 }
4670
4671 ha->exchoffld_size = totsz;
4672
4673 ql_log(ql_log_info, vha, 0xd016,
4674 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4675 max_cnt, actual_cnt, size, totsz);
4676
4677 ql_log(ql_log_info, vha, 0xd017,
4678 "Exchange Buffers requested size = 0x%x\n",
4679 ha->exchoffld_size);
4680
4681 /* Get consistent memory for extended logins */
4682 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4683 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4684 if (!ha->exchoffld_buf) {
4685 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4686 "Failed to allocate memory for Exchange Offload.\n");
4687
4688 if (ha->max_exchg >
4689 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4690 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4691 } else if (ha->max_exchg >
4692 (FW_DEF_EXCHANGES_CNT + 512)) {
4693 ha->max_exchg -= 512;
4694 } else {
4695 ha->flags.exchoffld_enabled = 0;
4696 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4697 "Disabling Exchange offload due to lack of memory\n");
4698 }
4699 ha->exchoffld_size = 0;
4700
4701 return -ENOMEM;
4702 }
4703 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4704 /* pathological case */
4705 qla2x00_free_exchoffld_buffer(ha);
4706 ha->exchoffld_size = 0;
4707 ha->flags.exchoffld_enabled = 0;
4708 ql_log(ql_log_info, vha, 0xd016,
4709 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4710 ha->exchoffld_size, actual_cnt, size, totsz);
4711 return 0;
4712 }
4713
4714 /* Now configure the dma buffer */
4715 rval = qla_set_exchoffld_mem_cfg(vha);
4716 if (rval) {
4717 ql_log(ql_log_fatal, vha, 0xd02e,
4718 "Setup exchange offload buffer ****FAILED****.\n");
4719 qla2x00_free_exchoffld_buffer(ha);
4720 } else {
4721 /* re-adjust number of target exchange */
4722 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4723
4724 if (qla_ini_mode_enabled(vha))
4725 icb->exchange_count = 0;
4726 else
4727 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4728 }
4729
4730 return rval;
4731 }
4732
4733 /*
4734 * qla2x00_free_exchoffld_buffer
4735 *
4736 * Input:
4737 * ha = adapter block pointer
4738 */
4739 void
qla2x00_free_exchoffld_buffer(struct qla_hw_data * ha)4740 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4741 {
4742 if (ha->exchoffld_buf) {
4743 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4744 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4745 ha->exchoffld_buf = NULL;
4746 ha->exchoffld_size = 0;
4747 }
4748 }
4749
4750 /*
4751 * qla2x00_free_fw_dump
4752 * Frees fw dump stuff.
4753 *
4754 * Input:
4755 * ha = adapter block pointer
4756 */
4757 static void
qla2x00_free_fw_dump(struct qla_hw_data * ha)4758 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4759 {
4760 struct fwdt *fwdt = ha->fwdt;
4761 uint j;
4762
4763 if (ha->fce)
4764 dma_free_coherent(&ha->pdev->dev,
4765 FCE_SIZE, ha->fce, ha->fce_dma);
4766
4767 if (ha->eft)
4768 dma_free_coherent(&ha->pdev->dev,
4769 EFT_SIZE, ha->eft, ha->eft_dma);
4770
4771 vfree(ha->fw_dump);
4772
4773 ha->fce = NULL;
4774 ha->fce_dma = 0;
4775 ha->flags.fce_enabled = 0;
4776 ha->eft = NULL;
4777 ha->eft_dma = 0;
4778 ha->fw_dumped = false;
4779 ha->fw_dump_cap_flags = 0;
4780 ha->fw_dump_reading = 0;
4781 ha->fw_dump = NULL;
4782 ha->fw_dump_len = 0;
4783
4784 for (j = 0; j < 2; j++, fwdt++) {
4785 vfree(fwdt->template);
4786 fwdt->template = NULL;
4787 fwdt->length = 0;
4788 }
4789 }
4790
4791 /*
4792 * qla2x00_mem_free
4793 * Frees all adapter allocated memory.
4794 *
4795 * Input:
4796 * ha = adapter block pointer.
4797 */
4798 static void
qla2x00_mem_free(struct qla_hw_data * ha)4799 qla2x00_mem_free(struct qla_hw_data *ha)
4800 {
4801 qla2x00_free_fw_dump(ha);
4802
4803 if (ha->mctp_dump)
4804 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4805 ha->mctp_dump_dma);
4806 ha->mctp_dump = NULL;
4807
4808 mempool_destroy(ha->srb_mempool);
4809 ha->srb_mempool = NULL;
4810
4811 if (ha->dcbx_tlv)
4812 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4813 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4814 ha->dcbx_tlv = NULL;
4815
4816 if (ha->xgmac_data)
4817 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4818 ha->xgmac_data, ha->xgmac_data_dma);
4819 ha->xgmac_data = NULL;
4820
4821 if (ha->sns_cmd)
4822 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4823 ha->sns_cmd, ha->sns_cmd_dma);
4824 ha->sns_cmd = NULL;
4825 ha->sns_cmd_dma = 0;
4826
4827 if (ha->ct_sns)
4828 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4829 ha->ct_sns, ha->ct_sns_dma);
4830 ha->ct_sns = NULL;
4831 ha->ct_sns_dma = 0;
4832
4833 if (ha->sfp_data)
4834 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4835 ha->sfp_data_dma);
4836 ha->sfp_data = NULL;
4837
4838 if (ha->flt)
4839 dma_free_coherent(&ha->pdev->dev,
4840 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4841 ha->flt, ha->flt_dma);
4842 ha->flt = NULL;
4843 ha->flt_dma = 0;
4844
4845 if (ha->ms_iocb)
4846 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4847 ha->ms_iocb = NULL;
4848 ha->ms_iocb_dma = 0;
4849
4850 if (ha->sf_init_cb)
4851 dma_pool_free(ha->s_dma_pool,
4852 ha->sf_init_cb, ha->sf_init_cb_dma);
4853
4854 if (ha->ex_init_cb)
4855 dma_pool_free(ha->s_dma_pool,
4856 ha->ex_init_cb, ha->ex_init_cb_dma);
4857 ha->ex_init_cb = NULL;
4858 ha->ex_init_cb_dma = 0;
4859
4860 if (ha->async_pd)
4861 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4862 ha->async_pd = NULL;
4863 ha->async_pd_dma = 0;
4864
4865 dma_pool_destroy(ha->s_dma_pool);
4866 ha->s_dma_pool = NULL;
4867
4868 if (ha->gid_list)
4869 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4870 ha->gid_list, ha->gid_list_dma);
4871 ha->gid_list = NULL;
4872 ha->gid_list_dma = 0;
4873
4874 if (IS_QLA82XX(ha)) {
4875 if (!list_empty(&ha->gbl_dsd_list)) {
4876 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4877
4878 /* clean up allocated prev pool */
4879 list_for_each_entry_safe(dsd_ptr,
4880 tdsd_ptr, &ha->gbl_dsd_list, list) {
4881 dma_pool_free(ha->dl_dma_pool,
4882 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4883 list_del(&dsd_ptr->list);
4884 kfree(dsd_ptr);
4885 }
4886 }
4887 }
4888
4889 dma_pool_destroy(ha->dl_dma_pool);
4890 ha->dl_dma_pool = NULL;
4891
4892 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4893 ha->fcp_cmnd_dma_pool = NULL;
4894
4895 mempool_destroy(ha->ctx_mempool);
4896 ha->ctx_mempool = NULL;
4897
4898 if (ql2xenabledif && ha->dif_bundl_pool) {
4899 struct dsd_dma *dsd, *nxt;
4900
4901 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4902 list) {
4903 list_del(&dsd->list);
4904 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4905 dsd->dsd_list_dma);
4906 ha->dif_bundle_dma_allocs--;
4907 kfree(dsd);
4908 ha->dif_bundle_kallocs--;
4909 ha->pool.unusable.count--;
4910 }
4911 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4912 list_del(&dsd->list);
4913 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4914 dsd->dsd_list_dma);
4915 ha->dif_bundle_dma_allocs--;
4916 kfree(dsd);
4917 ha->dif_bundle_kallocs--;
4918 }
4919 }
4920
4921 dma_pool_destroy(ha->dif_bundl_pool);
4922 ha->dif_bundl_pool = NULL;
4923
4924 qlt_mem_free(ha);
4925 qla_remove_hostmap(ha);
4926
4927 if (ha->init_cb)
4928 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
4929 ha->init_cb, ha->init_cb_dma);
4930
4931 dma_pool_destroy(ha->purex_dma_pool);
4932 ha->purex_dma_pool = NULL;
4933
4934 if (ha->elsrej.c) {
4935 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
4936 ha->elsrej.c, ha->elsrej.cdma);
4937 ha->elsrej.c = NULL;
4938 }
4939
4940 ha->init_cb = NULL;
4941 ha->init_cb_dma = 0;
4942
4943 vfree(ha->optrom_buffer);
4944 ha->optrom_buffer = NULL;
4945 kfree(ha->nvram);
4946 ha->nvram = NULL;
4947 kfree(ha->npiv_info);
4948 ha->npiv_info = NULL;
4949 kfree(ha->swl);
4950 ha->swl = NULL;
4951 kfree(ha->loop_id_map);
4952 ha->sf_init_cb = NULL;
4953 ha->sf_init_cb_dma = 0;
4954 ha->loop_id_map = NULL;
4955 }
4956
qla2x00_create_host(struct scsi_host_template * sht,struct qla_hw_data * ha)4957 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4958 struct qla_hw_data *ha)
4959 {
4960 struct Scsi_Host *host;
4961 struct scsi_qla_host *vha = NULL;
4962
4963 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4964 if (!host) {
4965 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4966 "Failed to allocate host from the scsi layer, aborting.\n");
4967 return NULL;
4968 }
4969
4970 /* Clear our data area */
4971 vha = shost_priv(host);
4972 memset(vha, 0, sizeof(scsi_qla_host_t));
4973
4974 vha->host = host;
4975 vha->host_no = host->host_no;
4976 vha->hw = ha;
4977
4978 vha->qlini_mode = ql2x_ini_mode;
4979 vha->ql2xexchoffld = ql2xexchoffld;
4980 vha->ql2xiniexchg = ql2xiniexchg;
4981
4982 INIT_LIST_HEAD(&vha->vp_fcports);
4983 INIT_LIST_HEAD(&vha->work_list);
4984 INIT_LIST_HEAD(&vha->list);
4985 INIT_LIST_HEAD(&vha->qla_cmd_list);
4986 INIT_LIST_HEAD(&vha->logo_list);
4987 INIT_LIST_HEAD(&vha->plogi_ack_list);
4988 INIT_LIST_HEAD(&vha->qp_list);
4989 INIT_LIST_HEAD(&vha->gnl.fcports);
4990 INIT_LIST_HEAD(&vha->gpnid_list);
4991 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
4992
4993 INIT_LIST_HEAD(&vha->purex_list.head);
4994 spin_lock_init(&vha->purex_list.lock);
4995
4996 spin_lock_init(&vha->work_lock);
4997 spin_lock_init(&vha->cmd_list_lock);
4998 init_waitqueue_head(&vha->fcport_waitQ);
4999 init_waitqueue_head(&vha->vref_waitq);
5000 qla_enode_init(vha);
5001 qla_edb_init(vha);
5002
5003
5004 vha->gnl.size = sizeof(struct get_name_list_extended) *
5005 (ha->max_loop_id + 1);
5006 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
5007 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
5008 if (!vha->gnl.l) {
5009 ql_log(ql_log_fatal, vha, 0xd04a,
5010 "Alloc failed for name list.\n");
5011 scsi_host_put(vha->host);
5012 return NULL;
5013 }
5014
5015 /* todo: what about ext login? */
5016 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
5017 vha->scan.l = vmalloc(vha->scan.size);
5018 if (!vha->scan.l) {
5019 ql_log(ql_log_fatal, vha, 0xd04a,
5020 "Alloc failed for scan database.\n");
5021 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
5022 vha->gnl.l, vha->gnl.ldma);
5023 vha->gnl.l = NULL;
5024 scsi_host_put(vha->host);
5025 return NULL;
5026 }
5027 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
5028
5029 sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no);
5030 ql_dbg(ql_dbg_init, vha, 0x0041,
5031 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
5032 vha->host, vha->hw, vha,
5033 dev_name(&(ha->pdev->dev)));
5034
5035 return vha;
5036 }
5037
5038 struct qla_work_evt *
qla2x00_alloc_work(struct scsi_qla_host * vha,enum qla_work_type type)5039 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
5040 {
5041 struct qla_work_evt *e;
5042 uint8_t bail;
5043
5044 if (test_bit(UNLOADING, &vha->dpc_flags))
5045 return NULL;
5046
5047 QLA_VHA_MARK_BUSY(vha, bail);
5048 if (bail)
5049 return NULL;
5050
5051 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
5052 if (!e) {
5053 QLA_VHA_MARK_NOT_BUSY(vha);
5054 return NULL;
5055 }
5056
5057 INIT_LIST_HEAD(&e->list);
5058 e->type = type;
5059 e->flags = QLA_EVT_FLAG_FREE;
5060 return e;
5061 }
5062
5063 int
qla2x00_post_work(struct scsi_qla_host * vha,struct qla_work_evt * e)5064 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
5065 {
5066 unsigned long flags;
5067 bool q = false;
5068
5069 spin_lock_irqsave(&vha->work_lock, flags);
5070 list_add_tail(&e->list, &vha->work_list);
5071
5072 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
5073 q = true;
5074
5075 spin_unlock_irqrestore(&vha->work_lock, flags);
5076
5077 if (q)
5078 queue_work(vha->hw->wq, &vha->iocb_work);
5079
5080 return QLA_SUCCESS;
5081 }
5082
5083 int
qla2x00_post_aen_work(struct scsi_qla_host * vha,enum fc_host_event_code code,u32 data)5084 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
5085 u32 data)
5086 {
5087 struct qla_work_evt *e;
5088
5089 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
5090 if (!e)
5091 return QLA_FUNCTION_FAILED;
5092
5093 e->u.aen.code = code;
5094 e->u.aen.data = data;
5095 return qla2x00_post_work(vha, e);
5096 }
5097
5098 int
qla2x00_post_idc_ack_work(struct scsi_qla_host * vha,uint16_t * mb)5099 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
5100 {
5101 struct qla_work_evt *e;
5102
5103 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
5104 if (!e)
5105 return QLA_FUNCTION_FAILED;
5106
5107 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
5108 return qla2x00_post_work(vha, e);
5109 }
5110
5111 #define qla2x00_post_async_work(name, type) \
5112 int qla2x00_post_async_##name##_work( \
5113 struct scsi_qla_host *vha, \
5114 fc_port_t *fcport, uint16_t *data) \
5115 { \
5116 struct qla_work_evt *e; \
5117 \
5118 e = qla2x00_alloc_work(vha, type); \
5119 if (!e) \
5120 return QLA_FUNCTION_FAILED; \
5121 \
5122 e->u.logio.fcport = fcport; \
5123 if (data) { \
5124 e->u.logio.data[0] = data[0]; \
5125 e->u.logio.data[1] = data[1]; \
5126 } \
5127 fcport->flags |= FCF_ASYNC_ACTIVE; \
5128 return qla2x00_post_work(vha, e); \
5129 }
5130
5131 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
5132 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
5133 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
5134 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
5135 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
5136
5137 int
qla2x00_post_uevent_work(struct scsi_qla_host * vha,u32 code)5138 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
5139 {
5140 struct qla_work_evt *e;
5141
5142 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
5143 if (!e)
5144 return QLA_FUNCTION_FAILED;
5145
5146 e->u.uevent.code = code;
5147 return qla2x00_post_work(vha, e);
5148 }
5149
5150 static void
qla2x00_uevent_emit(struct scsi_qla_host * vha,u32 code)5151 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
5152 {
5153 char event_string[40];
5154 char *envp[] = { event_string, NULL };
5155
5156 switch (code) {
5157 case QLA_UEVENT_CODE_FW_DUMP:
5158 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
5159 vha->host_no);
5160 break;
5161 default:
5162 /* do nothing */
5163 break;
5164 }
5165 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5166 }
5167
5168 int
qlafx00_post_aenfx_work(struct scsi_qla_host * vha,uint32_t evtcode,uint32_t * data,int cnt)5169 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5170 uint32_t *data, int cnt)
5171 {
5172 struct qla_work_evt *e;
5173
5174 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5175 if (!e)
5176 return QLA_FUNCTION_FAILED;
5177
5178 e->u.aenfx.evtcode = evtcode;
5179 e->u.aenfx.count = cnt;
5180 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5181 return qla2x00_post_work(vha, e);
5182 }
5183
qla24xx_sched_upd_fcport(fc_port_t * fcport)5184 void qla24xx_sched_upd_fcport(fc_port_t *fcport)
5185 {
5186 unsigned long flags;
5187
5188 if (IS_SW_RESV_ADDR(fcport->d_id))
5189 return;
5190
5191 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5192 if (fcport->disc_state == DSC_UPD_FCPORT) {
5193 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5194 return;
5195 }
5196 fcport->jiffies_at_registration = jiffies;
5197 fcport->sec_since_registration = 0;
5198 fcport->next_disc_state = DSC_DELETED;
5199 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5200 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5201
5202 queue_work(system_unbound_wq, &fcport->reg_work);
5203 }
5204
5205 static
qla24xx_create_new_sess(struct scsi_qla_host * vha,struct qla_work_evt * e)5206 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5207 {
5208 unsigned long flags;
5209 fc_port_t *fcport = NULL, *tfcp;
5210 struct qlt_plogi_ack_t *pla =
5211 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5212 uint8_t free_fcport = 0;
5213
5214 ql_dbg(ql_dbg_disc, vha, 0xffff,
5215 "%s %d %8phC enter\n",
5216 __func__, __LINE__, e->u.new_sess.port_name);
5217
5218 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5219 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5220 if (fcport) {
5221 fcport->d_id = e->u.new_sess.id;
5222 if (pla) {
5223 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5224 memcpy(fcport->node_name,
5225 pla->iocb.u.isp24.u.plogi.node_name,
5226 WWN_SIZE);
5227 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5228 /* we took an extra ref_count to prevent PLOGI ACK when
5229 * fcport/sess has not been created.
5230 */
5231 pla->ref_count--;
5232 }
5233 } else {
5234 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5235 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5236 if (fcport) {
5237 fcport->d_id = e->u.new_sess.id;
5238 fcport->flags |= FCF_FABRIC_DEVICE;
5239 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5240 fcport->tgt_short_link_down_cnt = 0;
5241
5242 memcpy(fcport->port_name, e->u.new_sess.port_name,
5243 WWN_SIZE);
5244
5245 fcport->fc4_type = e->u.new_sess.fc4_type;
5246 if (NVME_PRIORITY(vha->hw, fcport))
5247 fcport->do_prli_nvme = 1;
5248 else
5249 fcport->do_prli_nvme = 0;
5250
5251 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5252 fcport->dm_login_expire = jiffies +
5253 QLA_N2N_WAIT_TIME * HZ;
5254 fcport->fc4_type = FS_FC4TYPE_FCP;
5255 fcport->n2n_flag = 1;
5256 if (vha->flags.nvme_enabled)
5257 fcport->fc4_type |= FS_FC4TYPE_NVME;
5258 }
5259
5260 } else {
5261 ql_dbg(ql_dbg_disc, vha, 0xffff,
5262 "%s %8phC mem alloc fail.\n",
5263 __func__, e->u.new_sess.port_name);
5264
5265 if (pla) {
5266 list_del(&pla->list);
5267 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5268 }
5269 return;
5270 }
5271
5272 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5273 /* search again to make sure no one else got ahead */
5274 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5275 e->u.new_sess.port_name, 1);
5276 if (tfcp) {
5277 /* should rarily happen */
5278 ql_dbg(ql_dbg_disc, vha, 0xffff,
5279 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5280 __func__, tfcp->port_name, tfcp->disc_state,
5281 tfcp->fw_login_state);
5282
5283 free_fcport = 1;
5284 } else {
5285 list_add_tail(&fcport->list, &vha->vp_fcports);
5286
5287 }
5288 if (pla) {
5289 qlt_plogi_ack_link(vha, pla, fcport,
5290 QLT_PLOGI_LINK_SAME_WWN);
5291 pla->ref_count--;
5292 }
5293 }
5294 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5295
5296 if (fcport) {
5297 fcport->id_changed = 1;
5298 fcport->scan_state = QLA_FCPORT_FOUND;
5299 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5300 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5301
5302 if (pla) {
5303 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5304 u16 wd3_lo;
5305
5306 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5307 fcport->local = 0;
5308 fcport->loop_id =
5309 le16_to_cpu(
5310 pla->iocb.u.isp24.nport_handle);
5311 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5312 wd3_lo =
5313 le16_to_cpu(
5314 pla->iocb.u.isp24.u.prli.wd3_lo);
5315
5316 if (wd3_lo & BIT_7)
5317 fcport->conf_compl_supported = 1;
5318
5319 if ((wd3_lo & BIT_4) == 0)
5320 fcport->port_type = FCT_INITIATOR;
5321 else
5322 fcport->port_type = FCT_TARGET;
5323 }
5324 qlt_plogi_ack_unref(vha, pla);
5325 } else {
5326 fc_port_t *dfcp = NULL;
5327
5328 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5329 tfcp = qla2x00_find_fcport_by_nportid(vha,
5330 &e->u.new_sess.id, 1);
5331 if (tfcp && (tfcp != fcport)) {
5332 /*
5333 * We have a conflict fcport with same NportID.
5334 */
5335 ql_dbg(ql_dbg_disc, vha, 0xffff,
5336 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5337 __func__, tfcp->port_name, tfcp->disc_state,
5338 tfcp->fw_login_state);
5339
5340 switch (tfcp->disc_state) {
5341 case DSC_DELETED:
5342 break;
5343 case DSC_DELETE_PEND:
5344 fcport->login_pause = 1;
5345 tfcp->conflict = fcport;
5346 break;
5347 default:
5348 fcport->login_pause = 1;
5349 tfcp->conflict = fcport;
5350 dfcp = tfcp;
5351 break;
5352 }
5353 }
5354 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5355 if (dfcp)
5356 qlt_schedule_sess_for_deletion(tfcp);
5357
5358 if (N2N_TOPO(vha->hw)) {
5359 fcport->flags &= ~FCF_FABRIC_DEVICE;
5360 fcport->keep_nport_handle = 1;
5361 if (vha->flags.nvme_enabled) {
5362 fcport->fc4_type =
5363 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
5364 fcport->n2n_flag = 1;
5365 }
5366 fcport->fw_login_state = 0;
5367
5368 schedule_delayed_work(&vha->scan.scan_work, 5);
5369 } else {
5370 qla24xx_fcport_handle_login(vha, fcport);
5371 }
5372 }
5373 }
5374
5375 if (free_fcport) {
5376 qla2x00_free_fcport(fcport);
5377 if (pla) {
5378 list_del(&pla->list);
5379 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5380 }
5381 }
5382 }
5383
qla_sp_retry(struct scsi_qla_host * vha,struct qla_work_evt * e)5384 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5385 {
5386 struct srb *sp = e->u.iosb.sp;
5387 int rval;
5388
5389 rval = qla2x00_start_sp(sp);
5390 if (rval != QLA_SUCCESS) {
5391 ql_dbg(ql_dbg_disc, vha, 0x2043,
5392 "%s: %s: Re-issue IOCB failed (%d).\n",
5393 __func__, sp->name, rval);
5394 qla24xx_sp_unmap(vha, sp);
5395 }
5396 }
5397
5398 void
qla2x00_do_work(struct scsi_qla_host * vha)5399 qla2x00_do_work(struct scsi_qla_host *vha)
5400 {
5401 struct qla_work_evt *e, *tmp;
5402 unsigned long flags;
5403 LIST_HEAD(work);
5404 int rc;
5405
5406 spin_lock_irqsave(&vha->work_lock, flags);
5407 list_splice_init(&vha->work_list, &work);
5408 spin_unlock_irqrestore(&vha->work_lock, flags);
5409
5410 list_for_each_entry_safe(e, tmp, &work, list) {
5411 rc = QLA_SUCCESS;
5412 switch (e->type) {
5413 case QLA_EVT_AEN:
5414 fc_host_post_event(vha->host, fc_get_event_number(),
5415 e->u.aen.code, e->u.aen.data);
5416 break;
5417 case QLA_EVT_IDC_ACK:
5418 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5419 break;
5420 case QLA_EVT_ASYNC_LOGIN:
5421 qla2x00_async_login(vha, e->u.logio.fcport,
5422 e->u.logio.data);
5423 break;
5424 case QLA_EVT_ASYNC_LOGOUT:
5425 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5426 break;
5427 case QLA_EVT_ASYNC_ADISC:
5428 qla2x00_async_adisc(vha, e->u.logio.fcport,
5429 e->u.logio.data);
5430 break;
5431 case QLA_EVT_UEVENT:
5432 qla2x00_uevent_emit(vha, e->u.uevent.code);
5433 break;
5434 case QLA_EVT_AENFX:
5435 qlafx00_process_aen(vha, e);
5436 break;
5437 case QLA_EVT_GPNID:
5438 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5439 break;
5440 case QLA_EVT_UNMAP:
5441 qla24xx_sp_unmap(vha, e->u.iosb.sp);
5442 break;
5443 case QLA_EVT_RELOGIN:
5444 qla2x00_relogin(vha);
5445 break;
5446 case QLA_EVT_NEW_SESS:
5447 qla24xx_create_new_sess(vha, e);
5448 break;
5449 case QLA_EVT_GPDB:
5450 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5451 e->u.fcport.opt);
5452 break;
5453 case QLA_EVT_PRLI:
5454 qla24xx_async_prli(vha, e->u.fcport.fcport);
5455 break;
5456 case QLA_EVT_GPSC:
5457 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5458 break;
5459 case QLA_EVT_GNL:
5460 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5461 break;
5462 case QLA_EVT_NACK:
5463 qla24xx_do_nack_work(vha, e);
5464 break;
5465 case QLA_EVT_ASYNC_PRLO:
5466 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5467 break;
5468 case QLA_EVT_ASYNC_PRLO_DONE:
5469 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5470 e->u.logio.data);
5471 break;
5472 case QLA_EVT_GPNFT:
5473 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5474 e->u.gpnft.sp);
5475 break;
5476 case QLA_EVT_GPNFT_DONE:
5477 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5478 break;
5479 case QLA_EVT_GNNFT_DONE:
5480 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5481 break;
5482 case QLA_EVT_GNNID:
5483 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5484 break;
5485 case QLA_EVT_GFPNID:
5486 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5487 break;
5488 case QLA_EVT_SP_RETRY:
5489 qla_sp_retry(vha, e);
5490 break;
5491 case QLA_EVT_IIDMA:
5492 qla_do_iidma_work(vha, e->u.fcport.fcport);
5493 break;
5494 case QLA_EVT_ELS_PLOGI:
5495 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5496 e->u.fcport.fcport, false);
5497 break;
5498 case QLA_EVT_SA_REPLACE:
5499 rc = qla24xx_issue_sa_replace_iocb(vha, e);
5500 break;
5501 }
5502
5503 if (rc == EAGAIN) {
5504 /* put 'work' at head of 'vha->work_list' */
5505 spin_lock_irqsave(&vha->work_lock, flags);
5506 list_splice(&work, &vha->work_list);
5507 spin_unlock_irqrestore(&vha->work_lock, flags);
5508 break;
5509 }
5510 list_del_init(&e->list);
5511 if (e->flags & QLA_EVT_FLAG_FREE)
5512 kfree(e);
5513
5514 /* For each work completed decrement vha ref count */
5515 QLA_VHA_MARK_NOT_BUSY(vha);
5516 }
5517 }
5518
qla24xx_post_relogin_work(struct scsi_qla_host * vha)5519 int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5520 {
5521 struct qla_work_evt *e;
5522
5523 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5524
5525 if (!e) {
5526 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5527 return QLA_FUNCTION_FAILED;
5528 }
5529
5530 return qla2x00_post_work(vha, e);
5531 }
5532
5533 /* Relogins all the fcports of a vport
5534 * Context: dpc thread
5535 */
qla2x00_relogin(struct scsi_qla_host * vha)5536 void qla2x00_relogin(struct scsi_qla_host *vha)
5537 {
5538 fc_port_t *fcport;
5539 int status, relogin_needed = 0;
5540 struct event_arg ea;
5541
5542 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5543 /*
5544 * If the port is not ONLINE then try to login
5545 * to it if we haven't run out of retries.
5546 */
5547 if (atomic_read(&fcport->state) != FCS_ONLINE &&
5548 fcport->login_retry) {
5549 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5550 fcport->disc_state == DSC_LOGIN_AUTH_PEND ||
5551 fcport->disc_state == DSC_LOGIN_COMPLETE)
5552 continue;
5553
5554 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5555 fcport->disc_state == DSC_DELETE_PEND) {
5556 relogin_needed = 1;
5557 } else {
5558 if (vha->hw->current_topology != ISP_CFG_NL) {
5559 memset(&ea, 0, sizeof(ea));
5560 ea.fcport = fcport;
5561 qla24xx_handle_relogin_event(vha, &ea);
5562 } else if (vha->hw->current_topology ==
5563 ISP_CFG_NL &&
5564 IS_QLA2XXX_MIDTYPE(vha->hw)) {
5565 (void)qla24xx_fcport_handle_login(vha,
5566 fcport);
5567 } else if (vha->hw->current_topology ==
5568 ISP_CFG_NL) {
5569 fcport->login_retry--;
5570 status =
5571 qla2x00_local_device_login(vha,
5572 fcport);
5573 if (status == QLA_SUCCESS) {
5574 fcport->old_loop_id =
5575 fcport->loop_id;
5576 ql_dbg(ql_dbg_disc, vha, 0x2003,
5577 "Port login OK: logged in ID 0x%x.\n",
5578 fcport->loop_id);
5579 qla2x00_update_fcport
5580 (vha, fcport);
5581 } else if (status == 1) {
5582 set_bit(RELOGIN_NEEDED,
5583 &vha->dpc_flags);
5584 /* retry the login again */
5585 ql_dbg(ql_dbg_disc, vha, 0x2007,
5586 "Retrying %d login again loop_id 0x%x.\n",
5587 fcport->login_retry,
5588 fcport->loop_id);
5589 } else {
5590 fcport->login_retry = 0;
5591 }
5592
5593 if (fcport->login_retry == 0 &&
5594 status != QLA_SUCCESS)
5595 qla2x00_clear_loop_id(fcport);
5596 }
5597 }
5598 }
5599 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5600 break;
5601 }
5602
5603 if (relogin_needed)
5604 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5605
5606 ql_dbg(ql_dbg_disc, vha, 0x400e,
5607 "Relogin end.\n");
5608 }
5609
5610 /* Schedule work on any of the dpc-workqueues */
5611 void
qla83xx_schedule_work(scsi_qla_host_t * base_vha,int work_code)5612 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5613 {
5614 struct qla_hw_data *ha = base_vha->hw;
5615
5616 switch (work_code) {
5617 case MBA_IDC_AEN: /* 0x8200 */
5618 if (ha->dpc_lp_wq)
5619 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5620 break;
5621
5622 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5623 if (!ha->flags.nic_core_reset_hdlr_active) {
5624 if (ha->dpc_hp_wq)
5625 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5626 } else
5627 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5628 "NIC Core reset is already active. Skip "
5629 "scheduling it again.\n");
5630 break;
5631 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5632 if (ha->dpc_hp_wq)
5633 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5634 break;
5635 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5636 if (ha->dpc_hp_wq)
5637 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5638 break;
5639 default:
5640 ql_log(ql_log_warn, base_vha, 0xb05f,
5641 "Unknown work-code=0x%x.\n", work_code);
5642 }
5643
5644 return;
5645 }
5646
5647 /* Work: Perform NIC Core Unrecoverable state handling */
5648 void
qla83xx_nic_core_unrecoverable_work(struct work_struct * work)5649 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5650 {
5651 struct qla_hw_data *ha =
5652 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5653 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5654 uint32_t dev_state = 0;
5655
5656 qla83xx_idc_lock(base_vha, 0);
5657 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5658 qla83xx_reset_ownership(base_vha);
5659 if (ha->flags.nic_core_reset_owner) {
5660 ha->flags.nic_core_reset_owner = 0;
5661 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5662 QLA8XXX_DEV_FAILED);
5663 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5664 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5665 }
5666 qla83xx_idc_unlock(base_vha, 0);
5667 }
5668
5669 /* Work: Execute IDC state handler */
5670 void
qla83xx_idc_state_handler_work(struct work_struct * work)5671 qla83xx_idc_state_handler_work(struct work_struct *work)
5672 {
5673 struct qla_hw_data *ha =
5674 container_of(work, struct qla_hw_data, idc_state_handler);
5675 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5676 uint32_t dev_state = 0;
5677
5678 qla83xx_idc_lock(base_vha, 0);
5679 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5680 if (dev_state == QLA8XXX_DEV_FAILED ||
5681 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5682 qla83xx_idc_state_handler(base_vha);
5683 qla83xx_idc_unlock(base_vha, 0);
5684 }
5685
5686 static int
qla83xx_check_nic_core_fw_alive(scsi_qla_host_t * base_vha)5687 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5688 {
5689 int rval = QLA_SUCCESS;
5690 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5691 uint32_t heart_beat_counter1, heart_beat_counter2;
5692
5693 do {
5694 if (time_after(jiffies, heart_beat_wait)) {
5695 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5696 "Nic Core f/w is not alive.\n");
5697 rval = QLA_FUNCTION_FAILED;
5698 break;
5699 }
5700
5701 qla83xx_idc_lock(base_vha, 0);
5702 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5703 &heart_beat_counter1);
5704 qla83xx_idc_unlock(base_vha, 0);
5705 msleep(100);
5706 qla83xx_idc_lock(base_vha, 0);
5707 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5708 &heart_beat_counter2);
5709 qla83xx_idc_unlock(base_vha, 0);
5710 } while (heart_beat_counter1 == heart_beat_counter2);
5711
5712 return rval;
5713 }
5714
5715 /* Work: Perform NIC Core Reset handling */
5716 void
qla83xx_nic_core_reset_work(struct work_struct * work)5717 qla83xx_nic_core_reset_work(struct work_struct *work)
5718 {
5719 struct qla_hw_data *ha =
5720 container_of(work, struct qla_hw_data, nic_core_reset);
5721 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5722 uint32_t dev_state = 0;
5723
5724 if (IS_QLA2031(ha)) {
5725 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5726 ql_log(ql_log_warn, base_vha, 0xb081,
5727 "Failed to dump mctp\n");
5728 return;
5729 }
5730
5731 if (!ha->flags.nic_core_reset_hdlr_active) {
5732 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5733 qla83xx_idc_lock(base_vha, 0);
5734 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5735 &dev_state);
5736 qla83xx_idc_unlock(base_vha, 0);
5737 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5738 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5739 "Nic Core f/w is alive.\n");
5740 return;
5741 }
5742 }
5743
5744 ha->flags.nic_core_reset_hdlr_active = 1;
5745 if (qla83xx_nic_core_reset(base_vha)) {
5746 /* NIC Core reset failed. */
5747 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5748 "NIC Core reset failed.\n");
5749 }
5750 ha->flags.nic_core_reset_hdlr_active = 0;
5751 }
5752 }
5753
5754 /* Work: Handle 8200 IDC aens */
5755 void
qla83xx_service_idc_aen(struct work_struct * work)5756 qla83xx_service_idc_aen(struct work_struct *work)
5757 {
5758 struct qla_hw_data *ha =
5759 container_of(work, struct qla_hw_data, idc_aen);
5760 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5761 uint32_t dev_state, idc_control;
5762
5763 qla83xx_idc_lock(base_vha, 0);
5764 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5765 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5766 qla83xx_idc_unlock(base_vha, 0);
5767 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5768 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5769 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5770 "Application requested NIC Core Reset.\n");
5771 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5772 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5773 QLA_SUCCESS) {
5774 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5775 "Other protocol driver requested NIC Core Reset.\n");
5776 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5777 }
5778 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5779 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5780 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5781 }
5782 }
5783
5784 /*
5785 * Control the frequency of IDC lock retries
5786 */
5787 #define QLA83XX_WAIT_LOGIC_MS 100
5788
5789 static int
qla83xx_force_lock_recovery(scsi_qla_host_t * base_vha)5790 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5791 {
5792 int rval;
5793 uint32_t data;
5794 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5795 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5796 struct qla_hw_data *ha = base_vha->hw;
5797
5798 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5799 "Trying force recovery of the IDC lock.\n");
5800
5801 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5802 if (rval)
5803 return rval;
5804
5805 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5806 return QLA_SUCCESS;
5807 } else {
5808 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5809 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5810 data);
5811 if (rval)
5812 return rval;
5813
5814 msleep(200);
5815
5816 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5817 &data);
5818 if (rval)
5819 return rval;
5820
5821 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5822 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5823 ~(idc_lck_rcvry_stage_mask));
5824 rval = qla83xx_wr_reg(base_vha,
5825 QLA83XX_IDC_LOCK_RECOVERY, data);
5826 if (rval)
5827 return rval;
5828
5829 /* Forcefully perform IDC UnLock */
5830 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5831 &data);
5832 if (rval)
5833 return rval;
5834 /* Clear lock-id by setting 0xff */
5835 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5836 0xff);
5837 if (rval)
5838 return rval;
5839 /* Clear lock-recovery by setting 0x0 */
5840 rval = qla83xx_wr_reg(base_vha,
5841 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5842 if (rval)
5843 return rval;
5844 } else
5845 return QLA_SUCCESS;
5846 }
5847
5848 return rval;
5849 }
5850
5851 static int
qla83xx_idc_lock_recovery(scsi_qla_host_t * base_vha)5852 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5853 {
5854 int rval = QLA_SUCCESS;
5855 uint32_t o_drv_lockid, n_drv_lockid;
5856 unsigned long lock_recovery_timeout;
5857
5858 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5859 retry_lockid:
5860 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5861 if (rval)
5862 goto exit;
5863
5864 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5865 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5866 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5867 return QLA_SUCCESS;
5868 else
5869 return QLA_FUNCTION_FAILED;
5870 }
5871
5872 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5873 if (rval)
5874 goto exit;
5875
5876 if (o_drv_lockid == n_drv_lockid) {
5877 msleep(QLA83XX_WAIT_LOGIC_MS);
5878 goto retry_lockid;
5879 } else
5880 return QLA_SUCCESS;
5881
5882 exit:
5883 return rval;
5884 }
5885
5886 /*
5887 * Context: task, can sleep
5888 */
5889 void
qla83xx_idc_lock(scsi_qla_host_t * base_vha,uint16_t requester_id)5890 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5891 {
5892 uint32_t data;
5893 uint32_t lock_owner;
5894 struct qla_hw_data *ha = base_vha->hw;
5895
5896 might_sleep();
5897
5898 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5899 retry_lock:
5900 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5901 == QLA_SUCCESS) {
5902 if (data) {
5903 /* Setting lock-id to our function-number */
5904 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5905 ha->portnum);
5906 } else {
5907 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5908 &lock_owner);
5909 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5910 "Failed to acquire IDC lock, acquired by %d, "
5911 "retrying...\n", lock_owner);
5912
5913 /* Retry/Perform IDC-Lock recovery */
5914 if (qla83xx_idc_lock_recovery(base_vha)
5915 == QLA_SUCCESS) {
5916 msleep(QLA83XX_WAIT_LOGIC_MS);
5917 goto retry_lock;
5918 } else
5919 ql_log(ql_log_warn, base_vha, 0xb075,
5920 "IDC Lock recovery FAILED.\n");
5921 }
5922
5923 }
5924
5925 return;
5926 }
5927
5928 static bool
qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host * vha,struct purex_entry_24xx * purex)5929 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha,
5930 struct purex_entry_24xx *purex)
5931 {
5932 char fwstr[16];
5933 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
5934 struct port_database_24xx *pdb;
5935
5936 /* Domain Controller is always logged-out. */
5937 /* if RDP request is not from Domain Controller: */
5938 if (sid != 0xfffc01)
5939 return false;
5940
5941 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);
5942
5943 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL);
5944 if (!pdb) {
5945 ql_dbg(ql_dbg_init, vha, 0x0181,
5946 "%s: Failed allocate pdb\n", __func__);
5947 } else if (qla24xx_get_port_database(vha,
5948 le16_to_cpu(purex->nport_handle), pdb)) {
5949 ql_dbg(ql_dbg_init, vha, 0x0181,
5950 "%s: Failed get pdb sid=%x\n", __func__, sid);
5951 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
5952 pdb->current_login_state != PDS_PRLI_COMPLETE) {
5953 ql_dbg(ql_dbg_init, vha, 0x0181,
5954 "%s: Port not logged in sid=%#x\n", __func__, sid);
5955 } else {
5956 /* RDP request is from logged in port */
5957 kfree(pdb);
5958 return false;
5959 }
5960 kfree(pdb);
5961
5962 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
5963 fwstr[strcspn(fwstr, " ")] = 0;
5964 /* if FW version allows RDP response length upto 2048 bytes: */
5965 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
5966 return false;
5967
5968 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);
5969
5970 /* RDP response length is to be reduced to maximum 256 bytes */
5971 return true;
5972 }
5973
5974 /*
5975 * Function Name: qla24xx_process_purex_iocb
5976 *
5977 * Description:
5978 * Prepare a RDP response and send to Fabric switch
5979 *
5980 * PARAMETERS:
5981 * vha: SCSI qla host
5982 * purex: RDP request received by HBA
5983 */
qla24xx_process_purex_rdp(struct scsi_qla_host * vha,struct purex_item * item)5984 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
5985 struct purex_item *item)
5986 {
5987 struct qla_hw_data *ha = vha->hw;
5988 struct purex_entry_24xx *purex =
5989 (struct purex_entry_24xx *)&item->iocb;
5990 dma_addr_t rsp_els_dma;
5991 dma_addr_t rsp_payload_dma;
5992 dma_addr_t stat_dma;
5993 dma_addr_t sfp_dma;
5994 struct els_entry_24xx *rsp_els = NULL;
5995 struct rdp_rsp_payload *rsp_payload = NULL;
5996 struct link_statistics *stat = NULL;
5997 uint8_t *sfp = NULL;
5998 uint16_t sfp_flags = 0;
5999 uint rsp_payload_length = sizeof(*rsp_payload);
6000 int rval;
6001
6002 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
6003 "%s: Enter\n", __func__);
6004
6005 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
6006 "-------- ELS REQ -------\n");
6007 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
6008 purex, sizeof(*purex));
6009
6010 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
6011 rsp_payload_length =
6012 offsetof(typeof(*rsp_payload), optical_elmt_desc);
6013 ql_dbg(ql_dbg_init, vha, 0x0181,
6014 "Reducing RSP payload length to %u bytes...\n",
6015 rsp_payload_length);
6016 }
6017
6018 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6019 &rsp_els_dma, GFP_KERNEL);
6020 if (!rsp_els) {
6021 ql_log(ql_log_warn, vha, 0x0183,
6022 "Failed allocate dma buffer ELS RSP.\n");
6023 goto dealloc;
6024 }
6025
6026 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6027 &rsp_payload_dma, GFP_KERNEL);
6028 if (!rsp_payload) {
6029 ql_log(ql_log_warn, vha, 0x0184,
6030 "Failed allocate dma buffer ELS RSP payload.\n");
6031 goto dealloc;
6032 }
6033
6034 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6035 &sfp_dma, GFP_KERNEL);
6036
6037 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
6038 &stat_dma, GFP_KERNEL);
6039
6040 /* Prepare Response IOCB */
6041 rsp_els->entry_type = ELS_IOCB_TYPE;
6042 rsp_els->entry_count = 1;
6043 rsp_els->sys_define = 0;
6044 rsp_els->entry_status = 0;
6045 rsp_els->handle = 0;
6046 rsp_els->nport_handle = purex->nport_handle;
6047 rsp_els->tx_dsd_count = cpu_to_le16(1);
6048 rsp_els->vp_index = purex->vp_idx;
6049 rsp_els->sof_type = EST_SOFI3;
6050 rsp_els->rx_xchg_address = purex->rx_xchg_addr;
6051 rsp_els->rx_dsd_count = 0;
6052 rsp_els->opcode = purex->els_frame_payload[0];
6053
6054 rsp_els->d_id[0] = purex->s_id[0];
6055 rsp_els->d_id[1] = purex->s_id[1];
6056 rsp_els->d_id[2] = purex->s_id[2];
6057
6058 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
6059 rsp_els->rx_byte_count = 0;
6060 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
6061
6062 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
6063 rsp_els->tx_len = rsp_els->tx_byte_count;
6064
6065 rsp_els->rx_address = 0;
6066 rsp_els->rx_len = 0;
6067
6068 /* Prepare Response Payload */
6069 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
6070 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
6071 sizeof(rsp_payload->hdr));
6072
6073 /* Link service Request Info Descriptor */
6074 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
6075 rsp_payload->ls_req_info_desc.desc_len =
6076 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
6077 rsp_payload->ls_req_info_desc.req_payload_word_0 =
6078 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6079
6080 /* Link service Request Info Descriptor 2 */
6081 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
6082 rsp_payload->ls_req_info_desc2.desc_len =
6083 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
6084 rsp_payload->ls_req_info_desc2.req_payload_word_0 =
6085 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6086
6087
6088 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
6089 rsp_payload->sfp_diag_desc.desc_len =
6090 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
6091
6092 if (sfp) {
6093 /* SFP Flags */
6094 memset(sfp, 0, SFP_RTDI_LEN);
6095 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
6096 if (!rval) {
6097 /* SFP Flags bits 3-0: Port Tx Laser Type */
6098 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
6099 sfp_flags |= BIT_0; /* short wave */
6100 else if (sfp[0] & BIT_1)
6101 sfp_flags |= BIT_1; /* long wave 1310nm */
6102 else if (sfp[1] & BIT_4)
6103 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
6104 }
6105
6106 /* SFP Type */
6107 memset(sfp, 0, SFP_RTDI_LEN);
6108 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
6109 if (!rval) {
6110 sfp_flags |= BIT_4; /* optical */
6111 if (sfp[0] == 0x3)
6112 sfp_flags |= BIT_6; /* sfp+ */
6113 }
6114
6115 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
6116
6117 /* SFP Diagnostics */
6118 memset(sfp, 0, SFP_RTDI_LEN);
6119 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
6120 if (!rval) {
6121 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6122 rsp_payload->sfp_diag_desc.temperature = trx[0];
6123 rsp_payload->sfp_diag_desc.vcc = trx[1];
6124 rsp_payload->sfp_diag_desc.tx_bias = trx[2];
6125 rsp_payload->sfp_diag_desc.tx_power = trx[3];
6126 rsp_payload->sfp_diag_desc.rx_power = trx[4];
6127 }
6128 }
6129
6130 /* Port Speed Descriptor */
6131 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
6132 rsp_payload->port_speed_desc.desc_len =
6133 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
6134 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
6135 qla25xx_fdmi_port_speed_capability(ha));
6136 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
6137 qla25xx_fdmi_port_speed_currently(ha));
6138
6139 /* Link Error Status Descriptor */
6140 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
6141 rsp_payload->ls_err_desc.desc_len =
6142 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
6143
6144 if (stat) {
6145 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
6146 if (!rval) {
6147 rsp_payload->ls_err_desc.link_fail_cnt =
6148 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
6149 rsp_payload->ls_err_desc.loss_sync_cnt =
6150 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
6151 rsp_payload->ls_err_desc.loss_sig_cnt =
6152 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
6153 rsp_payload->ls_err_desc.prim_seq_err_cnt =
6154 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
6155 rsp_payload->ls_err_desc.inval_xmit_word_cnt =
6156 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
6157 rsp_payload->ls_err_desc.inval_crc_cnt =
6158 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
6159 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6160 }
6161 }
6162
6163 /* Portname Descriptor */
6164 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6165 rsp_payload->port_name_diag_desc.desc_len =
6166 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6167 memcpy(rsp_payload->port_name_diag_desc.WWNN,
6168 vha->node_name,
6169 sizeof(rsp_payload->port_name_diag_desc.WWNN));
6170 memcpy(rsp_payload->port_name_diag_desc.WWPN,
6171 vha->port_name,
6172 sizeof(rsp_payload->port_name_diag_desc.WWPN));
6173
6174 /* F-Port Portname Descriptor */
6175 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6176 rsp_payload->port_name_direct_desc.desc_len =
6177 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6178 memcpy(rsp_payload->port_name_direct_desc.WWNN,
6179 vha->fabric_node_name,
6180 sizeof(rsp_payload->port_name_direct_desc.WWNN));
6181 memcpy(rsp_payload->port_name_direct_desc.WWPN,
6182 vha->fabric_port_name,
6183 sizeof(rsp_payload->port_name_direct_desc.WWPN));
6184
6185 /* Bufer Credit Descriptor */
6186 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6187 rsp_payload->buffer_credit_desc.desc_len =
6188 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6189 rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6190 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6191 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6192
6193 if (ha->flags.plogi_template_valid) {
6194 uint32_t tmp =
6195 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
6196 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
6197 }
6198
6199 if (rsp_payload_length < sizeof(*rsp_payload))
6200 goto send;
6201
6202 /* Optical Element Descriptor, Temperature */
6203 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6204 rsp_payload->optical_elmt_desc[0].desc_len =
6205 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6206 /* Optical Element Descriptor, Voltage */
6207 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6208 rsp_payload->optical_elmt_desc[1].desc_len =
6209 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6210 /* Optical Element Descriptor, Tx Bias Current */
6211 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6212 rsp_payload->optical_elmt_desc[2].desc_len =
6213 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6214 /* Optical Element Descriptor, Tx Power */
6215 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6216 rsp_payload->optical_elmt_desc[3].desc_len =
6217 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6218 /* Optical Element Descriptor, Rx Power */
6219 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6220 rsp_payload->optical_elmt_desc[4].desc_len =
6221 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6222
6223 if (sfp) {
6224 memset(sfp, 0, SFP_RTDI_LEN);
6225 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
6226 if (!rval) {
6227 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
6228
6229 /* Optical Element Descriptor, Temperature */
6230 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6231 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6232 rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6233 rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6234 rsp_payload->optical_elmt_desc[0].element_flags =
6235 cpu_to_be32(1 << 28);
6236
6237 /* Optical Element Descriptor, Voltage */
6238 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6239 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6240 rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6241 rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6242 rsp_payload->optical_elmt_desc[1].element_flags =
6243 cpu_to_be32(2 << 28);
6244
6245 /* Optical Element Descriptor, Tx Bias Current */
6246 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6247 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6248 rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6249 rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6250 rsp_payload->optical_elmt_desc[2].element_flags =
6251 cpu_to_be32(3 << 28);
6252
6253 /* Optical Element Descriptor, Tx Power */
6254 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6255 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6256 rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6257 rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6258 rsp_payload->optical_elmt_desc[3].element_flags =
6259 cpu_to_be32(4 << 28);
6260
6261 /* Optical Element Descriptor, Rx Power */
6262 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6263 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6264 rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6265 rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6266 rsp_payload->optical_elmt_desc[4].element_flags =
6267 cpu_to_be32(5 << 28);
6268 }
6269
6270 memset(sfp, 0, SFP_RTDI_LEN);
6271 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
6272 if (!rval) {
6273 /* Temperature high/low alarm/warning */
6274 rsp_payload->optical_elmt_desc[0].element_flags |=
6275 cpu_to_be32(
6276 (sfp[0] >> 7 & 1) << 3 |
6277 (sfp[0] >> 6 & 1) << 2 |
6278 (sfp[4] >> 7 & 1) << 1 |
6279 (sfp[4] >> 6 & 1) << 0);
6280
6281 /* Voltage high/low alarm/warning */
6282 rsp_payload->optical_elmt_desc[1].element_flags |=
6283 cpu_to_be32(
6284 (sfp[0] >> 5 & 1) << 3 |
6285 (sfp[0] >> 4 & 1) << 2 |
6286 (sfp[4] >> 5 & 1) << 1 |
6287 (sfp[4] >> 4 & 1) << 0);
6288
6289 /* Tx Bias Current high/low alarm/warning */
6290 rsp_payload->optical_elmt_desc[2].element_flags |=
6291 cpu_to_be32(
6292 (sfp[0] >> 3 & 1) << 3 |
6293 (sfp[0] >> 2 & 1) << 2 |
6294 (sfp[4] >> 3 & 1) << 1 |
6295 (sfp[4] >> 2 & 1) << 0);
6296
6297 /* Tx Power high/low alarm/warning */
6298 rsp_payload->optical_elmt_desc[3].element_flags |=
6299 cpu_to_be32(
6300 (sfp[0] >> 1 & 1) << 3 |
6301 (sfp[0] >> 0 & 1) << 2 |
6302 (sfp[4] >> 1 & 1) << 1 |
6303 (sfp[4] >> 0 & 1) << 0);
6304
6305 /* Rx Power high/low alarm/warning */
6306 rsp_payload->optical_elmt_desc[4].element_flags |=
6307 cpu_to_be32(
6308 (sfp[1] >> 7 & 1) << 3 |
6309 (sfp[1] >> 6 & 1) << 2 |
6310 (sfp[5] >> 7 & 1) << 1 |
6311 (sfp[5] >> 6 & 1) << 0);
6312 }
6313 }
6314
6315 /* Optical Product Data Descriptor */
6316 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6317 rsp_payload->optical_prod_desc.desc_len =
6318 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6319
6320 if (sfp) {
6321 memset(sfp, 0, SFP_RTDI_LEN);
6322 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
6323 if (!rval) {
6324 memcpy(rsp_payload->optical_prod_desc.vendor_name,
6325 sfp + 0,
6326 sizeof(rsp_payload->optical_prod_desc.vendor_name));
6327 memcpy(rsp_payload->optical_prod_desc.part_number,
6328 sfp + 20,
6329 sizeof(rsp_payload->optical_prod_desc.part_number));
6330 memcpy(rsp_payload->optical_prod_desc.revision,
6331 sfp + 36,
6332 sizeof(rsp_payload->optical_prod_desc.revision));
6333 memcpy(rsp_payload->optical_prod_desc.serial_number,
6334 sfp + 48,
6335 sizeof(rsp_payload->optical_prod_desc.serial_number));
6336 }
6337
6338 memset(sfp, 0, SFP_RTDI_LEN);
6339 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
6340 if (!rval) {
6341 memcpy(rsp_payload->optical_prod_desc.date,
6342 sfp + 0,
6343 sizeof(rsp_payload->optical_prod_desc.date));
6344 }
6345 }
6346
6347 send:
6348 ql_dbg(ql_dbg_init, vha, 0x0183,
6349 "Sending ELS Response to RDP Request...\n");
6350 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
6351 "-------- ELS RSP -------\n");
6352 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
6353 rsp_els, sizeof(*rsp_els));
6354 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
6355 "-------- ELS RSP PAYLOAD -------\n");
6356 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
6357 rsp_payload, rsp_payload_length);
6358
6359 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0);
6360
6361 if (rval) {
6362 ql_log(ql_log_warn, vha, 0x0188,
6363 "%s: iocb failed to execute -> %x\n", __func__, rval);
6364 } else if (rsp_els->comp_status) {
6365 ql_log(ql_log_warn, vha, 0x0189,
6366 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6367 __func__, rsp_els->comp_status,
6368 rsp_els->error_subcode_1, rsp_els->error_subcode_2);
6369 } else {
6370 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
6371 }
6372
6373 dealloc:
6374 if (stat)
6375 dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6376 stat, stat_dma);
6377 if (sfp)
6378 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6379 sfp, sfp_dma);
6380 if (rsp_payload)
6381 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6382 rsp_payload, rsp_payload_dma);
6383 if (rsp_els)
6384 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6385 rsp_els, rsp_els_dma);
6386 }
6387
6388 void
qla24xx_free_purex_item(struct purex_item * item)6389 qla24xx_free_purex_item(struct purex_item *item)
6390 {
6391 if (item == &item->vha->default_item)
6392 memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6393 else
6394 kfree(item);
6395 }
6396
qla24xx_process_purex_list(struct purex_list * list)6397 void qla24xx_process_purex_list(struct purex_list *list)
6398 {
6399 struct list_head head = LIST_HEAD_INIT(head);
6400 struct purex_item *item, *next;
6401 ulong flags;
6402
6403 spin_lock_irqsave(&list->lock, flags);
6404 list_splice_init(&list->head, &head);
6405 spin_unlock_irqrestore(&list->lock, flags);
6406
6407 list_for_each_entry_safe(item, next, &head, list) {
6408 list_del(&item->list);
6409 item->process_item(item->vha, item);
6410 qla24xx_free_purex_item(item);
6411 }
6412 }
6413
6414 /*
6415 * Context: task, can sleep
6416 */
6417 void
qla83xx_idc_unlock(scsi_qla_host_t * base_vha,uint16_t requester_id)6418 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6419 {
6420 #if 0
6421 uint16_t options = (requester_id << 15) | BIT_7;
6422 #endif
6423 uint16_t retry;
6424 uint32_t data;
6425 struct qla_hw_data *ha = base_vha->hw;
6426
6427 might_sleep();
6428
6429 /* IDC-unlock implementation using driver-unlock/lock-id
6430 * remote registers
6431 */
6432 retry = 0;
6433 retry_unlock:
6434 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
6435 == QLA_SUCCESS) {
6436 if (data == ha->portnum) {
6437 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
6438 /* Clearing lock-id by setting 0xff */
6439 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
6440 } else if (retry < 10) {
6441 /* SV: XXX: IDC unlock retrying needed here? */
6442
6443 /* Retry for IDC-unlock */
6444 msleep(QLA83XX_WAIT_LOGIC_MS);
6445 retry++;
6446 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
6447 "Failed to release IDC lock, retrying=%d\n", retry);
6448 goto retry_unlock;
6449 }
6450 } else if (retry < 10) {
6451 /* Retry for IDC-unlock */
6452 msleep(QLA83XX_WAIT_LOGIC_MS);
6453 retry++;
6454 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
6455 "Failed to read drv-lockid, retrying=%d\n", retry);
6456 goto retry_unlock;
6457 }
6458
6459 return;
6460
6461 #if 0
6462 /* XXX: IDC-unlock implementation using access-control mbx */
6463 retry = 0;
6464 retry_unlock2:
6465 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
6466 if (retry < 10) {
6467 /* Retry for IDC-unlock */
6468 msleep(QLA83XX_WAIT_LOGIC_MS);
6469 retry++;
6470 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
6471 "Failed to release IDC lock, retrying=%d\n", retry);
6472 goto retry_unlock2;
6473 }
6474 }
6475
6476 return;
6477 #endif
6478 }
6479
6480 int
__qla83xx_set_drv_presence(scsi_qla_host_t * vha)6481 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6482 {
6483 int rval = QLA_SUCCESS;
6484 struct qla_hw_data *ha = vha->hw;
6485 uint32_t drv_presence;
6486
6487 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6488 if (rval == QLA_SUCCESS) {
6489 drv_presence |= (1 << ha->portnum);
6490 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6491 drv_presence);
6492 }
6493
6494 return rval;
6495 }
6496
6497 int
qla83xx_set_drv_presence(scsi_qla_host_t * vha)6498 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6499 {
6500 int rval = QLA_SUCCESS;
6501
6502 qla83xx_idc_lock(vha, 0);
6503 rval = __qla83xx_set_drv_presence(vha);
6504 qla83xx_idc_unlock(vha, 0);
6505
6506 return rval;
6507 }
6508
6509 int
__qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6510 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6511 {
6512 int rval = QLA_SUCCESS;
6513 struct qla_hw_data *ha = vha->hw;
6514 uint32_t drv_presence;
6515
6516 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6517 if (rval == QLA_SUCCESS) {
6518 drv_presence &= ~(1 << ha->portnum);
6519 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6520 drv_presence);
6521 }
6522
6523 return rval;
6524 }
6525
6526 int
qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6527 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6528 {
6529 int rval = QLA_SUCCESS;
6530
6531 qla83xx_idc_lock(vha, 0);
6532 rval = __qla83xx_clear_drv_presence(vha);
6533 qla83xx_idc_unlock(vha, 0);
6534
6535 return rval;
6536 }
6537
6538 static void
qla83xx_need_reset_handler(scsi_qla_host_t * vha)6539 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
6540 {
6541 struct qla_hw_data *ha = vha->hw;
6542 uint32_t drv_ack, drv_presence;
6543 unsigned long ack_timeout;
6544
6545 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6546 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6547 while (1) {
6548 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6549 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6550 if ((drv_ack & drv_presence) == drv_presence)
6551 break;
6552
6553 if (time_after_eq(jiffies, ack_timeout)) {
6554 ql_log(ql_log_warn, vha, 0xb067,
6555 "RESET ACK TIMEOUT! drv_presence=0x%x "
6556 "drv_ack=0x%x\n", drv_presence, drv_ack);
6557 /*
6558 * The function(s) which did not ack in time are forced
6559 * to withdraw any further participation in the IDC
6560 * reset.
6561 */
6562 if (drv_ack != drv_presence)
6563 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6564 drv_ack);
6565 break;
6566 }
6567
6568 qla83xx_idc_unlock(vha, 0);
6569 msleep(1000);
6570 qla83xx_idc_lock(vha, 0);
6571 }
6572
6573 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
6574 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6575 }
6576
6577 static int
qla83xx_device_bootstrap(scsi_qla_host_t * vha)6578 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
6579 {
6580 int rval = QLA_SUCCESS;
6581 uint32_t idc_control;
6582
6583 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
6584 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
6585
6586 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6587 __qla83xx_get_idc_control(vha, &idc_control);
6588 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
6589 __qla83xx_set_idc_control(vha, 0);
6590
6591 qla83xx_idc_unlock(vha, 0);
6592 rval = qla83xx_restart_nic_firmware(vha);
6593 qla83xx_idc_lock(vha, 0);
6594
6595 if (rval != QLA_SUCCESS) {
6596 ql_log(ql_log_fatal, vha, 0xb06a,
6597 "Failed to restart NIC f/w.\n");
6598 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6599 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6600 } else {
6601 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6602 "Success in restarting nic f/w.\n");
6603 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6604 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6605 }
6606
6607 return rval;
6608 }
6609
6610 /* Assumes idc_lock always held on entry */
6611 int
qla83xx_idc_state_handler(scsi_qla_host_t * base_vha)6612 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6613 {
6614 struct qla_hw_data *ha = base_vha->hw;
6615 int rval = QLA_SUCCESS;
6616 unsigned long dev_init_timeout;
6617 uint32_t dev_state;
6618
6619 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6620 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6621
6622 while (1) {
6623
6624 if (time_after_eq(jiffies, dev_init_timeout)) {
6625 ql_log(ql_log_warn, base_vha, 0xb06e,
6626 "Initialization TIMEOUT!\n");
6627 /* Init timeout. Disable further NIC Core
6628 * communication.
6629 */
6630 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6631 QLA8XXX_DEV_FAILED);
6632 ql_log(ql_log_info, base_vha, 0xb06f,
6633 "HW State: FAILED.\n");
6634 }
6635
6636 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6637 switch (dev_state) {
6638 case QLA8XXX_DEV_READY:
6639 if (ha->flags.nic_core_reset_owner)
6640 qla83xx_idc_audit(base_vha,
6641 IDC_AUDIT_COMPLETION);
6642 ha->flags.nic_core_reset_owner = 0;
6643 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6644 "Reset_owner reset by 0x%x.\n",
6645 ha->portnum);
6646 goto exit;
6647 case QLA8XXX_DEV_COLD:
6648 if (ha->flags.nic_core_reset_owner)
6649 rval = qla83xx_device_bootstrap(base_vha);
6650 else {
6651 /* Wait for AEN to change device-state */
6652 qla83xx_idc_unlock(base_vha, 0);
6653 msleep(1000);
6654 qla83xx_idc_lock(base_vha, 0);
6655 }
6656 break;
6657 case QLA8XXX_DEV_INITIALIZING:
6658 /* Wait for AEN to change device-state */
6659 qla83xx_idc_unlock(base_vha, 0);
6660 msleep(1000);
6661 qla83xx_idc_lock(base_vha, 0);
6662 break;
6663 case QLA8XXX_DEV_NEED_RESET:
6664 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6665 qla83xx_need_reset_handler(base_vha);
6666 else {
6667 /* Wait for AEN to change device-state */
6668 qla83xx_idc_unlock(base_vha, 0);
6669 msleep(1000);
6670 qla83xx_idc_lock(base_vha, 0);
6671 }
6672 /* reset timeout value after need reset handler */
6673 dev_init_timeout = jiffies +
6674 (ha->fcoe_dev_init_timeout * HZ);
6675 break;
6676 case QLA8XXX_DEV_NEED_QUIESCENT:
6677 /* XXX: DEBUG for now */
6678 qla83xx_idc_unlock(base_vha, 0);
6679 msleep(1000);
6680 qla83xx_idc_lock(base_vha, 0);
6681 break;
6682 case QLA8XXX_DEV_QUIESCENT:
6683 /* XXX: DEBUG for now */
6684 if (ha->flags.quiesce_owner)
6685 goto exit;
6686
6687 qla83xx_idc_unlock(base_vha, 0);
6688 msleep(1000);
6689 qla83xx_idc_lock(base_vha, 0);
6690 dev_init_timeout = jiffies +
6691 (ha->fcoe_dev_init_timeout * HZ);
6692 break;
6693 case QLA8XXX_DEV_FAILED:
6694 if (ha->flags.nic_core_reset_owner)
6695 qla83xx_idc_audit(base_vha,
6696 IDC_AUDIT_COMPLETION);
6697 ha->flags.nic_core_reset_owner = 0;
6698 __qla83xx_clear_drv_presence(base_vha);
6699 qla83xx_idc_unlock(base_vha, 0);
6700 qla8xxx_dev_failed_handler(base_vha);
6701 rval = QLA_FUNCTION_FAILED;
6702 qla83xx_idc_lock(base_vha, 0);
6703 goto exit;
6704 case QLA8XXX_BAD_VALUE:
6705 qla83xx_idc_unlock(base_vha, 0);
6706 msleep(1000);
6707 qla83xx_idc_lock(base_vha, 0);
6708 break;
6709 default:
6710 ql_log(ql_log_warn, base_vha, 0xb071,
6711 "Unknown Device State: %x.\n", dev_state);
6712 qla83xx_idc_unlock(base_vha, 0);
6713 qla8xxx_dev_failed_handler(base_vha);
6714 rval = QLA_FUNCTION_FAILED;
6715 qla83xx_idc_lock(base_vha, 0);
6716 goto exit;
6717 }
6718 }
6719
6720 exit:
6721 return rval;
6722 }
6723
6724 void
qla2x00_disable_board_on_pci_error(struct work_struct * work)6725 qla2x00_disable_board_on_pci_error(struct work_struct *work)
6726 {
6727 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6728 board_disable);
6729 struct pci_dev *pdev = ha->pdev;
6730 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6731
6732 ql_log(ql_log_warn, base_vha, 0x015b,
6733 "Disabling adapter.\n");
6734
6735 if (!atomic_read(&pdev->enable_cnt)) {
6736 ql_log(ql_log_info, base_vha, 0xfffc,
6737 "PCI device disabled, no action req for PCI error=%lx\n",
6738 base_vha->pci_flags);
6739 return;
6740 }
6741
6742 /*
6743 * if UNLOADING flag is already set, then continue unload,
6744 * where it was set first.
6745 */
6746 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
6747 return;
6748
6749 qla2x00_wait_for_sess_deletion(base_vha);
6750
6751 qla2x00_delete_all_vps(ha, base_vha);
6752
6753 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6754
6755 qla2x00_dfs_remove(base_vha);
6756
6757 qla84xx_put_chip(base_vha);
6758
6759 if (base_vha->timer_active)
6760 qla2x00_stop_timer(base_vha);
6761
6762 base_vha->flags.online = 0;
6763
6764 qla2x00_destroy_deferred_work(ha);
6765
6766 /*
6767 * Do not try to stop beacon blink as it will issue a mailbox
6768 * command.
6769 */
6770 qla2x00_free_sysfs_attr(base_vha, false);
6771
6772 fc_remove_host(base_vha->host);
6773
6774 scsi_remove_host(base_vha->host);
6775
6776 base_vha->flags.init_done = 0;
6777 qla25xx_delete_queues(base_vha);
6778 qla2x00_free_fcports(base_vha);
6779 qla2x00_free_irqs(base_vha);
6780 qla2x00_mem_free(ha);
6781 qla82xx_md_free(base_vha);
6782 qla2x00_free_queues(ha);
6783
6784 qla2x00_unmap_iobases(ha);
6785
6786 pci_release_selected_regions(ha->pdev, ha->bars);
6787 pci_disable_pcie_error_reporting(pdev);
6788 pci_disable_device(pdev);
6789
6790 /*
6791 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6792 */
6793 }
6794
6795 /**************************************************************************
6796 * qla2x00_do_dpc
6797 * This kernel thread is a task that is schedule by the interrupt handler
6798 * to perform the background processing for interrupts.
6799 *
6800 * Notes:
6801 * This task always run in the context of a kernel thread. It
6802 * is kick-off by the driver's detect code and starts up
6803 * up one per adapter. It immediately goes to sleep and waits for
6804 * some fibre event. When either the interrupt handler or
6805 * the timer routine detects a event it will one of the task
6806 * bits then wake us up.
6807 **************************************************************************/
6808 static int
qla2x00_do_dpc(void * data)6809 qla2x00_do_dpc(void *data)
6810 {
6811 scsi_qla_host_t *base_vha;
6812 struct qla_hw_data *ha;
6813 uint32_t online;
6814 struct qla_qpair *qpair;
6815
6816 ha = (struct qla_hw_data *)data;
6817 base_vha = pci_get_drvdata(ha->pdev);
6818
6819 set_user_nice(current, MIN_NICE);
6820
6821 set_current_state(TASK_INTERRUPTIBLE);
6822 while (!kthread_should_stop()) {
6823 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6824 "DPC handler sleeping.\n");
6825
6826 schedule();
6827
6828 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags))
6829 qla_pci_set_eeh_busy(base_vha);
6830
6831 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6832 goto end_loop;
6833
6834 if (ha->flags.eeh_busy) {
6835 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6836 "eeh_busy=%d.\n", ha->flags.eeh_busy);
6837 goto end_loop;
6838 }
6839
6840 ha->dpc_active = 1;
6841
6842 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6843 "DPC handler waking up, dpc_flags=0x%lx.\n",
6844 base_vha->dpc_flags);
6845
6846 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6847 break;
6848
6849 if (IS_P3P_TYPE(ha)) {
6850 if (IS_QLA8044(ha)) {
6851 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6852 &base_vha->dpc_flags)) {
6853 qla8044_idc_lock(ha);
6854 qla8044_wr_direct(base_vha,
6855 QLA8044_CRB_DEV_STATE_INDEX,
6856 QLA8XXX_DEV_FAILED);
6857 qla8044_idc_unlock(ha);
6858 ql_log(ql_log_info, base_vha, 0x4004,
6859 "HW State: FAILED.\n");
6860 qla8044_device_state_handler(base_vha);
6861 continue;
6862 }
6863
6864 } else {
6865 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6866 &base_vha->dpc_flags)) {
6867 qla82xx_idc_lock(ha);
6868 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6869 QLA8XXX_DEV_FAILED);
6870 qla82xx_idc_unlock(ha);
6871 ql_log(ql_log_info, base_vha, 0x0151,
6872 "HW State: FAILED.\n");
6873 qla82xx_device_state_handler(base_vha);
6874 continue;
6875 }
6876 }
6877
6878 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6879 &base_vha->dpc_flags)) {
6880
6881 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6882 "FCoE context reset scheduled.\n");
6883 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6884 &base_vha->dpc_flags))) {
6885 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6886 /* FCoE-ctx reset failed.
6887 * Escalate to chip-reset
6888 */
6889 set_bit(ISP_ABORT_NEEDED,
6890 &base_vha->dpc_flags);
6891 }
6892 clear_bit(ABORT_ISP_ACTIVE,
6893 &base_vha->dpc_flags);
6894 }
6895
6896 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6897 "FCoE context reset end.\n");
6898 }
6899 } else if (IS_QLAFX00(ha)) {
6900 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6901 &base_vha->dpc_flags)) {
6902 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6903 "Firmware Reset Recovery\n");
6904 if (qlafx00_reset_initialize(base_vha)) {
6905 /* Failed. Abort isp later. */
6906 if (!test_bit(UNLOADING,
6907 &base_vha->dpc_flags)) {
6908 set_bit(ISP_UNRECOVERABLE,
6909 &base_vha->dpc_flags);
6910 ql_dbg(ql_dbg_dpc, base_vha,
6911 0x4021,
6912 "Reset Recovery Failed\n");
6913 }
6914 }
6915 }
6916
6917 if (test_and_clear_bit(FX00_TARGET_SCAN,
6918 &base_vha->dpc_flags)) {
6919 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6920 "ISPFx00 Target Scan scheduled\n");
6921 if (qlafx00_rescan_isp(base_vha)) {
6922 if (!test_bit(UNLOADING,
6923 &base_vha->dpc_flags))
6924 set_bit(ISP_UNRECOVERABLE,
6925 &base_vha->dpc_flags);
6926 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6927 "ISPFx00 Target Scan Failed\n");
6928 }
6929 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6930 "ISPFx00 Target Scan End\n");
6931 }
6932 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6933 &base_vha->dpc_flags)) {
6934 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6935 "ISPFx00 Host Info resend scheduled\n");
6936 qlafx00_fx_disc(base_vha,
6937 &base_vha->hw->mr.fcport,
6938 FXDISC_REG_HOST_INFO);
6939 }
6940 }
6941
6942 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6943 &base_vha->dpc_flags)) {
6944 /* Semantic:
6945 * - NO-OP -- await next ISP-ABORT. Preferred method
6946 * to minimize disruptions that will occur
6947 * when a forced chip-reset occurs.
6948 * - Force -- ISP-ABORT scheduled.
6949 */
6950 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
6951 }
6952
6953 if (test_and_clear_bit
6954 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6955 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
6956 bool do_reset = true;
6957
6958 switch (base_vha->qlini_mode) {
6959 case QLA2XXX_INI_MODE_ENABLED:
6960 break;
6961 case QLA2XXX_INI_MODE_DISABLED:
6962 if (!qla_tgt_mode_enabled(base_vha) &&
6963 !ha->flags.fw_started)
6964 do_reset = false;
6965 break;
6966 case QLA2XXX_INI_MODE_DUAL:
6967 if (!qla_dual_mode_enabled(base_vha) &&
6968 !ha->flags.fw_started)
6969 do_reset = false;
6970 break;
6971 default:
6972 break;
6973 }
6974
6975 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
6976 &base_vha->dpc_flags))) {
6977 base_vha->flags.online = 1;
6978 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6979 "ISP abort scheduled.\n");
6980 if (ha->isp_ops->abort_isp(base_vha)) {
6981 /* failed. retry later */
6982 set_bit(ISP_ABORT_NEEDED,
6983 &base_vha->dpc_flags);
6984 }
6985 clear_bit(ABORT_ISP_ACTIVE,
6986 &base_vha->dpc_flags);
6987 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6988 "ISP abort end.\n");
6989 }
6990 }
6991
6992 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
6993 if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
6994 qla24xx_process_purex_list
6995 (&base_vha->purex_list);
6996 clear_bit(PROCESS_PUREX_IOCB,
6997 &base_vha->dpc_flags);
6998 }
6999 }
7000
7001 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
7002 &base_vha->dpc_flags)) {
7003 qla2x00_update_fcports(base_vha);
7004 }
7005
7006 if (IS_QLAFX00(ha))
7007 goto loop_resync_check;
7008
7009 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7010 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
7011 "Quiescence mode scheduled.\n");
7012 if (IS_P3P_TYPE(ha)) {
7013 if (IS_QLA82XX(ha))
7014 qla82xx_device_state_handler(base_vha);
7015 if (IS_QLA8044(ha))
7016 qla8044_device_state_handler(base_vha);
7017 clear_bit(ISP_QUIESCE_NEEDED,
7018 &base_vha->dpc_flags);
7019 if (!ha->flags.quiesce_owner) {
7020 qla2x00_perform_loop_resync(base_vha);
7021 if (IS_QLA82XX(ha)) {
7022 qla82xx_idc_lock(ha);
7023 qla82xx_clear_qsnt_ready(
7024 base_vha);
7025 qla82xx_idc_unlock(ha);
7026 } else if (IS_QLA8044(ha)) {
7027 qla8044_idc_lock(ha);
7028 qla8044_clear_qsnt_ready(
7029 base_vha);
7030 qla8044_idc_unlock(ha);
7031 }
7032 }
7033 } else {
7034 clear_bit(ISP_QUIESCE_NEEDED,
7035 &base_vha->dpc_flags);
7036 qla2x00_quiesce_io(base_vha);
7037 }
7038 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
7039 "Quiescence mode end.\n");
7040 }
7041
7042 if (test_and_clear_bit(RESET_MARKER_NEEDED,
7043 &base_vha->dpc_flags) &&
7044 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
7045
7046 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
7047 "Reset marker scheduled.\n");
7048 qla2x00_rst_aen(base_vha);
7049 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7050 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
7051 "Reset marker end.\n");
7052 }
7053
7054 /* Retry each device up to login retry count */
7055 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
7056 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
7057 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
7058
7059 if (!base_vha->relogin_jif ||
7060 time_after_eq(jiffies, base_vha->relogin_jif)) {
7061 base_vha->relogin_jif = jiffies + HZ;
7062 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
7063
7064 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
7065 "Relogin scheduled.\n");
7066 qla24xx_post_relogin_work(base_vha);
7067 }
7068 }
7069 loop_resync_check:
7070 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
7071 &base_vha->dpc_flags)) {
7072
7073 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
7074 "Loop resync scheduled.\n");
7075
7076 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
7077 &base_vha->dpc_flags))) {
7078
7079 qla2x00_loop_resync(base_vha);
7080
7081 clear_bit(LOOP_RESYNC_ACTIVE,
7082 &base_vha->dpc_flags);
7083 }
7084
7085 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
7086 "Loop resync end.\n");
7087 }
7088
7089 if (IS_QLAFX00(ha))
7090 goto intr_on_check;
7091
7092 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
7093 atomic_read(&base_vha->loop_state) == LOOP_READY) {
7094 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
7095 qla2xxx_flash_npiv_conf(base_vha);
7096 }
7097
7098 intr_on_check:
7099 if (!ha->interrupts_on)
7100 ha->isp_ops->enable_intrs(ha);
7101
7102 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
7103 &base_vha->dpc_flags)) {
7104 if (ha->beacon_blink_led == 1)
7105 ha->isp_ops->beacon_blink(base_vha);
7106 }
7107
7108 /* qpair online check */
7109 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
7110 &base_vha->dpc_flags)) {
7111 if (ha->flags.eeh_busy ||
7112 ha->flags.pci_channel_io_perm_failure)
7113 online = 0;
7114 else
7115 online = 1;
7116
7117 mutex_lock(&ha->mq_lock);
7118 list_for_each_entry(qpair, &base_vha->qp_list,
7119 qp_list_elem)
7120 qpair->online = online;
7121 mutex_unlock(&ha->mq_lock);
7122 }
7123
7124 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
7125 &base_vha->dpc_flags)) {
7126 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold;
7127
7128 if (threshold > ha->orig_fw_xcb_count)
7129 threshold = ha->orig_fw_xcb_count;
7130
7131 ql_log(ql_log_info, base_vha, 0xffffff,
7132 "SET ZIO Activity exchange threshold to %d.\n",
7133 threshold);
7134 if (qla27xx_set_zio_threshold(base_vha, threshold)) {
7135 ql_log(ql_log_info, base_vha, 0xffffff,
7136 "Unable to SET ZIO Activity exchange threshold to %d.\n",
7137 threshold);
7138 }
7139 }
7140
7141 if (!IS_QLAFX00(ha))
7142 qla2x00_do_dpc_all_vps(base_vha);
7143
7144 if (test_and_clear_bit(N2N_LINK_RESET,
7145 &base_vha->dpc_flags)) {
7146 qla2x00_lip_reset(base_vha);
7147 }
7148
7149 ha->dpc_active = 0;
7150 end_loop:
7151 set_current_state(TASK_INTERRUPTIBLE);
7152 } /* End of while(1) */
7153 __set_current_state(TASK_RUNNING);
7154
7155 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
7156 "DPC handler exiting.\n");
7157
7158 /*
7159 * Make sure that nobody tries to wake us up again.
7160 */
7161 ha->dpc_active = 0;
7162
7163 /* Cleanup any residual CTX SRBs. */
7164 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
7165
7166 return 0;
7167 }
7168
7169 void
qla2xxx_wake_dpc(struct scsi_qla_host * vha)7170 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
7171 {
7172 struct qla_hw_data *ha = vha->hw;
7173 struct task_struct *t = ha->dpc_thread;
7174
7175 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
7176 wake_up_process(t);
7177 }
7178
7179 /*
7180 * qla2x00_rst_aen
7181 * Processes asynchronous reset.
7182 *
7183 * Input:
7184 * ha = adapter block pointer.
7185 */
7186 static void
qla2x00_rst_aen(scsi_qla_host_t * vha)7187 qla2x00_rst_aen(scsi_qla_host_t *vha)
7188 {
7189 if (vha->flags.online && !vha->flags.reset_active &&
7190 !atomic_read(&vha->loop_down_timer) &&
7191 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
7192 do {
7193 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7194
7195 /*
7196 * Issue marker command only when we are going to start
7197 * the I/O.
7198 */
7199 vha->marker_needed = 1;
7200 } while (!atomic_read(&vha->loop_down_timer) &&
7201 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
7202 }
7203 }
7204
qla_do_heartbeat(struct scsi_qla_host * vha)7205 static bool qla_do_heartbeat(struct scsi_qla_host *vha)
7206 {
7207 struct qla_hw_data *ha = vha->hw;
7208 u32 cmpl_cnt;
7209 u16 i;
7210 bool do_heartbeat = false;
7211
7212 /*
7213 * Allow do_heartbeat only if we don’t have any active interrupts,
7214 * but there are still IOs outstanding with firmware.
7215 */
7216 cmpl_cnt = ha->base_qpair->cmd_completion_cnt;
7217 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt &&
7218 cmpl_cnt != ha->base_qpair->cmd_cnt) {
7219 do_heartbeat = true;
7220 goto skip;
7221 }
7222 ha->base_qpair->prev_completion_cnt = cmpl_cnt;
7223
7224 for (i = 0; i < ha->max_qpairs; i++) {
7225 if (ha->queue_pair_map[i]) {
7226 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt;
7227 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt &&
7228 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) {
7229 do_heartbeat = true;
7230 break;
7231 }
7232 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt;
7233 }
7234 }
7235
7236 skip:
7237 return do_heartbeat;
7238 }
7239
qla_heart_beat(struct scsi_qla_host * vha,u16 dpc_started)7240 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started)
7241 {
7242 struct qla_hw_data *ha = vha->hw;
7243
7244 if (vha->vp_idx)
7245 return;
7246
7247 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha))
7248 return;
7249
7250 /*
7251 * dpc thread cannot run if heartbeat is running at the same time.
7252 * We also do not want to starve heartbeat task. Therefore, do
7253 * heartbeat task at least once every 5 seconds.
7254 */
7255 if (dpc_started &&
7256 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ))
7257 return;
7258
7259 if (qla_do_heartbeat(vha)) {
7260 ha->last_heartbeat_run_jiffies = jiffies;
7261 queue_work(ha->wq, &ha->heartbeat_work);
7262 }
7263 }
7264
qla_wind_down_chip(scsi_qla_host_t * vha)7265 static void qla_wind_down_chip(scsi_qla_host_t *vha)
7266 {
7267 struct qla_hw_data *ha = vha->hw;
7268
7269 if (!ha->flags.eeh_busy)
7270 return;
7271 if (ha->pci_error_state)
7272 /* system is trying to recover */
7273 return;
7274
7275 /*
7276 * Current system is not handling PCIE error. At this point, this is
7277 * best effort to wind down the adapter.
7278 */
7279 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) &&
7280 !ha->flags.eeh_flush) {
7281 ql_log(ql_log_info, vha, 0x9009,
7282 "PCI Error detected, attempting to reset hardware.\n");
7283
7284 ha->isp_ops->reset_chip(vha);
7285 ha->isp_ops->disable_intrs(ha);
7286
7287 ha->flags.eeh_flush = EEH_FLUSH_RDY;
7288 ha->eeh_jif = jiffies;
7289
7290 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY &&
7291 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) {
7292 pci_clear_master(ha->pdev);
7293
7294 /* flush all command */
7295 qla2x00_abort_isp_cleanup(vha);
7296 ha->flags.eeh_flush = EEH_FLUSH_DONE;
7297
7298 ql_log(ql_log_info, vha, 0x900a,
7299 "PCI Error handling complete, all IOs aborted.\n");
7300 }
7301 }
7302
7303 /**************************************************************************
7304 * qla2x00_timer
7305 *
7306 * Description:
7307 * One second timer
7308 *
7309 * Context: Interrupt
7310 ***************************************************************************/
7311 void
qla2x00_timer(struct timer_list * t)7312 qla2x00_timer(struct timer_list *t)
7313 {
7314 scsi_qla_host_t *vha = from_timer(vha, t, timer);
7315 unsigned long cpu_flags = 0;
7316 int start_dpc = 0;
7317 int index;
7318 srb_t *sp;
7319 uint16_t w;
7320 struct qla_hw_data *ha = vha->hw;
7321 struct req_que *req;
7322 unsigned long flags;
7323 fc_port_t *fcport = NULL;
7324
7325 if (ha->flags.eeh_busy) {
7326 qla_wind_down_chip(vha);
7327
7328 ql_dbg(ql_dbg_timer, vha, 0x6000,
7329 "EEH = %d, restarting timer.\n",
7330 ha->flags.eeh_busy);
7331 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7332 return;
7333 }
7334
7335 /*
7336 * Hardware read to raise pending EEH errors during mailbox waits. If
7337 * the read returns -1 then disable the board.
7338 */
7339 if (!pci_channel_offline(ha->pdev)) {
7340 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
7341 qla2x00_check_reg16_for_disconnect(vha, w);
7342 }
7343
7344 /* Make sure qla82xx_watchdog is run only for physical port */
7345 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
7346 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7347 start_dpc++;
7348 if (IS_QLA82XX(ha))
7349 qla82xx_watchdog(vha);
7350 else if (IS_QLA8044(ha))
7351 qla8044_watchdog(vha);
7352 }
7353
7354 if (!vha->vp_idx && IS_QLAFX00(ha))
7355 qlafx00_timer_routine(vha);
7356
7357 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7358 vha->link_down_time++;
7359
7360 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
7361 list_for_each_entry(fcport, &vha->vp_fcports, list) {
7362 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7363 fcport->tgt_link_down_time++;
7364 }
7365 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
7366
7367 /* Loop down handler. */
7368 if (atomic_read(&vha->loop_down_timer) > 0 &&
7369 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7370 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
7371 && vha->flags.online) {
7372
7373 if (atomic_read(&vha->loop_down_timer) ==
7374 vha->loop_down_abort_time) {
7375
7376 ql_log(ql_log_info, vha, 0x6008,
7377 "Loop down - aborting the queues before time expires.\n");
7378
7379 if (!IS_QLA2100(ha) && vha->link_down_timeout)
7380 atomic_set(&vha->loop_state, LOOP_DEAD);
7381
7382 /*
7383 * Schedule an ISP abort to return any FCP2-device
7384 * commands.
7385 */
7386 /* NPIV - scan physical port only */
7387 if (!vha->vp_idx) {
7388 spin_lock_irqsave(&ha->hardware_lock,
7389 cpu_flags);
7390 req = ha->req_q_map[0];
7391 for (index = 1;
7392 index < req->num_outstanding_cmds;
7393 index++) {
7394 fc_port_t *sfcp;
7395
7396 sp = req->outstanding_cmds[index];
7397 if (!sp)
7398 continue;
7399 if (sp->cmd_type != TYPE_SRB)
7400 continue;
7401 if (sp->type != SRB_SCSI_CMD)
7402 continue;
7403 sfcp = sp->fcport;
7404 if (!(sfcp->flags & FCF_FCP2_DEVICE))
7405 continue;
7406
7407 if (IS_QLA82XX(ha))
7408 set_bit(FCOE_CTX_RESET_NEEDED,
7409 &vha->dpc_flags);
7410 else
7411 set_bit(ISP_ABORT_NEEDED,
7412 &vha->dpc_flags);
7413 break;
7414 }
7415 spin_unlock_irqrestore(&ha->hardware_lock,
7416 cpu_flags);
7417 }
7418 start_dpc++;
7419 }
7420
7421 /* if the loop has been down for 4 minutes, reinit adapter */
7422 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
7423 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7424 ql_log(ql_log_warn, vha, 0x6009,
7425 "Loop down - aborting ISP.\n");
7426
7427 if (IS_QLA82XX(ha))
7428 set_bit(FCOE_CTX_RESET_NEEDED,
7429 &vha->dpc_flags);
7430 else
7431 set_bit(ISP_ABORT_NEEDED,
7432 &vha->dpc_flags);
7433 }
7434 }
7435 ql_dbg(ql_dbg_timer, vha, 0x600a,
7436 "Loop down - seconds remaining %d.\n",
7437 atomic_read(&vha->loop_down_timer));
7438 }
7439 /* Check if beacon LED needs to be blinked for physical host only */
7440 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
7441 /* There is no beacon_blink function for ISP82xx */
7442 if (!IS_P3P_TYPE(ha)) {
7443 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7444 start_dpc++;
7445 }
7446 }
7447
7448 /* check if edif running */
7449 if (vha->hw->flags.edif_enabled)
7450 qla_edif_timer(vha);
7451
7452 /* Process any deferred work. */
7453 if (!list_empty(&vha->work_list)) {
7454 unsigned long flags;
7455 bool q = false;
7456
7457 spin_lock_irqsave(&vha->work_lock, flags);
7458 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7459 q = true;
7460 spin_unlock_irqrestore(&vha->work_lock, flags);
7461 if (q)
7462 queue_work(vha->hw->wq, &vha->iocb_work);
7463 }
7464
7465 /*
7466 * FC-NVME
7467 * see if the active AEN count has changed from what was last reported.
7468 */
7469 index = atomic_read(&ha->nvme_active_aen_cnt);
7470 if (!vha->vp_idx &&
7471 (index != ha->nvme_last_rptd_aen) &&
7472 ha->zio_mode == QLA_ZIO_MODE_6 &&
7473 !ha->flags.host_shutting_down) {
7474 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7475 ql_log(ql_log_info, vha, 0x3002,
7476 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
7477 ha->nvme_last_rptd_aen);
7478 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7479 start_dpc++;
7480 }
7481
7482 if (!vha->vp_idx &&
7483 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
7484 IS_ZIO_THRESHOLD_CAPABLE(ha)) {
7485 ql_log(ql_log_info, vha, 0x3002,
7486 "Sched: Set ZIO exchange threshold to %d.\n",
7487 ha->last_zio_threshold);
7488 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
7489 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7490 start_dpc++;
7491 }
7492
7493 /* borrowing w to signify dpc will run */
7494 w = 0;
7495 /* Schedule the DPC routine if needed */
7496 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7497 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
7498 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
7499 start_dpc ||
7500 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7501 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
7502 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7503 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
7504 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7505 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7506 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7507 ql_dbg(ql_dbg_timer, vha, 0x600b,
7508 "isp_abort_needed=%d loop_resync_needed=%d "
7509 "fcport_update_needed=%d start_dpc=%d "
7510 "reset_marker_needed=%d",
7511 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7512 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
7513 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
7514 start_dpc,
7515 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7516 ql_dbg(ql_dbg_timer, vha, 0x600c,
7517 "beacon_blink_needed=%d isp_unrecoverable=%d "
7518 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
7519 "relogin_needed=%d, Process_purex_iocb=%d.\n",
7520 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7521 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7522 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7523 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
7524 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7525 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
7526 qla2xxx_wake_dpc(vha);
7527 w = 1;
7528 }
7529
7530 qla_heart_beat(vha, w);
7531
7532 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7533 }
7534
7535 /* Firmware interface routines. */
7536
7537 #define FW_ISP21XX 0
7538 #define FW_ISP22XX 1
7539 #define FW_ISP2300 2
7540 #define FW_ISP2322 3
7541 #define FW_ISP24XX 4
7542 #define FW_ISP25XX 5
7543 #define FW_ISP81XX 6
7544 #define FW_ISP82XX 7
7545 #define FW_ISP2031 8
7546 #define FW_ISP8031 9
7547 #define FW_ISP27XX 10
7548 #define FW_ISP28XX 11
7549
7550 #define FW_FILE_ISP21XX "ql2100_fw.bin"
7551 #define FW_FILE_ISP22XX "ql2200_fw.bin"
7552 #define FW_FILE_ISP2300 "ql2300_fw.bin"
7553 #define FW_FILE_ISP2322 "ql2322_fw.bin"
7554 #define FW_FILE_ISP24XX "ql2400_fw.bin"
7555 #define FW_FILE_ISP25XX "ql2500_fw.bin"
7556 #define FW_FILE_ISP81XX "ql8100_fw.bin"
7557 #define FW_FILE_ISP82XX "ql8200_fw.bin"
7558 #define FW_FILE_ISP2031 "ql2600_fw.bin"
7559 #define FW_FILE_ISP8031 "ql8300_fw.bin"
7560 #define FW_FILE_ISP27XX "ql2700_fw.bin"
7561 #define FW_FILE_ISP28XX "ql2800_fw.bin"
7562
7563
7564 static DEFINE_MUTEX(qla_fw_lock);
7565
7566 static struct fw_blob qla_fw_blobs[] = {
7567 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
7568 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
7569 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
7570 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
7571 { .name = FW_FILE_ISP24XX, },
7572 { .name = FW_FILE_ISP25XX, },
7573 { .name = FW_FILE_ISP81XX, },
7574 { .name = FW_FILE_ISP82XX, },
7575 { .name = FW_FILE_ISP2031, },
7576 { .name = FW_FILE_ISP8031, },
7577 { .name = FW_FILE_ISP27XX, },
7578 { .name = FW_FILE_ISP28XX, },
7579 { .name = NULL, },
7580 };
7581
7582 struct fw_blob *
qla2x00_request_firmware(scsi_qla_host_t * vha)7583 qla2x00_request_firmware(scsi_qla_host_t *vha)
7584 {
7585 struct qla_hw_data *ha = vha->hw;
7586 struct fw_blob *blob;
7587
7588 if (IS_QLA2100(ha)) {
7589 blob = &qla_fw_blobs[FW_ISP21XX];
7590 } else if (IS_QLA2200(ha)) {
7591 blob = &qla_fw_blobs[FW_ISP22XX];
7592 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
7593 blob = &qla_fw_blobs[FW_ISP2300];
7594 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
7595 blob = &qla_fw_blobs[FW_ISP2322];
7596 } else if (IS_QLA24XX_TYPE(ha)) {
7597 blob = &qla_fw_blobs[FW_ISP24XX];
7598 } else if (IS_QLA25XX(ha)) {
7599 blob = &qla_fw_blobs[FW_ISP25XX];
7600 } else if (IS_QLA81XX(ha)) {
7601 blob = &qla_fw_blobs[FW_ISP81XX];
7602 } else if (IS_QLA82XX(ha)) {
7603 blob = &qla_fw_blobs[FW_ISP82XX];
7604 } else if (IS_QLA2031(ha)) {
7605 blob = &qla_fw_blobs[FW_ISP2031];
7606 } else if (IS_QLA8031(ha)) {
7607 blob = &qla_fw_blobs[FW_ISP8031];
7608 } else if (IS_QLA27XX(ha)) {
7609 blob = &qla_fw_blobs[FW_ISP27XX];
7610 } else if (IS_QLA28XX(ha)) {
7611 blob = &qla_fw_blobs[FW_ISP28XX];
7612 } else {
7613 return NULL;
7614 }
7615
7616 if (!blob->name)
7617 return NULL;
7618
7619 mutex_lock(&qla_fw_lock);
7620 if (blob->fw)
7621 goto out;
7622
7623 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7624 ql_log(ql_log_warn, vha, 0x0063,
7625 "Failed to load firmware image (%s).\n", blob->name);
7626 blob->fw = NULL;
7627 blob = NULL;
7628 }
7629
7630 out:
7631 mutex_unlock(&qla_fw_lock);
7632 return blob;
7633 }
7634
7635 static void
qla2x00_release_firmware(void)7636 qla2x00_release_firmware(void)
7637 {
7638 struct fw_blob *blob;
7639
7640 mutex_lock(&qla_fw_lock);
7641 for (blob = qla_fw_blobs; blob->name; blob++)
7642 release_firmware(blob->fw);
7643 mutex_unlock(&qla_fw_lock);
7644 }
7645
qla_pci_error_cleanup(scsi_qla_host_t * vha)7646 static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
7647 {
7648 struct qla_hw_data *ha = vha->hw;
7649 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7650 struct qla_qpair *qpair = NULL;
7651 struct scsi_qla_host *vp, *tvp;
7652 fc_port_t *fcport;
7653 int i;
7654 unsigned long flags;
7655
7656 ql_dbg(ql_dbg_aer, vha, 0x9000,
7657 "%s\n", __func__);
7658 ha->chip_reset++;
7659
7660 ha->base_qpair->chip_reset = ha->chip_reset;
7661 for (i = 0; i < ha->max_qpairs; i++) {
7662 if (ha->queue_pair_map[i])
7663 ha->queue_pair_map[i]->chip_reset =
7664 ha->base_qpair->chip_reset;
7665 }
7666
7667 /*
7668 * purge mailbox might take a while. Slot Reset/chip reset
7669 * will take care of the purge
7670 */
7671
7672 mutex_lock(&ha->mq_lock);
7673 ha->base_qpair->online = 0;
7674 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7675 qpair->online = 0;
7676 wmb();
7677 mutex_unlock(&ha->mq_lock);
7678
7679 qla2x00_mark_all_devices_lost(vha);
7680
7681 spin_lock_irqsave(&ha->vport_slock, flags);
7682 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7683 atomic_inc(&vp->vref_count);
7684 spin_unlock_irqrestore(&ha->vport_slock, flags);
7685 qla2x00_mark_all_devices_lost(vp);
7686 spin_lock_irqsave(&ha->vport_slock, flags);
7687 atomic_dec(&vp->vref_count);
7688 }
7689 spin_unlock_irqrestore(&ha->vport_slock, flags);
7690
7691 /* Clear all async request states across all VPs. */
7692 list_for_each_entry(fcport, &vha->vp_fcports, list)
7693 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7694
7695 spin_lock_irqsave(&ha->vport_slock, flags);
7696 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7697 atomic_inc(&vp->vref_count);
7698 spin_unlock_irqrestore(&ha->vport_slock, flags);
7699 list_for_each_entry(fcport, &vp->vp_fcports, list)
7700 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7701 spin_lock_irqsave(&ha->vport_slock, flags);
7702 atomic_dec(&vp->vref_count);
7703 }
7704 spin_unlock_irqrestore(&ha->vport_slock, flags);
7705 }
7706
7707
7708 static pci_ers_result_t
qla2xxx_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7709 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
7710 {
7711 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
7712 struct qla_hw_data *ha = vha->hw;
7713 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET;
7714
7715 ql_log(ql_log_warn, vha, 0x9000,
7716 "PCI error detected, state %x.\n", state);
7717 ha->pci_error_state = QLA_PCI_ERR_DETECTED;
7718
7719 if (!atomic_read(&pdev->enable_cnt)) {
7720 ql_log(ql_log_info, vha, 0xffff,
7721 "PCI device is disabled,state %x\n", state);
7722 ret = PCI_ERS_RESULT_NEED_RESET;
7723 goto out;
7724 }
7725
7726 switch (state) {
7727 case pci_channel_io_normal:
7728 qla_pci_set_eeh_busy(vha);
7729 if (ql2xmqsupport || ql2xnvmeenable) {
7730 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7731 qla2xxx_wake_dpc(vha);
7732 }
7733 ret = PCI_ERS_RESULT_CAN_RECOVER;
7734 break;
7735 case pci_channel_io_frozen:
7736 qla_pci_set_eeh_busy(vha);
7737 ret = PCI_ERS_RESULT_NEED_RESET;
7738 break;
7739 case pci_channel_io_perm_failure:
7740 ha->flags.pci_channel_io_perm_failure = 1;
7741 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
7742 if (ql2xmqsupport || ql2xnvmeenable) {
7743 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7744 qla2xxx_wake_dpc(vha);
7745 }
7746 ret = PCI_ERS_RESULT_DISCONNECT;
7747 }
7748 out:
7749 ql_dbg(ql_dbg_aer, vha, 0x600d,
7750 "PCI error detected returning [%x].\n", ret);
7751 return ret;
7752 }
7753
7754 static pci_ers_result_t
qla2xxx_pci_mmio_enabled(struct pci_dev * pdev)7755 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
7756 {
7757 int risc_paused = 0;
7758 uint32_t stat;
7759 unsigned long flags;
7760 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7761 struct qla_hw_data *ha = base_vha->hw;
7762 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7763 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
7764
7765 ql_log(ql_log_warn, base_vha, 0x9000,
7766 "mmio enabled\n");
7767
7768 ha->pci_error_state = QLA_PCI_MMIO_ENABLED;
7769
7770 if (IS_QLA82XX(ha))
7771 return PCI_ERS_RESULT_RECOVERED;
7772
7773 if (qla2x00_isp_reg_stat(ha)) {
7774 ql_log(ql_log_info, base_vha, 0x803f,
7775 "During mmio enabled, PCI/Register disconnect still detected.\n");
7776 goto out;
7777 }
7778
7779 spin_lock_irqsave(&ha->hardware_lock, flags);
7780 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
7781 stat = rd_reg_word(®->hccr);
7782 if (stat & HCCR_RISC_PAUSE)
7783 risc_paused = 1;
7784 } else if (IS_QLA23XX(ha)) {
7785 stat = rd_reg_dword(®->u.isp2300.host_status);
7786 if (stat & HSR_RISC_PAUSED)
7787 risc_paused = 1;
7788 } else if (IS_FWI2_CAPABLE(ha)) {
7789 stat = rd_reg_dword(®24->host_status);
7790 if (stat & HSRX_RISC_PAUSED)
7791 risc_paused = 1;
7792 }
7793 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7794
7795 if (risc_paused) {
7796 ql_log(ql_log_info, base_vha, 0x9003,
7797 "RISC paused -- mmio_enabled, Dumping firmware.\n");
7798 qla2xxx_dump_fw(base_vha);
7799 }
7800 out:
7801 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */
7802 ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7803 "mmio enabled returning.\n");
7804 return PCI_ERS_RESULT_NEED_RESET;
7805 }
7806
7807 static pci_ers_result_t
qla2xxx_pci_slot_reset(struct pci_dev * pdev)7808 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7809 {
7810 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
7811 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7812 struct qla_hw_data *ha = base_vha->hw;
7813 int rc;
7814 struct qla_qpair *qpair = NULL;
7815
7816 ql_log(ql_log_warn, base_vha, 0x9004,
7817 "Slot Reset.\n");
7818
7819 ha->pci_error_state = QLA_PCI_SLOT_RESET;
7820 /* Workaround: qla2xxx driver which access hardware earlier
7821 * needs error state to be pci_channel_io_online.
7822 * Otherwise mailbox command timesout.
7823 */
7824 pdev->error_state = pci_channel_io_normal;
7825
7826 pci_restore_state(pdev);
7827
7828 /* pci_restore_state() clears the saved_state flag of the device
7829 * save restored state which resets saved_state flag
7830 */
7831 pci_save_state(pdev);
7832
7833 if (ha->mem_only)
7834 rc = pci_enable_device_mem(pdev);
7835 else
7836 rc = pci_enable_device(pdev);
7837
7838 if (rc) {
7839 ql_log(ql_log_warn, base_vha, 0x9005,
7840 "Can't re-enable PCI device after reset.\n");
7841 goto exit_slot_reset;
7842 }
7843
7844
7845 if (ha->isp_ops->pci_config(base_vha))
7846 goto exit_slot_reset;
7847
7848 mutex_lock(&ha->mq_lock);
7849 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7850 qpair->online = 1;
7851 mutex_unlock(&ha->mq_lock);
7852
7853 ha->flags.eeh_busy = 0;
7854 base_vha->flags.online = 1;
7855 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7856 ha->isp_ops->abort_isp(base_vha);
7857 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7858
7859 if (qla2x00_isp_reg_stat(ha)) {
7860 ha->flags.eeh_busy = 1;
7861 qla_pci_error_cleanup(base_vha);
7862 ql_log(ql_log_warn, base_vha, 0x9005,
7863 "Device unable to recover from PCI error.\n");
7864 } else {
7865 ret = PCI_ERS_RESULT_RECOVERED;
7866 }
7867
7868 exit_slot_reset:
7869 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7870 "Slot Reset returning %x.\n", ret);
7871
7872 return ret;
7873 }
7874
7875 static void
qla2xxx_pci_resume(struct pci_dev * pdev)7876 qla2xxx_pci_resume(struct pci_dev *pdev)
7877 {
7878 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7879 struct qla_hw_data *ha = base_vha->hw;
7880 int ret;
7881
7882 ql_log(ql_log_warn, base_vha, 0x900f,
7883 "Pci Resume.\n");
7884
7885
7886 ret = qla2x00_wait_for_hba_online(base_vha);
7887 if (ret != QLA_SUCCESS) {
7888 ql_log(ql_log_fatal, base_vha, 0x9002,
7889 "The device failed to resume I/O from slot/link_reset.\n");
7890 }
7891 ha->pci_error_state = QLA_PCI_RESUME;
7892 ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7893 "Pci Resume returning.\n");
7894 }
7895
qla_pci_set_eeh_busy(struct scsi_qla_host * vha)7896 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha)
7897 {
7898 struct qla_hw_data *ha = vha->hw;
7899 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7900 bool do_cleanup = false;
7901 unsigned long flags;
7902
7903 if (ha->flags.eeh_busy)
7904 return;
7905
7906 spin_lock_irqsave(&base_vha->work_lock, flags);
7907 if (!ha->flags.eeh_busy) {
7908 ha->eeh_jif = jiffies;
7909 ha->flags.eeh_flush = 0;
7910
7911 ha->flags.eeh_busy = 1;
7912 do_cleanup = true;
7913 }
7914 spin_unlock_irqrestore(&base_vha->work_lock, flags);
7915
7916 if (do_cleanup)
7917 qla_pci_error_cleanup(base_vha);
7918 }
7919
7920 /*
7921 * this routine will schedule a task to pause IO from interrupt context
7922 * if caller sees a PCIE error event (register read = 0xf's)
7923 */
qla_schedule_eeh_work(struct scsi_qla_host * vha)7924 void qla_schedule_eeh_work(struct scsi_qla_host *vha)
7925 {
7926 struct qla_hw_data *ha = vha->hw;
7927 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7928
7929 if (ha->flags.eeh_busy)
7930 return;
7931
7932 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags);
7933 qla2xxx_wake_dpc(base_vha);
7934 }
7935
7936 static void
qla_pci_reset_prepare(struct pci_dev * pdev)7937 qla_pci_reset_prepare(struct pci_dev *pdev)
7938 {
7939 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7940 struct qla_hw_data *ha = base_vha->hw;
7941 struct qla_qpair *qpair;
7942
7943 ql_log(ql_log_warn, base_vha, 0xffff,
7944 "%s.\n", __func__);
7945
7946 /*
7947 * PCI FLR/function reset is about to reset the
7948 * slot. Stop the chip to stop all DMA access.
7949 * It is assumed that pci_reset_done will be called
7950 * after FLR to resume Chip operation.
7951 */
7952 ha->flags.eeh_busy = 1;
7953 mutex_lock(&ha->mq_lock);
7954 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7955 qpair->online = 0;
7956 mutex_unlock(&ha->mq_lock);
7957
7958 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7959 qla2x00_abort_isp_cleanup(base_vha);
7960 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
7961 }
7962
7963 static void
qla_pci_reset_done(struct pci_dev * pdev)7964 qla_pci_reset_done(struct pci_dev *pdev)
7965 {
7966 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7967 struct qla_hw_data *ha = base_vha->hw;
7968 struct qla_qpair *qpair;
7969
7970 ql_log(ql_log_warn, base_vha, 0xffff,
7971 "%s.\n", __func__);
7972
7973 /*
7974 * FLR just completed by PCI layer. Resume adapter
7975 */
7976 ha->flags.eeh_busy = 0;
7977 mutex_lock(&ha->mq_lock);
7978 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7979 qpair->online = 1;
7980 mutex_unlock(&ha->mq_lock);
7981
7982 base_vha->flags.online = 1;
7983 ha->isp_ops->abort_isp(base_vha);
7984 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7985 }
7986
qla2xxx_map_queues(struct Scsi_Host * shost)7987 static int qla2xxx_map_queues(struct Scsi_Host *shost)
7988 {
7989 int rc;
7990 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
7991 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
7992
7993 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
7994 rc = blk_mq_map_queues(qmap);
7995 else
7996 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
7997 return rc;
7998 }
7999
8000 struct scsi_host_template qla2xxx_driver_template = {
8001 .module = THIS_MODULE,
8002 .name = QLA2XXX_DRIVER_NAME,
8003 .queuecommand = qla2xxx_queuecommand,
8004
8005 .eh_timed_out = fc_eh_timed_out,
8006 .eh_abort_handler = qla2xxx_eh_abort,
8007 .eh_should_retry_cmd = fc_eh_should_retry_cmd,
8008 .eh_device_reset_handler = qla2xxx_eh_device_reset,
8009 .eh_target_reset_handler = qla2xxx_eh_target_reset,
8010 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
8011 .eh_host_reset_handler = qla2xxx_eh_host_reset,
8012
8013 .slave_configure = qla2xxx_slave_configure,
8014
8015 .slave_alloc = qla2xxx_slave_alloc,
8016 .slave_destroy = qla2xxx_slave_destroy,
8017 .scan_finished = qla2xxx_scan_finished,
8018 .scan_start = qla2xxx_scan_start,
8019 .change_queue_depth = scsi_change_queue_depth,
8020 .map_queues = qla2xxx_map_queues,
8021 .this_id = -1,
8022 .cmd_per_lun = 3,
8023 .sg_tablesize = SG_ALL,
8024
8025 .max_sectors = 0xFFFF,
8026 .shost_groups = qla2x00_host_groups,
8027
8028 .supported_mode = MODE_INITIATOR,
8029 .track_queue_depth = 1,
8030 .cmd_size = sizeof(srb_t),
8031 };
8032
8033 static const struct pci_error_handlers qla2xxx_err_handler = {
8034 .error_detected = qla2xxx_pci_error_detected,
8035 .mmio_enabled = qla2xxx_pci_mmio_enabled,
8036 .slot_reset = qla2xxx_pci_slot_reset,
8037 .resume = qla2xxx_pci_resume,
8038 .reset_prepare = qla_pci_reset_prepare,
8039 .reset_done = qla_pci_reset_done,
8040 };
8041
8042 static struct pci_device_id qla2xxx_pci_tbl[] = {
8043 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
8044 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
8045 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
8046 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
8047 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
8048 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
8049 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
8050 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
8051 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
8052 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
8053 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
8054 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
8055 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
8056 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
8057 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
8058 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
8059 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8060 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
8061 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
8062 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
8063 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
8064 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
8065 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
8066 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
8067 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
8068 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
8069 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
8070 { 0 },
8071 };
8072 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
8073
8074 static struct pci_driver qla2xxx_pci_driver = {
8075 .name = QLA2XXX_DRIVER_NAME,
8076 .driver = {
8077 .owner = THIS_MODULE,
8078 },
8079 .id_table = qla2xxx_pci_tbl,
8080 .probe = qla2x00_probe_one,
8081 .remove = qla2x00_remove_one,
8082 .shutdown = qla2x00_shutdown,
8083 .err_handler = &qla2xxx_err_handler,
8084 };
8085
8086 static const struct file_operations apidev_fops = {
8087 .owner = THIS_MODULE,
8088 .llseek = noop_llseek,
8089 };
8090
8091 /**
8092 * qla2x00_module_init - Module initialization.
8093 **/
8094 static int __init
qla2x00_module_init(void)8095 qla2x00_module_init(void)
8096 {
8097 int ret = 0;
8098
8099 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
8100 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
8101 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
8102 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
8103 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
8104 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
8105 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
8106 BUILD_BUG_ON(sizeof(request_t) != 64);
8107 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
8108 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
8109 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
8110 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
8111 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
8112 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
8113 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
8114 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
8115 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
8116 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
8117 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
8118 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
8119 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604);
8120 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
8121 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
8122 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
8123 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
8124 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
8125 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
8126 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
8127 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
8128 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
8129 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
8130 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
8131 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
8132 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
8133 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
8134 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
8135 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
8136 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
8137 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
8138 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
8139 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
8140 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
8141 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
8142 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
8143 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
8144 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
8145 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
8146 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
8147 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
8148 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
8149 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
8150 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
8151 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
8152 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
8153 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
8154 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
8155 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
8156 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
8157 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
8158 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
8159 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
8160 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
8161 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
8162 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
8163 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
8164 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
8165 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
8166 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
8167 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
8168 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
8169 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
8170 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
8171 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
8172 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
8173 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
8174 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
8175 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
8176 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
8177 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
8178 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
8179 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
8180 BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
8181 BUILD_BUG_ON(sizeof(sw_info_t) != 32);
8182 BUILD_BUG_ON(sizeof(target_id_t) != 2);
8183
8184 /* Allocate cache for SRBs. */
8185 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
8186 SLAB_HWCACHE_ALIGN, NULL);
8187 if (srb_cachep == NULL) {
8188 ql_log(ql_log_fatal, NULL, 0x0001,
8189 "Unable to allocate SRB cache...Failing load!.\n");
8190 return -ENOMEM;
8191 }
8192
8193 /* Initialize target kmem_cache and mem_pools */
8194 ret = qlt_init();
8195 if (ret < 0) {
8196 goto destroy_cache;
8197 } else if (ret > 0) {
8198 /*
8199 * If initiator mode is explictly disabled by qlt_init(),
8200 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
8201 * performing scsi_scan_target() during LOOP UP event.
8202 */
8203 qla2xxx_transport_functions.disable_target_scan = 1;
8204 qla2xxx_transport_vport_functions.disable_target_scan = 1;
8205 }
8206
8207 /* Derive version string. */
8208 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
8209 if (ql2xextended_error_logging)
8210 strcat(qla2x00_version_str, "-debug");
8211 if (ql2xextended_error_logging == 1)
8212 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
8213
8214 qla2xxx_transport_template =
8215 fc_attach_transport(&qla2xxx_transport_functions);
8216 if (!qla2xxx_transport_template) {
8217 ql_log(ql_log_fatal, NULL, 0x0002,
8218 "fc_attach_transport failed...Failing load!.\n");
8219 ret = -ENODEV;
8220 goto qlt_exit;
8221 }
8222
8223 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
8224 if (apidev_major < 0) {
8225 ql_log(ql_log_fatal, NULL, 0x0003,
8226 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
8227 }
8228
8229 qla2xxx_transport_vport_template =
8230 fc_attach_transport(&qla2xxx_transport_vport_functions);
8231 if (!qla2xxx_transport_vport_template) {
8232 ql_log(ql_log_fatal, NULL, 0x0004,
8233 "fc_attach_transport vport failed...Failing load!.\n");
8234 ret = -ENODEV;
8235 goto unreg_chrdev;
8236 }
8237 ql_log(ql_log_info, NULL, 0x0005,
8238 "QLogic Fibre Channel HBA Driver: %s.\n",
8239 qla2x00_version_str);
8240 ret = pci_register_driver(&qla2xxx_pci_driver);
8241 if (ret) {
8242 ql_log(ql_log_fatal, NULL, 0x0006,
8243 "pci_register_driver failed...ret=%d Failing load!.\n",
8244 ret);
8245 goto release_vport_transport;
8246 }
8247 return ret;
8248
8249 release_vport_transport:
8250 fc_release_transport(qla2xxx_transport_vport_template);
8251
8252 unreg_chrdev:
8253 if (apidev_major >= 0)
8254 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8255 fc_release_transport(qla2xxx_transport_template);
8256
8257 qlt_exit:
8258 qlt_exit();
8259
8260 destroy_cache:
8261 kmem_cache_destroy(srb_cachep);
8262 return ret;
8263 }
8264
8265 /**
8266 * qla2x00_module_exit - Module cleanup.
8267 **/
8268 static void __exit
qla2x00_module_exit(void)8269 qla2x00_module_exit(void)
8270 {
8271 pci_unregister_driver(&qla2xxx_pci_driver);
8272 qla2x00_release_firmware();
8273 kmem_cache_destroy(ctx_cachep);
8274 fc_release_transport(qla2xxx_transport_vport_template);
8275 if (apidev_major >= 0)
8276 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8277 fc_release_transport(qla2xxx_transport_template);
8278 qlt_exit();
8279 kmem_cache_destroy(srb_cachep);
8280 }
8281
8282 module_init(qla2x00_module_init);
8283 module_exit(qla2x00_module_exit);
8284
8285 MODULE_AUTHOR("QLogic Corporation");
8286 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
8287 MODULE_LICENSE("GPL");
8288 MODULE_FIRMWARE(FW_FILE_ISP21XX);
8289 MODULE_FIRMWARE(FW_FILE_ISP22XX);
8290 MODULE_FIRMWARE(FW_FILE_ISP2300);
8291 MODULE_FIRMWARE(FW_FILE_ISP2322);
8292 MODULE_FIRMWARE(FW_FILE_ISP24XX);
8293 MODULE_FIRMWARE(FW_FILE_ISP25XX);
8294