1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * QLogic Fibre Channel HBA Driver
4  * Copyright (c)  2003-2014 QLogic Corporation
5  */
6 #include "qla_def.h"
7 
8 #include <linux/moduleparam.h>
9 #include <linux/vmalloc.h>
10 #include <linux/delay.h>
11 #include <linux/kthread.h>
12 #include <linux/mutex.h>
13 #include <linux/kobject.h>
14 #include <linux/slab.h>
15 #include <linux/blk-mq-pci.h>
16 #include <linux/refcount.h>
17 #include <linux/crash_dump.h>
18 #include <linux/trace_events.h>
19 #include <linux/trace.h>
20 
21 #include <scsi/scsi_tcq.h>
22 #include <scsi/scsicam.h>
23 #include <scsi/scsi_transport.h>
24 #include <scsi/scsi_transport_fc.h>
25 
26 #include "qla_target.h"
27 
28 /*
29  * Driver version
30  */
31 char qla2x00_version_str[40];
32 
33 static int apidev_major;
34 
35 /*
36  * SRB allocation cache
37  */
38 struct kmem_cache *srb_cachep;
39 
40 static struct trace_array *qla_trc_array;
41 
42 int ql2xfulldump_on_mpifail;
43 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
45 		 "Set this to take full dump on MPI hang.");
46 
47 int ql2xenforce_iocb_limit = 2;
48 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR);
49 MODULE_PARM_DESC(ql2xenforce_iocb_limit,
50 		 "Enforce IOCB throttling, to avoid FW congestion. (default: 2) "
51 		 "1: track usage per queue, 2: track usage per adapter");
52 
53 /*
54  * CT6 CTX allocation cache
55  */
56 static struct kmem_cache *ctx_cachep;
57 /*
58  * error level for logging
59  */
60 uint ql_errlev = 0x8001;
61 
62 int ql2xsecenable;
63 module_param(ql2xsecenable, int, S_IRUGO);
64 MODULE_PARM_DESC(ql2xsecenable,
65 	"Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled.");
66 
67 static int ql2xenableclass2;
68 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
69 MODULE_PARM_DESC(ql2xenableclass2,
70 		"Specify if Class 2 operations are supported from the very "
71 		"beginning. Default is 0 - class 2 not supported.");
72 
73 
74 int ql2xlogintimeout = 20;
75 module_param(ql2xlogintimeout, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xlogintimeout,
77 		"Login timeout value in seconds.");
78 
79 int qlport_down_retry;
80 module_param(qlport_down_retry, int, S_IRUGO);
81 MODULE_PARM_DESC(qlport_down_retry,
82 		"Maximum number of command retries to a port that returns "
83 		"a PORT-DOWN status.");
84 
85 int ql2xplogiabsentdevice;
86 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
87 MODULE_PARM_DESC(ql2xplogiabsentdevice,
88 		"Option to enable PLOGI to devices that are not present after "
89 		"a Fabric scan.  This is needed for several broken switches. "
90 		"Default is 0 - no PLOGI. 1 - perform PLOGI.");
91 
92 int ql2xloginretrycount;
93 module_param(ql2xloginretrycount, int, S_IRUGO);
94 MODULE_PARM_DESC(ql2xloginretrycount,
95 		"Specify an alternate value for the NVRAM login retry count.");
96 
97 int ql2xallocfwdump = 1;
98 module_param(ql2xallocfwdump, int, S_IRUGO);
99 MODULE_PARM_DESC(ql2xallocfwdump,
100 		"Option to enable allocation of memory for a firmware dump "
101 		"during HBA initialization.  Memory allocation requirements "
102 		"vary by ISP type.  Default is 1 - allocate memory.");
103 
104 int ql2xextended_error_logging;
105 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
106 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
107 MODULE_PARM_DESC(ql2xextended_error_logging,
108 		"Option to enable extended error logging,\n"
109 		"\t\tDefault is 0 - no logging.  0x40000000 - Module Init & Probe.\n"
110 		"\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
111 		"\t\t0x08000000 - IO tracing.    0x04000000 - DPC Thread.\n"
112 		"\t\t0x02000000 - Async events.  0x01000000 - Timer routines.\n"
113 		"\t\t0x00800000 - User space.    0x00400000 - Task Management.\n"
114 		"\t\t0x00200000 - AER/EEH.       0x00100000 - Multi Q.\n"
115 		"\t\t0x00080000 - P3P Specific.  0x00040000 - Virtual Port.\n"
116 		"\t\t0x00020000 - Buffer Dump.   0x00010000 - Misc.\n"
117 		"\t\t0x00008000 - Verbose.       0x00004000 - Target.\n"
118 		"\t\t0x00002000 - Target Mgmt.   0x00001000 - Target TMF.\n"
119 		"\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
120 		"\t\t0x1e400000 - Preferred value for capturing essential "
121 		"debug information (equivalent to old "
122 		"ql2xextended_error_logging=1).\n"
123 		"\t\tDo LOGICAL OR of the value to enable more than one level");
124 
125 int ql2xextended_error_logging_ktrace = 1;
126 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR);
127 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace,
128 		"Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n");
129 
130 int ql2xshiftctondsd = 6;
131 module_param(ql2xshiftctondsd, int, S_IRUGO);
132 MODULE_PARM_DESC(ql2xshiftctondsd,
133 		"Set to control shifting of command type processing "
134 		"based on total number of SG elements.");
135 
136 int ql2xfdmienable = 1;
137 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
138 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
139 MODULE_PARM_DESC(ql2xfdmienable,
140 		"Enables FDMI registrations. "
141 		"0 - no FDMI registrations. "
142 		"1 - provide FDMI registrations (default).");
143 
144 #define MAX_Q_DEPTH	64
145 static int ql2xmaxqdepth = MAX_Q_DEPTH;
146 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
147 MODULE_PARM_DESC(ql2xmaxqdepth,
148 		"Maximum queue depth to set for each LUN. "
149 		"Default is 64.");
150 
151 int ql2xenabledif = 2;
152 module_param(ql2xenabledif, int, S_IRUGO);
153 MODULE_PARM_DESC(ql2xenabledif,
154 		" Enable T10-CRC-DIF:\n"
155 		" Default is 2.\n"
156 		"  0 -- No DIF Support\n"
157 		"  1 -- Enable DIF for all types\n"
158 		"  2 -- Enable DIF for all types, except Type 0.\n");
159 
160 #if (IS_ENABLED(CONFIG_NVME_FC))
161 int ql2xnvmeenable = 1;
162 #else
163 int ql2xnvmeenable;
164 #endif
165 module_param(ql2xnvmeenable, int, 0644);
166 MODULE_PARM_DESC(ql2xnvmeenable,
167     "Enables NVME support. "
168     "0 - no NVMe.  Default is Y");
169 
170 int ql2xenablehba_err_chk = 2;
171 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
172 MODULE_PARM_DESC(ql2xenablehba_err_chk,
173 		" Enable T10-CRC-DIF Error isolation by HBA:\n"
174 		" Default is 2.\n"
175 		"  0 -- Error isolation disabled\n"
176 		"  1 -- Error isolation enabled only for DIX Type 0\n"
177 		"  2 -- Error isolation enabled for all Types\n");
178 
179 int ql2xiidmaenable = 1;
180 module_param(ql2xiidmaenable, int, S_IRUGO);
181 MODULE_PARM_DESC(ql2xiidmaenable,
182 		"Enables iIDMA settings "
183 		"Default is 1 - perform iIDMA. 0 - no iIDMA.");
184 
185 int ql2xmqsupport = 1;
186 module_param(ql2xmqsupport, int, S_IRUGO);
187 MODULE_PARM_DESC(ql2xmqsupport,
188 		"Enable on demand multiple queue pairs support "
189 		"Default is 1 for supported. "
190 		"Set it to 0 to turn off mq qpair support.");
191 
192 int ql2xfwloadbin;
193 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
194 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
195 MODULE_PARM_DESC(ql2xfwloadbin,
196 		"Option to specify location from which to load ISP firmware:.\n"
197 		" 2 -- load firmware via the request_firmware() (hotplug).\n"
198 		"      interface.\n"
199 		" 1 -- load firmware from flash.\n"
200 		" 0 -- use default semantics.\n");
201 
202 int ql2xetsenable;
203 module_param(ql2xetsenable, int, S_IRUGO);
204 MODULE_PARM_DESC(ql2xetsenable,
205 		"Enables firmware ETS burst."
206 		"Default is 0 - skip ETS enablement.");
207 
208 int ql2xdbwr = 1;
209 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
210 MODULE_PARM_DESC(ql2xdbwr,
211 		"Option to specify scheme for request queue posting.\n"
212 		" 0 -- Regular doorbell.\n"
213 		" 1 -- CAMRAM doorbell (faster).\n");
214 
215 int ql2xgffidenable;
216 module_param(ql2xgffidenable, int, S_IRUGO);
217 MODULE_PARM_DESC(ql2xgffidenable,
218 		"Enables GFF_ID checks of port type. "
219 		"Default is 0 - Do not use GFF_ID information.");
220 
221 int ql2xasynctmfenable = 1;
222 module_param(ql2xasynctmfenable, int, S_IRUGO);
223 MODULE_PARM_DESC(ql2xasynctmfenable,
224 		"Enables issue of TM IOCBs asynchronously via IOCB mechanism"
225 		"Default is 1 - Issue TM IOCBs via mailbox mechanism.");
226 
227 int ql2xdontresethba;
228 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
229 MODULE_PARM_DESC(ql2xdontresethba,
230 		"Option to specify reset behaviour.\n"
231 		" 0 (Default) -- Reset on failure.\n"
232 		" 1 -- Do not reset on failure.\n");
233 
234 uint64_t ql2xmaxlun = MAX_LUNS;
235 module_param(ql2xmaxlun, ullong, S_IRUGO);
236 MODULE_PARM_DESC(ql2xmaxlun,
237 		"Defines the maximum LU number to register with the SCSI "
238 		"midlayer. Default is 65535.");
239 
240 int ql2xmdcapmask = 0x1F;
241 module_param(ql2xmdcapmask, int, S_IRUGO);
242 MODULE_PARM_DESC(ql2xmdcapmask,
243 		"Set the Minidump driver capture mask level. "
244 		"Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
245 
246 int ql2xmdenable = 1;
247 module_param(ql2xmdenable, int, S_IRUGO);
248 MODULE_PARM_DESC(ql2xmdenable,
249 		"Enable/disable MiniDump. "
250 		"0 - MiniDump disabled. "
251 		"1 (Default) - MiniDump enabled.");
252 
253 int ql2xexlogins;
254 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
255 MODULE_PARM_DESC(ql2xexlogins,
256 		 "Number of extended Logins. "
257 		 "0 (Default)- Disabled.");
258 
259 int ql2xexchoffld = 1024;
260 module_param(ql2xexchoffld, uint, 0644);
261 MODULE_PARM_DESC(ql2xexchoffld,
262 	"Number of target exchanges.");
263 
264 int ql2xiniexchg = 1024;
265 module_param(ql2xiniexchg, uint, 0644);
266 MODULE_PARM_DESC(ql2xiniexchg,
267 	"Number of initiator exchanges.");
268 
269 int ql2xfwholdabts;
270 module_param(ql2xfwholdabts, int, S_IRUGO);
271 MODULE_PARM_DESC(ql2xfwholdabts,
272 		"Allow FW to hold status IOCB until ABTS rsp received. "
273 		"0 (Default) Do not set fw option. "
274 		"1 - Set fw option to hold ABTS.");
275 
276 int ql2xmvasynctoatio = 1;
277 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
278 MODULE_PARM_DESC(ql2xmvasynctoatio,
279 		"Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
280 		"0 (Default). Do not move IOCBs"
281 		"1 - Move IOCBs.");
282 
283 int ql2xautodetectsfp = 1;
284 module_param(ql2xautodetectsfp, int, 0444);
285 MODULE_PARM_DESC(ql2xautodetectsfp,
286 		 "Detect SFP range and set appropriate distance.\n"
287 		 "1 (Default): Enable\n");
288 
289 int ql2xenablemsix = 1;
290 module_param(ql2xenablemsix, int, 0444);
291 MODULE_PARM_DESC(ql2xenablemsix,
292 		 "Set to enable MSI or MSI-X interrupt mechanism.\n"
293 		 " Default is 1, enable MSI-X interrupt mechanism.\n"
294 		 " 0 -- enable traditional pin-based mechanism.\n"
295 		 " 1 -- enable MSI-X interrupt mechanism.\n"
296 		 " 2 -- enable MSI interrupt mechanism.\n");
297 
298 int qla2xuseresexchforels;
299 module_param(qla2xuseresexchforels, int, 0444);
300 MODULE_PARM_DESC(qla2xuseresexchforels,
301 		 "Reserve 1/2 of emergency exchanges for ELS.\n"
302 		 " 0 (default): disabled");
303 
304 static int ql2xprotmask;
305 module_param(ql2xprotmask, int, 0644);
306 MODULE_PARM_DESC(ql2xprotmask,
307 		 "Override DIF/DIX protection capabilities mask\n"
308 		 "Default is 0 which sets protection mask based on "
309 		 "capabilities reported by HBA firmware.\n");
310 
311 static int ql2xprotguard;
312 module_param(ql2xprotguard, int, 0644);
313 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
314 		 "  0 -- Let HBA firmware decide\n"
315 		 "  1 -- Force T10 CRC\n"
316 		 "  2 -- Force IP checksum\n");
317 
318 int ql2xdifbundlinginternalbuffers;
319 module_param(ql2xdifbundlinginternalbuffers, int, 0644);
320 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
321     "Force using internal buffers for DIF information\n"
322     "0 (Default). Based on check.\n"
323     "1 Force using internal buffers\n");
324 
325 int ql2xsmartsan;
326 module_param(ql2xsmartsan, int, 0444);
327 module_param_named(smartsan, ql2xsmartsan, int, 0444);
328 MODULE_PARM_DESC(ql2xsmartsan,
329 		"Send SmartSAN Management Attributes for FDMI Registration."
330 		" Default is 0 - No SmartSAN registration,"
331 		" 1 - Register SmartSAN Management Attributes.");
332 
333 int ql2xrdpenable;
334 module_param(ql2xrdpenable, int, 0444);
335 module_param_named(rdpenable, ql2xrdpenable, int, 0444);
336 MODULE_PARM_DESC(ql2xrdpenable,
337 		"Enables RDP responses. "
338 		"0 - no RDP responses (default). "
339 		"1 - provide RDP responses.");
340 int ql2xabts_wait_nvme = 1;
341 module_param(ql2xabts_wait_nvme, int, 0444);
342 MODULE_PARM_DESC(ql2xabts_wait_nvme,
343 		 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)");
344 
345 
346 static u32 ql2xdelay_before_pci_error_handling = 5;
347 module_param(ql2xdelay_before_pci_error_handling, uint, 0644);
348 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling,
349 	"Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n");
350 
351 static void qla2x00_clear_drv_active(struct qla_hw_data *);
352 static void qla2x00_free_device(scsi_qla_host_t *);
353 static void qla2xxx_map_queues(struct Scsi_Host *shost);
354 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
355 
356 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES;
357 module_param(ql2xnvme_queues, uint, S_IRUGO);
358 MODULE_PARM_DESC(ql2xnvme_queues,
359 	"Number of NVMe Queues that can be configured.\n"
360 	"Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n"
361 	"1 - Minimum number of queues supported\n"
362 	"8 - Default value");
363 
364 int ql2xfc2target = 1;
365 module_param(ql2xfc2target, int, 0444);
366 MODULE_PARM_DESC(qla2xfc2target,
367 		  "Enables FC2 Target support. "
368 		  "0 - FC2 Target support is disabled. "
369 		  "1 - FC2 Target support is enabled (default).");
370 
371 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
372 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
373 
374 /* TODO Convert to inlines
375  *
376  * Timer routines
377  */
378 
379 __inline__ void
qla2x00_start_timer(scsi_qla_host_t * vha,unsigned long interval)380 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
381 {
382 	timer_setup(&vha->timer, qla2x00_timer, 0);
383 	vha->timer.expires = jiffies + interval * HZ;
384 	add_timer(&vha->timer);
385 	vha->timer_active = 1;
386 }
387 
388 static inline void
qla2x00_restart_timer(scsi_qla_host_t * vha,unsigned long interval)389 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
390 {
391 	/* Currently used for 82XX only. */
392 	if (vha->device_flags & DFLG_DEV_FAILED) {
393 		ql_dbg(ql_dbg_timer, vha, 0x600d,
394 		    "Device in a failed state, returning.\n");
395 		return;
396 	}
397 
398 	mod_timer(&vha->timer, jiffies + interval * HZ);
399 }
400 
401 static __inline__ void
qla2x00_stop_timer(scsi_qla_host_t * vha)402 qla2x00_stop_timer(scsi_qla_host_t *vha)
403 {
404 	del_timer_sync(&vha->timer);
405 	vha->timer_active = 0;
406 }
407 
408 static int qla2x00_do_dpc(void *data);
409 
410 static void qla2x00_rst_aen(scsi_qla_host_t *);
411 
412 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
413 	struct req_que **, struct rsp_que **);
414 static void qla2x00_free_fw_dump(struct qla_hw_data *);
415 static void qla2x00_mem_free(struct qla_hw_data *);
416 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
417 	struct qla_qpair *qpair);
418 
419 /* -------------------------------------------------------------------------- */
qla_init_base_qpair(struct scsi_qla_host * vha,struct req_que * req,struct rsp_que * rsp)420 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
421     struct rsp_que *rsp)
422 {
423 	struct qla_hw_data *ha = vha->hw;
424 
425 	rsp->qpair = ha->base_qpair;
426 	rsp->req = req;
427 	ha->base_qpair->hw = ha;
428 	ha->base_qpair->req = req;
429 	ha->base_qpair->rsp = rsp;
430 	ha->base_qpair->vha = vha;
431 	ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
432 	ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
433 	ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
434 	ha->base_qpair->srb_mempool = ha->srb_mempool;
435 	INIT_LIST_HEAD(&ha->base_qpair->hints_list);
436 	INIT_LIST_HEAD(&ha->base_qpair->dsd_list);
437 	ha->base_qpair->enable_class_2 = ql2xenableclass2;
438 	/* init qpair to this cpu. Will adjust at run time. */
439 	qla_cpu_update(rsp->qpair, raw_smp_processor_id());
440 	ha->base_qpair->pdev = ha->pdev;
441 
442 	if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
443 		ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
444 }
445 
qla2x00_alloc_queues(struct qla_hw_data * ha,struct req_que * req,struct rsp_que * rsp)446 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
447 				struct rsp_que *rsp)
448 {
449 	scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
450 
451 	ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
452 				GFP_KERNEL);
453 	if (!ha->req_q_map) {
454 		ql_log(ql_log_fatal, vha, 0x003b,
455 		    "Unable to allocate memory for request queue ptrs.\n");
456 		goto fail_req_map;
457 	}
458 
459 	ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
460 				GFP_KERNEL);
461 	if (!ha->rsp_q_map) {
462 		ql_log(ql_log_fatal, vha, 0x003c,
463 		    "Unable to allocate memory for response queue ptrs.\n");
464 		goto fail_rsp_map;
465 	}
466 
467 	ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
468 	if (ha->base_qpair == NULL) {
469 		ql_log(ql_log_warn, vha, 0x00e0,
470 		    "Failed to allocate base queue pair memory.\n");
471 		goto fail_base_qpair;
472 	}
473 
474 	qla_init_base_qpair(vha, req, rsp);
475 
476 	if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
477 		ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
478 			GFP_KERNEL);
479 		if (!ha->queue_pair_map) {
480 			ql_log(ql_log_fatal, vha, 0x0180,
481 			    "Unable to allocate memory for queue pair ptrs.\n");
482 			goto fail_qpair_map;
483 		}
484 		if (qla_mapq_alloc_qp_cpu_map(ha) != 0) {
485 			kfree(ha->queue_pair_map);
486 			ha->queue_pair_map = NULL;
487 			goto fail_qpair_map;
488 		}
489 	}
490 
491 	/*
492 	 * Make sure we record at least the request and response queue zero in
493 	 * case we need to free them if part of the probe fails.
494 	 */
495 	ha->rsp_q_map[0] = rsp;
496 	ha->req_q_map[0] = req;
497 	set_bit(0, ha->rsp_qid_map);
498 	set_bit(0, ha->req_qid_map);
499 	return 0;
500 
501 fail_qpair_map:
502 	kfree(ha->base_qpair);
503 	ha->base_qpair = NULL;
504 fail_base_qpair:
505 	kfree(ha->rsp_q_map);
506 	ha->rsp_q_map = NULL;
507 fail_rsp_map:
508 	kfree(ha->req_q_map);
509 	ha->req_q_map = NULL;
510 fail_req_map:
511 	return -ENOMEM;
512 }
513 
qla2x00_free_req_que(struct qla_hw_data * ha,struct req_que * req)514 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
515 {
516 	if (IS_QLAFX00(ha)) {
517 		if (req && req->ring_fx00)
518 			dma_free_coherent(&ha->pdev->dev,
519 			    (req->length_fx00 + 1) * sizeof(request_t),
520 			    req->ring_fx00, req->dma_fx00);
521 	} else if (req && req->ring)
522 		dma_free_coherent(&ha->pdev->dev,
523 		(req->length + 1) * sizeof(request_t),
524 		req->ring, req->dma);
525 
526 	if (req)
527 		kfree(req->outstanding_cmds);
528 
529 	kfree(req);
530 }
531 
qla2x00_free_rsp_que(struct qla_hw_data * ha,struct rsp_que * rsp)532 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
533 {
534 	if (IS_QLAFX00(ha)) {
535 		if (rsp && rsp->ring_fx00)
536 			dma_free_coherent(&ha->pdev->dev,
537 			    (rsp->length_fx00 + 1) * sizeof(request_t),
538 			    rsp->ring_fx00, rsp->dma_fx00);
539 	} else if (rsp && rsp->ring) {
540 		dma_free_coherent(&ha->pdev->dev,
541 		(rsp->length + 1) * sizeof(response_t),
542 		rsp->ring, rsp->dma);
543 	}
544 	kfree(rsp);
545 }
546 
qla2x00_free_queues(struct qla_hw_data * ha)547 static void qla2x00_free_queues(struct qla_hw_data *ha)
548 {
549 	struct req_que *req;
550 	struct rsp_que *rsp;
551 	int cnt;
552 	unsigned long flags;
553 
554 	if (ha->queue_pair_map) {
555 		kfree(ha->queue_pair_map);
556 		ha->queue_pair_map = NULL;
557 	}
558 	if (ha->base_qpair) {
559 		kfree(ha->base_qpair);
560 		ha->base_qpair = NULL;
561 	}
562 
563 	qla_mapq_free_qp_cpu_map(ha);
564 	spin_lock_irqsave(&ha->hardware_lock, flags);
565 	for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
566 		if (!test_bit(cnt, ha->req_qid_map))
567 			continue;
568 
569 		req = ha->req_q_map[cnt];
570 		clear_bit(cnt, ha->req_qid_map);
571 		ha->req_q_map[cnt] = NULL;
572 
573 		spin_unlock_irqrestore(&ha->hardware_lock, flags);
574 		qla2x00_free_req_que(ha, req);
575 		spin_lock_irqsave(&ha->hardware_lock, flags);
576 	}
577 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
578 
579 	kfree(ha->req_q_map);
580 	ha->req_q_map = NULL;
581 
582 
583 	spin_lock_irqsave(&ha->hardware_lock, flags);
584 	for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
585 		if (!test_bit(cnt, ha->rsp_qid_map))
586 			continue;
587 
588 		rsp = ha->rsp_q_map[cnt];
589 		clear_bit(cnt, ha->rsp_qid_map);
590 		ha->rsp_q_map[cnt] =  NULL;
591 		spin_unlock_irqrestore(&ha->hardware_lock, flags);
592 		qla2x00_free_rsp_que(ha, rsp);
593 		spin_lock_irqsave(&ha->hardware_lock, flags);
594 	}
595 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
596 
597 	kfree(ha->rsp_q_map);
598 	ha->rsp_q_map = NULL;
599 }
600 
601 static char *
qla2x00_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)602 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
603 {
604 	struct qla_hw_data *ha = vha->hw;
605 	static const char *const pci_bus_modes[] = {
606 		"33", "66", "100", "133",
607 	};
608 	uint16_t pci_bus;
609 
610 	pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
611 	if (pci_bus) {
612 		snprintf(str, str_len, "PCI-X (%s MHz)",
613 			 pci_bus_modes[pci_bus]);
614 	} else {
615 		pci_bus = (ha->pci_attr & BIT_8) >> 8;
616 		snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
617 	}
618 
619 	return str;
620 }
621 
622 static char *
qla24xx_pci_info_str(struct scsi_qla_host * vha,char * str,size_t str_len)623 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
624 {
625 	static const char *const pci_bus_modes[] = {
626 		"33", "66", "100", "133",
627 	};
628 	struct qla_hw_data *ha = vha->hw;
629 	uint32_t pci_bus;
630 
631 	if (pci_is_pcie(ha->pdev)) {
632 		uint32_t lstat, lspeed, lwidth;
633 		const char *speed_str;
634 
635 		pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
636 		lspeed = lstat & PCI_EXP_LNKCAP_SLS;
637 		lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
638 
639 		switch (lspeed) {
640 		case 1:
641 			speed_str = "2.5GT/s";
642 			break;
643 		case 2:
644 			speed_str = "5.0GT/s";
645 			break;
646 		case 3:
647 			speed_str = "8.0GT/s";
648 			break;
649 		case 4:
650 			speed_str = "16.0GT/s";
651 			break;
652 		default:
653 			speed_str = "<unknown>";
654 			break;
655 		}
656 		snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
657 
658 		return str;
659 	}
660 
661 	pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
662 	if (pci_bus == 0 || pci_bus == 8)
663 		snprintf(str, str_len, "PCI (%s MHz)",
664 			 pci_bus_modes[pci_bus >> 3]);
665 	else
666 		snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
667 			 pci_bus & 4 ? 2 : 1,
668 			 pci_bus_modes[pci_bus & 3]);
669 
670 	return str;
671 }
672 
673 static char *
qla2x00_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)674 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
675 {
676 	char un_str[10];
677 	struct qla_hw_data *ha = vha->hw;
678 
679 	snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
680 	    ha->fw_minor_version, ha->fw_subminor_version);
681 
682 	if (ha->fw_attributes & BIT_9) {
683 		strcat(str, "FLX");
684 		return (str);
685 	}
686 
687 	switch (ha->fw_attributes & 0xFF) {
688 	case 0x7:
689 		strcat(str, "EF");
690 		break;
691 	case 0x17:
692 		strcat(str, "TP");
693 		break;
694 	case 0x37:
695 		strcat(str, "IP");
696 		break;
697 	case 0x77:
698 		strcat(str, "VI");
699 		break;
700 	default:
701 		sprintf(un_str, "(%x)", ha->fw_attributes);
702 		strcat(str, un_str);
703 		break;
704 	}
705 	if (ha->fw_attributes & 0x100)
706 		strcat(str, "X");
707 
708 	return (str);
709 }
710 
711 static char *
qla24xx_fw_version_str(struct scsi_qla_host * vha,char * str,size_t size)712 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
713 {
714 	struct qla_hw_data *ha = vha->hw;
715 
716 	snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
717 	    ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
718 	return str;
719 }
720 
qla2x00_sp_free_dma(srb_t * sp)721 void qla2x00_sp_free_dma(srb_t *sp)
722 {
723 	struct qla_hw_data *ha = sp->vha->hw;
724 	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
725 
726 	if (sp->flags & SRB_DMA_VALID) {
727 		scsi_dma_unmap(cmd);
728 		sp->flags &= ~SRB_DMA_VALID;
729 	}
730 
731 	if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
732 		dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
733 		    scsi_prot_sg_count(cmd), cmd->sc_data_direction);
734 		sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
735 	}
736 
737 	if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
738 		/* List assured to be having elements */
739 		qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
740 		sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
741 	}
742 
743 	if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
744 		struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
745 
746 		dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
747 		sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
748 	}
749 
750 	if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
751 		struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
752 
753 		dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
754 		    ctx1->fcp_cmnd_dma);
755 		list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
756 		sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
757 		sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
758 	}
759 
760 	if (sp->flags & SRB_GOT_BUF)
761 		qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
762 }
763 
qla2x00_sp_compl(srb_t * sp,int res)764 void qla2x00_sp_compl(srb_t *sp, int res)
765 {
766 	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
767 	struct completion *comp = sp->comp;
768 
769 	/* kref: INIT */
770 	kref_put(&sp->cmd_kref, qla2x00_sp_release);
771 	cmd->result = res;
772 	sp->type = 0;
773 	scsi_done(cmd);
774 	if (comp)
775 		complete(comp);
776 }
777 
qla2xxx_qpair_sp_free_dma(srb_t * sp)778 void qla2xxx_qpair_sp_free_dma(srb_t *sp)
779 {
780 	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
781 	struct qla_hw_data *ha = sp->fcport->vha->hw;
782 
783 	if (sp->flags & SRB_DMA_VALID) {
784 		scsi_dma_unmap(cmd);
785 		sp->flags &= ~SRB_DMA_VALID;
786 	}
787 
788 	if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
789 		dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
790 		    scsi_prot_sg_count(cmd), cmd->sc_data_direction);
791 		sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
792 	}
793 
794 	if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
795 		/* List assured to be having elements */
796 		qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
797 		sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
798 	}
799 
800 	if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
801 		struct crc_context *difctx = sp->u.scmd.crc_ctx;
802 		struct dsd_dma *dif_dsd, *nxt_dsd;
803 
804 		list_for_each_entry_safe(dif_dsd, nxt_dsd,
805 		    &difctx->ldif_dma_hndl_list, list) {
806 			list_del(&dif_dsd->list);
807 			dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
808 			    dif_dsd->dsd_list_dma);
809 			kfree(dif_dsd);
810 			difctx->no_dif_bundl--;
811 		}
812 
813 		list_for_each_entry_safe(dif_dsd, nxt_dsd,
814 		    &difctx->ldif_dsd_list, list) {
815 			list_del(&dif_dsd->list);
816 			dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
817 			    dif_dsd->dsd_list_dma);
818 			kfree(dif_dsd);
819 			difctx->no_ldif_dsd--;
820 		}
821 
822 		if (difctx->no_ldif_dsd) {
823 			ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
824 			    "%s: difctx->no_ldif_dsd=%x\n",
825 			    __func__, difctx->no_ldif_dsd);
826 		}
827 
828 		if (difctx->no_dif_bundl) {
829 			ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
830 			    "%s: difctx->no_dif_bundl=%x\n",
831 			    __func__, difctx->no_dif_bundl);
832 		}
833 		sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
834 	}
835 
836 	if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
837 		struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx;
838 
839 		dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
840 		    ctx1->fcp_cmnd_dma);
841 		list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list);
842 		sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt;
843 		sp->qpair->dsd_avail += ctx1->dsd_use_cnt;
844 		sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
845 	}
846 
847 	if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
848 		struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
849 
850 		dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
851 		sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
852 	}
853 
854 	if (sp->flags & SRB_GOT_BUF)
855 		qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc);
856 }
857 
qla2xxx_qpair_sp_compl(srb_t * sp,int res)858 void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
859 {
860 	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
861 	struct completion *comp = sp->comp;
862 
863 	/* ref: INIT */
864 	kref_put(&sp->cmd_kref, qla2x00_sp_release);
865 	cmd->result = res;
866 	sp->type = 0;
867 	scsi_done(cmd);
868 	if (comp)
869 		complete(comp);
870 }
871 
872 static int
qla2xxx_queuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd)873 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
874 {
875 	scsi_qla_host_t *vha = shost_priv(host);
876 	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
877 	struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
878 	struct qla_hw_data *ha = vha->hw;
879 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
880 	srb_t *sp;
881 	int rval;
882 
883 	if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
884 	    WARN_ON_ONCE(!rport)) {
885 		cmd->result = DID_NO_CONNECT << 16;
886 		goto qc24_fail_command;
887 	}
888 
889 	if (ha->mqenable) {
890 		uint32_t tag;
891 		uint16_t hwq;
892 		struct qla_qpair *qpair = NULL;
893 
894 		tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd));
895 		hwq = blk_mq_unique_tag_to_hwq(tag);
896 		qpair = ha->queue_pair_map[hwq];
897 
898 		if (qpair)
899 			return qla2xxx_mqueuecommand(host, cmd, qpair);
900 	}
901 
902 	if (ha->flags.eeh_busy) {
903 		if (ha->flags.pci_channel_io_perm_failure) {
904 			ql_dbg(ql_dbg_aer, vha, 0x9010,
905 			    "PCI Channel IO permanent failure, exiting "
906 			    "cmd=%p.\n", cmd);
907 			cmd->result = DID_NO_CONNECT << 16;
908 		} else {
909 			ql_dbg(ql_dbg_aer, vha, 0x9011,
910 			    "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
911 			cmd->result = DID_REQUEUE << 16;
912 		}
913 		goto qc24_fail_command;
914 	}
915 
916 	rval = fc_remote_port_chkready(rport);
917 	if (rval) {
918 		cmd->result = rval;
919 		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
920 		    "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
921 		    cmd, rval);
922 		goto qc24_fail_command;
923 	}
924 
925 	if (!vha->flags.difdix_supported &&
926 		scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
927 			ql_dbg(ql_dbg_io, vha, 0x3004,
928 			    "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
929 			    cmd);
930 			cmd->result = DID_NO_CONNECT << 16;
931 			goto qc24_fail_command;
932 	}
933 
934 	if (!fcport || fcport->deleted) {
935 		cmd->result = DID_IMM_RETRY << 16;
936 		goto qc24_fail_command;
937 	}
938 
939 	if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
940 		if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
941 			atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
942 			ql_dbg(ql_dbg_io, vha, 0x3005,
943 			    "Returning DNC, fcport_state=%d loop_state=%d.\n",
944 			    atomic_read(&fcport->state),
945 			    atomic_read(&base_vha->loop_state));
946 			cmd->result = DID_NO_CONNECT << 16;
947 			goto qc24_fail_command;
948 		}
949 		goto qc24_target_busy;
950 	}
951 
952 	/*
953 	 * Return target busy if we've received a non-zero retry_delay_timer
954 	 * in a FCP_RSP.
955 	 */
956 	if (fcport->retry_delay_timestamp == 0) {
957 		/* retry delay not set */
958 	} else if (time_after(jiffies, fcport->retry_delay_timestamp))
959 		fcport->retry_delay_timestamp = 0;
960 	else
961 		goto qc24_target_busy;
962 
963 	sp = scsi_cmd_priv(cmd);
964 	/* ref: INIT */
965 	qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
966 
967 	sp->u.scmd.cmd = cmd;
968 	sp->type = SRB_SCSI_CMD;
969 	sp->free = qla2x00_sp_free_dma;
970 	sp->done = qla2x00_sp_compl;
971 
972 	rval = ha->isp_ops->start_scsi(sp);
973 	if (rval != QLA_SUCCESS) {
974 		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
975 		    "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
976 		goto qc24_host_busy_free_sp;
977 	}
978 
979 	return 0;
980 
981 qc24_host_busy_free_sp:
982 	/* ref: INIT */
983 	kref_put(&sp->cmd_kref, qla2x00_sp_release);
984 
985 qc24_target_busy:
986 	return SCSI_MLQUEUE_TARGET_BUSY;
987 
988 qc24_fail_command:
989 	scsi_done(cmd);
990 
991 	return 0;
992 }
993 
994 /* For MQ supported I/O */
995 int
qla2xxx_mqueuecommand(struct Scsi_Host * host,struct scsi_cmnd * cmd,struct qla_qpair * qpair)996 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
997     struct qla_qpair *qpair)
998 {
999 	scsi_qla_host_t *vha = shost_priv(host);
1000 	fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1001 	struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
1002 	struct qla_hw_data *ha = vha->hw;
1003 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1004 	srb_t *sp;
1005 	int rval;
1006 
1007 	rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16);
1008 	if (rval) {
1009 		cmd->result = rval;
1010 		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
1011 		    "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
1012 		    cmd, rval);
1013 		goto qc24_fail_command;
1014 	}
1015 
1016 	if (!qpair->online) {
1017 		ql_dbg(ql_dbg_io, vha, 0x3077,
1018 		       "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy);
1019 		cmd->result = DID_NO_CONNECT << 16;
1020 		goto qc24_fail_command;
1021 	}
1022 
1023 	if (!fcport || fcport->deleted) {
1024 		cmd->result = DID_IMM_RETRY << 16;
1025 		goto qc24_fail_command;
1026 	}
1027 
1028 	if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
1029 		if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
1030 			atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
1031 			ql_dbg(ql_dbg_io, vha, 0x3077,
1032 			    "Returning DNC, fcport_state=%d loop_state=%d.\n",
1033 			    atomic_read(&fcport->state),
1034 			    atomic_read(&base_vha->loop_state));
1035 			cmd->result = DID_NO_CONNECT << 16;
1036 			goto qc24_fail_command;
1037 		}
1038 		goto qc24_target_busy;
1039 	}
1040 
1041 	/*
1042 	 * Return target busy if we've received a non-zero retry_delay_timer
1043 	 * in a FCP_RSP.
1044 	 */
1045 	if (fcport->retry_delay_timestamp == 0) {
1046 		/* retry delay not set */
1047 	} else if (time_after(jiffies, fcport->retry_delay_timestamp))
1048 		fcport->retry_delay_timestamp = 0;
1049 	else
1050 		goto qc24_target_busy;
1051 
1052 	sp = scsi_cmd_priv(cmd);
1053 	/* ref: INIT */
1054 	qla2xxx_init_sp(sp, vha, qpair, fcport);
1055 
1056 	sp->u.scmd.cmd = cmd;
1057 	sp->type = SRB_SCSI_CMD;
1058 	sp->free = qla2xxx_qpair_sp_free_dma;
1059 	sp->done = qla2xxx_qpair_sp_compl;
1060 
1061 	rval = ha->isp_ops->start_scsi_mq(sp);
1062 	if (rval != QLA_SUCCESS) {
1063 		ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1064 		    "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1065 		goto qc24_host_busy_free_sp;
1066 	}
1067 
1068 	return 0;
1069 
1070 qc24_host_busy_free_sp:
1071 	/* ref: INIT */
1072 	kref_put(&sp->cmd_kref, qla2x00_sp_release);
1073 
1074 qc24_target_busy:
1075 	return SCSI_MLQUEUE_TARGET_BUSY;
1076 
1077 qc24_fail_command:
1078 	scsi_done(cmd);
1079 
1080 	return 0;
1081 }
1082 
1083 /*
1084  * qla2x00_wait_for_hba_online
1085  *    Wait till the HBA is online after going through
1086  *    <= MAX_RETRIES_OF_ISP_ABORT  or
1087  *    finally HBA is disabled ie marked offline
1088  *
1089  * Input:
1090  *     ha - pointer to host adapter structure
1091  *
1092  * Note:
1093  *    Does context switching-Release SPIN_LOCK
1094  *    (if any) before calling this routine.
1095  *
1096  * Return:
1097  *    Success (Adapter is online) : 0
1098  *    Failed  (Adapter is offline/disabled) : 1
1099  */
1100 int
qla2x00_wait_for_hba_online(scsi_qla_host_t * vha)1101 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1102 {
1103 	int		return_status;
1104 	unsigned long	wait_online;
1105 	struct qla_hw_data *ha = vha->hw;
1106 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1107 
1108 	wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1109 	while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1110 	    test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1111 	    test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1112 	    ha->dpc_active) && time_before(jiffies, wait_online)) {
1113 
1114 		msleep(1000);
1115 	}
1116 	if (base_vha->flags.online)
1117 		return_status = QLA_SUCCESS;
1118 	else
1119 		return_status = QLA_FUNCTION_FAILED;
1120 
1121 	return (return_status);
1122 }
1123 
test_fcport_count(scsi_qla_host_t * vha)1124 static inline int test_fcport_count(scsi_qla_host_t *vha)
1125 {
1126 	struct qla_hw_data *ha = vha->hw;
1127 	unsigned long flags;
1128 	int res;
1129 	/* Return 0 = sleep, x=wake */
1130 
1131 	spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1132 	ql_dbg(ql_dbg_init, vha, 0x00ec,
1133 	    "tgt %p, fcport_count=%d\n",
1134 	    vha, vha->fcport_count);
1135 	res = (vha->fcport_count == 0);
1136 	if  (res) {
1137 		struct fc_port *fcport;
1138 
1139 		list_for_each_entry(fcport, &vha->vp_fcports, list) {
1140 			if (fcport->deleted != QLA_SESS_DELETED) {
1141 				/* session(s) may not be fully logged in
1142 				 * (ie fcport_count=0), but session
1143 				 * deletion thread(s) may be inflight.
1144 				 */
1145 
1146 				res = 0;
1147 				break;
1148 			}
1149 		}
1150 	}
1151 	spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1152 
1153 	return res;
1154 }
1155 
1156 /*
1157  * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1158  * it has dependency on UNLOADING flag to stop device discovery
1159  */
1160 void
qla2x00_wait_for_sess_deletion(scsi_qla_host_t * vha)1161 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1162 {
1163 	u8 i;
1164 
1165 	qla2x00_mark_all_devices_lost(vha);
1166 
1167 	for (i = 0; i < 10; i++) {
1168 		if (wait_event_timeout(vha->fcport_waitQ,
1169 		    test_fcport_count(vha), HZ) > 0)
1170 			break;
1171 	}
1172 
1173 	flush_workqueue(vha->hw->wq);
1174 }
1175 
1176 /*
1177  * qla2x00_wait_for_hba_ready
1178  * Wait till the HBA is ready before doing driver unload
1179  *
1180  * Input:
1181  *     ha - pointer to host adapter structure
1182  *
1183  * Note:
1184  *    Does context switching-Release SPIN_LOCK
1185  *    (if any) before calling this routine.
1186  *
1187  */
1188 static void
qla2x00_wait_for_hba_ready(scsi_qla_host_t * vha)1189 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1190 {
1191 	struct qla_hw_data *ha = vha->hw;
1192 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1193 
1194 	while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1195 		ha->flags.mbox_busy) ||
1196 	       test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1197 	       test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1198 		if (test_bit(UNLOADING, &base_vha->dpc_flags))
1199 			break;
1200 		msleep(1000);
1201 	}
1202 }
1203 
1204 int
qla2x00_wait_for_chip_reset(scsi_qla_host_t * vha)1205 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1206 {
1207 	int		return_status;
1208 	unsigned long	wait_reset;
1209 	struct qla_hw_data *ha = vha->hw;
1210 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1211 
1212 	wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1213 	while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1214 	    test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1215 	    test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1216 	    ha->dpc_active) && time_before(jiffies, wait_reset)) {
1217 
1218 		msleep(1000);
1219 
1220 		if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1221 		    ha->flags.chip_reset_done)
1222 			break;
1223 	}
1224 	if (ha->flags.chip_reset_done)
1225 		return_status = QLA_SUCCESS;
1226 	else
1227 		return_status = QLA_FUNCTION_FAILED;
1228 
1229 	return return_status;
1230 }
1231 
1232 /**************************************************************************
1233 * qla2xxx_eh_abort
1234 *
1235 * Description:
1236 *    The abort function will abort the specified command.
1237 *
1238 * Input:
1239 *    cmd = Linux SCSI command packet to be aborted.
1240 *
1241 * Returns:
1242 *    Either SUCCESS or FAILED.
1243 *
1244 * Note:
1245 *    Only return FAILED if command not returned by firmware.
1246 **************************************************************************/
1247 static int
qla2xxx_eh_abort(struct scsi_cmnd * cmd)1248 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1249 {
1250 	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1251 	DECLARE_COMPLETION_ONSTACK(comp);
1252 	srb_t *sp;
1253 	int ret;
1254 	unsigned int id;
1255 	uint64_t lun;
1256 	int rval;
1257 	struct qla_hw_data *ha = vha->hw;
1258 	uint32_t ratov_j;
1259 	struct qla_qpair *qpair;
1260 	unsigned long flags;
1261 	int fast_fail_status = SUCCESS;
1262 
1263 	if (qla2x00_isp_reg_stat(ha)) {
1264 		ql_log(ql_log_info, vha, 0x8042,
1265 		    "PCI/Register disconnect, exiting.\n");
1266 		qla_pci_set_eeh_busy(vha);
1267 		return FAILED;
1268 	}
1269 
1270 	/* Save any FAST_IO_FAIL value to return later if abort succeeds */
1271 	ret = fc_block_scsi_eh(cmd);
1272 	if (ret != 0)
1273 		fast_fail_status = ret;
1274 
1275 	sp = scsi_cmd_priv(cmd);
1276 	qpair = sp->qpair;
1277 
1278 	vha->cmd_timeout_cnt++;
1279 
1280 	if ((sp->fcport && sp->fcport->deleted) || !qpair)
1281 		return fast_fail_status != SUCCESS ? fast_fail_status : FAILED;
1282 
1283 	spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1284 	sp->comp = &comp;
1285 	spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1286 
1287 
1288 	id = cmd->device->id;
1289 	lun = cmd->device->lun;
1290 
1291 	ql_dbg(ql_dbg_taskm, vha, 0x8002,
1292 	    "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1293 	    vha->host_no, id, lun, sp, cmd, sp->handle);
1294 
1295 	/*
1296 	 * Abort will release the original Command/sp from FW. Let the
1297 	 * original command call scsi_done. In return, he will wakeup
1298 	 * this sleeping thread.
1299 	 */
1300 	rval = ha->isp_ops->abort_command(sp);
1301 
1302 	ql_dbg(ql_dbg_taskm, vha, 0x8003,
1303 	       "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1304 
1305 	/* Wait for the command completion. */
1306 	ratov_j = ha->r_a_tov/10 * 4 * 1000;
1307 	ratov_j = msecs_to_jiffies(ratov_j);
1308 	switch (rval) {
1309 	case QLA_SUCCESS:
1310 		if (!wait_for_completion_timeout(&comp, ratov_j)) {
1311 			ql_dbg(ql_dbg_taskm, vha, 0xffff,
1312 			    "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1313 			    __func__, ha->r_a_tov/10);
1314 			ret = FAILED;
1315 		} else {
1316 			ret = fast_fail_status;
1317 		}
1318 		break;
1319 	default:
1320 		ret = FAILED;
1321 		break;
1322 	}
1323 
1324 	sp->comp = NULL;
1325 
1326 	ql_log(ql_log_info, vha, 0x801c,
1327 	    "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1328 	    vha->host_no, id, lun, ret);
1329 
1330 	return ret;
1331 }
1332 
1333 #define ABORT_POLLING_PERIOD	1000
1334 #define ABORT_WAIT_ITER		((2 * 1000) / (ABORT_POLLING_PERIOD))
1335 
1336 /*
1337  * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1338  */
1339 static int
__qla2x00_eh_wait_for_pending_commands(struct qla_qpair * qpair,unsigned int t,uint64_t l,enum nexus_wait_type type)1340 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t,
1341 				       uint64_t l, enum nexus_wait_type type)
1342 {
1343 	int cnt, match, status;
1344 	unsigned long flags;
1345 	scsi_qla_host_t *vha = qpair->vha;
1346 	struct req_que *req = qpair->req;
1347 	srb_t *sp;
1348 	struct scsi_cmnd *cmd;
1349 	unsigned long wait_iter = ABORT_WAIT_ITER;
1350 	bool found;
1351 	struct qla_hw_data *ha = vha->hw;
1352 
1353 	status = QLA_SUCCESS;
1354 
1355 	while (wait_iter--) {
1356 		found = false;
1357 
1358 		spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1359 		for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1360 			sp = req->outstanding_cmds[cnt];
1361 			if (!sp)
1362 				continue;
1363 			if (sp->type != SRB_SCSI_CMD)
1364 				continue;
1365 			if (vha->vp_idx != sp->vha->vp_idx)
1366 				continue;
1367 			match = 0;
1368 			cmd = GET_CMD_SP(sp);
1369 			switch (type) {
1370 			case WAIT_HOST:
1371 				match = 1;
1372 				break;
1373 			case WAIT_TARGET:
1374 				if (sp->fcport)
1375 					match = sp->fcport->d_id.b24 == t;
1376 				else
1377 					match = 0;
1378 				break;
1379 			case WAIT_LUN:
1380 				if (sp->fcport)
1381 					match = (sp->fcport->d_id.b24 == t &&
1382 						cmd->device->lun == l);
1383 				else
1384 					match = 0;
1385 				break;
1386 			}
1387 			if (!match)
1388 				continue;
1389 
1390 			spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1391 
1392 			if (unlikely(pci_channel_offline(ha->pdev)) ||
1393 			    ha->flags.eeh_busy) {
1394 				ql_dbg(ql_dbg_taskm, vha, 0x8005,
1395 				    "Return:eh_wait.\n");
1396 				return status;
1397 			}
1398 
1399 			/*
1400 			 * SRB_SCSI_CMD is still in the outstanding_cmds array.
1401 			 * it means scsi_done has not called. Wait for it to
1402 			 * clear from outstanding_cmds.
1403 			 */
1404 			msleep(ABORT_POLLING_PERIOD);
1405 			spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1406 			found = true;
1407 		}
1408 		spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1409 
1410 		if (!found)
1411 			break;
1412 	}
1413 
1414 	if (wait_iter == -1)
1415 		status = QLA_FUNCTION_FAILED;
1416 
1417 	return status;
1418 }
1419 
1420 int
qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t * vha,unsigned int t,uint64_t l,enum nexus_wait_type type)1421 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1422 				     uint64_t l, enum nexus_wait_type type)
1423 {
1424 	struct qla_qpair *qpair;
1425 	struct qla_hw_data *ha = vha->hw;
1426 	int i, status = QLA_SUCCESS;
1427 
1428 	status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l,
1429 							type);
1430 	for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) {
1431 		qpair = ha->queue_pair_map[i];
1432 		if (!qpair)
1433 			continue;
1434 		status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l,
1435 								type);
1436 	}
1437 	return status;
1438 }
1439 
1440 static char *reset_errors[] = {
1441 	"HBA not online",
1442 	"HBA not ready",
1443 	"Task management failed",
1444 	"Waiting for command completions",
1445 };
1446 
1447 static int
qla2xxx_eh_device_reset(struct scsi_cmnd * cmd)1448 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1449 {
1450 	struct scsi_device *sdev = cmd->device;
1451 	scsi_qla_host_t *vha = shost_priv(sdev->host);
1452 	struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1453 	fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1454 	struct qla_hw_data *ha = vha->hw;
1455 	int err;
1456 
1457 	if (qla2x00_isp_reg_stat(ha)) {
1458 		ql_log(ql_log_info, vha, 0x803e,
1459 		    "PCI/Register disconnect, exiting.\n");
1460 		qla_pci_set_eeh_busy(vha);
1461 		return FAILED;
1462 	}
1463 
1464 	if (!fcport) {
1465 		return FAILED;
1466 	}
1467 
1468 	err = fc_block_rport(rport);
1469 	if (err != 0)
1470 		return err;
1471 
1472 	if (fcport->deleted)
1473 		return FAILED;
1474 
1475 	ql_log(ql_log_info, vha, 0x8009,
1476 	    "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no,
1477 	    sdev->id, sdev->lun, cmd);
1478 
1479 	err = 0;
1480 	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1481 		ql_log(ql_log_warn, vha, 0x800a,
1482 		    "Wait for hba online failed for cmd=%p.\n", cmd);
1483 		goto eh_reset_failed;
1484 	}
1485 	err = 2;
1486 	if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1)
1487 		!= QLA_SUCCESS) {
1488 		ql_log(ql_log_warn, vha, 0x800c,
1489 		    "do_reset failed for cmd=%p.\n", cmd);
1490 		goto eh_reset_failed;
1491 	}
1492 	err = 3;
1493 	if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24,
1494 						 cmd->device->lun,
1495 						 WAIT_LUN) != QLA_SUCCESS) {
1496 		ql_log(ql_log_warn, vha, 0x800d,
1497 		    "wait for pending cmds failed for cmd=%p.\n", cmd);
1498 		goto eh_reset_failed;
1499 	}
1500 
1501 	ql_log(ql_log_info, vha, 0x800e,
1502 	    "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n",
1503 	    vha->host_no, sdev->id, sdev->lun, cmd);
1504 
1505 	return SUCCESS;
1506 
1507 eh_reset_failed:
1508 	ql_log(ql_log_info, vha, 0x800f,
1509 	    "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1510 	    reset_errors[err], vha->host_no, sdev->id, sdev->lun,
1511 	    cmd);
1512 	vha->reset_cmd_err_cnt++;
1513 	return FAILED;
1514 }
1515 
1516 static int
qla2xxx_eh_target_reset(struct scsi_cmnd * cmd)1517 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1518 {
1519 	struct scsi_device *sdev = cmd->device;
1520 	struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1521 	scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport));
1522 	struct qla_hw_data *ha = vha->hw;
1523 	fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
1524 	int err;
1525 
1526 	if (qla2x00_isp_reg_stat(ha)) {
1527 		ql_log(ql_log_info, vha, 0x803f,
1528 		    "PCI/Register disconnect, exiting.\n");
1529 		qla_pci_set_eeh_busy(vha);
1530 		return FAILED;
1531 	}
1532 
1533 	if (!fcport) {
1534 		return FAILED;
1535 	}
1536 
1537 	err = fc_block_rport(rport);
1538 	if (err != 0)
1539 		return err;
1540 
1541 	if (fcport->deleted)
1542 		return FAILED;
1543 
1544 	ql_log(ql_log_info, vha, 0x8009,
1545 	    "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no,
1546 	    sdev->id, cmd);
1547 
1548 	err = 0;
1549 	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1550 		ql_log(ql_log_warn, vha, 0x800a,
1551 		    "Wait for hba online failed for cmd=%p.\n", cmd);
1552 		goto eh_reset_failed;
1553 	}
1554 	err = 2;
1555 	if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) {
1556 		ql_log(ql_log_warn, vha, 0x800c,
1557 		    "target_reset failed for cmd=%p.\n", cmd);
1558 		goto eh_reset_failed;
1559 	}
1560 	err = 3;
1561 	if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 0,
1562 						 WAIT_TARGET) != QLA_SUCCESS) {
1563 		ql_log(ql_log_warn, vha, 0x800d,
1564 		    "wait for pending cmds failed for cmd=%p.\n", cmd);
1565 		goto eh_reset_failed;
1566 	}
1567 
1568 	ql_log(ql_log_info, vha, 0x800e,
1569 	    "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n",
1570 	    vha->host_no, sdev->id, cmd);
1571 
1572 	return SUCCESS;
1573 
1574 eh_reset_failed:
1575 	ql_log(ql_log_info, vha, 0x800f,
1576 	    "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n",
1577 	    reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1578 	    cmd);
1579 	vha->reset_cmd_err_cnt++;
1580 	return FAILED;
1581 }
1582 
1583 /**************************************************************************
1584 * qla2xxx_eh_bus_reset
1585 *
1586 * Description:
1587 *    The bus reset function will reset the bus and abort any executing
1588 *    commands.
1589 *
1590 * Input:
1591 *    cmd = Linux SCSI command packet of the command that cause the
1592 *          bus reset.
1593 *
1594 * Returns:
1595 *    SUCCESS/FAILURE (defined as macro in scsi.h).
1596 *
1597 **************************************************************************/
1598 static int
qla2xxx_eh_bus_reset(struct scsi_cmnd * cmd)1599 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1600 {
1601 	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1602 	int ret = FAILED;
1603 	unsigned int id;
1604 	uint64_t lun;
1605 	struct qla_hw_data *ha = vha->hw;
1606 
1607 	if (qla2x00_isp_reg_stat(ha)) {
1608 		ql_log(ql_log_info, vha, 0x8040,
1609 		    "PCI/Register disconnect, exiting.\n");
1610 		qla_pci_set_eeh_busy(vha);
1611 		return FAILED;
1612 	}
1613 
1614 	id = cmd->device->id;
1615 	lun = cmd->device->lun;
1616 
1617 	if (qla2x00_chip_is_down(vha))
1618 		return ret;
1619 
1620 	ql_log(ql_log_info, vha, 0x8012,
1621 	    "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1622 
1623 	if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1624 		ql_log(ql_log_fatal, vha, 0x8013,
1625 		    "Wait for hba online failed board disabled.\n");
1626 		goto eh_bus_reset_done;
1627 	}
1628 
1629 	if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1630 		ret = SUCCESS;
1631 
1632 	if (ret == FAILED)
1633 		goto eh_bus_reset_done;
1634 
1635 	/* Flush outstanding commands. */
1636 	if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1637 	    QLA_SUCCESS) {
1638 		ql_log(ql_log_warn, vha, 0x8014,
1639 		    "Wait for pending commands failed.\n");
1640 		ret = FAILED;
1641 	}
1642 
1643 eh_bus_reset_done:
1644 	ql_log(ql_log_warn, vha, 0x802b,
1645 	    "BUS RESET %s nexus=%ld:%d:%llu.\n",
1646 	    (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1647 
1648 	return ret;
1649 }
1650 
1651 /**************************************************************************
1652 * qla2xxx_eh_host_reset
1653 *
1654 * Description:
1655 *    The reset function will reset the Adapter.
1656 *
1657 * Input:
1658 *      cmd = Linux SCSI command packet of the command that cause the
1659 *            adapter reset.
1660 *
1661 * Returns:
1662 *      Either SUCCESS or FAILED.
1663 *
1664 * Note:
1665 **************************************************************************/
1666 static int
qla2xxx_eh_host_reset(struct scsi_cmnd * cmd)1667 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1668 {
1669 	scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1670 	struct qla_hw_data *ha = vha->hw;
1671 	int ret = FAILED;
1672 	unsigned int id;
1673 	uint64_t lun;
1674 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1675 
1676 	if (qla2x00_isp_reg_stat(ha)) {
1677 		ql_log(ql_log_info, vha, 0x8041,
1678 		    "PCI/Register disconnect, exiting.\n");
1679 		qla_pci_set_eeh_busy(vha);
1680 		return SUCCESS;
1681 	}
1682 
1683 	id = cmd->device->id;
1684 	lun = cmd->device->lun;
1685 
1686 	ql_log(ql_log_info, vha, 0x8018,
1687 	    "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1688 
1689 	/*
1690 	 * No point in issuing another reset if one is active.  Also do not
1691 	 * attempt a reset if we are updating flash.
1692 	 */
1693 	if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1694 		goto eh_host_reset_lock;
1695 
1696 	if (vha != base_vha) {
1697 		if (qla2x00_vp_abort_isp(vha))
1698 			goto eh_host_reset_lock;
1699 	} else {
1700 		if (IS_P3P_TYPE(vha->hw)) {
1701 			if (!qla82xx_fcoe_ctx_reset(vha)) {
1702 				/* Ctx reset success */
1703 				ret = SUCCESS;
1704 				goto eh_host_reset_lock;
1705 			}
1706 			/* fall thru if ctx reset failed */
1707 		}
1708 		if (ha->wq)
1709 			flush_workqueue(ha->wq);
1710 
1711 		set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1712 		if (ha->isp_ops->abort_isp(base_vha)) {
1713 			clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1714 			/* failed. schedule dpc to try */
1715 			set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1716 
1717 			if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1718 				ql_log(ql_log_warn, vha, 0x802a,
1719 				    "wait for hba online failed.\n");
1720 				goto eh_host_reset_lock;
1721 			}
1722 		}
1723 		clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1724 	}
1725 
1726 	/* Waiting for command to be returned to OS.*/
1727 	if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1728 		QLA_SUCCESS)
1729 		ret = SUCCESS;
1730 
1731 eh_host_reset_lock:
1732 	ql_log(ql_log_info, vha, 0x8017,
1733 	    "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1734 	    (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1735 
1736 	return ret;
1737 }
1738 
1739 /*
1740 * qla2x00_loop_reset
1741 *      Issue loop reset.
1742 *
1743 * Input:
1744 *      ha = adapter block pointer.
1745 *
1746 * Returns:
1747 *      0 = success
1748 */
1749 int
qla2x00_loop_reset(scsi_qla_host_t * vha)1750 qla2x00_loop_reset(scsi_qla_host_t *vha)
1751 {
1752 	int ret;
1753 	struct qla_hw_data *ha = vha->hw;
1754 
1755 	if (IS_QLAFX00(ha))
1756 		return QLA_SUCCESS;
1757 
1758 	if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1759 		atomic_set(&vha->loop_state, LOOP_DOWN);
1760 		atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1761 		qla2x00_mark_all_devices_lost(vha);
1762 		ret = qla2x00_full_login_lip(vha);
1763 		if (ret != QLA_SUCCESS) {
1764 			ql_dbg(ql_dbg_taskm, vha, 0x802d,
1765 			    "full_login_lip=%d.\n", ret);
1766 		}
1767 	}
1768 
1769 	if (ha->flags.enable_lip_reset) {
1770 		ret = qla2x00_lip_reset(vha);
1771 		if (ret != QLA_SUCCESS)
1772 			ql_dbg(ql_dbg_taskm, vha, 0x802e,
1773 			    "lip_reset failed (%d).\n", ret);
1774 	}
1775 
1776 	/* Issue marker command only when we are going to start the I/O */
1777 	vha->marker_needed = 1;
1778 
1779 	return QLA_SUCCESS;
1780 }
1781 
1782 /*
1783  * The caller must ensure that no completion interrupts will happen
1784  * while this function is in progress.
1785  */
qla2x00_abort_srb(struct qla_qpair * qp,srb_t * sp,const int res,unsigned long * flags)1786 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1787 			      unsigned long *flags)
1788 	__releases(qp->qp_lock_ptr)
1789 	__acquires(qp->qp_lock_ptr)
1790 {
1791 	DECLARE_COMPLETION_ONSTACK(comp);
1792 	scsi_qla_host_t *vha = qp->vha;
1793 	struct qla_hw_data *ha = vha->hw;
1794 	struct scsi_cmnd *cmd = GET_CMD_SP(sp);
1795 	int rval;
1796 	bool ret_cmd;
1797 	uint32_t ratov_j;
1798 
1799 	lockdep_assert_held(qp->qp_lock_ptr);
1800 
1801 	if (qla2x00_chip_is_down(vha)) {
1802 		sp->done(sp, res);
1803 		return;
1804 	}
1805 
1806 	if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1807 	    (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1808 	     !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1809 	     !qla2x00_isp_reg_stat(ha))) {
1810 		if (sp->comp) {
1811 			sp->done(sp, res);
1812 			return;
1813 		}
1814 
1815 		sp->comp = &comp;
1816 		spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1817 
1818 		rval = ha->isp_ops->abort_command(sp);
1819 		/* Wait for command completion. */
1820 		ret_cmd = false;
1821 		ratov_j = ha->r_a_tov/10 * 4 * 1000;
1822 		ratov_j = msecs_to_jiffies(ratov_j);
1823 		switch (rval) {
1824 		case QLA_SUCCESS:
1825 			if (wait_for_completion_timeout(&comp, ratov_j)) {
1826 				ql_dbg(ql_dbg_taskm, vha, 0xffff,
1827 				    "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1828 				    __func__, ha->r_a_tov/10);
1829 				ret_cmd = true;
1830 			}
1831 			/* else FW return SP to driver */
1832 			break;
1833 		default:
1834 			ret_cmd = true;
1835 			break;
1836 		}
1837 
1838 		spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1839 		switch (sp->type) {
1840 		case SRB_SCSI_CMD:
1841 			if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd)))
1842 				sp->done(sp, res);
1843 			break;
1844 		default:
1845 			if (ret_cmd)
1846 				sp->done(sp, res);
1847 			break;
1848 		}
1849 	} else {
1850 		sp->done(sp, res);
1851 	}
1852 }
1853 
1854 /*
1855  * The caller must ensure that no completion interrupts will happen
1856  * while this function is in progress.
1857  */
1858 static void
__qla2x00_abort_all_cmds(struct qla_qpair * qp,int res)1859 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1860 {
1861 	int cnt;
1862 	unsigned long flags;
1863 	srb_t *sp;
1864 	scsi_qla_host_t *vha = qp->vha;
1865 	struct qla_hw_data *ha = vha->hw;
1866 	struct req_que *req;
1867 	struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1868 	struct qla_tgt_cmd *cmd;
1869 
1870 	if (!ha->req_q_map)
1871 		return;
1872 	spin_lock_irqsave(qp->qp_lock_ptr, flags);
1873 	req = qp->req;
1874 	for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1875 		sp = req->outstanding_cmds[cnt];
1876 		if (sp) {
1877 			/*
1878 			 * perform lockless completion during driver unload
1879 			 */
1880 			if (qla2x00_chip_is_down(vha)) {
1881 				req->outstanding_cmds[cnt] = NULL;
1882 				spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1883 				sp->done(sp, res);
1884 				spin_lock_irqsave(qp->qp_lock_ptr, flags);
1885 				continue;
1886 			}
1887 
1888 			switch (sp->cmd_type) {
1889 			case TYPE_SRB:
1890 				qla2x00_abort_srb(qp, sp, res, &flags);
1891 				break;
1892 			case TYPE_TGT_CMD:
1893 				if (!vha->hw->tgt.tgt_ops || !tgt ||
1894 				    qla_ini_mode_enabled(vha)) {
1895 					ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1896 					    "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1897 					    vha->dpc_flags);
1898 					continue;
1899 				}
1900 				cmd = (struct qla_tgt_cmd *)sp;
1901 				cmd->aborted = 1;
1902 				break;
1903 			case TYPE_TGT_TMCMD:
1904 				/* Skip task management functions. */
1905 				break;
1906 			default:
1907 				break;
1908 			}
1909 			req->outstanding_cmds[cnt] = NULL;
1910 		}
1911 	}
1912 	spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1913 }
1914 
1915 /*
1916  * The caller must ensure that no completion interrupts will happen
1917  * while this function is in progress.
1918  */
1919 void
qla2x00_abort_all_cmds(scsi_qla_host_t * vha,int res)1920 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1921 {
1922 	int que;
1923 	struct qla_hw_data *ha = vha->hw;
1924 
1925 	/* Continue only if initialization complete. */
1926 	if (!ha->base_qpair)
1927 		return;
1928 	__qla2x00_abort_all_cmds(ha->base_qpair, res);
1929 
1930 	if (!ha->queue_pair_map)
1931 		return;
1932 	for (que = 0; que < ha->max_qpairs; que++) {
1933 		if (!ha->queue_pair_map[que])
1934 			continue;
1935 
1936 		__qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1937 	}
1938 }
1939 
1940 static int
qla2xxx_slave_alloc(struct scsi_device * sdev)1941 qla2xxx_slave_alloc(struct scsi_device *sdev)
1942 {
1943 	struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1944 
1945 	if (!rport || fc_remote_port_chkready(rport))
1946 		return -ENXIO;
1947 
1948 	sdev->hostdata = *(fc_port_t **)rport->dd_data;
1949 
1950 	return 0;
1951 }
1952 
1953 static int
qla2xxx_slave_configure(struct scsi_device * sdev)1954 qla2xxx_slave_configure(struct scsi_device *sdev)
1955 {
1956 	scsi_qla_host_t *vha = shost_priv(sdev->host);
1957 	struct req_que *req = vha->req;
1958 
1959 	if (IS_T10_PI_CAPABLE(vha->hw))
1960 		blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1961 
1962 	scsi_change_queue_depth(sdev, req->max_q_depth);
1963 	return 0;
1964 }
1965 
1966 static void
qla2xxx_slave_destroy(struct scsi_device * sdev)1967 qla2xxx_slave_destroy(struct scsi_device *sdev)
1968 {
1969 	sdev->hostdata = NULL;
1970 }
1971 
1972 /**
1973  * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1974  * @ha: HA context
1975  *
1976  * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1977  * supported addressing method.
1978  */
1979 static void
qla2x00_config_dma_addressing(struct qla_hw_data * ha)1980 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1981 {
1982 	/* Assume a 32bit DMA mask. */
1983 	ha->flags.enable_64bit_addressing = 0;
1984 
1985 	if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1986 		/* Any upper-dword bits set? */
1987 		if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1988 		    !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1989 			/* Ok, a 64bit DMA mask is applicable. */
1990 			ha->flags.enable_64bit_addressing = 1;
1991 			ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1992 			ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1993 			return;
1994 		}
1995 	}
1996 
1997 	dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1998 	dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1999 }
2000 
2001 static void
qla2x00_enable_intrs(struct qla_hw_data * ha)2002 qla2x00_enable_intrs(struct qla_hw_data *ha)
2003 {
2004 	unsigned long flags = 0;
2005 	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2006 
2007 	spin_lock_irqsave(&ha->hardware_lock, flags);
2008 	ha->interrupts_on = 1;
2009 	/* enable risc and host interrupts */
2010 	wrt_reg_word(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
2011 	rd_reg_word(&reg->ictrl);
2012 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
2013 
2014 }
2015 
2016 static void
qla2x00_disable_intrs(struct qla_hw_data * ha)2017 qla2x00_disable_intrs(struct qla_hw_data *ha)
2018 {
2019 	unsigned long flags = 0;
2020 	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2021 
2022 	spin_lock_irqsave(&ha->hardware_lock, flags);
2023 	ha->interrupts_on = 0;
2024 	/* disable risc and host interrupts */
2025 	wrt_reg_word(&reg->ictrl, 0);
2026 	rd_reg_word(&reg->ictrl);
2027 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
2028 }
2029 
2030 static void
qla24xx_enable_intrs(struct qla_hw_data * ha)2031 qla24xx_enable_intrs(struct qla_hw_data *ha)
2032 {
2033 	unsigned long flags = 0;
2034 	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2035 
2036 	spin_lock_irqsave(&ha->hardware_lock, flags);
2037 	ha->interrupts_on = 1;
2038 	wrt_reg_dword(&reg->ictrl, ICRX_EN_RISC_INT);
2039 	rd_reg_dword(&reg->ictrl);
2040 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
2041 }
2042 
2043 static void
qla24xx_disable_intrs(struct qla_hw_data * ha)2044 qla24xx_disable_intrs(struct qla_hw_data *ha)
2045 {
2046 	unsigned long flags = 0;
2047 	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2048 
2049 	if (IS_NOPOLLING_TYPE(ha))
2050 		return;
2051 	spin_lock_irqsave(&ha->hardware_lock, flags);
2052 	ha->interrupts_on = 0;
2053 	wrt_reg_dword(&reg->ictrl, 0);
2054 	rd_reg_dword(&reg->ictrl);
2055 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
2056 }
2057 
2058 static int
qla2x00_iospace_config(struct qla_hw_data * ha)2059 qla2x00_iospace_config(struct qla_hw_data *ha)
2060 {
2061 	resource_size_t pio;
2062 	uint16_t msix;
2063 
2064 	if (pci_request_selected_regions(ha->pdev, ha->bars,
2065 	    QLA2XXX_DRIVER_NAME)) {
2066 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
2067 		    "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2068 		    pci_name(ha->pdev));
2069 		goto iospace_error_exit;
2070 	}
2071 	if (!(ha->bars & 1))
2072 		goto skip_pio;
2073 
2074 	/* We only need PIO for Flash operations on ISP2312 v2 chips. */
2075 	pio = pci_resource_start(ha->pdev, 0);
2076 	if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
2077 		if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2078 			ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
2079 			    "Invalid pci I/O region size (%s).\n",
2080 			    pci_name(ha->pdev));
2081 			pio = 0;
2082 		}
2083 	} else {
2084 		ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
2085 		    "Region #0 no a PIO resource (%s).\n",
2086 		    pci_name(ha->pdev));
2087 		pio = 0;
2088 	}
2089 	ha->pio_address = pio;
2090 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2091 	    "PIO address=%llu.\n",
2092 	    (unsigned long long)ha->pio_address);
2093 
2094 skip_pio:
2095 	/* Use MMIO operations for all accesses. */
2096 	if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2097 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2098 		    "Region #1 not an MMIO resource (%s), aborting.\n",
2099 		    pci_name(ha->pdev));
2100 		goto iospace_error_exit;
2101 	}
2102 	if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2103 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2104 		    "Invalid PCI mem region size (%s), aborting.\n",
2105 		    pci_name(ha->pdev));
2106 		goto iospace_error_exit;
2107 	}
2108 
2109 	ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2110 	if (!ha->iobase) {
2111 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2112 		    "Cannot remap MMIO (%s), aborting.\n",
2113 		    pci_name(ha->pdev));
2114 		goto iospace_error_exit;
2115 	}
2116 
2117 	/* Determine queue resources */
2118 	ha->max_req_queues = ha->max_rsp_queues = 1;
2119 	ha->msix_count = QLA_BASE_VECTORS;
2120 
2121 	/* Check if FW supports MQ or not */
2122 	if (!(ha->fw_attributes & BIT_6))
2123 		goto mqiobase_exit;
2124 
2125 	if (!ql2xmqsupport || !ql2xnvmeenable ||
2126 	    (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2127 		goto mqiobase_exit;
2128 
2129 	ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2130 			pci_resource_len(ha->pdev, 3));
2131 	if (ha->mqiobase) {
2132 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2133 		    "MQIO Base=%p.\n", ha->mqiobase);
2134 		/* Read MSIX vector size of the board */
2135 		pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2136 		ha->msix_count = msix + 1;
2137 		/* Max queues are bounded by available msix vectors */
2138 		/* MB interrupt uses 1 vector */
2139 		ha->max_req_queues = ha->msix_count - 1;
2140 		ha->max_rsp_queues = ha->max_req_queues;
2141 		/* Queue pairs is the max value minus the base queue pair */
2142 		ha->max_qpairs = ha->max_rsp_queues - 1;
2143 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2144 		    "Max no of queues pairs: %d.\n", ha->max_qpairs);
2145 
2146 		ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2147 		    "MSI-X vector count: %d.\n", ha->msix_count);
2148 	} else
2149 		ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2150 		    "BAR 3 not enabled.\n");
2151 
2152 mqiobase_exit:
2153 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2154 	    "MSIX Count: %d.\n", ha->msix_count);
2155 	return (0);
2156 
2157 iospace_error_exit:
2158 	return (-ENOMEM);
2159 }
2160 
2161 
2162 static int
qla83xx_iospace_config(struct qla_hw_data * ha)2163 qla83xx_iospace_config(struct qla_hw_data *ha)
2164 {
2165 	uint16_t msix;
2166 
2167 	if (pci_request_selected_regions(ha->pdev, ha->bars,
2168 	    QLA2XXX_DRIVER_NAME)) {
2169 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2170 		    "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2171 		    pci_name(ha->pdev));
2172 
2173 		goto iospace_error_exit;
2174 	}
2175 
2176 	/* Use MMIO operations for all accesses. */
2177 	if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2178 		ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2179 		    "Invalid pci I/O region size (%s).\n",
2180 		    pci_name(ha->pdev));
2181 		goto iospace_error_exit;
2182 	}
2183 	if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2184 		ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2185 		    "Invalid PCI mem region size (%s), aborting\n",
2186 			pci_name(ha->pdev));
2187 		goto iospace_error_exit;
2188 	}
2189 
2190 	ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2191 	if (!ha->iobase) {
2192 		ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2193 		    "Cannot remap MMIO (%s), aborting.\n",
2194 		    pci_name(ha->pdev));
2195 		goto iospace_error_exit;
2196 	}
2197 
2198 	/* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2199 	/* 83XX 26XX always use MQ type access for queues
2200 	 * - mbar 2, a.k.a region 4 */
2201 	ha->max_req_queues = ha->max_rsp_queues = 1;
2202 	ha->msix_count = QLA_BASE_VECTORS;
2203 	ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2204 			pci_resource_len(ha->pdev, 4));
2205 
2206 	if (!ha->mqiobase) {
2207 		ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2208 		    "BAR2/region4 not enabled\n");
2209 		goto mqiobase_exit;
2210 	}
2211 
2212 	ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2213 			pci_resource_len(ha->pdev, 2));
2214 	if (ha->msixbase) {
2215 		/* Read MSIX vector size of the board */
2216 		pci_read_config_word(ha->pdev,
2217 		    QLA_83XX_PCI_MSIX_CONTROL, &msix);
2218 		ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE)  + 1;
2219 		/*
2220 		 * By default, driver uses at least two msix vectors
2221 		 * (default & rspq)
2222 		 */
2223 		if (ql2xmqsupport || ql2xnvmeenable) {
2224 			/* MB interrupt uses 1 vector */
2225 			ha->max_req_queues = ha->msix_count - 1;
2226 
2227 			/* ATIOQ needs 1 vector. That's 1 less QPair */
2228 			if (QLA_TGT_MODE_ENABLED())
2229 				ha->max_req_queues--;
2230 
2231 			ha->max_rsp_queues = ha->max_req_queues;
2232 
2233 			/* Queue pairs is the max value minus
2234 			 * the base queue pair */
2235 			ha->max_qpairs = ha->max_req_queues - 1;
2236 			ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2237 			    "Max no of queues pairs: %d.\n", ha->max_qpairs);
2238 		}
2239 		ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2240 		    "MSI-X vector count: %d.\n", ha->msix_count);
2241 	} else
2242 		ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2243 		    "BAR 1 not enabled.\n");
2244 
2245 mqiobase_exit:
2246 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2247 	    "MSIX Count: %d.\n", ha->msix_count);
2248 	return 0;
2249 
2250 iospace_error_exit:
2251 	return -ENOMEM;
2252 }
2253 
2254 static struct isp_operations qla2100_isp_ops = {
2255 	.pci_config		= qla2100_pci_config,
2256 	.reset_chip		= qla2x00_reset_chip,
2257 	.chip_diag		= qla2x00_chip_diag,
2258 	.config_rings		= qla2x00_config_rings,
2259 	.reset_adapter		= qla2x00_reset_adapter,
2260 	.nvram_config		= qla2x00_nvram_config,
2261 	.update_fw_options	= qla2x00_update_fw_options,
2262 	.load_risc		= qla2x00_load_risc,
2263 	.pci_info_str		= qla2x00_pci_info_str,
2264 	.fw_version_str		= qla2x00_fw_version_str,
2265 	.intr_handler		= qla2100_intr_handler,
2266 	.enable_intrs		= qla2x00_enable_intrs,
2267 	.disable_intrs		= qla2x00_disable_intrs,
2268 	.abort_command		= qla2x00_abort_command,
2269 	.target_reset		= qla2x00_abort_target,
2270 	.lun_reset		= qla2x00_lun_reset,
2271 	.fabric_login		= qla2x00_login_fabric,
2272 	.fabric_logout		= qla2x00_fabric_logout,
2273 	.calc_req_entries	= qla2x00_calc_iocbs_32,
2274 	.build_iocbs		= qla2x00_build_scsi_iocbs_32,
2275 	.prep_ms_iocb		= qla2x00_prep_ms_iocb,
2276 	.prep_ms_fdmi_iocb	= qla2x00_prep_ms_fdmi_iocb,
2277 	.read_nvram		= qla2x00_read_nvram_data,
2278 	.write_nvram		= qla2x00_write_nvram_data,
2279 	.fw_dump		= qla2100_fw_dump,
2280 	.beacon_on		= NULL,
2281 	.beacon_off		= NULL,
2282 	.beacon_blink		= NULL,
2283 	.read_optrom		= qla2x00_read_optrom_data,
2284 	.write_optrom		= qla2x00_write_optrom_data,
2285 	.get_flash_version	= qla2x00_get_flash_version,
2286 	.start_scsi		= qla2x00_start_scsi,
2287 	.start_scsi_mq          = NULL,
2288 	.abort_isp		= qla2x00_abort_isp,
2289 	.iospace_config     	= qla2x00_iospace_config,
2290 	.initialize_adapter	= qla2x00_initialize_adapter,
2291 };
2292 
2293 static struct isp_operations qla2300_isp_ops = {
2294 	.pci_config		= qla2300_pci_config,
2295 	.reset_chip		= qla2x00_reset_chip,
2296 	.chip_diag		= qla2x00_chip_diag,
2297 	.config_rings		= qla2x00_config_rings,
2298 	.reset_adapter		= qla2x00_reset_adapter,
2299 	.nvram_config		= qla2x00_nvram_config,
2300 	.update_fw_options	= qla2x00_update_fw_options,
2301 	.load_risc		= qla2x00_load_risc,
2302 	.pci_info_str		= qla2x00_pci_info_str,
2303 	.fw_version_str		= qla2x00_fw_version_str,
2304 	.intr_handler		= qla2300_intr_handler,
2305 	.enable_intrs		= qla2x00_enable_intrs,
2306 	.disable_intrs		= qla2x00_disable_intrs,
2307 	.abort_command		= qla2x00_abort_command,
2308 	.target_reset		= qla2x00_abort_target,
2309 	.lun_reset		= qla2x00_lun_reset,
2310 	.fabric_login		= qla2x00_login_fabric,
2311 	.fabric_logout		= qla2x00_fabric_logout,
2312 	.calc_req_entries	= qla2x00_calc_iocbs_32,
2313 	.build_iocbs		= qla2x00_build_scsi_iocbs_32,
2314 	.prep_ms_iocb		= qla2x00_prep_ms_iocb,
2315 	.prep_ms_fdmi_iocb	= qla2x00_prep_ms_fdmi_iocb,
2316 	.read_nvram		= qla2x00_read_nvram_data,
2317 	.write_nvram		= qla2x00_write_nvram_data,
2318 	.fw_dump		= qla2300_fw_dump,
2319 	.beacon_on		= qla2x00_beacon_on,
2320 	.beacon_off		= qla2x00_beacon_off,
2321 	.beacon_blink		= qla2x00_beacon_blink,
2322 	.read_optrom		= qla2x00_read_optrom_data,
2323 	.write_optrom		= qla2x00_write_optrom_data,
2324 	.get_flash_version	= qla2x00_get_flash_version,
2325 	.start_scsi		= qla2x00_start_scsi,
2326 	.start_scsi_mq          = NULL,
2327 	.abort_isp		= qla2x00_abort_isp,
2328 	.iospace_config		= qla2x00_iospace_config,
2329 	.initialize_adapter	= qla2x00_initialize_adapter,
2330 };
2331 
2332 static struct isp_operations qla24xx_isp_ops = {
2333 	.pci_config		= qla24xx_pci_config,
2334 	.reset_chip		= qla24xx_reset_chip,
2335 	.chip_diag		= qla24xx_chip_diag,
2336 	.config_rings		= qla24xx_config_rings,
2337 	.reset_adapter		= qla24xx_reset_adapter,
2338 	.nvram_config		= qla24xx_nvram_config,
2339 	.update_fw_options	= qla24xx_update_fw_options,
2340 	.load_risc		= qla24xx_load_risc,
2341 	.pci_info_str		= qla24xx_pci_info_str,
2342 	.fw_version_str		= qla24xx_fw_version_str,
2343 	.intr_handler		= qla24xx_intr_handler,
2344 	.enable_intrs		= qla24xx_enable_intrs,
2345 	.disable_intrs		= qla24xx_disable_intrs,
2346 	.abort_command		= qla24xx_abort_command,
2347 	.target_reset		= qla24xx_abort_target,
2348 	.lun_reset		= qla24xx_lun_reset,
2349 	.fabric_login		= qla24xx_login_fabric,
2350 	.fabric_logout		= qla24xx_fabric_logout,
2351 	.calc_req_entries	= NULL,
2352 	.build_iocbs		= NULL,
2353 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2354 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2355 	.read_nvram		= qla24xx_read_nvram_data,
2356 	.write_nvram		= qla24xx_write_nvram_data,
2357 	.fw_dump		= qla24xx_fw_dump,
2358 	.beacon_on		= qla24xx_beacon_on,
2359 	.beacon_off		= qla24xx_beacon_off,
2360 	.beacon_blink		= qla24xx_beacon_blink,
2361 	.read_optrom		= qla24xx_read_optrom_data,
2362 	.write_optrom		= qla24xx_write_optrom_data,
2363 	.get_flash_version	= qla24xx_get_flash_version,
2364 	.start_scsi		= qla24xx_start_scsi,
2365 	.start_scsi_mq          = NULL,
2366 	.abort_isp		= qla2x00_abort_isp,
2367 	.iospace_config		= qla2x00_iospace_config,
2368 	.initialize_adapter	= qla2x00_initialize_adapter,
2369 };
2370 
2371 static struct isp_operations qla25xx_isp_ops = {
2372 	.pci_config		= qla25xx_pci_config,
2373 	.reset_chip		= qla24xx_reset_chip,
2374 	.chip_diag		= qla24xx_chip_diag,
2375 	.config_rings		= qla24xx_config_rings,
2376 	.reset_adapter		= qla24xx_reset_adapter,
2377 	.nvram_config		= qla24xx_nvram_config,
2378 	.update_fw_options	= qla24xx_update_fw_options,
2379 	.load_risc		= qla24xx_load_risc,
2380 	.pci_info_str		= qla24xx_pci_info_str,
2381 	.fw_version_str		= qla24xx_fw_version_str,
2382 	.intr_handler		= qla24xx_intr_handler,
2383 	.enable_intrs		= qla24xx_enable_intrs,
2384 	.disable_intrs		= qla24xx_disable_intrs,
2385 	.abort_command		= qla24xx_abort_command,
2386 	.target_reset		= qla24xx_abort_target,
2387 	.lun_reset		= qla24xx_lun_reset,
2388 	.fabric_login		= qla24xx_login_fabric,
2389 	.fabric_logout		= qla24xx_fabric_logout,
2390 	.calc_req_entries	= NULL,
2391 	.build_iocbs		= NULL,
2392 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2393 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2394 	.read_nvram		= qla25xx_read_nvram_data,
2395 	.write_nvram		= qla25xx_write_nvram_data,
2396 	.fw_dump		= qla25xx_fw_dump,
2397 	.beacon_on		= qla24xx_beacon_on,
2398 	.beacon_off		= qla24xx_beacon_off,
2399 	.beacon_blink		= qla24xx_beacon_blink,
2400 	.read_optrom		= qla25xx_read_optrom_data,
2401 	.write_optrom		= qla24xx_write_optrom_data,
2402 	.get_flash_version	= qla24xx_get_flash_version,
2403 	.start_scsi		= qla24xx_dif_start_scsi,
2404 	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2405 	.abort_isp		= qla2x00_abort_isp,
2406 	.iospace_config		= qla2x00_iospace_config,
2407 	.initialize_adapter	= qla2x00_initialize_adapter,
2408 };
2409 
2410 static struct isp_operations qla81xx_isp_ops = {
2411 	.pci_config		= qla25xx_pci_config,
2412 	.reset_chip		= qla24xx_reset_chip,
2413 	.chip_diag		= qla24xx_chip_diag,
2414 	.config_rings		= qla24xx_config_rings,
2415 	.reset_adapter		= qla24xx_reset_adapter,
2416 	.nvram_config		= qla81xx_nvram_config,
2417 	.update_fw_options	= qla24xx_update_fw_options,
2418 	.load_risc		= qla81xx_load_risc,
2419 	.pci_info_str		= qla24xx_pci_info_str,
2420 	.fw_version_str		= qla24xx_fw_version_str,
2421 	.intr_handler		= qla24xx_intr_handler,
2422 	.enable_intrs		= qla24xx_enable_intrs,
2423 	.disable_intrs		= qla24xx_disable_intrs,
2424 	.abort_command		= qla24xx_abort_command,
2425 	.target_reset		= qla24xx_abort_target,
2426 	.lun_reset		= qla24xx_lun_reset,
2427 	.fabric_login		= qla24xx_login_fabric,
2428 	.fabric_logout		= qla24xx_fabric_logout,
2429 	.calc_req_entries	= NULL,
2430 	.build_iocbs		= NULL,
2431 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2432 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2433 	.read_nvram		= NULL,
2434 	.write_nvram		= NULL,
2435 	.fw_dump		= qla81xx_fw_dump,
2436 	.beacon_on		= qla24xx_beacon_on,
2437 	.beacon_off		= qla24xx_beacon_off,
2438 	.beacon_blink		= qla83xx_beacon_blink,
2439 	.read_optrom		= qla25xx_read_optrom_data,
2440 	.write_optrom		= qla24xx_write_optrom_data,
2441 	.get_flash_version	= qla24xx_get_flash_version,
2442 	.start_scsi		= qla24xx_dif_start_scsi,
2443 	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2444 	.abort_isp		= qla2x00_abort_isp,
2445 	.iospace_config		= qla2x00_iospace_config,
2446 	.initialize_adapter	= qla2x00_initialize_adapter,
2447 };
2448 
2449 static struct isp_operations qla82xx_isp_ops = {
2450 	.pci_config		= qla82xx_pci_config,
2451 	.reset_chip		= qla82xx_reset_chip,
2452 	.chip_diag		= qla24xx_chip_diag,
2453 	.config_rings		= qla82xx_config_rings,
2454 	.reset_adapter		= qla24xx_reset_adapter,
2455 	.nvram_config		= qla81xx_nvram_config,
2456 	.update_fw_options	= qla24xx_update_fw_options,
2457 	.load_risc		= qla82xx_load_risc,
2458 	.pci_info_str		= qla24xx_pci_info_str,
2459 	.fw_version_str		= qla24xx_fw_version_str,
2460 	.intr_handler		= qla82xx_intr_handler,
2461 	.enable_intrs		= qla82xx_enable_intrs,
2462 	.disable_intrs		= qla82xx_disable_intrs,
2463 	.abort_command		= qla24xx_abort_command,
2464 	.target_reset		= qla24xx_abort_target,
2465 	.lun_reset		= qla24xx_lun_reset,
2466 	.fabric_login		= qla24xx_login_fabric,
2467 	.fabric_logout		= qla24xx_fabric_logout,
2468 	.calc_req_entries	= NULL,
2469 	.build_iocbs		= NULL,
2470 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2471 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2472 	.read_nvram		= qla24xx_read_nvram_data,
2473 	.write_nvram		= qla24xx_write_nvram_data,
2474 	.fw_dump		= qla82xx_fw_dump,
2475 	.beacon_on		= qla82xx_beacon_on,
2476 	.beacon_off		= qla82xx_beacon_off,
2477 	.beacon_blink		= NULL,
2478 	.read_optrom		= qla82xx_read_optrom_data,
2479 	.write_optrom		= qla82xx_write_optrom_data,
2480 	.get_flash_version	= qla82xx_get_flash_version,
2481 	.start_scsi             = qla82xx_start_scsi,
2482 	.start_scsi_mq          = NULL,
2483 	.abort_isp		= qla82xx_abort_isp,
2484 	.iospace_config     	= qla82xx_iospace_config,
2485 	.initialize_adapter	= qla2x00_initialize_adapter,
2486 };
2487 
2488 static struct isp_operations qla8044_isp_ops = {
2489 	.pci_config		= qla82xx_pci_config,
2490 	.reset_chip		= qla82xx_reset_chip,
2491 	.chip_diag		= qla24xx_chip_diag,
2492 	.config_rings		= qla82xx_config_rings,
2493 	.reset_adapter		= qla24xx_reset_adapter,
2494 	.nvram_config		= qla81xx_nvram_config,
2495 	.update_fw_options	= qla24xx_update_fw_options,
2496 	.load_risc		= qla82xx_load_risc,
2497 	.pci_info_str		= qla24xx_pci_info_str,
2498 	.fw_version_str		= qla24xx_fw_version_str,
2499 	.intr_handler		= qla8044_intr_handler,
2500 	.enable_intrs		= qla82xx_enable_intrs,
2501 	.disable_intrs		= qla82xx_disable_intrs,
2502 	.abort_command		= qla24xx_abort_command,
2503 	.target_reset		= qla24xx_abort_target,
2504 	.lun_reset		= qla24xx_lun_reset,
2505 	.fabric_login		= qla24xx_login_fabric,
2506 	.fabric_logout		= qla24xx_fabric_logout,
2507 	.calc_req_entries	= NULL,
2508 	.build_iocbs		= NULL,
2509 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2510 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2511 	.read_nvram		= NULL,
2512 	.write_nvram		= NULL,
2513 	.fw_dump		= qla8044_fw_dump,
2514 	.beacon_on		= qla82xx_beacon_on,
2515 	.beacon_off		= qla82xx_beacon_off,
2516 	.beacon_blink		= NULL,
2517 	.read_optrom		= qla8044_read_optrom_data,
2518 	.write_optrom		= qla8044_write_optrom_data,
2519 	.get_flash_version	= qla82xx_get_flash_version,
2520 	.start_scsi             = qla82xx_start_scsi,
2521 	.start_scsi_mq          = NULL,
2522 	.abort_isp		= qla8044_abort_isp,
2523 	.iospace_config		= qla82xx_iospace_config,
2524 	.initialize_adapter	= qla2x00_initialize_adapter,
2525 };
2526 
2527 static struct isp_operations qla83xx_isp_ops = {
2528 	.pci_config		= qla25xx_pci_config,
2529 	.reset_chip		= qla24xx_reset_chip,
2530 	.chip_diag		= qla24xx_chip_diag,
2531 	.config_rings		= qla24xx_config_rings,
2532 	.reset_adapter		= qla24xx_reset_adapter,
2533 	.nvram_config		= qla81xx_nvram_config,
2534 	.update_fw_options	= qla24xx_update_fw_options,
2535 	.load_risc		= qla81xx_load_risc,
2536 	.pci_info_str		= qla24xx_pci_info_str,
2537 	.fw_version_str		= qla24xx_fw_version_str,
2538 	.intr_handler		= qla24xx_intr_handler,
2539 	.enable_intrs		= qla24xx_enable_intrs,
2540 	.disable_intrs		= qla24xx_disable_intrs,
2541 	.abort_command		= qla24xx_abort_command,
2542 	.target_reset		= qla24xx_abort_target,
2543 	.lun_reset		= qla24xx_lun_reset,
2544 	.fabric_login		= qla24xx_login_fabric,
2545 	.fabric_logout		= qla24xx_fabric_logout,
2546 	.calc_req_entries	= NULL,
2547 	.build_iocbs		= NULL,
2548 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2549 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2550 	.read_nvram		= NULL,
2551 	.write_nvram		= NULL,
2552 	.fw_dump		= qla83xx_fw_dump,
2553 	.beacon_on		= qla24xx_beacon_on,
2554 	.beacon_off		= qla24xx_beacon_off,
2555 	.beacon_blink		= qla83xx_beacon_blink,
2556 	.read_optrom		= qla25xx_read_optrom_data,
2557 	.write_optrom		= qla24xx_write_optrom_data,
2558 	.get_flash_version	= qla24xx_get_flash_version,
2559 	.start_scsi		= qla24xx_dif_start_scsi,
2560 	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2561 	.abort_isp		= qla2x00_abort_isp,
2562 	.iospace_config		= qla83xx_iospace_config,
2563 	.initialize_adapter	= qla2x00_initialize_adapter,
2564 };
2565 
2566 static struct isp_operations qlafx00_isp_ops = {
2567 	.pci_config		= qlafx00_pci_config,
2568 	.reset_chip		= qlafx00_soft_reset,
2569 	.chip_diag		= qlafx00_chip_diag,
2570 	.config_rings		= qlafx00_config_rings,
2571 	.reset_adapter		= qlafx00_soft_reset,
2572 	.nvram_config		= NULL,
2573 	.update_fw_options	= NULL,
2574 	.load_risc		= NULL,
2575 	.pci_info_str		= qlafx00_pci_info_str,
2576 	.fw_version_str		= qlafx00_fw_version_str,
2577 	.intr_handler		= qlafx00_intr_handler,
2578 	.enable_intrs		= qlafx00_enable_intrs,
2579 	.disable_intrs		= qlafx00_disable_intrs,
2580 	.abort_command		= qla24xx_async_abort_command,
2581 	.target_reset		= qlafx00_abort_target,
2582 	.lun_reset		= qlafx00_lun_reset,
2583 	.fabric_login		= NULL,
2584 	.fabric_logout		= NULL,
2585 	.calc_req_entries	= NULL,
2586 	.build_iocbs		= NULL,
2587 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2588 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2589 	.read_nvram		= qla24xx_read_nvram_data,
2590 	.write_nvram		= qla24xx_write_nvram_data,
2591 	.fw_dump		= NULL,
2592 	.beacon_on		= qla24xx_beacon_on,
2593 	.beacon_off		= qla24xx_beacon_off,
2594 	.beacon_blink		= NULL,
2595 	.read_optrom		= qla24xx_read_optrom_data,
2596 	.write_optrom		= qla24xx_write_optrom_data,
2597 	.get_flash_version	= qla24xx_get_flash_version,
2598 	.start_scsi		= qlafx00_start_scsi,
2599 	.start_scsi_mq          = NULL,
2600 	.abort_isp		= qlafx00_abort_isp,
2601 	.iospace_config		= qlafx00_iospace_config,
2602 	.initialize_adapter	= qlafx00_initialize_adapter,
2603 };
2604 
2605 static struct isp_operations qla27xx_isp_ops = {
2606 	.pci_config		= qla25xx_pci_config,
2607 	.reset_chip		= qla24xx_reset_chip,
2608 	.chip_diag		= qla24xx_chip_diag,
2609 	.config_rings		= qla24xx_config_rings,
2610 	.reset_adapter		= qla24xx_reset_adapter,
2611 	.nvram_config		= qla81xx_nvram_config,
2612 	.update_fw_options	= qla24xx_update_fw_options,
2613 	.load_risc		= qla81xx_load_risc,
2614 	.pci_info_str		= qla24xx_pci_info_str,
2615 	.fw_version_str		= qla24xx_fw_version_str,
2616 	.intr_handler		= qla24xx_intr_handler,
2617 	.enable_intrs		= qla24xx_enable_intrs,
2618 	.disable_intrs		= qla24xx_disable_intrs,
2619 	.abort_command		= qla24xx_abort_command,
2620 	.target_reset		= qla24xx_abort_target,
2621 	.lun_reset		= qla24xx_lun_reset,
2622 	.fabric_login		= qla24xx_login_fabric,
2623 	.fabric_logout		= qla24xx_fabric_logout,
2624 	.calc_req_entries	= NULL,
2625 	.build_iocbs		= NULL,
2626 	.prep_ms_iocb		= qla24xx_prep_ms_iocb,
2627 	.prep_ms_fdmi_iocb	= qla24xx_prep_ms_fdmi_iocb,
2628 	.read_nvram		= NULL,
2629 	.write_nvram		= NULL,
2630 	.fw_dump		= qla27xx_fwdump,
2631 	.mpi_fw_dump		= qla27xx_mpi_fwdump,
2632 	.beacon_on		= qla24xx_beacon_on,
2633 	.beacon_off		= qla24xx_beacon_off,
2634 	.beacon_blink		= qla83xx_beacon_blink,
2635 	.read_optrom		= qla25xx_read_optrom_data,
2636 	.write_optrom		= qla24xx_write_optrom_data,
2637 	.get_flash_version	= qla24xx_get_flash_version,
2638 	.start_scsi		= qla24xx_dif_start_scsi,
2639 	.start_scsi_mq          = qla2xxx_dif_start_scsi_mq,
2640 	.abort_isp		= qla2x00_abort_isp,
2641 	.iospace_config		= qla83xx_iospace_config,
2642 	.initialize_adapter	= qla2x00_initialize_adapter,
2643 };
2644 
2645 static inline void
qla2x00_set_isp_flags(struct qla_hw_data * ha)2646 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2647 {
2648 	ha->device_type = DT_EXTENDED_IDS;
2649 	switch (ha->pdev->device) {
2650 	case PCI_DEVICE_ID_QLOGIC_ISP2100:
2651 		ha->isp_type |= DT_ISP2100;
2652 		ha->device_type &= ~DT_EXTENDED_IDS;
2653 		ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2654 		break;
2655 	case PCI_DEVICE_ID_QLOGIC_ISP2200:
2656 		ha->isp_type |= DT_ISP2200;
2657 		ha->device_type &= ~DT_EXTENDED_IDS;
2658 		ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2659 		break;
2660 	case PCI_DEVICE_ID_QLOGIC_ISP2300:
2661 		ha->isp_type |= DT_ISP2300;
2662 		ha->device_type |= DT_ZIO_SUPPORTED;
2663 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2664 		break;
2665 	case PCI_DEVICE_ID_QLOGIC_ISP2312:
2666 		ha->isp_type |= DT_ISP2312;
2667 		ha->device_type |= DT_ZIO_SUPPORTED;
2668 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2669 		break;
2670 	case PCI_DEVICE_ID_QLOGIC_ISP2322:
2671 		ha->isp_type |= DT_ISP2322;
2672 		ha->device_type |= DT_ZIO_SUPPORTED;
2673 		if (ha->pdev->subsystem_vendor == 0x1028 &&
2674 		    ha->pdev->subsystem_device == 0x0170)
2675 			ha->device_type |= DT_OEM_001;
2676 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2677 		break;
2678 	case PCI_DEVICE_ID_QLOGIC_ISP6312:
2679 		ha->isp_type |= DT_ISP6312;
2680 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2681 		break;
2682 	case PCI_DEVICE_ID_QLOGIC_ISP6322:
2683 		ha->isp_type |= DT_ISP6322;
2684 		ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2685 		break;
2686 	case PCI_DEVICE_ID_QLOGIC_ISP2422:
2687 		ha->isp_type |= DT_ISP2422;
2688 		ha->device_type |= DT_ZIO_SUPPORTED;
2689 		ha->device_type |= DT_FWI2;
2690 		ha->device_type |= DT_IIDMA;
2691 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2692 		break;
2693 	case PCI_DEVICE_ID_QLOGIC_ISP2432:
2694 		ha->isp_type |= DT_ISP2432;
2695 		ha->device_type |= DT_ZIO_SUPPORTED;
2696 		ha->device_type |= DT_FWI2;
2697 		ha->device_type |= DT_IIDMA;
2698 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2699 		break;
2700 	case PCI_DEVICE_ID_QLOGIC_ISP8432:
2701 		ha->isp_type |= DT_ISP8432;
2702 		ha->device_type |= DT_ZIO_SUPPORTED;
2703 		ha->device_type |= DT_FWI2;
2704 		ha->device_type |= DT_IIDMA;
2705 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2706 		break;
2707 	case PCI_DEVICE_ID_QLOGIC_ISP5422:
2708 		ha->isp_type |= DT_ISP5422;
2709 		ha->device_type |= DT_FWI2;
2710 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2711 		break;
2712 	case PCI_DEVICE_ID_QLOGIC_ISP5432:
2713 		ha->isp_type |= DT_ISP5432;
2714 		ha->device_type |= DT_FWI2;
2715 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2716 		break;
2717 	case PCI_DEVICE_ID_QLOGIC_ISP2532:
2718 		ha->isp_type |= DT_ISP2532;
2719 		ha->device_type |= DT_ZIO_SUPPORTED;
2720 		ha->device_type |= DT_FWI2;
2721 		ha->device_type |= DT_IIDMA;
2722 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2723 		break;
2724 	case PCI_DEVICE_ID_QLOGIC_ISP8001:
2725 		ha->isp_type |= DT_ISP8001;
2726 		ha->device_type |= DT_ZIO_SUPPORTED;
2727 		ha->device_type |= DT_FWI2;
2728 		ha->device_type |= DT_IIDMA;
2729 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2730 		break;
2731 	case PCI_DEVICE_ID_QLOGIC_ISP8021:
2732 		ha->isp_type |= DT_ISP8021;
2733 		ha->device_type |= DT_ZIO_SUPPORTED;
2734 		ha->device_type |= DT_FWI2;
2735 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2736 		/* Initialize 82XX ISP flags */
2737 		qla82xx_init_flags(ha);
2738 		break;
2739 	 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2740 		ha->isp_type |= DT_ISP8044;
2741 		ha->device_type |= DT_ZIO_SUPPORTED;
2742 		ha->device_type |= DT_FWI2;
2743 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2744 		/* Initialize 82XX ISP flags */
2745 		qla82xx_init_flags(ha);
2746 		break;
2747 	case PCI_DEVICE_ID_QLOGIC_ISP2031:
2748 		ha->isp_type |= DT_ISP2031;
2749 		ha->device_type |= DT_ZIO_SUPPORTED;
2750 		ha->device_type |= DT_FWI2;
2751 		ha->device_type |= DT_IIDMA;
2752 		ha->device_type |= DT_T10_PI;
2753 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2754 		break;
2755 	case PCI_DEVICE_ID_QLOGIC_ISP8031:
2756 		ha->isp_type |= DT_ISP8031;
2757 		ha->device_type |= DT_ZIO_SUPPORTED;
2758 		ha->device_type |= DT_FWI2;
2759 		ha->device_type |= DT_IIDMA;
2760 		ha->device_type |= DT_T10_PI;
2761 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2762 		break;
2763 	case PCI_DEVICE_ID_QLOGIC_ISPF001:
2764 		ha->isp_type |= DT_ISPFX00;
2765 		break;
2766 	case PCI_DEVICE_ID_QLOGIC_ISP2071:
2767 		ha->isp_type |= DT_ISP2071;
2768 		ha->device_type |= DT_ZIO_SUPPORTED;
2769 		ha->device_type |= DT_FWI2;
2770 		ha->device_type |= DT_IIDMA;
2771 		ha->device_type |= DT_T10_PI;
2772 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2773 		break;
2774 	case PCI_DEVICE_ID_QLOGIC_ISP2271:
2775 		ha->isp_type |= DT_ISP2271;
2776 		ha->device_type |= DT_ZIO_SUPPORTED;
2777 		ha->device_type |= DT_FWI2;
2778 		ha->device_type |= DT_IIDMA;
2779 		ha->device_type |= DT_T10_PI;
2780 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2781 		break;
2782 	case PCI_DEVICE_ID_QLOGIC_ISP2261:
2783 		ha->isp_type |= DT_ISP2261;
2784 		ha->device_type |= DT_ZIO_SUPPORTED;
2785 		ha->device_type |= DT_FWI2;
2786 		ha->device_type |= DT_IIDMA;
2787 		ha->device_type |= DT_T10_PI;
2788 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2789 		break;
2790 	case PCI_DEVICE_ID_QLOGIC_ISP2081:
2791 	case PCI_DEVICE_ID_QLOGIC_ISP2089:
2792 		ha->isp_type |= DT_ISP2081;
2793 		ha->device_type |= DT_ZIO_SUPPORTED;
2794 		ha->device_type |= DT_FWI2;
2795 		ha->device_type |= DT_IIDMA;
2796 		ha->device_type |= DT_T10_PI;
2797 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2798 		break;
2799 	case PCI_DEVICE_ID_QLOGIC_ISP2281:
2800 	case PCI_DEVICE_ID_QLOGIC_ISP2289:
2801 		ha->isp_type |= DT_ISP2281;
2802 		ha->device_type |= DT_ZIO_SUPPORTED;
2803 		ha->device_type |= DT_FWI2;
2804 		ha->device_type |= DT_IIDMA;
2805 		ha->device_type |= DT_T10_PI;
2806 		ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2807 		break;
2808 	}
2809 
2810 	if (IS_QLA82XX(ha))
2811 		ha->port_no = ha->portnum & 1;
2812 	else {
2813 		/* Get adapter physical port no from interrupt pin register. */
2814 		pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2815 		if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2816 		    IS_QLA27XX(ha) || IS_QLA28XX(ha))
2817 			ha->port_no--;
2818 		else
2819 			ha->port_no = !(ha->port_no & 1);
2820 	}
2821 
2822 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2823 	    "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2824 	    ha->device_type, ha->port_no, ha->fw_srisc_address);
2825 }
2826 
2827 static void
qla2xxx_scan_start(struct Scsi_Host * shost)2828 qla2xxx_scan_start(struct Scsi_Host *shost)
2829 {
2830 	scsi_qla_host_t *vha = shost_priv(shost);
2831 
2832 	if (vha->hw->flags.running_gold_fw)
2833 		return;
2834 
2835 	set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2836 	set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2837 	set_bit(RSCN_UPDATE, &vha->dpc_flags);
2838 	set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2839 }
2840 
2841 static int
qla2xxx_scan_finished(struct Scsi_Host * shost,unsigned long time)2842 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2843 {
2844 	scsi_qla_host_t *vha = shost_priv(shost);
2845 
2846 	if (test_bit(UNLOADING, &vha->dpc_flags))
2847 		return 1;
2848 	if (!vha->host)
2849 		return 1;
2850 	if (time > vha->hw->loop_reset_delay * HZ)
2851 		return 1;
2852 
2853 	return atomic_read(&vha->loop_state) == LOOP_READY;
2854 }
2855 
qla_heartbeat_work_fn(struct work_struct * work)2856 static void qla_heartbeat_work_fn(struct work_struct *work)
2857 {
2858 	struct qla_hw_data *ha = container_of(work,
2859 		struct qla_hw_data, heartbeat_work);
2860 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2861 
2862 	if (!ha->flags.mbox_busy && base_vha->flags.init_done)
2863 		qla_no_op_mb(base_vha);
2864 }
2865 
qla2x00_iocb_work_fn(struct work_struct * work)2866 static void qla2x00_iocb_work_fn(struct work_struct *work)
2867 {
2868 	struct scsi_qla_host *vha = container_of(work,
2869 		struct scsi_qla_host, iocb_work);
2870 	struct qla_hw_data *ha = vha->hw;
2871 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2872 	int i = 2;
2873 	unsigned long flags;
2874 
2875 	if (test_bit(UNLOADING, &base_vha->dpc_flags))
2876 		return;
2877 
2878 	while (!list_empty(&vha->work_list) && i > 0) {
2879 		qla2x00_do_work(vha);
2880 		i--;
2881 	}
2882 
2883 	spin_lock_irqsave(&vha->work_lock, flags);
2884 	clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2885 	spin_unlock_irqrestore(&vha->work_lock, flags);
2886 }
2887 
2888 static void
qla_trace_init(void)2889 qla_trace_init(void)
2890 {
2891 	qla_trc_array = trace_array_get_by_name("qla2xxx");
2892 	if (!qla_trc_array) {
2893 		ql_log(ql_log_fatal, NULL, 0x0001,
2894 		       "Unable to create qla2xxx trace instance, instance logging will be disabled.\n");
2895 		return;
2896 	}
2897 
2898 	QLA_TRACE_ENABLE(qla_trc_array);
2899 }
2900 
2901 static void
qla_trace_uninit(void)2902 qla_trace_uninit(void)
2903 {
2904 	if (!qla_trc_array)
2905 		return;
2906 	trace_array_put(qla_trc_array);
2907 }
2908 
2909 /*
2910  * PCI driver interface
2911  */
2912 static int
qla2x00_probe_one(struct pci_dev * pdev,const struct pci_device_id * id)2913 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2914 {
2915 	int	ret = -ENODEV;
2916 	struct Scsi_Host *host;
2917 	scsi_qla_host_t *base_vha = NULL;
2918 	struct qla_hw_data *ha;
2919 	char pci_info[30];
2920 	char fw_str[30], wq_name[30];
2921 	struct scsi_host_template *sht;
2922 	int bars, mem_only = 0;
2923 	uint16_t req_length = 0, rsp_length = 0;
2924 	struct req_que *req = NULL;
2925 	struct rsp_que *rsp = NULL;
2926 	int i;
2927 
2928 	bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2929 	sht = &qla2xxx_driver_template;
2930 	if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2931 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2932 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2933 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2934 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2935 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2936 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2937 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2938 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2939 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2940 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2941 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2942 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2943 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2944 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2945 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2946 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2947 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2948 	    pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2949 		bars = pci_select_bars(pdev, IORESOURCE_MEM);
2950 		mem_only = 1;
2951 		ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2952 		    "Mem only adapter.\n");
2953 	}
2954 	ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2955 	    "Bars=%d.\n", bars);
2956 
2957 	if (mem_only) {
2958 		if (pci_enable_device_mem(pdev))
2959 			return ret;
2960 	} else {
2961 		if (pci_enable_device(pdev))
2962 			return ret;
2963 	}
2964 
2965 	if (is_kdump_kernel()) {
2966 		ql2xmqsupport = 0;
2967 		ql2xallocfwdump = 0;
2968 	}
2969 
2970 	ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2971 	if (!ha) {
2972 		ql_log_pci(ql_log_fatal, pdev, 0x0009,
2973 		    "Unable to allocate memory for ha.\n");
2974 		goto disable_device;
2975 	}
2976 	ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2977 	    "Memory allocated for ha=%p.\n", ha);
2978 	ha->pdev = pdev;
2979 	INIT_LIST_HEAD(&ha->tgt.q_full_list);
2980 	spin_lock_init(&ha->tgt.q_full_lock);
2981 	spin_lock_init(&ha->tgt.sess_lock);
2982 	spin_lock_init(&ha->tgt.atio_lock);
2983 
2984 	spin_lock_init(&ha->sadb_lock);
2985 	INIT_LIST_HEAD(&ha->sadb_tx_index_list);
2986 	INIT_LIST_HEAD(&ha->sadb_rx_index_list);
2987 
2988 	spin_lock_init(&ha->sadb_fp_lock);
2989 
2990 	if (qla_edif_sadb_build_free_pool(ha)) {
2991 		kfree(ha);
2992 		goto  disable_device;
2993 	}
2994 
2995 	atomic_set(&ha->nvme_active_aen_cnt, 0);
2996 
2997 	/* Clear our data area */
2998 	ha->bars = bars;
2999 	ha->mem_only = mem_only;
3000 	spin_lock_init(&ha->hardware_lock);
3001 	spin_lock_init(&ha->vport_slock);
3002 	mutex_init(&ha->selflogin_lock);
3003 	mutex_init(&ha->optrom_mutex);
3004 
3005 	/* Set ISP-type information. */
3006 	qla2x00_set_isp_flags(ha);
3007 
3008 	/* Set EEH reset type to fundamental if required by hba */
3009 	if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
3010 	    IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3011 		pdev->needs_freset = 1;
3012 
3013 	ha->prev_topology = 0;
3014 	ha->init_cb_size = sizeof(init_cb_t);
3015 	ha->link_data_rate = PORT_SPEED_UNKNOWN;
3016 	ha->optrom_size = OPTROM_SIZE_2300;
3017 	ha->max_exchg = FW_MAX_EXCHANGES_CNT;
3018 	atomic_set(&ha->num_pend_mbx_stage1, 0);
3019 	atomic_set(&ha->num_pend_mbx_stage2, 0);
3020 	atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
3021 	ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
3022 	INIT_LIST_HEAD(&ha->tmf_pending);
3023 	INIT_LIST_HEAD(&ha->tmf_active);
3024 
3025 	/* Assign ISP specific operations. */
3026 	if (IS_QLA2100(ha)) {
3027 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3028 		ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
3029 		req_length = REQUEST_ENTRY_CNT_2100;
3030 		rsp_length = RESPONSE_ENTRY_CNT_2100;
3031 		ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3032 		ha->gid_list_info_size = 4;
3033 		ha->flash_conf_off = ~0;
3034 		ha->flash_data_off = ~0;
3035 		ha->nvram_conf_off = ~0;
3036 		ha->nvram_data_off = ~0;
3037 		ha->isp_ops = &qla2100_isp_ops;
3038 	} else if (IS_QLA2200(ha)) {
3039 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3040 		ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
3041 		req_length = REQUEST_ENTRY_CNT_2200;
3042 		rsp_length = RESPONSE_ENTRY_CNT_2100;
3043 		ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
3044 		ha->gid_list_info_size = 4;
3045 		ha->flash_conf_off = ~0;
3046 		ha->flash_data_off = ~0;
3047 		ha->nvram_conf_off = ~0;
3048 		ha->nvram_data_off = ~0;
3049 		ha->isp_ops = &qla2100_isp_ops;
3050 	} else if (IS_QLA23XX(ha)) {
3051 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
3052 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3053 		req_length = REQUEST_ENTRY_CNT_2200;
3054 		rsp_length = RESPONSE_ENTRY_CNT_2300;
3055 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3056 		ha->gid_list_info_size = 6;
3057 		if (IS_QLA2322(ha) || IS_QLA6322(ha))
3058 			ha->optrom_size = OPTROM_SIZE_2322;
3059 		ha->flash_conf_off = ~0;
3060 		ha->flash_data_off = ~0;
3061 		ha->nvram_conf_off = ~0;
3062 		ha->nvram_data_off = ~0;
3063 		ha->isp_ops = &qla2300_isp_ops;
3064 	} else if (IS_QLA24XX_TYPE(ha)) {
3065 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3066 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3067 		req_length = REQUEST_ENTRY_CNT_24XX;
3068 		rsp_length = RESPONSE_ENTRY_CNT_2300;
3069 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3070 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3071 		ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3072 		ha->gid_list_info_size = 8;
3073 		ha->optrom_size = OPTROM_SIZE_24XX;
3074 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
3075 		ha->isp_ops = &qla24xx_isp_ops;
3076 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3077 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3078 		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3079 		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3080 	} else if (IS_QLA25XX(ha)) {
3081 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3082 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3083 		req_length = REQUEST_ENTRY_CNT_24XX;
3084 		rsp_length = RESPONSE_ENTRY_CNT_2300;
3085 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3086 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3087 		ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
3088 		ha->gid_list_info_size = 8;
3089 		ha->optrom_size = OPTROM_SIZE_25XX;
3090 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3091 		ha->isp_ops = &qla25xx_isp_ops;
3092 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3093 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3094 		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3095 		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3096 	} else if (IS_QLA81XX(ha)) {
3097 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3098 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3099 		req_length = REQUEST_ENTRY_CNT_24XX;
3100 		rsp_length = RESPONSE_ENTRY_CNT_2300;
3101 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3102 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3103 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3104 		ha->gid_list_info_size = 8;
3105 		ha->optrom_size = OPTROM_SIZE_81XX;
3106 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3107 		ha->isp_ops = &qla81xx_isp_ops;
3108 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3109 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3110 		ha->nvram_conf_off = ~0;
3111 		ha->nvram_data_off = ~0;
3112 	} else if (IS_QLA82XX(ha)) {
3113 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3114 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3115 		req_length = REQUEST_ENTRY_CNT_82XX;
3116 		rsp_length = RESPONSE_ENTRY_CNT_82XX;
3117 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3118 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3119 		ha->gid_list_info_size = 8;
3120 		ha->optrom_size = OPTROM_SIZE_82XX;
3121 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3122 		ha->isp_ops = &qla82xx_isp_ops;
3123 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3124 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3125 		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3126 		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3127 	} else if (IS_QLA8044(ha)) {
3128 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3129 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3130 		req_length = REQUEST_ENTRY_CNT_82XX;
3131 		rsp_length = RESPONSE_ENTRY_CNT_82XX;
3132 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3133 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3134 		ha->gid_list_info_size = 8;
3135 		ha->optrom_size = OPTROM_SIZE_83XX;
3136 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3137 		ha->isp_ops = &qla8044_isp_ops;
3138 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
3139 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
3140 		ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
3141 		ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
3142 	} else if (IS_QLA83XX(ha)) {
3143 		ha->portnum = PCI_FUNC(ha->pdev->devfn);
3144 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3145 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3146 		req_length = REQUEST_ENTRY_CNT_83XX;
3147 		rsp_length = RESPONSE_ENTRY_CNT_83XX;
3148 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3149 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3150 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3151 		ha->gid_list_info_size = 8;
3152 		ha->optrom_size = OPTROM_SIZE_83XX;
3153 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3154 		ha->isp_ops = &qla83xx_isp_ops;
3155 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3156 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3157 		ha->nvram_conf_off = ~0;
3158 		ha->nvram_data_off = ~0;
3159 	}  else if (IS_QLAFX00(ha)) {
3160 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3161 		ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3162 		ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3163 		req_length = REQUEST_ENTRY_CNT_FX00;
3164 		rsp_length = RESPONSE_ENTRY_CNT_FX00;
3165 		ha->isp_ops = &qlafx00_isp_ops;
3166 		ha->port_down_retry_count = 30; /* default value */
3167 		ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3168 		ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3169 		ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3170 		ha->mr.fw_hbt_en = 1;
3171 		ha->mr.host_info_resend = false;
3172 		ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3173 	} else if (IS_QLA27XX(ha)) {
3174 		ha->portnum = PCI_FUNC(ha->pdev->devfn);
3175 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3176 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3177 		req_length = REQUEST_ENTRY_CNT_83XX;
3178 		rsp_length = RESPONSE_ENTRY_CNT_83XX;
3179 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3180 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3181 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3182 		ha->gid_list_info_size = 8;
3183 		ha->optrom_size = OPTROM_SIZE_83XX;
3184 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3185 		ha->isp_ops = &qla27xx_isp_ops;
3186 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3187 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3188 		ha->nvram_conf_off = ~0;
3189 		ha->nvram_data_off = ~0;
3190 	} else if (IS_QLA28XX(ha)) {
3191 		ha->portnum = PCI_FUNC(ha->pdev->devfn);
3192 		ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3193 		ha->mbx_count = MAILBOX_REGISTER_COUNT;
3194 		req_length = REQUEST_ENTRY_CNT_83XX;
3195 		rsp_length = RESPONSE_ENTRY_CNT_83XX;
3196 		ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3197 		ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3198 		ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3199 		ha->gid_list_info_size = 8;
3200 		ha->optrom_size = OPTROM_SIZE_28XX;
3201 		ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3202 		ha->isp_ops = &qla27xx_isp_ops;
3203 		ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3204 		ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3205 		ha->nvram_conf_off = ~0;
3206 		ha->nvram_data_off = ~0;
3207 	}
3208 
3209 	ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3210 	    "mbx_count=%d, req_length=%d, "
3211 	    "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3212 	    "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3213 	    "max_fibre_devices=%d.\n",
3214 	    ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3215 	    ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3216 	    ha->nvram_npiv_size, ha->max_fibre_devices);
3217 	ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3218 	    "isp_ops=%p, flash_conf_off=%d, "
3219 	    "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3220 	    ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3221 	    ha->nvram_conf_off, ha->nvram_data_off);
3222 
3223 	/* Configure PCI I/O space */
3224 	ret = ha->isp_ops->iospace_config(ha);
3225 	if (ret)
3226 		goto iospace_config_failed;
3227 
3228 	ql_log_pci(ql_log_info, pdev, 0x001d,
3229 	    "Found an ISP%04X irq %d iobase 0x%p.\n",
3230 	    pdev->device, pdev->irq, ha->iobase);
3231 	mutex_init(&ha->vport_lock);
3232 	mutex_init(&ha->mq_lock);
3233 	init_completion(&ha->mbx_cmd_comp);
3234 	complete(&ha->mbx_cmd_comp);
3235 	init_completion(&ha->mbx_intr_comp);
3236 	init_completion(&ha->dcbx_comp);
3237 	init_completion(&ha->lb_portup_comp);
3238 
3239 	set_bit(0, (unsigned long *) ha->vp_idx_map);
3240 
3241 	qla2x00_config_dma_addressing(ha);
3242 	ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3243 	    "64 Bit addressing is %s.\n",
3244 	    ha->flags.enable_64bit_addressing ? "enable" :
3245 	    "disable");
3246 	ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3247 	if (ret) {
3248 		ql_log_pci(ql_log_fatal, pdev, 0x0031,
3249 		    "Failed to allocate memory for adapter, aborting.\n");
3250 
3251 		goto probe_hw_failed;
3252 	}
3253 
3254 	req->max_q_depth = MAX_Q_DEPTH;
3255 	if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3256 		req->max_q_depth = ql2xmaxqdepth;
3257 
3258 
3259 	base_vha = qla2x00_create_host(sht, ha);
3260 	if (!base_vha) {
3261 		ret = -ENOMEM;
3262 		goto probe_hw_failed;
3263 	}
3264 
3265 	pci_set_drvdata(pdev, base_vha);
3266 	set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3267 
3268 	host = base_vha->host;
3269 	base_vha->req = req;
3270 	if (IS_QLA2XXX_MIDTYPE(ha))
3271 		base_vha->mgmt_svr_loop_id =
3272 			qla2x00_reserve_mgmt_server_loop_id(base_vha);
3273 	else
3274 		base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3275 						base_vha->vp_idx;
3276 
3277 	/* Setup fcport template structure. */
3278 	ha->mr.fcport.vha = base_vha;
3279 	ha->mr.fcport.port_type = FCT_UNKNOWN;
3280 	ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3281 	qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3282 	ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3283 	ha->mr.fcport.scan_state = 1;
3284 
3285 	qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN |
3286 			    QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT |
3287 			    QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN);
3288 
3289 	/* Set the SG table size based on ISP type */
3290 	if (!IS_FWI2_CAPABLE(ha)) {
3291 		if (IS_QLA2100(ha))
3292 			host->sg_tablesize = 32;
3293 	} else {
3294 		if (!IS_QLA82XX(ha))
3295 			host->sg_tablesize = QLA_SG_ALL;
3296 	}
3297 	host->max_id = ha->max_fibre_devices;
3298 	host->cmd_per_lun = 3;
3299 	host->unique_id = host->host_no;
3300 
3301 	if (ql2xenabledif && ql2xenabledif != 2) {
3302 		ql_log(ql_log_warn, base_vha, 0x302d,
3303 		       "Invalid value for ql2xenabledif, resetting it to default (2)\n");
3304 		ql2xenabledif = 2;
3305 	}
3306 
3307 	if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3308 		host->max_cmd_len = 32;
3309 	else
3310 		host->max_cmd_len = MAX_CMDSZ;
3311 	host->max_channel = MAX_BUSES - 1;
3312 	/* Older HBAs support only 16-bit LUNs */
3313 	if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3314 	    ql2xmaxlun > 0xffff)
3315 		host->max_lun = 0xffff;
3316 	else
3317 		host->max_lun = ql2xmaxlun;
3318 	host->transportt = qla2xxx_transport_template;
3319 	sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3320 
3321 	ql_dbg(ql_dbg_init, base_vha, 0x0033,
3322 	    "max_id=%d this_id=%d "
3323 	    "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3324 	    "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3325 	    host->this_id, host->cmd_per_lun, host->unique_id,
3326 	    host->max_cmd_len, host->max_channel, host->max_lun,
3327 	    host->transportt, sht->vendor_id);
3328 
3329 	INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn);
3330 
3331 	/* Set up the irqs */
3332 	ret = qla2x00_request_irqs(ha, rsp);
3333 	if (ret)
3334 		goto probe_failed;
3335 
3336 	/* Alloc arrays of request and response ring ptrs */
3337 	ret = qla2x00_alloc_queues(ha, req, rsp);
3338 	if (ret) {
3339 		ql_log(ql_log_fatal, base_vha, 0x003d,
3340 		    "Failed to allocate memory for queue pointers..."
3341 		    "aborting.\n");
3342 		ret = -ENODEV;
3343 		goto probe_failed;
3344 	}
3345 
3346 	if (ha->mqenable) {
3347 		/* number of hardware queues supported by blk/scsi-mq*/
3348 		host->nr_hw_queues = ha->max_qpairs;
3349 
3350 		ql_dbg(ql_dbg_init, base_vha, 0x0192,
3351 			"blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3352 	} else {
3353 		if (ql2xnvmeenable) {
3354 			host->nr_hw_queues = ha->max_qpairs;
3355 			ql_dbg(ql_dbg_init, base_vha, 0x0194,
3356 			    "FC-NVMe support is enabled, HW queues=%d\n",
3357 			    host->nr_hw_queues);
3358 		} else {
3359 			ql_dbg(ql_dbg_init, base_vha, 0x0193,
3360 			    "blk/scsi-mq disabled.\n");
3361 		}
3362 	}
3363 
3364 	qlt_probe_one_stage1(base_vha, ha);
3365 
3366 	pci_save_state(pdev);
3367 
3368 	/* Assign back pointers */
3369 	rsp->req = req;
3370 	req->rsp = rsp;
3371 
3372 	if (IS_QLAFX00(ha)) {
3373 		ha->rsp_q_map[0] = rsp;
3374 		ha->req_q_map[0] = req;
3375 		set_bit(0, ha->req_qid_map);
3376 		set_bit(0, ha->rsp_qid_map);
3377 	}
3378 
3379 	/* FWI2-capable only. */
3380 	req->req_q_in = &ha->iobase->isp24.req_q_in;
3381 	req->req_q_out = &ha->iobase->isp24.req_q_out;
3382 	rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3383 	rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3384 	if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3385 	    IS_QLA28XX(ha)) {
3386 		req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3387 		req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3388 		rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3389 		rsp->rsp_q_out =  &ha->mqiobase->isp25mq.rsp_q_out;
3390 	}
3391 
3392 	if (IS_QLAFX00(ha)) {
3393 		req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3394 		req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3395 		rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3396 		rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3397 	}
3398 
3399 	if (IS_P3P_TYPE(ha)) {
3400 		req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3401 		rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3402 		rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3403 	}
3404 
3405 	ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3406 	    "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3407 	    ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3408 	ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3409 	    "req->req_q_in=%p req->req_q_out=%p "
3410 	    "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3411 	    req->req_q_in, req->req_q_out,
3412 	    rsp->rsp_q_in, rsp->rsp_q_out);
3413 	ql_dbg(ql_dbg_init, base_vha, 0x003e,
3414 	    "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3415 	    ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3416 	ql_dbg(ql_dbg_init, base_vha, 0x003f,
3417 	    "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3418 	    req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3419 
3420 	ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0);
3421 	if (unlikely(!ha->wq)) {
3422 		ret = -ENOMEM;
3423 		goto probe_failed;
3424 	}
3425 
3426 	if (ha->isp_ops->initialize_adapter(base_vha)) {
3427 		ql_log(ql_log_fatal, base_vha, 0x00d6,
3428 		    "Failed to initialize adapter - Adapter flags %x.\n",
3429 		    base_vha->device_flags);
3430 
3431 		if (IS_QLA82XX(ha)) {
3432 			qla82xx_idc_lock(ha);
3433 			qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3434 				QLA8XXX_DEV_FAILED);
3435 			qla82xx_idc_unlock(ha);
3436 			ql_log(ql_log_fatal, base_vha, 0x00d7,
3437 			    "HW State: FAILED.\n");
3438 		} else if (IS_QLA8044(ha)) {
3439 			qla8044_idc_lock(ha);
3440 			qla8044_wr_direct(base_vha,
3441 				QLA8044_CRB_DEV_STATE_INDEX,
3442 				QLA8XXX_DEV_FAILED);
3443 			qla8044_idc_unlock(ha);
3444 			ql_log(ql_log_fatal, base_vha, 0x0150,
3445 			    "HW State: FAILED.\n");
3446 		}
3447 
3448 		ret = -ENODEV;
3449 		goto probe_failed;
3450 	}
3451 
3452 	if (IS_QLAFX00(ha))
3453 		host->can_queue = QLAFX00_MAX_CANQUEUE;
3454 	else
3455 		host->can_queue = req->num_outstanding_cmds - 10;
3456 
3457 	ql_dbg(ql_dbg_init, base_vha, 0x0032,
3458 	    "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3459 	    host->can_queue, base_vha->req,
3460 	    base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3461 
3462 	/* Check if FW supports MQ or not for ISP25xx */
3463 	if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6))
3464 		ha->mqenable = 0;
3465 
3466 	if (ha->mqenable) {
3467 		bool startit = false;
3468 
3469 		if (QLA_TGT_MODE_ENABLED())
3470 			startit = false;
3471 
3472 		if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
3473 			startit = true;
3474 
3475 		/* Create start of day qpairs for Block MQ */
3476 		for (i = 0; i < ha->max_qpairs; i++)
3477 			qla2xxx_create_qpair(base_vha, 5, 0, startit);
3478 	}
3479 	qla_init_iocb_limit(base_vha);
3480 
3481 	if (ha->flags.running_gold_fw)
3482 		goto skip_dpc;
3483 
3484 	/*
3485 	 * Startup the kernel thread for this host adapter
3486 	 */
3487 	ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3488 	    "%s_dpc", base_vha->host_str);
3489 	if (IS_ERR(ha->dpc_thread)) {
3490 		ql_log(ql_log_fatal, base_vha, 0x00ed,
3491 		    "Failed to start DPC thread.\n");
3492 		ret = PTR_ERR(ha->dpc_thread);
3493 		ha->dpc_thread = NULL;
3494 		goto probe_failed;
3495 	}
3496 	ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3497 	    "DPC thread started successfully.\n");
3498 
3499 	/*
3500 	 * If we're not coming up in initiator mode, we might sit for
3501 	 * a while without waking up the dpc thread, which leads to a
3502 	 * stuck process warning.  So just kick the dpc once here and
3503 	 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3504 	 */
3505 	qla2xxx_wake_dpc(base_vha);
3506 
3507 	INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3508 
3509 	if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3510 		sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3511 		ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3512 		INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3513 
3514 		sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3515 		ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3516 		INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3517 		INIT_WORK(&ha->idc_state_handler,
3518 		    qla83xx_idc_state_handler_work);
3519 		INIT_WORK(&ha->nic_core_unrecoverable,
3520 		    qla83xx_nic_core_unrecoverable_work);
3521 	}
3522 
3523 skip_dpc:
3524 	list_add_tail(&base_vha->list, &ha->vp_list);
3525 	base_vha->host->irq = ha->pdev->irq;
3526 
3527 	/* Initialized the timer */
3528 	qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3529 	ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3530 	    "Started qla2x00_timer with "
3531 	    "interval=%d.\n", WATCH_INTERVAL);
3532 	ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3533 	    "Detected hba at address=%p.\n",
3534 	    ha);
3535 
3536 	if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3537 		if (ha->fw_attributes & BIT_4) {
3538 			int prot = 0, guard;
3539 
3540 			base_vha->flags.difdix_supported = 1;
3541 			ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3542 			    "Registering for DIF/DIX type 1 and 3 protection.\n");
3543 			if (ql2xprotmask)
3544 				scsi_host_set_prot(host, ql2xprotmask);
3545 			else
3546 				scsi_host_set_prot(host,
3547 				    prot | SHOST_DIF_TYPE1_PROTECTION
3548 				    | SHOST_DIF_TYPE2_PROTECTION
3549 				    | SHOST_DIF_TYPE3_PROTECTION
3550 				    | SHOST_DIX_TYPE1_PROTECTION
3551 				    | SHOST_DIX_TYPE2_PROTECTION
3552 				    | SHOST_DIX_TYPE3_PROTECTION);
3553 
3554 			guard = SHOST_DIX_GUARD_CRC;
3555 
3556 			if (IS_PI_IPGUARD_CAPABLE(ha) &&
3557 			    (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3558 				guard |= SHOST_DIX_GUARD_IP;
3559 
3560 			if (ql2xprotguard)
3561 				scsi_host_set_guard(host, ql2xprotguard);
3562 			else
3563 				scsi_host_set_guard(host, guard);
3564 		} else
3565 			base_vha->flags.difdix_supported = 0;
3566 	}
3567 
3568 	ha->isp_ops->enable_intrs(ha);
3569 
3570 	if (IS_QLAFX00(ha)) {
3571 		ret = qlafx00_fx_disc(base_vha,
3572 			&base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3573 		host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3574 		    QLA_SG_ALL : 128;
3575 	}
3576 
3577 	ret = scsi_add_host(host, &pdev->dev);
3578 	if (ret)
3579 		goto probe_failed;
3580 
3581 	base_vha->flags.init_done = 1;
3582 	base_vha->flags.online = 1;
3583 	ha->prev_minidump_failed = 0;
3584 
3585 	ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3586 	    "Init done and hba is online.\n");
3587 
3588 	if (qla_ini_mode_enabled(base_vha) ||
3589 		qla_dual_mode_enabled(base_vha))
3590 		scsi_scan_host(host);
3591 	else
3592 		ql_log(ql_log_info, base_vha, 0x0122,
3593 			"skipping scsi_scan_host() for non-initiator port\n");
3594 
3595 	qla2x00_alloc_sysfs_attr(base_vha);
3596 
3597 	if (IS_QLAFX00(ha)) {
3598 		ret = qlafx00_fx_disc(base_vha,
3599 			&base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3600 
3601 		/* Register system information */
3602 		ret =  qlafx00_fx_disc(base_vha,
3603 			&base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3604 	}
3605 
3606 	qla2x00_init_host_attr(base_vha);
3607 
3608 	qla2x00_dfs_setup(base_vha);
3609 
3610 	ql_log(ql_log_info, base_vha, 0x00fb,
3611 	    "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3612 	ql_log(ql_log_info, base_vha, 0x00fc,
3613 	    "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3614 	    pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3615 						       sizeof(pci_info)),
3616 	    pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3617 	    base_vha->host_no,
3618 	    ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3619 
3620 	qlt_add_target(ha, base_vha);
3621 
3622 	clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3623 
3624 	if (test_bit(UNLOADING, &base_vha->dpc_flags))
3625 		return -ENODEV;
3626 
3627 	return 0;
3628 
3629 probe_failed:
3630 	qla_enode_stop(base_vha);
3631 	qla_edb_stop(base_vha);
3632 	vfree(base_vha->scan.l);
3633 	if (base_vha->gnl.l) {
3634 		dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3635 				base_vha->gnl.l, base_vha->gnl.ldma);
3636 		base_vha->gnl.l = NULL;
3637 	}
3638 
3639 	if (base_vha->timer_active)
3640 		qla2x00_stop_timer(base_vha);
3641 	base_vha->flags.online = 0;
3642 	if (ha->dpc_thread) {
3643 		struct task_struct *t = ha->dpc_thread;
3644 
3645 		ha->dpc_thread = NULL;
3646 		kthread_stop(t);
3647 	}
3648 
3649 	qla2x00_free_device(base_vha);
3650 	scsi_host_put(base_vha->host);
3651 	/*
3652 	 * Need to NULL out local req/rsp after
3653 	 * qla2x00_free_device => qla2x00_free_queues frees
3654 	 * what these are pointing to. Or else we'll
3655 	 * fall over below in qla2x00_free_req/rsp_que.
3656 	 */
3657 	req = NULL;
3658 	rsp = NULL;
3659 
3660 probe_hw_failed:
3661 	qla2x00_mem_free(ha);
3662 	qla2x00_free_req_que(ha, req);
3663 	qla2x00_free_rsp_que(ha, rsp);
3664 	qla2x00_clear_drv_active(ha);
3665 
3666 iospace_config_failed:
3667 	if (IS_P3P_TYPE(ha)) {
3668 		if (!ha->nx_pcibase)
3669 			iounmap((device_reg_t *)ha->nx_pcibase);
3670 		if (!ql2xdbwr)
3671 			iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3672 	} else {
3673 		if (ha->iobase)
3674 			iounmap(ha->iobase);
3675 		if (ha->cregbase)
3676 			iounmap(ha->cregbase);
3677 	}
3678 	pci_release_selected_regions(ha->pdev, ha->bars);
3679 	kfree(ha);
3680 
3681 disable_device:
3682 	pci_disable_device(pdev);
3683 	return ret;
3684 }
3685 
__qla_set_remove_flag(scsi_qla_host_t * base_vha)3686 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3687 {
3688 	scsi_qla_host_t *vp;
3689 	unsigned long flags;
3690 	struct qla_hw_data *ha;
3691 
3692 	if (!base_vha)
3693 		return;
3694 
3695 	ha = base_vha->hw;
3696 
3697 	spin_lock_irqsave(&ha->vport_slock, flags);
3698 	list_for_each_entry(vp, &ha->vp_list, list)
3699 		set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3700 
3701 	/*
3702 	 * Indicate device removal to prevent future board_disable
3703 	 * and wait until any pending board_disable has completed.
3704 	 */
3705 	set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3706 	spin_unlock_irqrestore(&ha->vport_slock, flags);
3707 }
3708 
3709 static void
qla2x00_shutdown(struct pci_dev * pdev)3710 qla2x00_shutdown(struct pci_dev *pdev)
3711 {
3712 	scsi_qla_host_t *vha;
3713 	struct qla_hw_data  *ha;
3714 
3715 	vha = pci_get_drvdata(pdev);
3716 	ha = vha->hw;
3717 
3718 	ql_log(ql_log_info, vha, 0xfffa,
3719 		"Adapter shutdown\n");
3720 
3721 	/*
3722 	 * Prevent future board_disable and wait
3723 	 * until any pending board_disable has completed.
3724 	 */
3725 	__qla_set_remove_flag(vha);
3726 	cancel_work_sync(&ha->board_disable);
3727 
3728 	if (!atomic_read(&pdev->enable_cnt))
3729 		return;
3730 
3731 	/* Notify ISPFX00 firmware */
3732 	if (IS_QLAFX00(ha))
3733 		qlafx00_driver_shutdown(vha, 20);
3734 
3735 	/* Turn-off FCE trace */
3736 	if (ha->flags.fce_enabled) {
3737 		qla2x00_disable_fce_trace(vha, NULL, NULL);
3738 		ha->flags.fce_enabled = 0;
3739 	}
3740 
3741 	/* Turn-off EFT trace */
3742 	if (ha->eft)
3743 		qla2x00_disable_eft_trace(vha);
3744 
3745 	if (IS_QLA25XX(ha) ||  IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3746 	    IS_QLA28XX(ha)) {
3747 		if (ha->flags.fw_started)
3748 			qla2x00_abort_isp_cleanup(vha);
3749 	} else {
3750 		/* Stop currently executing firmware. */
3751 		qla2x00_try_to_stop_firmware(vha);
3752 	}
3753 
3754 	/* Disable timer */
3755 	if (vha->timer_active)
3756 		qla2x00_stop_timer(vha);
3757 
3758 	/* Turn adapter off line */
3759 	vha->flags.online = 0;
3760 
3761 	/* turn-off interrupts on the card */
3762 	if (ha->interrupts_on) {
3763 		vha->flags.init_done = 0;
3764 		ha->isp_ops->disable_intrs(ha);
3765 	}
3766 
3767 	qla2x00_free_irqs(vha);
3768 
3769 	qla2x00_free_fw_dump(ha);
3770 
3771 	pci_disable_device(pdev);
3772 	ql_log(ql_log_info, vha, 0xfffe,
3773 		"Adapter shutdown successfully.\n");
3774 }
3775 
3776 /* Deletes all the virtual ports for a given ha */
3777 static void
qla2x00_delete_all_vps(struct qla_hw_data * ha,scsi_qla_host_t * base_vha)3778 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3779 {
3780 	scsi_qla_host_t *vha;
3781 	unsigned long flags;
3782 
3783 	mutex_lock(&ha->vport_lock);
3784 	while (ha->cur_vport_count) {
3785 		spin_lock_irqsave(&ha->vport_slock, flags);
3786 
3787 		BUG_ON(base_vha->list.next == &ha->vp_list);
3788 		/* This assumes first entry in ha->vp_list is always base vha */
3789 		vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3790 		scsi_host_get(vha->host);
3791 
3792 		spin_unlock_irqrestore(&ha->vport_slock, flags);
3793 		mutex_unlock(&ha->vport_lock);
3794 
3795 		qla_nvme_delete(vha);
3796 
3797 		fc_vport_terminate(vha->fc_vport);
3798 		scsi_host_put(vha->host);
3799 
3800 		mutex_lock(&ha->vport_lock);
3801 	}
3802 	mutex_unlock(&ha->vport_lock);
3803 }
3804 
3805 /* Stops all deferred work threads */
3806 static void
qla2x00_destroy_deferred_work(struct qla_hw_data * ha)3807 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3808 {
3809 	/* Cancel all work and destroy DPC workqueues */
3810 	if (ha->dpc_lp_wq) {
3811 		cancel_work_sync(&ha->idc_aen);
3812 		destroy_workqueue(ha->dpc_lp_wq);
3813 		ha->dpc_lp_wq = NULL;
3814 	}
3815 
3816 	if (ha->dpc_hp_wq) {
3817 		cancel_work_sync(&ha->nic_core_reset);
3818 		cancel_work_sync(&ha->idc_state_handler);
3819 		cancel_work_sync(&ha->nic_core_unrecoverable);
3820 		destroy_workqueue(ha->dpc_hp_wq);
3821 		ha->dpc_hp_wq = NULL;
3822 	}
3823 
3824 	/* Kill the kernel thread for this host */
3825 	if (ha->dpc_thread) {
3826 		struct task_struct *t = ha->dpc_thread;
3827 
3828 		/*
3829 		 * qla2xxx_wake_dpc checks for ->dpc_thread
3830 		 * so we need to zero it out.
3831 		 */
3832 		ha->dpc_thread = NULL;
3833 		kthread_stop(t);
3834 	}
3835 }
3836 
3837 static void
qla2x00_unmap_iobases(struct qla_hw_data * ha)3838 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3839 {
3840 	if (IS_QLA82XX(ha)) {
3841 
3842 		iounmap((device_reg_t *)ha->nx_pcibase);
3843 		if (!ql2xdbwr)
3844 			iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3845 	} else {
3846 		if (ha->iobase)
3847 			iounmap(ha->iobase);
3848 
3849 		if (ha->cregbase)
3850 			iounmap(ha->cregbase);
3851 
3852 		if (ha->mqiobase)
3853 			iounmap(ha->mqiobase);
3854 
3855 		if (ha->msixbase)
3856 			iounmap(ha->msixbase);
3857 	}
3858 }
3859 
3860 static void
qla2x00_clear_drv_active(struct qla_hw_data * ha)3861 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3862 {
3863 	if (IS_QLA8044(ha)) {
3864 		qla8044_idc_lock(ha);
3865 		qla8044_clear_drv_active(ha);
3866 		qla8044_idc_unlock(ha);
3867 	} else if (IS_QLA82XX(ha)) {
3868 		qla82xx_idc_lock(ha);
3869 		qla82xx_clear_drv_active(ha);
3870 		qla82xx_idc_unlock(ha);
3871 	}
3872 }
3873 
3874 static void
qla2x00_remove_one(struct pci_dev * pdev)3875 qla2x00_remove_one(struct pci_dev *pdev)
3876 {
3877 	scsi_qla_host_t *base_vha;
3878 	struct qla_hw_data  *ha;
3879 
3880 	base_vha = pci_get_drvdata(pdev);
3881 	ha = base_vha->hw;
3882 	ql_log(ql_log_info, base_vha, 0xb079,
3883 	    "Removing driver\n");
3884 	__qla_set_remove_flag(base_vha);
3885 	cancel_work_sync(&ha->board_disable);
3886 
3887 	/*
3888 	 * If the PCI device is disabled then there was a PCI-disconnect and
3889 	 * qla2x00_disable_board_on_pci_error has taken care of most of the
3890 	 * resources.
3891 	 */
3892 	if (!atomic_read(&pdev->enable_cnt)) {
3893 		dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3894 		    base_vha->gnl.l, base_vha->gnl.ldma);
3895 		base_vha->gnl.l = NULL;
3896 		scsi_host_put(base_vha->host);
3897 		kfree(ha);
3898 		pci_set_drvdata(pdev, NULL);
3899 		return;
3900 	}
3901 	qla2x00_wait_for_hba_ready(base_vha);
3902 
3903 	/*
3904 	 * if UNLOADING flag is already set, then continue unload,
3905 	 * where it was set first.
3906 	 */
3907 	if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3908 		return;
3909 
3910 	if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3911 	    IS_QLA28XX(ha)) {
3912 		if (ha->flags.fw_started)
3913 			qla2x00_abort_isp_cleanup(base_vha);
3914 	} else if (!IS_QLAFX00(ha)) {
3915 		if (IS_QLA8031(ha)) {
3916 			ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3917 			    "Clearing fcoe driver presence.\n");
3918 			if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3919 				ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3920 				    "Error while clearing DRV-Presence.\n");
3921 		}
3922 
3923 		qla2x00_try_to_stop_firmware(base_vha);
3924 	}
3925 
3926 	qla2x00_wait_for_sess_deletion(base_vha);
3927 
3928 	qla_nvme_delete(base_vha);
3929 
3930 	dma_free_coherent(&ha->pdev->dev,
3931 		base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3932 
3933 	base_vha->gnl.l = NULL;
3934 	qla_enode_stop(base_vha);
3935 	qla_edb_stop(base_vha);
3936 
3937 	vfree(base_vha->scan.l);
3938 
3939 	if (IS_QLAFX00(ha))
3940 		qlafx00_driver_shutdown(base_vha, 20);
3941 
3942 	qla2x00_delete_all_vps(ha, base_vha);
3943 
3944 	qla2x00_dfs_remove(base_vha);
3945 
3946 	qla84xx_put_chip(base_vha);
3947 
3948 	/* Disable timer */
3949 	if (base_vha->timer_active)
3950 		qla2x00_stop_timer(base_vha);
3951 
3952 	base_vha->flags.online = 0;
3953 
3954 	/* free DMA memory */
3955 	if (ha->exlogin_buf)
3956 		qla2x00_free_exlogin_buffer(ha);
3957 
3958 	/* free DMA memory */
3959 	if (ha->exchoffld_buf)
3960 		qla2x00_free_exchoffld_buffer(ha);
3961 
3962 	qla2x00_destroy_deferred_work(ha);
3963 
3964 	qlt_remove_target(ha, base_vha);
3965 
3966 	qla2x00_free_sysfs_attr(base_vha, true);
3967 
3968 	fc_remove_host(base_vha->host);
3969 
3970 	scsi_remove_host(base_vha->host);
3971 
3972 	qla2x00_free_device(base_vha);
3973 
3974 	qla2x00_clear_drv_active(ha);
3975 
3976 	scsi_host_put(base_vha->host);
3977 
3978 	qla2x00_unmap_iobases(ha);
3979 
3980 	pci_release_selected_regions(ha->pdev, ha->bars);
3981 	kfree(ha);
3982 
3983 	pci_disable_device(pdev);
3984 }
3985 
3986 static inline void
qla24xx_free_purex_list(struct purex_list * list)3987 qla24xx_free_purex_list(struct purex_list *list)
3988 {
3989 	struct purex_item *item, *next;
3990 	ulong flags;
3991 
3992 	spin_lock_irqsave(&list->lock, flags);
3993 	list_for_each_entry_safe(item, next, &list->head, list) {
3994 		list_del(&item->list);
3995 		if (item == &item->vha->default_item)
3996 			continue;
3997 		kfree(item);
3998 	}
3999 	spin_unlock_irqrestore(&list->lock, flags);
4000 }
4001 
4002 static void
qla2x00_free_device(scsi_qla_host_t * vha)4003 qla2x00_free_device(scsi_qla_host_t *vha)
4004 {
4005 	struct qla_hw_data *ha = vha->hw;
4006 
4007 	qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
4008 
4009 	/* Disable timer */
4010 	if (vha->timer_active)
4011 		qla2x00_stop_timer(vha);
4012 
4013 	qla25xx_delete_queues(vha);
4014 	vha->flags.online = 0;
4015 
4016 	/* turn-off interrupts on the card */
4017 	if (ha->interrupts_on) {
4018 		vha->flags.init_done = 0;
4019 		ha->isp_ops->disable_intrs(ha);
4020 	}
4021 
4022 	qla2x00_free_fcports(vha);
4023 
4024 	qla2x00_free_irqs(vha);
4025 
4026 	/* Flush the work queue and remove it */
4027 	if (ha->wq) {
4028 		destroy_workqueue(ha->wq);
4029 		ha->wq = NULL;
4030 	}
4031 
4032 
4033 	qla24xx_free_purex_list(&vha->purex_list);
4034 
4035 	qla2x00_mem_free(ha);
4036 
4037 	qla82xx_md_free(vha);
4038 
4039 	qla_edif_sadb_release_free_pool(ha);
4040 	qla_edif_sadb_release(ha);
4041 
4042 	qla2x00_free_queues(ha);
4043 }
4044 
qla2x00_free_fcports(struct scsi_qla_host * vha)4045 void qla2x00_free_fcports(struct scsi_qla_host *vha)
4046 {
4047 	fc_port_t *fcport, *tfcport;
4048 
4049 	list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
4050 		qla2x00_free_fcport(fcport);
4051 }
4052 
4053 static inline void
qla2x00_schedule_rport_del(struct scsi_qla_host * vha,fc_port_t * fcport)4054 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
4055 {
4056 	int now;
4057 
4058 	if (!fcport->rport)
4059 		return;
4060 
4061 	if (fcport->rport) {
4062 		ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
4063 		    "%s %8phN. rport %p roles %x\n",
4064 		    __func__, fcport->port_name, fcport->rport,
4065 		    fcport->rport->roles);
4066 		fc_remote_port_delete(fcport->rport);
4067 	}
4068 	qlt_do_generation_tick(vha, &now);
4069 }
4070 
4071 /*
4072  * qla2x00_mark_device_lost Updates fcport state when device goes offline.
4073  *
4074  * Input: ha = adapter block pointer.  fcport = port structure pointer.
4075  *
4076  * Return: None.
4077  *
4078  * Context:
4079  */
qla2x00_mark_device_lost(scsi_qla_host_t * vha,fc_port_t * fcport,int do_login)4080 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
4081     int do_login)
4082 {
4083 	if (IS_QLAFX00(vha->hw)) {
4084 		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4085 		qla2x00_schedule_rport_del(vha, fcport);
4086 		return;
4087 	}
4088 
4089 	if (atomic_read(&fcport->state) == FCS_ONLINE &&
4090 	    vha->vp_idx == fcport->vha->vp_idx) {
4091 		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4092 		qla2x00_schedule_rport_del(vha, fcport);
4093 	}
4094 
4095 	/*
4096 	 * We may need to retry the login, so don't change the state of the
4097 	 * port but do the retries.
4098 	 */
4099 	if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
4100 		qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
4101 
4102 	if (!do_login)
4103 		return;
4104 
4105 	set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4106 }
4107 
4108 void
qla2x00_mark_all_devices_lost(scsi_qla_host_t * vha)4109 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
4110 {
4111 	fc_port_t *fcport;
4112 
4113 	ql_dbg(ql_dbg_disc, vha, 0x20f1,
4114 	    "Mark all dev lost\n");
4115 
4116 	list_for_each_entry(fcport, &vha->vp_fcports, list) {
4117 		if (ql2xfc2target &&
4118 		    fcport->loop_id != FC_NO_LOOP_ID &&
4119 		    (fcport->flags & FCF_FCP2_DEVICE) &&
4120 		    fcport->port_type == FCT_TARGET &&
4121 		    !qla2x00_reset_active(vha)) {
4122 			ql_dbg(ql_dbg_disc, vha, 0x211a,
4123 			       "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC",
4124 			       fcport->flags, fcport->port_type,
4125 			       fcport->d_id.b24, fcport->port_name);
4126 			continue;
4127 		}
4128 		fcport->scan_state = 0;
4129 		qlt_schedule_sess_for_deletion(fcport);
4130 	}
4131 }
4132 
qla2x00_set_reserved_loop_ids(struct qla_hw_data * ha)4133 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
4134 {
4135 	int i;
4136 
4137 	if (IS_FWI2_CAPABLE(ha))
4138 		return;
4139 
4140 	for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
4141 		set_bit(i, ha->loop_id_map);
4142 	set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
4143 	set_bit(BROADCAST, ha->loop_id_map);
4144 }
4145 
4146 /*
4147 * qla2x00_mem_alloc
4148 *      Allocates adapter memory.
4149 *
4150 * Returns:
4151 *      0  = success.
4152 *      !0  = failure.
4153 */
4154 static int
qla2x00_mem_alloc(struct qla_hw_data * ha,uint16_t req_len,uint16_t rsp_len,struct req_que ** req,struct rsp_que ** rsp)4155 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
4156 	struct req_que **req, struct rsp_que **rsp)
4157 {
4158 	char	name[16];
4159 	int rc;
4160 
4161 	if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) {
4162 		ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL);
4163 		if (!ha->vp_map)
4164 			goto fail;
4165 	}
4166 
4167 	ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
4168 		&ha->init_cb_dma, GFP_KERNEL);
4169 	if (!ha->init_cb)
4170 		goto fail_free_vp_map;
4171 
4172 	rc = btree_init32(&ha->host_map);
4173 	if (rc)
4174 		goto fail_free_init_cb;
4175 
4176 	if (qlt_mem_alloc(ha) < 0)
4177 		goto fail_free_btree;
4178 
4179 	ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
4180 		qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
4181 	if (!ha->gid_list)
4182 		goto fail_free_tgt_mem;
4183 
4184 	ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
4185 	if (!ha->srb_mempool)
4186 		goto fail_free_gid_list;
4187 
4188 	if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) {
4189 		/* Allocate cache for CT6 Ctx. */
4190 		if (!ctx_cachep) {
4191 			ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4192 				sizeof(struct ct6_dsd), 0,
4193 				SLAB_HWCACHE_ALIGN, NULL);
4194 			if (!ctx_cachep)
4195 				goto fail_free_srb_mempool;
4196 		}
4197 		ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4198 			ctx_cachep);
4199 		if (!ha->ctx_mempool)
4200 			goto fail_free_srb_mempool;
4201 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4202 		    "ctx_cachep=%p ctx_mempool=%p.\n",
4203 		    ctx_cachep, ha->ctx_mempool);
4204 	}
4205 
4206 	/* Get memory for cached NVRAM */
4207 	ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4208 	if (!ha->nvram)
4209 		goto fail_free_ctx_mempool;
4210 
4211 	snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4212 		ha->pdev->device);
4213 	ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4214 		DMA_POOL_SIZE, 8, 0);
4215 	if (!ha->s_dma_pool)
4216 		goto fail_free_nvram;
4217 
4218 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4219 	    "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4220 	    ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4221 
4222 	if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) {
4223 		ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4224 			DSD_LIST_DMA_POOL_SIZE, 8, 0);
4225 		if (!ha->dl_dma_pool) {
4226 			ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4227 			    "Failed to allocate memory for dl_dma_pool.\n");
4228 			goto fail_s_dma_pool;
4229 		}
4230 
4231 		ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4232 			FCP_CMND_DMA_POOL_SIZE, 8, 0);
4233 		if (!ha->fcp_cmnd_dma_pool) {
4234 			ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4235 			    "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4236 			goto fail_dl_dma_pool;
4237 		}
4238 
4239 		if (ql2xenabledif) {
4240 			u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4241 			struct dsd_dma *dsd, *nxt;
4242 			uint i;
4243 			/* Creata a DMA pool of buffers for DIF bundling */
4244 			ha->dif_bundl_pool = dma_pool_create(name,
4245 			    &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4246 			if (!ha->dif_bundl_pool) {
4247 				ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4248 				    "%s: failed create dif_bundl_pool\n",
4249 				    __func__);
4250 				goto fail_dif_bundl_dma_pool;
4251 			}
4252 
4253 			INIT_LIST_HEAD(&ha->pool.good.head);
4254 			INIT_LIST_HEAD(&ha->pool.unusable.head);
4255 			ha->pool.good.count = 0;
4256 			ha->pool.unusable.count = 0;
4257 			for (i = 0; i < 128; i++) {
4258 				dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4259 				if (!dsd) {
4260 					ql_dbg_pci(ql_dbg_init, ha->pdev,
4261 					    0xe0ee, "%s: failed alloc dsd\n",
4262 					    __func__);
4263 					return -ENOMEM;
4264 				}
4265 				ha->dif_bundle_kallocs++;
4266 
4267 				dsd->dsd_addr = dma_pool_alloc(
4268 				    ha->dif_bundl_pool, GFP_ATOMIC,
4269 				    &dsd->dsd_list_dma);
4270 				if (!dsd->dsd_addr) {
4271 					ql_dbg_pci(ql_dbg_init, ha->pdev,
4272 					    0xe0ee,
4273 					    "%s: failed alloc ->dsd_addr\n",
4274 					    __func__);
4275 					kfree(dsd);
4276 					ha->dif_bundle_kallocs--;
4277 					continue;
4278 				}
4279 				ha->dif_bundle_dma_allocs++;
4280 
4281 				/*
4282 				 * if DMA buffer crosses 4G boundary,
4283 				 * put it on bad list
4284 				 */
4285 				if (MSD(dsd->dsd_list_dma) ^
4286 				    MSD(dsd->dsd_list_dma + bufsize)) {
4287 					list_add_tail(&dsd->list,
4288 					    &ha->pool.unusable.head);
4289 					ha->pool.unusable.count++;
4290 				} else {
4291 					list_add_tail(&dsd->list,
4292 					    &ha->pool.good.head);
4293 					ha->pool.good.count++;
4294 				}
4295 			}
4296 
4297 			/* return the good ones back to the pool */
4298 			list_for_each_entry_safe(dsd, nxt,
4299 			    &ha->pool.good.head, list) {
4300 				list_del(&dsd->list);
4301 				dma_pool_free(ha->dif_bundl_pool,
4302 				    dsd->dsd_addr, dsd->dsd_list_dma);
4303 				ha->dif_bundle_dma_allocs--;
4304 				kfree(dsd);
4305 				ha->dif_bundle_kallocs--;
4306 			}
4307 
4308 			ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4309 			    "%s: dif dma pool (good=%u unusable=%u)\n",
4310 			    __func__, ha->pool.good.count,
4311 			    ha->pool.unusable.count);
4312 		}
4313 
4314 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4315 		    "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4316 		    ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4317 		    ha->dif_bundl_pool);
4318 	}
4319 
4320 	/* Allocate memory for SNS commands */
4321 	if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4322 	/* Get consistent memory allocated for SNS commands */
4323 		ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4324 		sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4325 		if (!ha->sns_cmd)
4326 			goto fail_dma_pool;
4327 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4328 		    "sns_cmd: %p.\n", ha->sns_cmd);
4329 	} else {
4330 	/* Get consistent memory allocated for MS IOCB */
4331 		ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4332 			&ha->ms_iocb_dma);
4333 		if (!ha->ms_iocb)
4334 			goto fail_dma_pool;
4335 	/* Get consistent memory allocated for CT SNS commands */
4336 		ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4337 			sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4338 		if (!ha->ct_sns)
4339 			goto fail_free_ms_iocb;
4340 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4341 		    "ms_iocb=%p ct_sns=%p.\n",
4342 		    ha->ms_iocb, ha->ct_sns);
4343 	}
4344 
4345 	/* Allocate memory for request ring */
4346 	*req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4347 	if (!*req) {
4348 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4349 		    "Failed to allocate memory for req.\n");
4350 		goto fail_req;
4351 	}
4352 	(*req)->length = req_len;
4353 	(*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4354 		((*req)->length + 1) * sizeof(request_t),
4355 		&(*req)->dma, GFP_KERNEL);
4356 	if (!(*req)->ring) {
4357 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4358 		    "Failed to allocate memory for req_ring.\n");
4359 		goto fail_req_ring;
4360 	}
4361 	/* Allocate memory for response ring */
4362 	*rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4363 	if (!*rsp) {
4364 		ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4365 		    "Failed to allocate memory for rsp.\n");
4366 		goto fail_rsp;
4367 	}
4368 	(*rsp)->hw = ha;
4369 	(*rsp)->length = rsp_len;
4370 	(*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4371 		((*rsp)->length + 1) * sizeof(response_t),
4372 		&(*rsp)->dma, GFP_KERNEL);
4373 	if (!(*rsp)->ring) {
4374 		ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4375 		    "Failed to allocate memory for rsp_ring.\n");
4376 		goto fail_rsp_ring;
4377 	}
4378 	(*req)->rsp = *rsp;
4379 	(*rsp)->req = *req;
4380 	ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4381 	    "req=%p req->length=%d req->ring=%p rsp=%p "
4382 	    "rsp->length=%d rsp->ring=%p.\n",
4383 	    *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4384 	    (*rsp)->ring);
4385 	/* Allocate memory for NVRAM data for vports */
4386 	if (ha->nvram_npiv_size) {
4387 		ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4388 					sizeof(struct qla_npiv_entry),
4389 					GFP_KERNEL);
4390 		if (!ha->npiv_info) {
4391 			ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4392 			    "Failed to allocate memory for npiv_info.\n");
4393 			goto fail_npiv_info;
4394 		}
4395 	} else
4396 		ha->npiv_info = NULL;
4397 
4398 	/* Get consistent memory allocated for EX-INIT-CB. */
4399 	if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4400 	    IS_QLA28XX(ha)) {
4401 		ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4402 		    &ha->ex_init_cb_dma);
4403 		if (!ha->ex_init_cb)
4404 			goto fail_ex_init_cb;
4405 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4406 		    "ex_init_cb=%p.\n", ha->ex_init_cb);
4407 	}
4408 
4409 	/* Get consistent memory allocated for Special Features-CB. */
4410 	if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4411 		ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL,
4412 						&ha->sf_init_cb_dma);
4413 		if (!ha->sf_init_cb)
4414 			goto fail_sf_init_cb;
4415 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4416 			   "sf_init_cb=%p.\n", ha->sf_init_cb);
4417 	}
4418 
4419 
4420 	/* Get consistent memory allocated for Async Port-Database. */
4421 	if (!IS_FWI2_CAPABLE(ha)) {
4422 		ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4423 			&ha->async_pd_dma);
4424 		if (!ha->async_pd)
4425 			goto fail_async_pd;
4426 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4427 		    "async_pd=%p.\n", ha->async_pd);
4428 	}
4429 
4430 	INIT_LIST_HEAD(&ha->vp_list);
4431 
4432 	/* Allocate memory for our loop_id bitmap */
4433 	ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4434 				  sizeof(long),
4435 				  GFP_KERNEL);
4436 	if (!ha->loop_id_map)
4437 		goto fail_loop_id_map;
4438 	else {
4439 		qla2x00_set_reserved_loop_ids(ha);
4440 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4441 		    "loop_id_map=%p.\n", ha->loop_id_map);
4442 	}
4443 
4444 	ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4445 	    SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4446 	if (!ha->sfp_data) {
4447 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4448 		    "Unable to allocate memory for SFP read-data.\n");
4449 		goto fail_sfp_data;
4450 	}
4451 
4452 	ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4453 	    sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4454 	    GFP_KERNEL);
4455 	if (!ha->flt) {
4456 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4457 		    "Unable to allocate memory for FLT.\n");
4458 		goto fail_flt_buffer;
4459 	}
4460 
4461 	/* allocate the purex dma pool */
4462 	ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4463 	    ELS_MAX_PAYLOAD, 8, 0);
4464 
4465 	if (!ha->purex_dma_pool) {
4466 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4467 		    "Unable to allocate purex_dma_pool.\n");
4468 		goto fail_flt;
4469 	}
4470 
4471 	ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16;
4472 	ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev,
4473 					  ha->elsrej.size,
4474 					  &ha->elsrej.cdma,
4475 					  GFP_KERNEL);
4476 	if (!ha->elsrej.c) {
4477 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4478 		    "Alloc failed for els reject cmd.\n");
4479 		goto fail_elsrej;
4480 	}
4481 	ha->elsrej.c->er_cmd = ELS_LS_RJT;
4482 	ha->elsrej.c->er_reason = ELS_RJT_LOGIC;
4483 	ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA;
4484 
4485 	ha->lsrjt.size = sizeof(struct fcnvme_ls_rjt);
4486 	ha->lsrjt.c = dma_alloc_coherent(&ha->pdev->dev, ha->lsrjt.size,
4487 			&ha->lsrjt.cdma, GFP_KERNEL);
4488 	if (!ha->lsrjt.c) {
4489 		ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff,
4490 			   "Alloc failed for nvme fc reject cmd.\n");
4491 		goto fail_lsrjt;
4492 	}
4493 
4494 	return 0;
4495 
4496 fail_lsrjt:
4497 	dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
4498 			  ha->elsrej.c, ha->elsrej.cdma);
4499 fail_elsrej:
4500 	dma_pool_destroy(ha->purex_dma_pool);
4501 fail_flt:
4502 	dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4503 	    ha->flt, ha->flt_dma);
4504 
4505 fail_flt_buffer:
4506 	dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4507 	    ha->sfp_data, ha->sfp_data_dma);
4508 fail_sfp_data:
4509 	kfree(ha->loop_id_map);
4510 fail_loop_id_map:
4511 	dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4512 fail_async_pd:
4513 	dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4514 fail_sf_init_cb:
4515 	dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4516 fail_ex_init_cb:
4517 	kfree(ha->npiv_info);
4518 fail_npiv_info:
4519 	dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4520 		sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4521 	(*rsp)->ring = NULL;
4522 	(*rsp)->dma = 0;
4523 fail_rsp_ring:
4524 	kfree(*rsp);
4525 	*rsp = NULL;
4526 fail_rsp:
4527 	dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4528 		sizeof(request_t), (*req)->ring, (*req)->dma);
4529 	(*req)->ring = NULL;
4530 	(*req)->dma = 0;
4531 fail_req_ring:
4532 	kfree(*req);
4533 	*req = NULL;
4534 fail_req:
4535 	dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4536 		ha->ct_sns, ha->ct_sns_dma);
4537 	ha->ct_sns = NULL;
4538 	ha->ct_sns_dma = 0;
4539 fail_free_ms_iocb:
4540 	dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4541 	ha->ms_iocb = NULL;
4542 	ha->ms_iocb_dma = 0;
4543 
4544 	if (ha->sns_cmd)
4545 		dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4546 		    ha->sns_cmd, ha->sns_cmd_dma);
4547 fail_dma_pool:
4548 	if (ql2xenabledif) {
4549 		struct dsd_dma *dsd, *nxt;
4550 
4551 		list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4552 		    list) {
4553 			list_del(&dsd->list);
4554 			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4555 			    dsd->dsd_list_dma);
4556 			ha->dif_bundle_dma_allocs--;
4557 			kfree(dsd);
4558 			ha->dif_bundle_kallocs--;
4559 			ha->pool.unusable.count--;
4560 		}
4561 		dma_pool_destroy(ha->dif_bundl_pool);
4562 		ha->dif_bundl_pool = NULL;
4563 	}
4564 
4565 fail_dif_bundl_dma_pool:
4566 	if (IS_QLA82XX(ha) || ql2xenabledif) {
4567 		dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4568 		ha->fcp_cmnd_dma_pool = NULL;
4569 	}
4570 fail_dl_dma_pool:
4571 	if (IS_QLA82XX(ha) || ql2xenabledif) {
4572 		dma_pool_destroy(ha->dl_dma_pool);
4573 		ha->dl_dma_pool = NULL;
4574 	}
4575 fail_s_dma_pool:
4576 	dma_pool_destroy(ha->s_dma_pool);
4577 	ha->s_dma_pool = NULL;
4578 fail_free_nvram:
4579 	kfree(ha->nvram);
4580 	ha->nvram = NULL;
4581 fail_free_ctx_mempool:
4582 	mempool_destroy(ha->ctx_mempool);
4583 	ha->ctx_mempool = NULL;
4584 fail_free_srb_mempool:
4585 	mempool_destroy(ha->srb_mempool);
4586 	ha->srb_mempool = NULL;
4587 fail_free_gid_list:
4588 	dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4589 	ha->gid_list,
4590 	ha->gid_list_dma);
4591 	ha->gid_list = NULL;
4592 	ha->gid_list_dma = 0;
4593 fail_free_tgt_mem:
4594 	qlt_mem_free(ha);
4595 fail_free_btree:
4596 	btree_destroy32(&ha->host_map);
4597 fail_free_init_cb:
4598 	dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4599 	ha->init_cb_dma);
4600 	ha->init_cb = NULL;
4601 	ha->init_cb_dma = 0;
4602 fail_free_vp_map:
4603 	kfree(ha->vp_map);
4604 fail:
4605 	ql_log(ql_log_fatal, NULL, 0x0030,
4606 	    "Memory allocation failure.\n");
4607 	return -ENOMEM;
4608 }
4609 
4610 int
qla2x00_set_exlogins_buffer(scsi_qla_host_t * vha)4611 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4612 {
4613 	int rval;
4614 	uint16_t	size, max_cnt;
4615 	uint32_t temp;
4616 	struct qla_hw_data *ha = vha->hw;
4617 
4618 	/* Return if we don't need to alloacate any extended logins */
4619 	if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400)
4620 		return QLA_SUCCESS;
4621 
4622 	if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4623 		return QLA_SUCCESS;
4624 
4625 	ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4626 	max_cnt = 0;
4627 	rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4628 	if (rval != QLA_SUCCESS) {
4629 		ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4630 		    "Failed to get exlogin status.\n");
4631 		return rval;
4632 	}
4633 
4634 	temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4635 	temp *= size;
4636 
4637 	if (temp != ha->exlogin_size) {
4638 		qla2x00_free_exlogin_buffer(ha);
4639 		ha->exlogin_size = temp;
4640 
4641 		ql_log(ql_log_info, vha, 0xd024,
4642 		    "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4643 		    max_cnt, size, temp);
4644 
4645 		ql_log(ql_log_info, vha, 0xd025,
4646 		    "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4647 
4648 		/* Get consistent memory for extended logins */
4649 		ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4650 			ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4651 		if (!ha->exlogin_buf) {
4652 			ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4653 		    "Failed to allocate memory for exlogin_buf_dma.\n");
4654 			return -ENOMEM;
4655 		}
4656 	}
4657 
4658 	/* Now configure the dma buffer */
4659 	rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4660 	if (rval) {
4661 		ql_log(ql_log_fatal, vha, 0xd033,
4662 		    "Setup extended login buffer  ****FAILED****.\n");
4663 		qla2x00_free_exlogin_buffer(ha);
4664 	}
4665 
4666 	return rval;
4667 }
4668 
4669 /*
4670 * qla2x00_free_exlogin_buffer
4671 *
4672 * Input:
4673 *	ha = adapter block pointer
4674 */
4675 void
qla2x00_free_exlogin_buffer(struct qla_hw_data * ha)4676 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4677 {
4678 	if (ha->exlogin_buf) {
4679 		dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4680 		    ha->exlogin_buf, ha->exlogin_buf_dma);
4681 		ha->exlogin_buf = NULL;
4682 		ha->exlogin_size = 0;
4683 	}
4684 }
4685 
4686 static void
qla2x00_number_of_exch(scsi_qla_host_t * vha,u32 * ret_cnt,u16 max_cnt)4687 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4688 {
4689 	u32 temp;
4690 	struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
4691 	*ret_cnt = FW_DEF_EXCHANGES_CNT;
4692 
4693 	if (max_cnt > vha->hw->max_exchg)
4694 		max_cnt = vha->hw->max_exchg;
4695 
4696 	if (qla_ini_mode_enabled(vha)) {
4697 		if (vha->ql2xiniexchg > max_cnt)
4698 			vha->ql2xiniexchg = max_cnt;
4699 
4700 		if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4701 			*ret_cnt = vha->ql2xiniexchg;
4702 
4703 	} else if (qla_tgt_mode_enabled(vha)) {
4704 		if (vha->ql2xexchoffld > max_cnt) {
4705 			vha->ql2xexchoffld = max_cnt;
4706 			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4707 		}
4708 
4709 		if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4710 			*ret_cnt = vha->ql2xexchoffld;
4711 	} else if (qla_dual_mode_enabled(vha)) {
4712 		temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4713 		if (temp > max_cnt) {
4714 			vha->ql2xiniexchg -= (temp - max_cnt)/2;
4715 			vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4716 			temp = max_cnt;
4717 			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4718 		}
4719 
4720 		if (temp > FW_DEF_EXCHANGES_CNT)
4721 			*ret_cnt = temp;
4722 	}
4723 }
4724 
4725 int
qla2x00_set_exchoffld_buffer(scsi_qla_host_t * vha)4726 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4727 {
4728 	int rval;
4729 	u16	size, max_cnt;
4730 	u32 actual_cnt, totsz;
4731 	struct qla_hw_data *ha = vha->hw;
4732 
4733 	if (!ha->flags.exchoffld_enabled)
4734 		return QLA_SUCCESS;
4735 
4736 	if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4737 		return QLA_SUCCESS;
4738 
4739 	max_cnt = 0;
4740 	rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4741 	if (rval != QLA_SUCCESS) {
4742 		ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4743 		    "Failed to get exlogin status.\n");
4744 		return rval;
4745 	}
4746 
4747 	qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4748 	ql_log(ql_log_info, vha, 0xd014,
4749 	    "Actual exchange offload count: %d.\n", actual_cnt);
4750 
4751 	totsz = actual_cnt * size;
4752 
4753 	if (totsz != ha->exchoffld_size) {
4754 		qla2x00_free_exchoffld_buffer(ha);
4755 		if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4756 			ha->exchoffld_size = 0;
4757 			ha->flags.exchoffld_enabled = 0;
4758 			return QLA_SUCCESS;
4759 		}
4760 
4761 		ha->exchoffld_size = totsz;
4762 
4763 		ql_log(ql_log_info, vha, 0xd016,
4764 		    "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4765 		    max_cnt, actual_cnt, size, totsz);
4766 
4767 		ql_log(ql_log_info, vha, 0xd017,
4768 		    "Exchange Buffers requested size = 0x%x\n",
4769 		    ha->exchoffld_size);
4770 
4771 		/* Get consistent memory for extended logins */
4772 		ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4773 			ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4774 		if (!ha->exchoffld_buf) {
4775 			ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4776 			"Failed to allocate memory for Exchange Offload.\n");
4777 
4778 			if (ha->max_exchg >
4779 			    (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4780 				ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4781 			} else if (ha->max_exchg >
4782 			    (FW_DEF_EXCHANGES_CNT + 512)) {
4783 				ha->max_exchg -= 512;
4784 			} else {
4785 				ha->flags.exchoffld_enabled = 0;
4786 				ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4787 				    "Disabling Exchange offload due to lack of memory\n");
4788 			}
4789 			ha->exchoffld_size = 0;
4790 
4791 			return -ENOMEM;
4792 		}
4793 	} else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4794 		/* pathological case */
4795 		qla2x00_free_exchoffld_buffer(ha);
4796 		ha->exchoffld_size = 0;
4797 		ha->flags.exchoffld_enabled = 0;
4798 		ql_log(ql_log_info, vha, 0xd016,
4799 		    "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4800 		    ha->exchoffld_size, actual_cnt, size, totsz);
4801 		return 0;
4802 	}
4803 
4804 	/* Now configure the dma buffer */
4805 	rval = qla_set_exchoffld_mem_cfg(vha);
4806 	if (rval) {
4807 		ql_log(ql_log_fatal, vha, 0xd02e,
4808 		    "Setup exchange offload buffer ****FAILED****.\n");
4809 		qla2x00_free_exchoffld_buffer(ha);
4810 	} else {
4811 		/* re-adjust number of target exchange */
4812 		struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4813 
4814 		if (qla_ini_mode_enabled(vha))
4815 			icb->exchange_count = 0;
4816 		else
4817 			icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4818 	}
4819 
4820 	return rval;
4821 }
4822 
4823 /*
4824 * qla2x00_free_exchoffld_buffer
4825 *
4826 * Input:
4827 *	ha = adapter block pointer
4828 */
4829 void
qla2x00_free_exchoffld_buffer(struct qla_hw_data * ha)4830 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4831 {
4832 	if (ha->exchoffld_buf) {
4833 		dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4834 		    ha->exchoffld_buf, ha->exchoffld_buf_dma);
4835 		ha->exchoffld_buf = NULL;
4836 		ha->exchoffld_size = 0;
4837 	}
4838 }
4839 
4840 /*
4841 * qla2x00_free_fw_dump
4842 *	Frees fw dump stuff.
4843 *
4844 * Input:
4845 *	ha = adapter block pointer
4846 */
4847 static void
qla2x00_free_fw_dump(struct qla_hw_data * ha)4848 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4849 {
4850 	struct fwdt *fwdt = ha->fwdt;
4851 	uint j;
4852 
4853 	if (ha->fce)
4854 		dma_free_coherent(&ha->pdev->dev,
4855 		    FCE_SIZE, ha->fce, ha->fce_dma);
4856 
4857 	if (ha->eft)
4858 		dma_free_coherent(&ha->pdev->dev,
4859 		    EFT_SIZE, ha->eft, ha->eft_dma);
4860 
4861 	vfree(ha->fw_dump);
4862 
4863 	ha->fce = NULL;
4864 	ha->fce_dma = 0;
4865 	ha->flags.fce_enabled = 0;
4866 	ha->eft = NULL;
4867 	ha->eft_dma = 0;
4868 	ha->fw_dumped = false;
4869 	ha->fw_dump_cap_flags = 0;
4870 	ha->fw_dump_reading = 0;
4871 	ha->fw_dump = NULL;
4872 	ha->fw_dump_len = 0;
4873 
4874 	for (j = 0; j < 2; j++, fwdt++) {
4875 		vfree(fwdt->template);
4876 		fwdt->template = NULL;
4877 		fwdt->length = 0;
4878 	}
4879 }
4880 
4881 /*
4882 * qla2x00_mem_free
4883 *      Frees all adapter allocated memory.
4884 *
4885 * Input:
4886 *      ha = adapter block pointer.
4887 */
4888 static void
qla2x00_mem_free(struct qla_hw_data * ha)4889 qla2x00_mem_free(struct qla_hw_data *ha)
4890 {
4891 	qla2x00_free_fw_dump(ha);
4892 
4893 	if (ha->mctp_dump)
4894 		dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4895 		    ha->mctp_dump_dma);
4896 	ha->mctp_dump = NULL;
4897 
4898 	mempool_destroy(ha->srb_mempool);
4899 	ha->srb_mempool = NULL;
4900 
4901 	if (ha->dcbx_tlv)
4902 		dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4903 		    ha->dcbx_tlv, ha->dcbx_tlv_dma);
4904 	ha->dcbx_tlv = NULL;
4905 
4906 	if (ha->xgmac_data)
4907 		dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4908 		    ha->xgmac_data, ha->xgmac_data_dma);
4909 	ha->xgmac_data = NULL;
4910 
4911 	if (ha->sns_cmd)
4912 		dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4913 		ha->sns_cmd, ha->sns_cmd_dma);
4914 	ha->sns_cmd = NULL;
4915 	ha->sns_cmd_dma = 0;
4916 
4917 	if (ha->ct_sns)
4918 		dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4919 		ha->ct_sns, ha->ct_sns_dma);
4920 	ha->ct_sns = NULL;
4921 	ha->ct_sns_dma = 0;
4922 
4923 	if (ha->sfp_data)
4924 		dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4925 		    ha->sfp_data_dma);
4926 	ha->sfp_data = NULL;
4927 
4928 	if (ha->flt)
4929 		dma_free_coherent(&ha->pdev->dev,
4930 		    sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
4931 		    ha->flt, ha->flt_dma);
4932 	ha->flt = NULL;
4933 	ha->flt_dma = 0;
4934 
4935 	if (ha->ms_iocb)
4936 		dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4937 	ha->ms_iocb = NULL;
4938 	ha->ms_iocb_dma = 0;
4939 
4940 	if (ha->sf_init_cb)
4941 		dma_pool_free(ha->s_dma_pool,
4942 			      ha->sf_init_cb, ha->sf_init_cb_dma);
4943 
4944 	if (ha->ex_init_cb)
4945 		dma_pool_free(ha->s_dma_pool,
4946 			ha->ex_init_cb, ha->ex_init_cb_dma);
4947 	ha->ex_init_cb = NULL;
4948 	ha->ex_init_cb_dma = 0;
4949 
4950 	if (ha->async_pd)
4951 		dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4952 	ha->async_pd = NULL;
4953 	ha->async_pd_dma = 0;
4954 
4955 	dma_pool_destroy(ha->s_dma_pool);
4956 	ha->s_dma_pool = NULL;
4957 
4958 	if (ha->gid_list)
4959 		dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4960 		ha->gid_list, ha->gid_list_dma);
4961 	ha->gid_list = NULL;
4962 	ha->gid_list_dma = 0;
4963 
4964 	if (ha->base_qpair && !list_empty(&ha->base_qpair->dsd_list)) {
4965 		struct dsd_dma *dsd_ptr, *tdsd_ptr;
4966 
4967 		/* clean up allocated prev pool */
4968 		list_for_each_entry_safe(dsd_ptr, tdsd_ptr,
4969 					 &ha->base_qpair->dsd_list, list) {
4970 			dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr,
4971 				      dsd_ptr->dsd_list_dma);
4972 			list_del(&dsd_ptr->list);
4973 			kfree(dsd_ptr);
4974 		}
4975 	}
4976 
4977 	dma_pool_destroy(ha->dl_dma_pool);
4978 	ha->dl_dma_pool = NULL;
4979 
4980 	dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4981 	ha->fcp_cmnd_dma_pool = NULL;
4982 
4983 	mempool_destroy(ha->ctx_mempool);
4984 	ha->ctx_mempool = NULL;
4985 
4986 	if (ql2xenabledif && ha->dif_bundl_pool) {
4987 		struct dsd_dma *dsd, *nxt;
4988 
4989 		list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4990 					 list) {
4991 			list_del(&dsd->list);
4992 			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4993 				      dsd->dsd_list_dma);
4994 			ha->dif_bundle_dma_allocs--;
4995 			kfree(dsd);
4996 			ha->dif_bundle_kallocs--;
4997 			ha->pool.unusable.count--;
4998 		}
4999 		list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
5000 			list_del(&dsd->list);
5001 			dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
5002 				      dsd->dsd_list_dma);
5003 			ha->dif_bundle_dma_allocs--;
5004 			kfree(dsd);
5005 			ha->dif_bundle_kallocs--;
5006 		}
5007 	}
5008 
5009 	dma_pool_destroy(ha->dif_bundl_pool);
5010 	ha->dif_bundl_pool = NULL;
5011 
5012 	qlt_mem_free(ha);
5013 	qla_remove_hostmap(ha);
5014 
5015 	if (ha->init_cb)
5016 		dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
5017 			ha->init_cb, ha->init_cb_dma);
5018 
5019 	dma_pool_destroy(ha->purex_dma_pool);
5020 	ha->purex_dma_pool = NULL;
5021 
5022 	if (ha->elsrej.c) {
5023 		dma_free_coherent(&ha->pdev->dev, ha->elsrej.size,
5024 		    ha->elsrej.c, ha->elsrej.cdma);
5025 		ha->elsrej.c = NULL;
5026 	}
5027 
5028 	if (ha->lsrjt.c) {
5029 		dma_free_coherent(&ha->pdev->dev, ha->lsrjt.size, ha->lsrjt.c,
5030 				  ha->lsrjt.cdma);
5031 		ha->lsrjt.c = NULL;
5032 	}
5033 
5034 	ha->init_cb = NULL;
5035 	ha->init_cb_dma = 0;
5036 
5037 	vfree(ha->optrom_buffer);
5038 	ha->optrom_buffer = NULL;
5039 	kfree(ha->nvram);
5040 	ha->nvram = NULL;
5041 	kfree(ha->npiv_info);
5042 	ha->npiv_info = NULL;
5043 	kfree(ha->swl);
5044 	ha->swl = NULL;
5045 	kfree(ha->loop_id_map);
5046 	ha->sf_init_cb = NULL;
5047 	ha->sf_init_cb_dma = 0;
5048 	ha->loop_id_map = NULL;
5049 
5050 	kfree(ha->vp_map);
5051 	ha->vp_map = NULL;
5052 }
5053 
qla2x00_create_host(const struct scsi_host_template * sht,struct qla_hw_data * ha)5054 struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht,
5055 					  struct qla_hw_data *ha)
5056 {
5057 	struct Scsi_Host *host;
5058 	struct scsi_qla_host *vha = NULL;
5059 
5060 	host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
5061 	if (!host) {
5062 		ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
5063 		    "Failed to allocate host from the scsi layer, aborting.\n");
5064 		return NULL;
5065 	}
5066 
5067 	/* Clear our data area */
5068 	vha = shost_priv(host);
5069 	memset(vha, 0, sizeof(scsi_qla_host_t));
5070 
5071 	vha->host = host;
5072 	vha->host_no = host->host_no;
5073 	vha->hw = ha;
5074 
5075 	vha->qlini_mode = ql2x_ini_mode;
5076 	vha->ql2xexchoffld = ql2xexchoffld;
5077 	vha->ql2xiniexchg = ql2xiniexchg;
5078 
5079 	INIT_LIST_HEAD(&vha->vp_fcports);
5080 	INIT_LIST_HEAD(&vha->work_list);
5081 	INIT_LIST_HEAD(&vha->list);
5082 	INIT_LIST_HEAD(&vha->qla_cmd_list);
5083 	INIT_LIST_HEAD(&vha->logo_list);
5084 	INIT_LIST_HEAD(&vha->plogi_ack_list);
5085 	INIT_LIST_HEAD(&vha->qp_list);
5086 	INIT_LIST_HEAD(&vha->gnl.fcports);
5087 	INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
5088 
5089 	INIT_LIST_HEAD(&vha->purex_list.head);
5090 	spin_lock_init(&vha->purex_list.lock);
5091 
5092 	spin_lock_init(&vha->work_lock);
5093 	spin_lock_init(&vha->cmd_list_lock);
5094 	init_waitqueue_head(&vha->fcport_waitQ);
5095 	init_waitqueue_head(&vha->vref_waitq);
5096 	qla_enode_init(vha);
5097 	qla_edb_init(vha);
5098 
5099 
5100 	vha->gnl.size = sizeof(struct get_name_list_extended) *
5101 			(ha->max_loop_id + 1);
5102 	vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
5103 	    vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
5104 	if (!vha->gnl.l) {
5105 		ql_log(ql_log_fatal, vha, 0xd04a,
5106 		    "Alloc failed for name list.\n");
5107 		scsi_host_put(vha->host);
5108 		return NULL;
5109 	}
5110 
5111 	/* todo: what about ext login? */
5112 	vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
5113 	vha->scan.l = vmalloc(vha->scan.size);
5114 	if (!vha->scan.l) {
5115 		ql_log(ql_log_fatal, vha, 0xd04a,
5116 		    "Alloc failed for scan database.\n");
5117 		dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
5118 		    vha->gnl.l, vha->gnl.ldma);
5119 		vha->gnl.l = NULL;
5120 		scsi_host_put(vha->host);
5121 		return NULL;
5122 	}
5123 	INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
5124 
5125 	snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu",
5126 		 QLA2XXX_DRIVER_NAME, vha->host_no);
5127 	ql_dbg(ql_dbg_init, vha, 0x0041,
5128 	    "Allocated the host=%p hw=%p vha=%p dev_name=%s",
5129 	    vha->host, vha->hw, vha,
5130 	    dev_name(&(ha->pdev->dev)));
5131 
5132 	return vha;
5133 }
5134 
5135 struct qla_work_evt *
qla2x00_alloc_work(struct scsi_qla_host * vha,enum qla_work_type type)5136 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
5137 {
5138 	struct qla_work_evt *e;
5139 
5140 	if (test_bit(UNLOADING, &vha->dpc_flags))
5141 		return NULL;
5142 
5143 	if (qla_vha_mark_busy(vha))
5144 		return NULL;
5145 
5146 	e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
5147 	if (!e) {
5148 		QLA_VHA_MARK_NOT_BUSY(vha);
5149 		return NULL;
5150 	}
5151 
5152 	INIT_LIST_HEAD(&e->list);
5153 	e->type = type;
5154 	e->flags = QLA_EVT_FLAG_FREE;
5155 	return e;
5156 }
5157 
5158 int
qla2x00_post_work(struct scsi_qla_host * vha,struct qla_work_evt * e)5159 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
5160 {
5161 	unsigned long flags;
5162 	bool q = false;
5163 
5164 	spin_lock_irqsave(&vha->work_lock, flags);
5165 	list_add_tail(&e->list, &vha->work_list);
5166 
5167 	if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
5168 		q = true;
5169 
5170 	spin_unlock_irqrestore(&vha->work_lock, flags);
5171 
5172 	if (q)
5173 		queue_work(vha->hw->wq, &vha->iocb_work);
5174 
5175 	return QLA_SUCCESS;
5176 }
5177 
5178 int
qla2x00_post_aen_work(struct scsi_qla_host * vha,enum fc_host_event_code code,u32 data)5179 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
5180     u32 data)
5181 {
5182 	struct qla_work_evt *e;
5183 
5184 	e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
5185 	if (!e)
5186 		return QLA_FUNCTION_FAILED;
5187 
5188 	e->u.aen.code = code;
5189 	e->u.aen.data = data;
5190 	return qla2x00_post_work(vha, e);
5191 }
5192 
5193 int
qla2x00_post_idc_ack_work(struct scsi_qla_host * vha,uint16_t * mb)5194 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
5195 {
5196 	struct qla_work_evt *e;
5197 
5198 	e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
5199 	if (!e)
5200 		return QLA_FUNCTION_FAILED;
5201 
5202 	memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
5203 	return qla2x00_post_work(vha, e);
5204 }
5205 
5206 #define qla2x00_post_async_work(name, type)	\
5207 int qla2x00_post_async_##name##_work(		\
5208     struct scsi_qla_host *vha,			\
5209     fc_port_t *fcport, uint16_t *data)		\
5210 {						\
5211 	struct qla_work_evt *e;			\
5212 						\
5213 	e = qla2x00_alloc_work(vha, type);	\
5214 	if (!e)					\
5215 		return QLA_FUNCTION_FAILED;	\
5216 						\
5217 	e->u.logio.fcport = fcport;		\
5218 	if (data) {				\
5219 		e->u.logio.data[0] = data[0];	\
5220 		e->u.logio.data[1] = data[1];	\
5221 	}					\
5222 	fcport->flags |= FCF_ASYNC_ACTIVE;	\
5223 	return qla2x00_post_work(vha, e);	\
5224 }
5225 
5226 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
5227 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
5228 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
5229 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
5230 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
5231 
5232 int
qla2x00_post_uevent_work(struct scsi_qla_host * vha,u32 code)5233 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
5234 {
5235 	struct qla_work_evt *e;
5236 
5237 	e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
5238 	if (!e)
5239 		return QLA_FUNCTION_FAILED;
5240 
5241 	e->u.uevent.code = code;
5242 	return qla2x00_post_work(vha, e);
5243 }
5244 
5245 static void
qla2x00_uevent_emit(struct scsi_qla_host * vha,u32 code)5246 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
5247 {
5248 	char event_string[40];
5249 	char *envp[] = { event_string, NULL };
5250 
5251 	switch (code) {
5252 	case QLA_UEVENT_CODE_FW_DUMP:
5253 		snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu",
5254 		    vha->host_no);
5255 		break;
5256 	default:
5257 		/* do nothing */
5258 		break;
5259 	}
5260 	kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5261 }
5262 
5263 int
qlafx00_post_aenfx_work(struct scsi_qla_host * vha,uint32_t evtcode,uint32_t * data,int cnt)5264 qlafx00_post_aenfx_work(struct scsi_qla_host *vha,  uint32_t evtcode,
5265 			uint32_t *data, int cnt)
5266 {
5267 	struct qla_work_evt *e;
5268 
5269 	e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5270 	if (!e)
5271 		return QLA_FUNCTION_FAILED;
5272 
5273 	e->u.aenfx.evtcode = evtcode;
5274 	e->u.aenfx.count = cnt;
5275 	memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5276 	return qla2x00_post_work(vha, e);
5277 }
5278 
qla24xx_sched_upd_fcport(fc_port_t * fcport)5279 void qla24xx_sched_upd_fcport(fc_port_t *fcport)
5280 {
5281 	unsigned long flags;
5282 
5283 	if (IS_SW_RESV_ADDR(fcport->d_id))
5284 		return;
5285 
5286 	spin_lock_irqsave(&fcport->vha->work_lock, flags);
5287 	if (fcport->disc_state == DSC_UPD_FCPORT) {
5288 		spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5289 		return;
5290 	}
5291 	fcport->jiffies_at_registration = jiffies;
5292 	fcport->sec_since_registration = 0;
5293 	fcport->next_disc_state = DSC_DELETED;
5294 	qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5295 	spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5296 
5297 	queue_work(system_unbound_wq, &fcport->reg_work);
5298 }
5299 
5300 static
qla24xx_create_new_sess(struct scsi_qla_host * vha,struct qla_work_evt * e)5301 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5302 {
5303 	unsigned long flags;
5304 	fc_port_t *fcport =  NULL, *tfcp;
5305 	struct qlt_plogi_ack_t *pla =
5306 	    (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5307 	uint8_t free_fcport = 0;
5308 
5309 	ql_dbg(ql_dbg_disc, vha, 0xffff,
5310 	    "%s %d %8phC enter\n",
5311 	    __func__, __LINE__, e->u.new_sess.port_name);
5312 
5313 	spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5314 	fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5315 	if (fcport) {
5316 		fcport->d_id = e->u.new_sess.id;
5317 		if (pla) {
5318 			fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5319 			memcpy(fcport->node_name,
5320 			    pla->iocb.u.isp24.u.plogi.node_name,
5321 			    WWN_SIZE);
5322 			qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5323 			/* we took an extra ref_count to prevent PLOGI ACK when
5324 			 * fcport/sess has not been created.
5325 			 */
5326 			pla->ref_count--;
5327 		}
5328 	} else {
5329 		spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5330 		fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5331 		if (fcport) {
5332 			fcport->d_id = e->u.new_sess.id;
5333 			fcport->flags |= FCF_FABRIC_DEVICE;
5334 			fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5335 			fcport->tgt_short_link_down_cnt = 0;
5336 
5337 			memcpy(fcport->port_name, e->u.new_sess.port_name,
5338 			    WWN_SIZE);
5339 
5340 			fcport->fc4_type = e->u.new_sess.fc4_type;
5341 			if (NVME_PRIORITY(vha->hw, fcport))
5342 				fcport->do_prli_nvme = 1;
5343 			else
5344 				fcport->do_prli_nvme = 0;
5345 
5346 			if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5347 				fcport->dm_login_expire = jiffies +
5348 					QLA_N2N_WAIT_TIME * HZ;
5349 				fcport->fc4_type = FS_FC4TYPE_FCP;
5350 				fcport->n2n_flag = 1;
5351 				if (vha->flags.nvme_enabled)
5352 					fcport->fc4_type |= FS_FC4TYPE_NVME;
5353 			}
5354 
5355 		} else {
5356 			ql_dbg(ql_dbg_disc, vha, 0xffff,
5357 				   "%s %8phC mem alloc fail.\n",
5358 				   __func__, e->u.new_sess.port_name);
5359 
5360 			if (pla) {
5361 				list_del(&pla->list);
5362 				kmem_cache_free(qla_tgt_plogi_cachep, pla);
5363 			}
5364 			return;
5365 		}
5366 
5367 		spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5368 		/* search again to make sure no one else got ahead */
5369 		tfcp = qla2x00_find_fcport_by_wwpn(vha,
5370 		    e->u.new_sess.port_name, 1);
5371 		if (tfcp) {
5372 			/* should rarily happen */
5373 			ql_dbg(ql_dbg_disc, vha, 0xffff,
5374 			    "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5375 			    __func__, tfcp->port_name, tfcp->disc_state,
5376 			    tfcp->fw_login_state);
5377 
5378 			free_fcport = 1;
5379 		} else {
5380 			list_add_tail(&fcport->list, &vha->vp_fcports);
5381 
5382 		}
5383 		if (pla) {
5384 			qlt_plogi_ack_link(vha, pla, fcport,
5385 			    QLT_PLOGI_LINK_SAME_WWN);
5386 			pla->ref_count--;
5387 		}
5388 	}
5389 	spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5390 
5391 	if (fcport) {
5392 		fcport->id_changed = 1;
5393 		fcport->scan_state = QLA_FCPORT_FOUND;
5394 		fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5395 		memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5396 
5397 		if (pla) {
5398 			if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5399 				u16 wd3_lo;
5400 
5401 				fcport->fw_login_state = DSC_LS_PRLI_PEND;
5402 				fcport->local = 0;
5403 				fcport->loop_id =
5404 					le16_to_cpu(
5405 					    pla->iocb.u.isp24.nport_handle);
5406 				fcport->fw_login_state = DSC_LS_PRLI_PEND;
5407 				wd3_lo =
5408 				    le16_to_cpu(
5409 					pla->iocb.u.isp24.u.prli.wd3_lo);
5410 
5411 				if (wd3_lo & BIT_7)
5412 					fcport->conf_compl_supported = 1;
5413 
5414 				if ((wd3_lo & BIT_4) == 0)
5415 					fcport->port_type = FCT_INITIATOR;
5416 				else
5417 					fcport->port_type = FCT_TARGET;
5418 			}
5419 			qlt_plogi_ack_unref(vha, pla);
5420 		} else {
5421 			fc_port_t *dfcp = NULL;
5422 
5423 			spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5424 			tfcp = qla2x00_find_fcport_by_nportid(vha,
5425 			    &e->u.new_sess.id, 1);
5426 			if (tfcp && (tfcp != fcport)) {
5427 				/*
5428 				 * We have a conflict fcport with same NportID.
5429 				 */
5430 				ql_dbg(ql_dbg_disc, vha, 0xffff,
5431 				    "%s %8phC found conflict b4 add. DS %d LS %d\n",
5432 				    __func__, tfcp->port_name, tfcp->disc_state,
5433 				    tfcp->fw_login_state);
5434 
5435 				switch (tfcp->disc_state) {
5436 				case DSC_DELETED:
5437 					break;
5438 				case DSC_DELETE_PEND:
5439 					fcport->login_pause = 1;
5440 					tfcp->conflict = fcport;
5441 					break;
5442 				default:
5443 					fcport->login_pause = 1;
5444 					tfcp->conflict = fcport;
5445 					dfcp = tfcp;
5446 					break;
5447 				}
5448 			}
5449 			spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5450 			if (dfcp)
5451 				qlt_schedule_sess_for_deletion(tfcp);
5452 
5453 			if (N2N_TOPO(vha->hw)) {
5454 				fcport->flags &= ~FCF_FABRIC_DEVICE;
5455 				fcport->keep_nport_handle = 1;
5456 				if (vha->flags.nvme_enabled) {
5457 					fcport->fc4_type =
5458 					    (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
5459 					fcport->n2n_flag = 1;
5460 				}
5461 				fcport->fw_login_state = 0;
5462 
5463 				schedule_delayed_work(&vha->scan.scan_work, 5);
5464 			} else {
5465 				qla24xx_fcport_handle_login(vha, fcport);
5466 			}
5467 		}
5468 	}
5469 
5470 	if (free_fcport) {
5471 		qla2x00_free_fcport(fcport);
5472 		if (pla) {
5473 			list_del(&pla->list);
5474 			kmem_cache_free(qla_tgt_plogi_cachep, pla);
5475 		}
5476 	}
5477 }
5478 
qla_sp_retry(struct scsi_qla_host * vha,struct qla_work_evt * e)5479 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5480 {
5481 	struct srb *sp = e->u.iosb.sp;
5482 	int rval;
5483 
5484 	rval = qla2x00_start_sp(sp);
5485 	if (rval != QLA_SUCCESS) {
5486 		ql_dbg(ql_dbg_disc, vha, 0x2043,
5487 		    "%s: %s: Re-issue IOCB failed (%d).\n",
5488 		    __func__, sp->name, rval);
5489 		qla24xx_sp_unmap(vha, sp);
5490 	}
5491 }
5492 
5493 void
qla2x00_do_work(struct scsi_qla_host * vha)5494 qla2x00_do_work(struct scsi_qla_host *vha)
5495 {
5496 	struct qla_work_evt *e, *tmp;
5497 	unsigned long flags;
5498 	LIST_HEAD(work);
5499 	int rc;
5500 
5501 	spin_lock_irqsave(&vha->work_lock, flags);
5502 	list_splice_init(&vha->work_list, &work);
5503 	spin_unlock_irqrestore(&vha->work_lock, flags);
5504 
5505 	list_for_each_entry_safe(e, tmp, &work, list) {
5506 		rc = QLA_SUCCESS;
5507 		switch (e->type) {
5508 		case QLA_EVT_AEN:
5509 			fc_host_post_event(vha->host, fc_get_event_number(),
5510 			    e->u.aen.code, e->u.aen.data);
5511 			break;
5512 		case QLA_EVT_IDC_ACK:
5513 			qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5514 			break;
5515 		case QLA_EVT_ASYNC_LOGIN:
5516 			qla2x00_async_login(vha, e->u.logio.fcport,
5517 			    e->u.logio.data);
5518 			break;
5519 		case QLA_EVT_ASYNC_LOGOUT:
5520 			rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5521 			break;
5522 		case QLA_EVT_ASYNC_ADISC:
5523 			qla2x00_async_adisc(vha, e->u.logio.fcport,
5524 			    e->u.logio.data);
5525 			break;
5526 		case QLA_EVT_UEVENT:
5527 			qla2x00_uevent_emit(vha, e->u.uevent.code);
5528 			break;
5529 		case QLA_EVT_AENFX:
5530 			qlafx00_process_aen(vha, e);
5531 			break;
5532 		case QLA_EVT_UNMAP:
5533 			qla24xx_sp_unmap(vha, e->u.iosb.sp);
5534 			break;
5535 		case QLA_EVT_RELOGIN:
5536 			qla2x00_relogin(vha);
5537 			break;
5538 		case QLA_EVT_NEW_SESS:
5539 			qla24xx_create_new_sess(vha, e);
5540 			break;
5541 		case QLA_EVT_GPDB:
5542 			qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5543 			    e->u.fcport.opt);
5544 			break;
5545 		case QLA_EVT_PRLI:
5546 			qla24xx_async_prli(vha, e->u.fcport.fcport);
5547 			break;
5548 		case QLA_EVT_GPSC:
5549 			qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5550 			break;
5551 		case QLA_EVT_GNL:
5552 			qla24xx_async_gnl(vha, e->u.fcport.fcport);
5553 			break;
5554 		case QLA_EVT_NACK:
5555 			qla24xx_do_nack_work(vha, e);
5556 			break;
5557 		case QLA_EVT_ASYNC_PRLO:
5558 			rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5559 			break;
5560 		case QLA_EVT_ASYNC_PRLO_DONE:
5561 			qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5562 			    e->u.logio.data);
5563 			break;
5564 		case QLA_EVT_GPNFT:
5565 			qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5566 			    e->u.gpnft.sp);
5567 			break;
5568 		case QLA_EVT_GPNFT_DONE:
5569 			qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5570 			break;
5571 		case QLA_EVT_GNNFT_DONE:
5572 			qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5573 			break;
5574 		case QLA_EVT_GFPNID:
5575 			qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5576 			break;
5577 		case QLA_EVT_SP_RETRY:
5578 			qla_sp_retry(vha, e);
5579 			break;
5580 		case QLA_EVT_IIDMA:
5581 			qla_do_iidma_work(vha, e->u.fcport.fcport);
5582 			break;
5583 		case QLA_EVT_ELS_PLOGI:
5584 			qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5585 			    e->u.fcport.fcport, false);
5586 			break;
5587 		case QLA_EVT_SA_REPLACE:
5588 			rc = qla24xx_issue_sa_replace_iocb(vha, e);
5589 			break;
5590 		}
5591 
5592 		if (rc == EAGAIN) {
5593 			/* put 'work' at head of 'vha->work_list' */
5594 			spin_lock_irqsave(&vha->work_lock, flags);
5595 			list_splice(&work, &vha->work_list);
5596 			spin_unlock_irqrestore(&vha->work_lock, flags);
5597 			break;
5598 		}
5599 		list_del_init(&e->list);
5600 		if (e->flags & QLA_EVT_FLAG_FREE)
5601 			kfree(e);
5602 
5603 		/* For each work completed decrement vha ref count */
5604 		QLA_VHA_MARK_NOT_BUSY(vha);
5605 	}
5606 }
5607 
qla24xx_post_relogin_work(struct scsi_qla_host * vha)5608 int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5609 {
5610 	struct qla_work_evt *e;
5611 
5612 	e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5613 
5614 	if (!e) {
5615 		set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5616 		return QLA_FUNCTION_FAILED;
5617 	}
5618 
5619 	return qla2x00_post_work(vha, e);
5620 }
5621 
5622 /* Relogins all the fcports of a vport
5623  * Context: dpc thread
5624  */
qla2x00_relogin(struct scsi_qla_host * vha)5625 void qla2x00_relogin(struct scsi_qla_host *vha)
5626 {
5627 	fc_port_t       *fcport;
5628 	int status, relogin_needed = 0;
5629 	struct event_arg ea;
5630 
5631 	list_for_each_entry(fcport, &vha->vp_fcports, list) {
5632 		/*
5633 		 * If the port is not ONLINE then try to login
5634 		 * to it if we haven't run out of retries.
5635 		 */
5636 		if (atomic_read(&fcport->state) != FCS_ONLINE &&
5637 		    fcport->login_retry) {
5638 			if (fcport->scan_state != QLA_FCPORT_FOUND ||
5639 			    fcport->disc_state == DSC_LOGIN_AUTH_PEND ||
5640 			    fcport->disc_state == DSC_LOGIN_COMPLETE)
5641 				continue;
5642 
5643 			if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5644 				fcport->disc_state == DSC_DELETE_PEND) {
5645 				relogin_needed = 1;
5646 			} else {
5647 				if (vha->hw->current_topology != ISP_CFG_NL) {
5648 					memset(&ea, 0, sizeof(ea));
5649 					ea.fcport = fcport;
5650 					qla24xx_handle_relogin_event(vha, &ea);
5651 				} else if (vha->hw->current_topology ==
5652 					 ISP_CFG_NL &&
5653 					IS_QLA2XXX_MIDTYPE(vha->hw)) {
5654 					(void)qla24xx_fcport_handle_login(vha,
5655 									fcport);
5656 				} else if (vha->hw->current_topology ==
5657 				    ISP_CFG_NL) {
5658 					fcport->login_retry--;
5659 					status =
5660 					    qla2x00_local_device_login(vha,
5661 						fcport);
5662 					if (status == QLA_SUCCESS) {
5663 						fcport->old_loop_id =
5664 						    fcport->loop_id;
5665 						ql_dbg(ql_dbg_disc, vha, 0x2003,
5666 						    "Port login OK: logged in ID 0x%x.\n",
5667 						    fcport->loop_id);
5668 						qla2x00_update_fcport
5669 							(vha, fcport);
5670 					} else if (status == 1) {
5671 						set_bit(RELOGIN_NEEDED,
5672 						    &vha->dpc_flags);
5673 						/* retry the login again */
5674 						ql_dbg(ql_dbg_disc, vha, 0x2007,
5675 						    "Retrying %d login again loop_id 0x%x.\n",
5676 						    fcport->login_retry,
5677 						    fcport->loop_id);
5678 					} else {
5679 						fcport->login_retry = 0;
5680 					}
5681 
5682 					if (fcport->login_retry == 0 &&
5683 					    status != QLA_SUCCESS)
5684 						qla2x00_clear_loop_id(fcport);
5685 				}
5686 			}
5687 		}
5688 		if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5689 			break;
5690 	}
5691 
5692 	if (relogin_needed)
5693 		set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5694 
5695 	ql_dbg(ql_dbg_disc, vha, 0x400e,
5696 	    "Relogin end.\n");
5697 }
5698 
5699 /* Schedule work on any of the dpc-workqueues */
5700 void
qla83xx_schedule_work(scsi_qla_host_t * base_vha,int work_code)5701 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5702 {
5703 	struct qla_hw_data *ha = base_vha->hw;
5704 
5705 	switch (work_code) {
5706 	case MBA_IDC_AEN: /* 0x8200 */
5707 		if (ha->dpc_lp_wq)
5708 			queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5709 		break;
5710 
5711 	case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5712 		if (!ha->flags.nic_core_reset_hdlr_active) {
5713 			if (ha->dpc_hp_wq)
5714 				queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5715 		} else
5716 			ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5717 			    "NIC Core reset is already active. Skip "
5718 			    "scheduling it again.\n");
5719 		break;
5720 	case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5721 		if (ha->dpc_hp_wq)
5722 			queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5723 		break;
5724 	case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5725 		if (ha->dpc_hp_wq)
5726 			queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5727 		break;
5728 	default:
5729 		ql_log(ql_log_warn, base_vha, 0xb05f,
5730 		    "Unknown work-code=0x%x.\n", work_code);
5731 	}
5732 
5733 	return;
5734 }
5735 
5736 /* Work: Perform NIC Core Unrecoverable state handling */
5737 void
qla83xx_nic_core_unrecoverable_work(struct work_struct * work)5738 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5739 {
5740 	struct qla_hw_data *ha =
5741 		container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5742 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5743 	uint32_t dev_state = 0;
5744 
5745 	qla83xx_idc_lock(base_vha, 0);
5746 	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5747 	qla83xx_reset_ownership(base_vha);
5748 	if (ha->flags.nic_core_reset_owner) {
5749 		ha->flags.nic_core_reset_owner = 0;
5750 		qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5751 		    QLA8XXX_DEV_FAILED);
5752 		ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5753 		qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5754 	}
5755 	qla83xx_idc_unlock(base_vha, 0);
5756 }
5757 
5758 /* Work: Execute IDC state handler */
5759 void
qla83xx_idc_state_handler_work(struct work_struct * work)5760 qla83xx_idc_state_handler_work(struct work_struct *work)
5761 {
5762 	struct qla_hw_data *ha =
5763 		container_of(work, struct qla_hw_data, idc_state_handler);
5764 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5765 	uint32_t dev_state = 0;
5766 
5767 	qla83xx_idc_lock(base_vha, 0);
5768 	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5769 	if (dev_state == QLA8XXX_DEV_FAILED ||
5770 			dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5771 		qla83xx_idc_state_handler(base_vha);
5772 	qla83xx_idc_unlock(base_vha, 0);
5773 }
5774 
5775 static int
qla83xx_check_nic_core_fw_alive(scsi_qla_host_t * base_vha)5776 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5777 {
5778 	int rval = QLA_SUCCESS;
5779 	unsigned long heart_beat_wait = jiffies + (1 * HZ);
5780 	uint32_t heart_beat_counter1, heart_beat_counter2;
5781 
5782 	do {
5783 		if (time_after(jiffies, heart_beat_wait)) {
5784 			ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5785 			    "Nic Core f/w is not alive.\n");
5786 			rval = QLA_FUNCTION_FAILED;
5787 			break;
5788 		}
5789 
5790 		qla83xx_idc_lock(base_vha, 0);
5791 		qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5792 		    &heart_beat_counter1);
5793 		qla83xx_idc_unlock(base_vha, 0);
5794 		msleep(100);
5795 		qla83xx_idc_lock(base_vha, 0);
5796 		qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5797 		    &heart_beat_counter2);
5798 		qla83xx_idc_unlock(base_vha, 0);
5799 	} while (heart_beat_counter1 == heart_beat_counter2);
5800 
5801 	return rval;
5802 }
5803 
5804 /* Work: Perform NIC Core Reset handling */
5805 void
qla83xx_nic_core_reset_work(struct work_struct * work)5806 qla83xx_nic_core_reset_work(struct work_struct *work)
5807 {
5808 	struct qla_hw_data *ha =
5809 		container_of(work, struct qla_hw_data, nic_core_reset);
5810 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5811 	uint32_t dev_state = 0;
5812 
5813 	if (IS_QLA2031(ha)) {
5814 		if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5815 			ql_log(ql_log_warn, base_vha, 0xb081,
5816 			    "Failed to dump mctp\n");
5817 		return;
5818 	}
5819 
5820 	if (!ha->flags.nic_core_reset_hdlr_active) {
5821 		if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5822 			qla83xx_idc_lock(base_vha, 0);
5823 			qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5824 			    &dev_state);
5825 			qla83xx_idc_unlock(base_vha, 0);
5826 			if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5827 				ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5828 				    "Nic Core f/w is alive.\n");
5829 				return;
5830 			}
5831 		}
5832 
5833 		ha->flags.nic_core_reset_hdlr_active = 1;
5834 		if (qla83xx_nic_core_reset(base_vha)) {
5835 			/* NIC Core reset failed. */
5836 			ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5837 			    "NIC Core reset failed.\n");
5838 		}
5839 		ha->flags.nic_core_reset_hdlr_active = 0;
5840 	}
5841 }
5842 
5843 /* Work: Handle 8200 IDC aens */
5844 void
qla83xx_service_idc_aen(struct work_struct * work)5845 qla83xx_service_idc_aen(struct work_struct *work)
5846 {
5847 	struct qla_hw_data *ha =
5848 		container_of(work, struct qla_hw_data, idc_aen);
5849 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5850 	uint32_t dev_state, idc_control;
5851 
5852 	qla83xx_idc_lock(base_vha, 0);
5853 	qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5854 	qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5855 	qla83xx_idc_unlock(base_vha, 0);
5856 	if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5857 		if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5858 			ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5859 			    "Application requested NIC Core Reset.\n");
5860 			qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5861 		} else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5862 		    QLA_SUCCESS) {
5863 			ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5864 			    "Other protocol driver requested NIC Core Reset.\n");
5865 			qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5866 		}
5867 	} else if (dev_state == QLA8XXX_DEV_FAILED ||
5868 			dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5869 		qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5870 	}
5871 }
5872 
5873 /*
5874  * Control the frequency of IDC lock retries
5875  */
5876 #define QLA83XX_WAIT_LOGIC_MS	100
5877 
5878 static int
qla83xx_force_lock_recovery(scsi_qla_host_t * base_vha)5879 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5880 {
5881 	int rval;
5882 	uint32_t data;
5883 	uint32_t idc_lck_rcvry_stage_mask = 0x3;
5884 	uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5885 	struct qla_hw_data *ha = base_vha->hw;
5886 
5887 	ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5888 	    "Trying force recovery of the IDC lock.\n");
5889 
5890 	rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5891 	if (rval)
5892 		return rval;
5893 
5894 	if ((data & idc_lck_rcvry_stage_mask) > 0) {
5895 		return QLA_SUCCESS;
5896 	} else {
5897 		data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5898 		rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5899 		    data);
5900 		if (rval)
5901 			return rval;
5902 
5903 		msleep(200);
5904 
5905 		rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5906 		    &data);
5907 		if (rval)
5908 			return rval;
5909 
5910 		if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5911 			data &= (IDC_LOCK_RECOVERY_STAGE2 |
5912 					~(idc_lck_rcvry_stage_mask));
5913 			rval = qla83xx_wr_reg(base_vha,
5914 			    QLA83XX_IDC_LOCK_RECOVERY, data);
5915 			if (rval)
5916 				return rval;
5917 
5918 			/* Forcefully perform IDC UnLock */
5919 			rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5920 			    &data);
5921 			if (rval)
5922 				return rval;
5923 			/* Clear lock-id by setting 0xff */
5924 			rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5925 			    0xff);
5926 			if (rval)
5927 				return rval;
5928 			/* Clear lock-recovery by setting 0x0 */
5929 			rval = qla83xx_wr_reg(base_vha,
5930 			    QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5931 			if (rval)
5932 				return rval;
5933 		} else
5934 			return QLA_SUCCESS;
5935 	}
5936 
5937 	return rval;
5938 }
5939 
5940 static int
qla83xx_idc_lock_recovery(scsi_qla_host_t * base_vha)5941 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5942 {
5943 	int rval = QLA_SUCCESS;
5944 	uint32_t o_drv_lockid, n_drv_lockid;
5945 	unsigned long lock_recovery_timeout;
5946 
5947 	lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5948 retry_lockid:
5949 	rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5950 	if (rval)
5951 		goto exit;
5952 
5953 	/* MAX wait time before forcing IDC Lock recovery = 2 secs */
5954 	if (time_after_eq(jiffies, lock_recovery_timeout)) {
5955 		if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5956 			return QLA_SUCCESS;
5957 		else
5958 			return QLA_FUNCTION_FAILED;
5959 	}
5960 
5961 	rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5962 	if (rval)
5963 		goto exit;
5964 
5965 	if (o_drv_lockid == n_drv_lockid) {
5966 		msleep(QLA83XX_WAIT_LOGIC_MS);
5967 		goto retry_lockid;
5968 	} else
5969 		return QLA_SUCCESS;
5970 
5971 exit:
5972 	return rval;
5973 }
5974 
5975 /*
5976  * Context: task, can sleep
5977  */
5978 void
qla83xx_idc_lock(scsi_qla_host_t * base_vha,uint16_t requester_id)5979 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5980 {
5981 	uint32_t data;
5982 	uint32_t lock_owner;
5983 	struct qla_hw_data *ha = base_vha->hw;
5984 
5985 	might_sleep();
5986 
5987 	/* IDC-lock implementation using driver-lock/lock-id remote registers */
5988 retry_lock:
5989 	if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5990 	    == QLA_SUCCESS) {
5991 		if (data) {
5992 			/* Setting lock-id to our function-number */
5993 			qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5994 			    ha->portnum);
5995 		} else {
5996 			qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5997 			    &lock_owner);
5998 			ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5999 			    "Failed to acquire IDC lock, acquired by %d, "
6000 			    "retrying...\n", lock_owner);
6001 
6002 			/* Retry/Perform IDC-Lock recovery */
6003 			if (qla83xx_idc_lock_recovery(base_vha)
6004 			    == QLA_SUCCESS) {
6005 				msleep(QLA83XX_WAIT_LOGIC_MS);
6006 				goto retry_lock;
6007 			} else
6008 				ql_log(ql_log_warn, base_vha, 0xb075,
6009 				    "IDC Lock recovery FAILED.\n");
6010 		}
6011 
6012 	}
6013 
6014 	return;
6015 }
6016 
6017 static bool
qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host * vha,struct purex_entry_24xx * purex)6018 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha,
6019 	struct purex_entry_24xx *purex)
6020 {
6021 	char fwstr[16];
6022 	u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
6023 	struct port_database_24xx *pdb;
6024 
6025 	/* Domain Controller is always logged-out. */
6026 	/* if RDP request is not from Domain Controller: */
6027 	if (sid != 0xfffc01)
6028 		return false;
6029 
6030 	ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);
6031 
6032 	pdb = kzalloc(sizeof(*pdb), GFP_KERNEL);
6033 	if (!pdb) {
6034 		ql_dbg(ql_dbg_init, vha, 0x0181,
6035 		    "%s: Failed allocate pdb\n", __func__);
6036 	} else if (qla24xx_get_port_database(vha,
6037 				le16_to_cpu(purex->nport_handle), pdb)) {
6038 		ql_dbg(ql_dbg_init, vha, 0x0181,
6039 		    "%s: Failed get pdb sid=%x\n", __func__, sid);
6040 	} else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
6041 	    pdb->current_login_state != PDS_PRLI_COMPLETE) {
6042 		ql_dbg(ql_dbg_init, vha, 0x0181,
6043 		    "%s: Port not logged in sid=%#x\n", __func__, sid);
6044 	} else {
6045 		/* RDP request is from logged in port */
6046 		kfree(pdb);
6047 		return false;
6048 	}
6049 	kfree(pdb);
6050 
6051 	vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
6052 	fwstr[strcspn(fwstr, " ")] = 0;
6053 	/* if FW version allows RDP response length upto 2048 bytes: */
6054 	if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
6055 		return false;
6056 
6057 	ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);
6058 
6059 	/* RDP response length is to be reduced to maximum 256 bytes */
6060 	return true;
6061 }
6062 
6063 /*
6064  * Function Name: qla24xx_process_purex_iocb
6065  *
6066  * Description:
6067  * Prepare a RDP response and send to Fabric switch
6068  *
6069  * PARAMETERS:
6070  * vha:	SCSI qla host
6071  * purex: RDP request received by HBA
6072  */
qla24xx_process_purex_rdp(struct scsi_qla_host * vha,struct purex_item * item)6073 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
6074 			       struct purex_item *item)
6075 {
6076 	struct qla_hw_data *ha = vha->hw;
6077 	struct purex_entry_24xx *purex =
6078 	    (struct purex_entry_24xx *)&item->iocb;
6079 	dma_addr_t rsp_els_dma;
6080 	dma_addr_t rsp_payload_dma;
6081 	dma_addr_t stat_dma;
6082 	dma_addr_t sfp_dma;
6083 	struct els_entry_24xx *rsp_els = NULL;
6084 	struct rdp_rsp_payload *rsp_payload = NULL;
6085 	struct link_statistics *stat = NULL;
6086 	uint8_t *sfp = NULL;
6087 	uint16_t sfp_flags = 0;
6088 	uint rsp_payload_length = sizeof(*rsp_payload);
6089 	int rval;
6090 
6091 	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
6092 	    "%s: Enter\n", __func__);
6093 
6094 	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
6095 	    "-------- ELS REQ -------\n");
6096 	ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
6097 	    purex, sizeof(*purex));
6098 
6099 	if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
6100 		rsp_payload_length =
6101 		    offsetof(typeof(*rsp_payload), optical_elmt_desc);
6102 		ql_dbg(ql_dbg_init, vha, 0x0181,
6103 		    "Reducing RSP payload length to %u bytes...\n",
6104 		    rsp_payload_length);
6105 	}
6106 
6107 	rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6108 	    &rsp_els_dma, GFP_KERNEL);
6109 	if (!rsp_els) {
6110 		ql_log(ql_log_warn, vha, 0x0183,
6111 		    "Failed allocate dma buffer ELS RSP.\n");
6112 		goto dealloc;
6113 	}
6114 
6115 	rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6116 	    &rsp_payload_dma, GFP_KERNEL);
6117 	if (!rsp_payload) {
6118 		ql_log(ql_log_warn, vha, 0x0184,
6119 		    "Failed allocate dma buffer ELS RSP payload.\n");
6120 		goto dealloc;
6121 	}
6122 
6123 	sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6124 	    &sfp_dma, GFP_KERNEL);
6125 
6126 	stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
6127 	    &stat_dma, GFP_KERNEL);
6128 
6129 	/* Prepare Response IOCB */
6130 	rsp_els->entry_type = ELS_IOCB_TYPE;
6131 	rsp_els->entry_count = 1;
6132 	rsp_els->sys_define = 0;
6133 	rsp_els->entry_status = 0;
6134 	rsp_els->handle = 0;
6135 	rsp_els->nport_handle = purex->nport_handle;
6136 	rsp_els->tx_dsd_count = cpu_to_le16(1);
6137 	rsp_els->vp_index = purex->vp_idx;
6138 	rsp_els->sof_type = EST_SOFI3;
6139 	rsp_els->rx_xchg_address = purex->rx_xchg_addr;
6140 	rsp_els->rx_dsd_count = 0;
6141 	rsp_els->opcode = purex->els_frame_payload[0];
6142 
6143 	rsp_els->d_id[0] = purex->s_id[0];
6144 	rsp_els->d_id[1] = purex->s_id[1];
6145 	rsp_els->d_id[2] = purex->s_id[2];
6146 
6147 	rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
6148 	rsp_els->rx_byte_count = 0;
6149 	rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
6150 
6151 	put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
6152 	rsp_els->tx_len = rsp_els->tx_byte_count;
6153 
6154 	rsp_els->rx_address = 0;
6155 	rsp_els->rx_len = 0;
6156 
6157 	/* Prepare Response Payload */
6158 	rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
6159 	rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
6160 					   sizeof(rsp_payload->hdr));
6161 
6162 	/* Link service Request Info Descriptor */
6163 	rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
6164 	rsp_payload->ls_req_info_desc.desc_len =
6165 	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
6166 	rsp_payload->ls_req_info_desc.req_payload_word_0 =
6167 	    cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6168 
6169 	/* Link service Request Info Descriptor 2 */
6170 	rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
6171 	rsp_payload->ls_req_info_desc2.desc_len =
6172 	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
6173 	rsp_payload->ls_req_info_desc2.req_payload_word_0 =
6174 	    cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6175 
6176 
6177 	rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
6178 	rsp_payload->sfp_diag_desc.desc_len =
6179 		cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
6180 
6181 	if (sfp) {
6182 		/* SFP Flags */
6183 		memset(sfp, 0, SFP_RTDI_LEN);
6184 		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
6185 		if (!rval) {
6186 			/* SFP Flags bits 3-0: Port Tx Laser Type */
6187 			if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
6188 				sfp_flags |= BIT_0; /* short wave */
6189 			else if (sfp[0] & BIT_1)
6190 				sfp_flags |= BIT_1; /* long wave 1310nm */
6191 			else if (sfp[1] & BIT_4)
6192 				sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
6193 		}
6194 
6195 		/* SFP Type */
6196 		memset(sfp, 0, SFP_RTDI_LEN);
6197 		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
6198 		if (!rval) {
6199 			sfp_flags |= BIT_4; /* optical */
6200 			if (sfp[0] == 0x3)
6201 				sfp_flags |= BIT_6; /* sfp+ */
6202 		}
6203 
6204 		rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
6205 
6206 		/* SFP Diagnostics */
6207 		memset(sfp, 0, SFP_RTDI_LEN);
6208 		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
6209 		if (!rval) {
6210 			__be16 *trx = (__force __be16 *)sfp; /* already be16 */
6211 			rsp_payload->sfp_diag_desc.temperature = trx[0];
6212 			rsp_payload->sfp_diag_desc.vcc = trx[1];
6213 			rsp_payload->sfp_diag_desc.tx_bias = trx[2];
6214 			rsp_payload->sfp_diag_desc.tx_power = trx[3];
6215 			rsp_payload->sfp_diag_desc.rx_power = trx[4];
6216 		}
6217 	}
6218 
6219 	/* Port Speed Descriptor */
6220 	rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
6221 	rsp_payload->port_speed_desc.desc_len =
6222 	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
6223 	rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
6224 	    qla25xx_fdmi_port_speed_capability(ha));
6225 	rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
6226 	    qla25xx_fdmi_port_speed_currently(ha));
6227 
6228 	/* Link Error Status Descriptor */
6229 	rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
6230 	rsp_payload->ls_err_desc.desc_len =
6231 		cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
6232 
6233 	if (stat) {
6234 		rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
6235 		if (!rval) {
6236 			rsp_payload->ls_err_desc.link_fail_cnt =
6237 			    cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
6238 			rsp_payload->ls_err_desc.loss_sync_cnt =
6239 			    cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
6240 			rsp_payload->ls_err_desc.loss_sig_cnt =
6241 			    cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
6242 			rsp_payload->ls_err_desc.prim_seq_err_cnt =
6243 			    cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
6244 			rsp_payload->ls_err_desc.inval_xmit_word_cnt =
6245 			    cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
6246 			rsp_payload->ls_err_desc.inval_crc_cnt =
6247 			    cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
6248 			rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6249 		}
6250 	}
6251 
6252 	/* Portname Descriptor */
6253 	rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6254 	rsp_payload->port_name_diag_desc.desc_len =
6255 	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6256 	memcpy(rsp_payload->port_name_diag_desc.WWNN,
6257 	    vha->node_name,
6258 	    sizeof(rsp_payload->port_name_diag_desc.WWNN));
6259 	memcpy(rsp_payload->port_name_diag_desc.WWPN,
6260 	    vha->port_name,
6261 	    sizeof(rsp_payload->port_name_diag_desc.WWPN));
6262 
6263 	/* F-Port Portname Descriptor */
6264 	rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6265 	rsp_payload->port_name_direct_desc.desc_len =
6266 	    cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6267 	memcpy(rsp_payload->port_name_direct_desc.WWNN,
6268 	    vha->fabric_node_name,
6269 	    sizeof(rsp_payload->port_name_direct_desc.WWNN));
6270 	memcpy(rsp_payload->port_name_direct_desc.WWPN,
6271 	    vha->fabric_port_name,
6272 	    sizeof(rsp_payload->port_name_direct_desc.WWPN));
6273 
6274 	/* Bufer Credit Descriptor */
6275 	rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6276 	rsp_payload->buffer_credit_desc.desc_len =
6277 		cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6278 	rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6279 	rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6280 	rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6281 
6282 	if (ha->flags.plogi_template_valid) {
6283 		uint32_t tmp =
6284 		be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred);
6285 		rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp);
6286 	}
6287 
6288 	if (rsp_payload_length < sizeof(*rsp_payload))
6289 		goto send;
6290 
6291 	/* Optical Element Descriptor, Temperature */
6292 	rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6293 	rsp_payload->optical_elmt_desc[0].desc_len =
6294 		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6295 	/* Optical Element Descriptor, Voltage */
6296 	rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6297 	rsp_payload->optical_elmt_desc[1].desc_len =
6298 		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6299 	/* Optical Element Descriptor, Tx Bias Current */
6300 	rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6301 	rsp_payload->optical_elmt_desc[2].desc_len =
6302 		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6303 	/* Optical Element Descriptor, Tx Power */
6304 	rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6305 	rsp_payload->optical_elmt_desc[3].desc_len =
6306 		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6307 	/* Optical Element Descriptor, Rx Power */
6308 	rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6309 	rsp_payload->optical_elmt_desc[4].desc_len =
6310 		cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6311 
6312 	if (sfp) {
6313 		memset(sfp, 0, SFP_RTDI_LEN);
6314 		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
6315 		if (!rval) {
6316 			__be16 *trx = (__force __be16 *)sfp; /* already be16 */
6317 
6318 			/* Optical Element Descriptor, Temperature */
6319 			rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6320 			rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6321 			rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6322 			rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6323 			rsp_payload->optical_elmt_desc[0].element_flags =
6324 			    cpu_to_be32(1 << 28);
6325 
6326 			/* Optical Element Descriptor, Voltage */
6327 			rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6328 			rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6329 			rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6330 			rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6331 			rsp_payload->optical_elmt_desc[1].element_flags =
6332 			    cpu_to_be32(2 << 28);
6333 
6334 			/* Optical Element Descriptor, Tx Bias Current */
6335 			rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6336 			rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6337 			rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6338 			rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6339 			rsp_payload->optical_elmt_desc[2].element_flags =
6340 			    cpu_to_be32(3 << 28);
6341 
6342 			/* Optical Element Descriptor, Tx Power */
6343 			rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6344 			rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6345 			rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6346 			rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6347 			rsp_payload->optical_elmt_desc[3].element_flags =
6348 			    cpu_to_be32(4 << 28);
6349 
6350 			/* Optical Element Descriptor, Rx Power */
6351 			rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6352 			rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6353 			rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6354 			rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6355 			rsp_payload->optical_elmt_desc[4].element_flags =
6356 			    cpu_to_be32(5 << 28);
6357 		}
6358 
6359 		memset(sfp, 0, SFP_RTDI_LEN);
6360 		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
6361 		if (!rval) {
6362 			/* Temperature high/low alarm/warning */
6363 			rsp_payload->optical_elmt_desc[0].element_flags |=
6364 			    cpu_to_be32(
6365 				(sfp[0] >> 7 & 1) << 3 |
6366 				(sfp[0] >> 6 & 1) << 2 |
6367 				(sfp[4] >> 7 & 1) << 1 |
6368 				(sfp[4] >> 6 & 1) << 0);
6369 
6370 			/* Voltage high/low alarm/warning */
6371 			rsp_payload->optical_elmt_desc[1].element_flags |=
6372 			    cpu_to_be32(
6373 				(sfp[0] >> 5 & 1) << 3 |
6374 				(sfp[0] >> 4 & 1) << 2 |
6375 				(sfp[4] >> 5 & 1) << 1 |
6376 				(sfp[4] >> 4 & 1) << 0);
6377 
6378 			/* Tx Bias Current high/low alarm/warning */
6379 			rsp_payload->optical_elmt_desc[2].element_flags |=
6380 			    cpu_to_be32(
6381 				(sfp[0] >> 3 & 1) << 3 |
6382 				(sfp[0] >> 2 & 1) << 2 |
6383 				(sfp[4] >> 3 & 1) << 1 |
6384 				(sfp[4] >> 2 & 1) << 0);
6385 
6386 			/* Tx Power high/low alarm/warning */
6387 			rsp_payload->optical_elmt_desc[3].element_flags |=
6388 			    cpu_to_be32(
6389 				(sfp[0] >> 1 & 1) << 3 |
6390 				(sfp[0] >> 0 & 1) << 2 |
6391 				(sfp[4] >> 1 & 1) << 1 |
6392 				(sfp[4] >> 0 & 1) << 0);
6393 
6394 			/* Rx Power high/low alarm/warning */
6395 			rsp_payload->optical_elmt_desc[4].element_flags |=
6396 			    cpu_to_be32(
6397 				(sfp[1] >> 7 & 1) << 3 |
6398 				(sfp[1] >> 6 & 1) << 2 |
6399 				(sfp[5] >> 7 & 1) << 1 |
6400 				(sfp[5] >> 6 & 1) << 0);
6401 		}
6402 	}
6403 
6404 	/* Optical Product Data Descriptor */
6405 	rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6406 	rsp_payload->optical_prod_desc.desc_len =
6407 		cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6408 
6409 	if (sfp) {
6410 		memset(sfp, 0, SFP_RTDI_LEN);
6411 		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
6412 		if (!rval) {
6413 			memcpy(rsp_payload->optical_prod_desc.vendor_name,
6414 			    sfp + 0,
6415 			    sizeof(rsp_payload->optical_prod_desc.vendor_name));
6416 			memcpy(rsp_payload->optical_prod_desc.part_number,
6417 			    sfp + 20,
6418 			    sizeof(rsp_payload->optical_prod_desc.part_number));
6419 			memcpy(rsp_payload->optical_prod_desc.revision,
6420 			    sfp + 36,
6421 			    sizeof(rsp_payload->optical_prod_desc.revision));
6422 			memcpy(rsp_payload->optical_prod_desc.serial_number,
6423 			    sfp + 48,
6424 			    sizeof(rsp_payload->optical_prod_desc.serial_number));
6425 		}
6426 
6427 		memset(sfp, 0, SFP_RTDI_LEN);
6428 		rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
6429 		if (!rval) {
6430 			memcpy(rsp_payload->optical_prod_desc.date,
6431 			    sfp + 0,
6432 			    sizeof(rsp_payload->optical_prod_desc.date));
6433 		}
6434 	}
6435 
6436 send:
6437 	ql_dbg(ql_dbg_init, vha, 0x0183,
6438 	    "Sending ELS Response to RDP Request...\n");
6439 	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
6440 	    "-------- ELS RSP -------\n");
6441 	ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
6442 	    rsp_els, sizeof(*rsp_els));
6443 	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
6444 	    "-------- ELS RSP PAYLOAD -------\n");
6445 	ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
6446 	    rsp_payload, rsp_payload_length);
6447 
6448 	rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0);
6449 
6450 	if (rval) {
6451 		ql_log(ql_log_warn, vha, 0x0188,
6452 		    "%s: iocb failed to execute -> %x\n", __func__, rval);
6453 	} else if (rsp_els->comp_status) {
6454 		ql_log(ql_log_warn, vha, 0x0189,
6455 		    "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6456 		    __func__, rsp_els->comp_status,
6457 		    rsp_els->error_subcode_1, rsp_els->error_subcode_2);
6458 	} else {
6459 		ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
6460 	}
6461 
6462 dealloc:
6463 	if (stat)
6464 		dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6465 		    stat, stat_dma);
6466 	if (sfp)
6467 		dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6468 		    sfp, sfp_dma);
6469 	if (rsp_payload)
6470 		dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6471 		    rsp_payload, rsp_payload_dma);
6472 	if (rsp_els)
6473 		dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6474 		    rsp_els, rsp_els_dma);
6475 }
6476 
6477 void
qla24xx_free_purex_item(struct purex_item * item)6478 qla24xx_free_purex_item(struct purex_item *item)
6479 {
6480 	if (item == &item->vha->default_item)
6481 		memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6482 	else
6483 		kfree(item);
6484 }
6485 
qla24xx_process_purex_list(struct purex_list * list)6486 void qla24xx_process_purex_list(struct purex_list *list)
6487 {
6488 	struct list_head head = LIST_HEAD_INIT(head);
6489 	struct purex_item *item, *next;
6490 	ulong flags;
6491 
6492 	spin_lock_irqsave(&list->lock, flags);
6493 	list_splice_init(&list->head, &head);
6494 	spin_unlock_irqrestore(&list->lock, flags);
6495 
6496 	list_for_each_entry_safe(item, next, &head, list) {
6497 		list_del(&item->list);
6498 		item->process_item(item->vha, item);
6499 		qla24xx_free_purex_item(item);
6500 	}
6501 }
6502 
6503 /*
6504  * Context: task, can sleep
6505  */
6506 void
qla83xx_idc_unlock(scsi_qla_host_t * base_vha,uint16_t requester_id)6507 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6508 {
6509 #if 0
6510 	uint16_t options = (requester_id << 15) | BIT_7;
6511 #endif
6512 	uint16_t retry;
6513 	uint32_t data;
6514 	struct qla_hw_data *ha = base_vha->hw;
6515 
6516 	might_sleep();
6517 
6518 	/* IDC-unlock implementation using driver-unlock/lock-id
6519 	 * remote registers
6520 	 */
6521 	retry = 0;
6522 retry_unlock:
6523 	if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
6524 	    == QLA_SUCCESS) {
6525 		if (data == ha->portnum) {
6526 			qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
6527 			/* Clearing lock-id by setting 0xff */
6528 			qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
6529 		} else if (retry < 10) {
6530 			/* SV: XXX: IDC unlock retrying needed here? */
6531 
6532 			/* Retry for IDC-unlock */
6533 			msleep(QLA83XX_WAIT_LOGIC_MS);
6534 			retry++;
6535 			ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
6536 			    "Failed to release IDC lock, retrying=%d\n", retry);
6537 			goto retry_unlock;
6538 		}
6539 	} else if (retry < 10) {
6540 		/* Retry for IDC-unlock */
6541 		msleep(QLA83XX_WAIT_LOGIC_MS);
6542 		retry++;
6543 		ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
6544 		    "Failed to read drv-lockid, retrying=%d\n", retry);
6545 		goto retry_unlock;
6546 	}
6547 
6548 	return;
6549 
6550 #if 0
6551 	/* XXX: IDC-unlock implementation using access-control mbx */
6552 	retry = 0;
6553 retry_unlock2:
6554 	if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
6555 		if (retry < 10) {
6556 			/* Retry for IDC-unlock */
6557 			msleep(QLA83XX_WAIT_LOGIC_MS);
6558 			retry++;
6559 			ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
6560 			    "Failed to release IDC lock, retrying=%d\n", retry);
6561 			goto retry_unlock2;
6562 		}
6563 	}
6564 
6565 	return;
6566 #endif
6567 }
6568 
6569 int
__qla83xx_set_drv_presence(scsi_qla_host_t * vha)6570 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6571 {
6572 	int rval = QLA_SUCCESS;
6573 	struct qla_hw_data *ha = vha->hw;
6574 	uint32_t drv_presence;
6575 
6576 	rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6577 	if (rval == QLA_SUCCESS) {
6578 		drv_presence |= (1 << ha->portnum);
6579 		rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6580 		    drv_presence);
6581 	}
6582 
6583 	return rval;
6584 }
6585 
6586 int
qla83xx_set_drv_presence(scsi_qla_host_t * vha)6587 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6588 {
6589 	int rval = QLA_SUCCESS;
6590 
6591 	qla83xx_idc_lock(vha, 0);
6592 	rval = __qla83xx_set_drv_presence(vha);
6593 	qla83xx_idc_unlock(vha, 0);
6594 
6595 	return rval;
6596 }
6597 
6598 int
__qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6599 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6600 {
6601 	int rval = QLA_SUCCESS;
6602 	struct qla_hw_data *ha = vha->hw;
6603 	uint32_t drv_presence;
6604 
6605 	rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6606 	if (rval == QLA_SUCCESS) {
6607 		drv_presence &= ~(1 << ha->portnum);
6608 		rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6609 		    drv_presence);
6610 	}
6611 
6612 	return rval;
6613 }
6614 
6615 int
qla83xx_clear_drv_presence(scsi_qla_host_t * vha)6616 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6617 {
6618 	int rval = QLA_SUCCESS;
6619 
6620 	qla83xx_idc_lock(vha, 0);
6621 	rval = __qla83xx_clear_drv_presence(vha);
6622 	qla83xx_idc_unlock(vha, 0);
6623 
6624 	return rval;
6625 }
6626 
6627 static void
qla83xx_need_reset_handler(scsi_qla_host_t * vha)6628 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
6629 {
6630 	struct qla_hw_data *ha = vha->hw;
6631 	uint32_t drv_ack, drv_presence;
6632 	unsigned long ack_timeout;
6633 
6634 	/* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6635 	ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6636 	while (1) {
6637 		qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6638 		qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6639 		if ((drv_ack & drv_presence) == drv_presence)
6640 			break;
6641 
6642 		if (time_after_eq(jiffies, ack_timeout)) {
6643 			ql_log(ql_log_warn, vha, 0xb067,
6644 			    "RESET ACK TIMEOUT! drv_presence=0x%x "
6645 			    "drv_ack=0x%x\n", drv_presence, drv_ack);
6646 			/*
6647 			 * The function(s) which did not ack in time are forced
6648 			 * to withdraw any further participation in the IDC
6649 			 * reset.
6650 			 */
6651 			if (drv_ack != drv_presence)
6652 				qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6653 				    drv_ack);
6654 			break;
6655 		}
6656 
6657 		qla83xx_idc_unlock(vha, 0);
6658 		msleep(1000);
6659 		qla83xx_idc_lock(vha, 0);
6660 	}
6661 
6662 	qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
6663 	ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6664 }
6665 
6666 static int
qla83xx_device_bootstrap(scsi_qla_host_t * vha)6667 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
6668 {
6669 	int rval = QLA_SUCCESS;
6670 	uint32_t idc_control;
6671 
6672 	qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
6673 	ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
6674 
6675 	/* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6676 	__qla83xx_get_idc_control(vha, &idc_control);
6677 	idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
6678 	__qla83xx_set_idc_control(vha, 0);
6679 
6680 	qla83xx_idc_unlock(vha, 0);
6681 	rval = qla83xx_restart_nic_firmware(vha);
6682 	qla83xx_idc_lock(vha, 0);
6683 
6684 	if (rval != QLA_SUCCESS) {
6685 		ql_log(ql_log_fatal, vha, 0xb06a,
6686 		    "Failed to restart NIC f/w.\n");
6687 		qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6688 		ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6689 	} else {
6690 		ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6691 		    "Success in restarting nic f/w.\n");
6692 		qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6693 		ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6694 	}
6695 
6696 	return rval;
6697 }
6698 
6699 /* Assumes idc_lock always held on entry */
6700 int
qla83xx_idc_state_handler(scsi_qla_host_t * base_vha)6701 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6702 {
6703 	struct qla_hw_data *ha = base_vha->hw;
6704 	int rval = QLA_SUCCESS;
6705 	unsigned long dev_init_timeout;
6706 	uint32_t dev_state;
6707 
6708 	/* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6709 	dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6710 
6711 	while (1) {
6712 
6713 		if (time_after_eq(jiffies, dev_init_timeout)) {
6714 			ql_log(ql_log_warn, base_vha, 0xb06e,
6715 			    "Initialization TIMEOUT!\n");
6716 			/* Init timeout. Disable further NIC Core
6717 			 * communication.
6718 			 */
6719 			qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6720 				QLA8XXX_DEV_FAILED);
6721 			ql_log(ql_log_info, base_vha, 0xb06f,
6722 			    "HW State: FAILED.\n");
6723 		}
6724 
6725 		qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6726 		switch (dev_state) {
6727 		case QLA8XXX_DEV_READY:
6728 			if (ha->flags.nic_core_reset_owner)
6729 				qla83xx_idc_audit(base_vha,
6730 				    IDC_AUDIT_COMPLETION);
6731 			ha->flags.nic_core_reset_owner = 0;
6732 			ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6733 			    "Reset_owner reset by 0x%x.\n",
6734 			    ha->portnum);
6735 			goto exit;
6736 		case QLA8XXX_DEV_COLD:
6737 			if (ha->flags.nic_core_reset_owner)
6738 				rval = qla83xx_device_bootstrap(base_vha);
6739 			else {
6740 			/* Wait for AEN to change device-state */
6741 				qla83xx_idc_unlock(base_vha, 0);
6742 				msleep(1000);
6743 				qla83xx_idc_lock(base_vha, 0);
6744 			}
6745 			break;
6746 		case QLA8XXX_DEV_INITIALIZING:
6747 			/* Wait for AEN to change device-state */
6748 			qla83xx_idc_unlock(base_vha, 0);
6749 			msleep(1000);
6750 			qla83xx_idc_lock(base_vha, 0);
6751 			break;
6752 		case QLA8XXX_DEV_NEED_RESET:
6753 			if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6754 				qla83xx_need_reset_handler(base_vha);
6755 			else {
6756 				/* Wait for AEN to change device-state */
6757 				qla83xx_idc_unlock(base_vha, 0);
6758 				msleep(1000);
6759 				qla83xx_idc_lock(base_vha, 0);
6760 			}
6761 			/* reset timeout value after need reset handler */
6762 			dev_init_timeout = jiffies +
6763 			    (ha->fcoe_dev_init_timeout * HZ);
6764 			break;
6765 		case QLA8XXX_DEV_NEED_QUIESCENT:
6766 			/* XXX: DEBUG for now */
6767 			qla83xx_idc_unlock(base_vha, 0);
6768 			msleep(1000);
6769 			qla83xx_idc_lock(base_vha, 0);
6770 			break;
6771 		case QLA8XXX_DEV_QUIESCENT:
6772 			/* XXX: DEBUG for now */
6773 			if (ha->flags.quiesce_owner)
6774 				goto exit;
6775 
6776 			qla83xx_idc_unlock(base_vha, 0);
6777 			msleep(1000);
6778 			qla83xx_idc_lock(base_vha, 0);
6779 			dev_init_timeout = jiffies +
6780 			    (ha->fcoe_dev_init_timeout * HZ);
6781 			break;
6782 		case QLA8XXX_DEV_FAILED:
6783 			if (ha->flags.nic_core_reset_owner)
6784 				qla83xx_idc_audit(base_vha,
6785 				    IDC_AUDIT_COMPLETION);
6786 			ha->flags.nic_core_reset_owner = 0;
6787 			__qla83xx_clear_drv_presence(base_vha);
6788 			qla83xx_idc_unlock(base_vha, 0);
6789 			qla8xxx_dev_failed_handler(base_vha);
6790 			rval = QLA_FUNCTION_FAILED;
6791 			qla83xx_idc_lock(base_vha, 0);
6792 			goto exit;
6793 		case QLA8XXX_BAD_VALUE:
6794 			qla83xx_idc_unlock(base_vha, 0);
6795 			msleep(1000);
6796 			qla83xx_idc_lock(base_vha, 0);
6797 			break;
6798 		default:
6799 			ql_log(ql_log_warn, base_vha, 0xb071,
6800 			    "Unknown Device State: %x.\n", dev_state);
6801 			qla83xx_idc_unlock(base_vha, 0);
6802 			qla8xxx_dev_failed_handler(base_vha);
6803 			rval = QLA_FUNCTION_FAILED;
6804 			qla83xx_idc_lock(base_vha, 0);
6805 			goto exit;
6806 		}
6807 	}
6808 
6809 exit:
6810 	return rval;
6811 }
6812 
6813 void
qla2x00_disable_board_on_pci_error(struct work_struct * work)6814 qla2x00_disable_board_on_pci_error(struct work_struct *work)
6815 {
6816 	struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6817 	    board_disable);
6818 	struct pci_dev *pdev = ha->pdev;
6819 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6820 
6821 	ql_log(ql_log_warn, base_vha, 0x015b,
6822 	    "Disabling adapter.\n");
6823 
6824 	if (!atomic_read(&pdev->enable_cnt)) {
6825 		ql_log(ql_log_info, base_vha, 0xfffc,
6826 		    "PCI device disabled, no action req for PCI error=%lx\n",
6827 		    base_vha->pci_flags);
6828 		return;
6829 	}
6830 
6831 	/*
6832 	 * if UNLOADING flag is already set, then continue unload,
6833 	 * where it was set first.
6834 	 */
6835 	if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
6836 		return;
6837 
6838 	qla2x00_wait_for_sess_deletion(base_vha);
6839 
6840 	qla2x00_delete_all_vps(ha, base_vha);
6841 
6842 	qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6843 
6844 	qla2x00_dfs_remove(base_vha);
6845 
6846 	qla84xx_put_chip(base_vha);
6847 
6848 	if (base_vha->timer_active)
6849 		qla2x00_stop_timer(base_vha);
6850 
6851 	base_vha->flags.online = 0;
6852 
6853 	qla2x00_destroy_deferred_work(ha);
6854 
6855 	/*
6856 	 * Do not try to stop beacon blink as it will issue a mailbox
6857 	 * command.
6858 	 */
6859 	qla2x00_free_sysfs_attr(base_vha, false);
6860 
6861 	fc_remove_host(base_vha->host);
6862 
6863 	scsi_remove_host(base_vha->host);
6864 
6865 	base_vha->flags.init_done = 0;
6866 	qla25xx_delete_queues(base_vha);
6867 	qla2x00_free_fcports(base_vha);
6868 	qla2x00_free_irqs(base_vha);
6869 	qla2x00_mem_free(ha);
6870 	qla82xx_md_free(base_vha);
6871 	qla2x00_free_queues(ha);
6872 
6873 	qla2x00_unmap_iobases(ha);
6874 
6875 	pci_release_selected_regions(ha->pdev, ha->bars);
6876 	pci_disable_device(pdev);
6877 
6878 	/*
6879 	 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6880 	 */
6881 }
6882 
6883 /**************************************************************************
6884 * qla2x00_do_dpc
6885 *   This kernel thread is a task that is schedule by the interrupt handler
6886 *   to perform the background processing for interrupts.
6887 *
6888 * Notes:
6889 * This task always run in the context of a kernel thread.  It
6890 * is kick-off by the driver's detect code and starts up
6891 * up one per adapter. It immediately goes to sleep and waits for
6892 * some fibre event.  When either the interrupt handler or
6893 * the timer routine detects a event it will one of the task
6894 * bits then wake us up.
6895 **************************************************************************/
6896 static int
qla2x00_do_dpc(void * data)6897 qla2x00_do_dpc(void *data)
6898 {
6899 	scsi_qla_host_t *base_vha;
6900 	struct qla_hw_data *ha;
6901 	uint32_t online;
6902 	struct qla_qpair *qpair;
6903 
6904 	ha = (struct qla_hw_data *)data;
6905 	base_vha = pci_get_drvdata(ha->pdev);
6906 
6907 	set_user_nice(current, MIN_NICE);
6908 
6909 	set_current_state(TASK_INTERRUPTIBLE);
6910 	while (!kthread_should_stop()) {
6911 		ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6912 		    "DPC handler sleeping.\n");
6913 
6914 		schedule();
6915 
6916 		if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags))
6917 			qla_pci_set_eeh_busy(base_vha);
6918 
6919 		if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6920 			goto end_loop;
6921 
6922 		if (ha->flags.eeh_busy) {
6923 			ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6924 			    "eeh_busy=%d.\n", ha->flags.eeh_busy);
6925 			goto end_loop;
6926 		}
6927 
6928 		ha->dpc_active = 1;
6929 
6930 		ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6931 		    "DPC handler waking up, dpc_flags=0x%lx.\n",
6932 		    base_vha->dpc_flags);
6933 
6934 		if (test_bit(UNLOADING, &base_vha->dpc_flags))
6935 			break;
6936 
6937 		if (IS_P3P_TYPE(ha)) {
6938 			if (IS_QLA8044(ha)) {
6939 				if (test_and_clear_bit(ISP_UNRECOVERABLE,
6940 					&base_vha->dpc_flags)) {
6941 					qla8044_idc_lock(ha);
6942 					qla8044_wr_direct(base_vha,
6943 						QLA8044_CRB_DEV_STATE_INDEX,
6944 						QLA8XXX_DEV_FAILED);
6945 					qla8044_idc_unlock(ha);
6946 					ql_log(ql_log_info, base_vha, 0x4004,
6947 						"HW State: FAILED.\n");
6948 					qla8044_device_state_handler(base_vha);
6949 					continue;
6950 				}
6951 
6952 			} else {
6953 				if (test_and_clear_bit(ISP_UNRECOVERABLE,
6954 					&base_vha->dpc_flags)) {
6955 					qla82xx_idc_lock(ha);
6956 					qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6957 						QLA8XXX_DEV_FAILED);
6958 					qla82xx_idc_unlock(ha);
6959 					ql_log(ql_log_info, base_vha, 0x0151,
6960 						"HW State: FAILED.\n");
6961 					qla82xx_device_state_handler(base_vha);
6962 					continue;
6963 				}
6964 			}
6965 
6966 			if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6967 				&base_vha->dpc_flags)) {
6968 
6969 				ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6970 				    "FCoE context reset scheduled.\n");
6971 				if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6972 					&base_vha->dpc_flags))) {
6973 					if (qla82xx_fcoe_ctx_reset(base_vha)) {
6974 						/* FCoE-ctx reset failed.
6975 						 * Escalate to chip-reset
6976 						 */
6977 						set_bit(ISP_ABORT_NEEDED,
6978 							&base_vha->dpc_flags);
6979 					}
6980 					clear_bit(ABORT_ISP_ACTIVE,
6981 						&base_vha->dpc_flags);
6982 				}
6983 
6984 				ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6985 				    "FCoE context reset end.\n");
6986 			}
6987 		} else if (IS_QLAFX00(ha)) {
6988 			if (test_and_clear_bit(ISP_UNRECOVERABLE,
6989 				&base_vha->dpc_flags)) {
6990 				ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6991 				    "Firmware Reset Recovery\n");
6992 				if (qlafx00_reset_initialize(base_vha)) {
6993 					/* Failed. Abort isp later. */
6994 					if (!test_bit(UNLOADING,
6995 					    &base_vha->dpc_flags)) {
6996 						set_bit(ISP_UNRECOVERABLE,
6997 						    &base_vha->dpc_flags);
6998 						ql_dbg(ql_dbg_dpc, base_vha,
6999 						    0x4021,
7000 						    "Reset Recovery Failed\n");
7001 					}
7002 				}
7003 			}
7004 
7005 			if (test_and_clear_bit(FX00_TARGET_SCAN,
7006 				&base_vha->dpc_flags)) {
7007 				ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
7008 				    "ISPFx00 Target Scan scheduled\n");
7009 				if (qlafx00_rescan_isp(base_vha)) {
7010 					if (!test_bit(UNLOADING,
7011 					    &base_vha->dpc_flags))
7012 						set_bit(ISP_UNRECOVERABLE,
7013 						    &base_vha->dpc_flags);
7014 					ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
7015 					    "ISPFx00 Target Scan Failed\n");
7016 				}
7017 				ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
7018 				    "ISPFx00 Target Scan End\n");
7019 			}
7020 			if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
7021 				&base_vha->dpc_flags)) {
7022 				ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
7023 				    "ISPFx00 Host Info resend scheduled\n");
7024 				qlafx00_fx_disc(base_vha,
7025 				    &base_vha->hw->mr.fcport,
7026 				    FXDISC_REG_HOST_INFO);
7027 			}
7028 		}
7029 
7030 		if (test_and_clear_bit(DETECT_SFP_CHANGE,
7031 		    &base_vha->dpc_flags)) {
7032 			/* Semantic:
7033 			 *  - NO-OP -- await next ISP-ABORT. Preferred method
7034 			 *             to minimize disruptions that will occur
7035 			 *             when a forced chip-reset occurs.
7036 			 *  - Force -- ISP-ABORT scheduled.
7037 			 */
7038 			/* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
7039 		}
7040 
7041 		if (test_and_clear_bit
7042 		    (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
7043 		    !test_bit(UNLOADING, &base_vha->dpc_flags)) {
7044 			bool do_reset = true;
7045 
7046 			switch (base_vha->qlini_mode) {
7047 			case QLA2XXX_INI_MODE_ENABLED:
7048 				break;
7049 			case QLA2XXX_INI_MODE_DISABLED:
7050 				if (!qla_tgt_mode_enabled(base_vha) &&
7051 				    !ha->flags.fw_started)
7052 					do_reset = false;
7053 				break;
7054 			case QLA2XXX_INI_MODE_DUAL:
7055 				if (!qla_dual_mode_enabled(base_vha) &&
7056 				    !ha->flags.fw_started)
7057 					do_reset = false;
7058 				break;
7059 			default:
7060 				break;
7061 			}
7062 
7063 			if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
7064 			    &base_vha->dpc_flags))) {
7065 				base_vha->flags.online = 1;
7066 				ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
7067 				    "ISP abort scheduled.\n");
7068 				if (ha->isp_ops->abort_isp(base_vha)) {
7069 					/* failed. retry later */
7070 					set_bit(ISP_ABORT_NEEDED,
7071 					    &base_vha->dpc_flags);
7072 				}
7073 				clear_bit(ABORT_ISP_ACTIVE,
7074 						&base_vha->dpc_flags);
7075 				ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
7076 				    "ISP abort end.\n");
7077 			}
7078 		}
7079 
7080 		if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
7081 			if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
7082 				qla24xx_process_purex_list
7083 					(&base_vha->purex_list);
7084 				clear_bit(PROCESS_PUREX_IOCB,
7085 				    &base_vha->dpc_flags);
7086 			}
7087 		}
7088 
7089 		if (IS_QLAFX00(ha))
7090 			goto loop_resync_check;
7091 
7092 		if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7093 			ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
7094 			    "Quiescence mode scheduled.\n");
7095 			if (IS_P3P_TYPE(ha)) {
7096 				if (IS_QLA82XX(ha))
7097 					qla82xx_device_state_handler(base_vha);
7098 				if (IS_QLA8044(ha))
7099 					qla8044_device_state_handler(base_vha);
7100 				clear_bit(ISP_QUIESCE_NEEDED,
7101 				    &base_vha->dpc_flags);
7102 				if (!ha->flags.quiesce_owner) {
7103 					qla2x00_perform_loop_resync(base_vha);
7104 					if (IS_QLA82XX(ha)) {
7105 						qla82xx_idc_lock(ha);
7106 						qla82xx_clear_qsnt_ready(
7107 						    base_vha);
7108 						qla82xx_idc_unlock(ha);
7109 					} else if (IS_QLA8044(ha)) {
7110 						qla8044_idc_lock(ha);
7111 						qla8044_clear_qsnt_ready(
7112 						    base_vha);
7113 						qla8044_idc_unlock(ha);
7114 					}
7115 				}
7116 			} else {
7117 				clear_bit(ISP_QUIESCE_NEEDED,
7118 				    &base_vha->dpc_flags);
7119 				qla2x00_quiesce_io(base_vha);
7120 			}
7121 			ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
7122 			    "Quiescence mode end.\n");
7123 		}
7124 
7125 		if (test_and_clear_bit(RESET_MARKER_NEEDED,
7126 				&base_vha->dpc_flags) &&
7127 		    (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
7128 
7129 			ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
7130 			    "Reset marker scheduled.\n");
7131 			qla2x00_rst_aen(base_vha);
7132 			clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7133 			ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
7134 			    "Reset marker end.\n");
7135 		}
7136 
7137 		/* Retry each device up to login retry count */
7138 		if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
7139 		    !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
7140 		    atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
7141 
7142 			if (!base_vha->relogin_jif ||
7143 			    time_after_eq(jiffies, base_vha->relogin_jif)) {
7144 				base_vha->relogin_jif = jiffies + HZ;
7145 				clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
7146 
7147 				ql_dbg(ql_dbg_disc, base_vha, 0x400d,
7148 				    "Relogin scheduled.\n");
7149 				qla24xx_post_relogin_work(base_vha);
7150 			}
7151 		}
7152 loop_resync_check:
7153 		if (!qla2x00_reset_active(base_vha) &&
7154 		    test_and_clear_bit(LOOP_RESYNC_NEEDED,
7155 		    &base_vha->dpc_flags)) {
7156 			/*
7157 			 * Allow abort_isp to complete before moving on to scanning.
7158 			 */
7159 			ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
7160 			    "Loop resync scheduled.\n");
7161 
7162 			if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
7163 			    &base_vha->dpc_flags))) {
7164 
7165 				qla2x00_loop_resync(base_vha);
7166 
7167 				clear_bit(LOOP_RESYNC_ACTIVE,
7168 						&base_vha->dpc_flags);
7169 			}
7170 
7171 			ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
7172 			    "Loop resync end.\n");
7173 		}
7174 
7175 		if (IS_QLAFX00(ha))
7176 			goto intr_on_check;
7177 
7178 		if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
7179 		    atomic_read(&base_vha->loop_state) == LOOP_READY) {
7180 			clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
7181 			qla2xxx_flash_npiv_conf(base_vha);
7182 		}
7183 
7184 intr_on_check:
7185 		if (!ha->interrupts_on)
7186 			ha->isp_ops->enable_intrs(ha);
7187 
7188 		if (test_and_clear_bit(BEACON_BLINK_NEEDED,
7189 					&base_vha->dpc_flags)) {
7190 			if (ha->beacon_blink_led == 1)
7191 				ha->isp_ops->beacon_blink(base_vha);
7192 		}
7193 
7194 		/* qpair online check */
7195 		if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
7196 		    &base_vha->dpc_flags)) {
7197 			if (ha->flags.eeh_busy ||
7198 			    ha->flags.pci_channel_io_perm_failure)
7199 				online = 0;
7200 			else
7201 				online = 1;
7202 
7203 			mutex_lock(&ha->mq_lock);
7204 			list_for_each_entry(qpair, &base_vha->qp_list,
7205 			    qp_list_elem)
7206 			qpair->online = online;
7207 			mutex_unlock(&ha->mq_lock);
7208 		}
7209 
7210 		if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
7211 				       &base_vha->dpc_flags)) {
7212 			u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold;
7213 
7214 			if (threshold > ha->orig_fw_xcb_count)
7215 				threshold = ha->orig_fw_xcb_count;
7216 
7217 			ql_log(ql_log_info, base_vha, 0xffffff,
7218 			       "SET ZIO Activity exchange threshold to %d.\n",
7219 			       threshold);
7220 			if (qla27xx_set_zio_threshold(base_vha, threshold)) {
7221 				ql_log(ql_log_info, base_vha, 0xffffff,
7222 				       "Unable to SET ZIO Activity exchange threshold to %d.\n",
7223 				       threshold);
7224 			}
7225 		}
7226 
7227 		if (!IS_QLAFX00(ha))
7228 			qla2x00_do_dpc_all_vps(base_vha);
7229 
7230 		if (test_and_clear_bit(N2N_LINK_RESET,
7231 			&base_vha->dpc_flags)) {
7232 			qla2x00_lip_reset(base_vha);
7233 		}
7234 
7235 		ha->dpc_active = 0;
7236 end_loop:
7237 		set_current_state(TASK_INTERRUPTIBLE);
7238 	} /* End of while(1) */
7239 	__set_current_state(TASK_RUNNING);
7240 
7241 	ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
7242 	    "DPC handler exiting.\n");
7243 
7244 	/*
7245 	 * Make sure that nobody tries to wake us up again.
7246 	 */
7247 	ha->dpc_active = 0;
7248 
7249 	/* Cleanup any residual CTX SRBs. */
7250 	qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
7251 
7252 	return 0;
7253 }
7254 
7255 void
qla2xxx_wake_dpc(struct scsi_qla_host * vha)7256 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
7257 {
7258 	struct qla_hw_data *ha = vha->hw;
7259 	struct task_struct *t = ha->dpc_thread;
7260 
7261 	if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
7262 		wake_up_process(t);
7263 }
7264 
7265 /*
7266 *  qla2x00_rst_aen
7267 *      Processes asynchronous reset.
7268 *
7269 * Input:
7270 *      ha  = adapter block pointer.
7271 */
7272 static void
qla2x00_rst_aen(scsi_qla_host_t * vha)7273 qla2x00_rst_aen(scsi_qla_host_t *vha)
7274 {
7275 	if (vha->flags.online && !vha->flags.reset_active &&
7276 	    !atomic_read(&vha->loop_down_timer) &&
7277 	    !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
7278 		do {
7279 			clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7280 
7281 			/*
7282 			 * Issue marker command only when we are going to start
7283 			 * the I/O.
7284 			 */
7285 			vha->marker_needed = 1;
7286 		} while (!atomic_read(&vha->loop_down_timer) &&
7287 		    (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
7288 	}
7289 }
7290 
qla_do_heartbeat(struct scsi_qla_host * vha)7291 static bool qla_do_heartbeat(struct scsi_qla_host *vha)
7292 {
7293 	struct qla_hw_data *ha = vha->hw;
7294 	u32 cmpl_cnt;
7295 	u16 i;
7296 	bool do_heartbeat = false;
7297 
7298 	/*
7299 	 * Allow do_heartbeat only if we don’t have any active interrupts,
7300 	 * but there are still IOs outstanding with firmware.
7301 	 */
7302 	cmpl_cnt = ha->base_qpair->cmd_completion_cnt;
7303 	if (cmpl_cnt == ha->base_qpair->prev_completion_cnt &&
7304 	    cmpl_cnt != ha->base_qpair->cmd_cnt) {
7305 		do_heartbeat = true;
7306 		goto skip;
7307 	}
7308 	ha->base_qpair->prev_completion_cnt = cmpl_cnt;
7309 
7310 	for (i = 0; i < ha->max_qpairs; i++) {
7311 		if (ha->queue_pair_map[i]) {
7312 			cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt;
7313 			if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt &&
7314 			    cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) {
7315 				do_heartbeat = true;
7316 				break;
7317 			}
7318 			ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt;
7319 		}
7320 	}
7321 
7322 skip:
7323 	return do_heartbeat;
7324 }
7325 
qla_heart_beat(struct scsi_qla_host * vha,u16 dpc_started)7326 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started)
7327 {
7328 	struct qla_hw_data *ha = vha->hw;
7329 
7330 	if (vha->vp_idx)
7331 		return;
7332 
7333 	if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha))
7334 		return;
7335 
7336 	/*
7337 	 * dpc thread cannot run if heartbeat is running at the same time.
7338 	 * We also do not want to starve heartbeat task. Therefore, do
7339 	 * heartbeat task at least once every 5 seconds.
7340 	 */
7341 	if (dpc_started &&
7342 	    time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ))
7343 		return;
7344 
7345 	if (qla_do_heartbeat(vha)) {
7346 		ha->last_heartbeat_run_jiffies = jiffies;
7347 		queue_work(ha->wq, &ha->heartbeat_work);
7348 	}
7349 }
7350 
qla_wind_down_chip(scsi_qla_host_t * vha)7351 static void qla_wind_down_chip(scsi_qla_host_t *vha)
7352 {
7353 	struct qla_hw_data *ha = vha->hw;
7354 
7355 	if (!ha->flags.eeh_busy)
7356 		return;
7357 	if (ha->pci_error_state)
7358 		/* system is trying to recover */
7359 		return;
7360 
7361 	/*
7362 	 * Current system is not handling PCIE error.  At this point, this is
7363 	 * best effort to wind down the adapter.
7364 	 */
7365 	if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) &&
7366 	    !ha->flags.eeh_flush) {
7367 		ql_log(ql_log_info, vha, 0x9009,
7368 		    "PCI Error detected, attempting to reset hardware.\n");
7369 
7370 		ha->isp_ops->reset_chip(vha);
7371 		ha->isp_ops->disable_intrs(ha);
7372 
7373 		ha->flags.eeh_flush = EEH_FLUSH_RDY;
7374 		ha->eeh_jif = jiffies;
7375 
7376 	} else if (ha->flags.eeh_flush == EEH_FLUSH_RDY &&
7377 	    time_after_eq(jiffies, ha->eeh_jif +  5 * HZ)) {
7378 		pci_clear_master(ha->pdev);
7379 
7380 		/* flush all command */
7381 		qla2x00_abort_isp_cleanup(vha);
7382 		ha->flags.eeh_flush = EEH_FLUSH_DONE;
7383 
7384 		ql_log(ql_log_info, vha, 0x900a,
7385 		    "PCI Error handling complete, all IOs aborted.\n");
7386 	}
7387 }
7388 
7389 /**************************************************************************
7390 *   qla2x00_timer
7391 *
7392 * Description:
7393 *   One second timer
7394 *
7395 * Context: Interrupt
7396 ***************************************************************************/
7397 void
qla2x00_timer(struct timer_list * t)7398 qla2x00_timer(struct timer_list *t)
7399 {
7400 	scsi_qla_host_t *vha = from_timer(vha, t, timer);
7401 	unsigned long	cpu_flags = 0;
7402 	int		start_dpc = 0;
7403 	int		index;
7404 	srb_t		*sp;
7405 	uint16_t        w;
7406 	struct qla_hw_data *ha = vha->hw;
7407 	struct req_que *req;
7408 	unsigned long flags;
7409 	fc_port_t *fcport = NULL;
7410 
7411 	if (ha->flags.eeh_busy) {
7412 		qla_wind_down_chip(vha);
7413 
7414 		ql_dbg(ql_dbg_timer, vha, 0x6000,
7415 		    "EEH = %d, restarting timer.\n",
7416 		    ha->flags.eeh_busy);
7417 		qla2x00_restart_timer(vha, WATCH_INTERVAL);
7418 		return;
7419 	}
7420 
7421 	/*
7422 	 * Hardware read to raise pending EEH errors during mailbox waits. If
7423 	 * the read returns -1 then disable the board.
7424 	 */
7425 	if (!pci_channel_offline(ha->pdev)) {
7426 		pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
7427 		qla2x00_check_reg16_for_disconnect(vha, w);
7428 	}
7429 
7430 	/* Make sure qla82xx_watchdog is run only for physical port */
7431 	if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
7432 		if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7433 			start_dpc++;
7434 		if (IS_QLA82XX(ha))
7435 			qla82xx_watchdog(vha);
7436 		else if (IS_QLA8044(ha))
7437 			qla8044_watchdog(vha);
7438 	}
7439 
7440 	if (!vha->vp_idx && IS_QLAFX00(ha))
7441 		qlafx00_timer_routine(vha);
7442 
7443 	if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7444 		vha->link_down_time++;
7445 
7446 	spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
7447 	list_for_each_entry(fcport, &vha->vp_fcports, list) {
7448 		if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME)
7449 			fcport->tgt_link_down_time++;
7450 	}
7451 	spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
7452 
7453 	/* Loop down handler. */
7454 	if (atomic_read(&vha->loop_down_timer) > 0 &&
7455 	    !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7456 	    !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
7457 		&& vha->flags.online) {
7458 
7459 		if (atomic_read(&vha->loop_down_timer) ==
7460 		    vha->loop_down_abort_time) {
7461 
7462 			ql_log(ql_log_info, vha, 0x6008,
7463 			    "Loop down - aborting the queues before time expires.\n");
7464 
7465 			if (!IS_QLA2100(ha) && vha->link_down_timeout)
7466 				atomic_set(&vha->loop_state, LOOP_DEAD);
7467 
7468 			/*
7469 			 * Schedule an ISP abort to return any FCP2-device
7470 			 * commands.
7471 			 */
7472 			/* NPIV - scan physical port only */
7473 			if (!vha->vp_idx) {
7474 				spin_lock_irqsave(&ha->hardware_lock,
7475 				    cpu_flags);
7476 				req = ha->req_q_map[0];
7477 				for (index = 1;
7478 				    index < req->num_outstanding_cmds;
7479 				    index++) {
7480 					fc_port_t *sfcp;
7481 
7482 					sp = req->outstanding_cmds[index];
7483 					if (!sp)
7484 						continue;
7485 					if (sp->cmd_type != TYPE_SRB)
7486 						continue;
7487 					if (sp->type != SRB_SCSI_CMD)
7488 						continue;
7489 					sfcp = sp->fcport;
7490 					if (!(sfcp->flags & FCF_FCP2_DEVICE))
7491 						continue;
7492 
7493 					if (IS_QLA82XX(ha))
7494 						set_bit(FCOE_CTX_RESET_NEEDED,
7495 							&vha->dpc_flags);
7496 					else
7497 						set_bit(ISP_ABORT_NEEDED,
7498 							&vha->dpc_flags);
7499 					break;
7500 				}
7501 				spin_unlock_irqrestore(&ha->hardware_lock,
7502 								cpu_flags);
7503 			}
7504 			start_dpc++;
7505 		}
7506 
7507 		/* if the loop has been down for 4 minutes, reinit adapter */
7508 		if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
7509 			if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) {
7510 				ql_log(ql_log_warn, vha, 0x6009,
7511 				    "Loop down - aborting ISP.\n");
7512 
7513 				if (IS_QLA82XX(ha))
7514 					set_bit(FCOE_CTX_RESET_NEEDED,
7515 						&vha->dpc_flags);
7516 				else
7517 					set_bit(ISP_ABORT_NEEDED,
7518 						&vha->dpc_flags);
7519 			}
7520 		}
7521 		ql_dbg(ql_dbg_timer, vha, 0x600a,
7522 		    "Loop down - seconds remaining %d.\n",
7523 		    atomic_read(&vha->loop_down_timer));
7524 	}
7525 	/* Check if beacon LED needs to be blinked for physical host only */
7526 	if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
7527 		/* There is no beacon_blink function for ISP82xx */
7528 		if (!IS_P3P_TYPE(ha)) {
7529 			set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7530 			start_dpc++;
7531 		}
7532 	}
7533 
7534 	/* check if edif running */
7535 	if (vha->hw->flags.edif_enabled)
7536 		qla_edif_timer(vha);
7537 
7538 	/* Process any deferred work. */
7539 	if (!list_empty(&vha->work_list)) {
7540 		unsigned long flags;
7541 		bool q = false;
7542 
7543 		spin_lock_irqsave(&vha->work_lock, flags);
7544 		if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7545 			q = true;
7546 		spin_unlock_irqrestore(&vha->work_lock, flags);
7547 		if (q)
7548 			queue_work(vha->hw->wq, &vha->iocb_work);
7549 	}
7550 
7551 	/*
7552 	 * FC-NVME
7553 	 * see if the active AEN count has changed from what was last reported.
7554 	 */
7555 	index = atomic_read(&ha->nvme_active_aen_cnt);
7556 	if (!vha->vp_idx &&
7557 	    (index != ha->nvme_last_rptd_aen) &&
7558 	    ha->zio_mode == QLA_ZIO_MODE_6 &&
7559 	    !ha->flags.host_shutting_down) {
7560 		ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
7561 		ql_log(ql_log_info, vha, 0x3002,
7562 		    "nvme: Sched: Set ZIO exchange threshold to %d.\n",
7563 		    ha->nvme_last_rptd_aen);
7564 		set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7565 		start_dpc++;
7566 	}
7567 
7568 	if (!vha->vp_idx &&
7569 	    atomic_read(&ha->zio_threshold) != ha->last_zio_threshold &&
7570 	    IS_ZIO_THRESHOLD_CAPABLE(ha)) {
7571 		ql_log(ql_log_info, vha, 0x3002,
7572 		    "Sched: Set ZIO exchange threshold to %d.\n",
7573 		    ha->last_zio_threshold);
7574 		ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
7575 		set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7576 		start_dpc++;
7577 	}
7578 	qla_adjust_buf(vha);
7579 
7580 	/* borrowing w to signify dpc will run */
7581 	w = 0;
7582 	/* Schedule the DPC routine if needed */
7583 	if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7584 	    test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
7585 	    start_dpc ||
7586 	    test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7587 	    test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
7588 	    test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7589 	    test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
7590 	    test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7591 	    test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7592 	    test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7593 		ql_dbg(ql_dbg_timer, vha, 0x600b,
7594 		    "isp_abort_needed=%d loop_resync_needed=%d "
7595 		    "start_dpc=%d reset_marker_needed=%d",
7596 		    test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7597 		    test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
7598 		    start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7599 		ql_dbg(ql_dbg_timer, vha, 0x600c,
7600 		    "beacon_blink_needed=%d isp_unrecoverable=%d "
7601 		    "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
7602 		    "relogin_needed=%d, Process_purex_iocb=%d.\n",
7603 		    test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7604 		    test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7605 		    test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7606 		    test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
7607 		    test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7608 		    test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
7609 		qla2xxx_wake_dpc(vha);
7610 		w = 1;
7611 	}
7612 
7613 	qla_heart_beat(vha, w);
7614 
7615 	qla2x00_restart_timer(vha, WATCH_INTERVAL);
7616 }
7617 
7618 /* Firmware interface routines. */
7619 
7620 #define FW_ISP21XX	0
7621 #define FW_ISP22XX	1
7622 #define FW_ISP2300	2
7623 #define FW_ISP2322	3
7624 #define FW_ISP24XX	4
7625 #define FW_ISP25XX	5
7626 #define FW_ISP81XX	6
7627 #define FW_ISP82XX	7
7628 #define FW_ISP2031	8
7629 #define FW_ISP8031	9
7630 #define FW_ISP27XX	10
7631 #define FW_ISP28XX	11
7632 
7633 #define FW_FILE_ISP21XX	"ql2100_fw.bin"
7634 #define FW_FILE_ISP22XX	"ql2200_fw.bin"
7635 #define FW_FILE_ISP2300	"ql2300_fw.bin"
7636 #define FW_FILE_ISP2322	"ql2322_fw.bin"
7637 #define FW_FILE_ISP24XX	"ql2400_fw.bin"
7638 #define FW_FILE_ISP25XX	"ql2500_fw.bin"
7639 #define FW_FILE_ISP81XX	"ql8100_fw.bin"
7640 #define FW_FILE_ISP82XX	"ql8200_fw.bin"
7641 #define FW_FILE_ISP2031	"ql2600_fw.bin"
7642 #define FW_FILE_ISP8031	"ql8300_fw.bin"
7643 #define FW_FILE_ISP27XX	"ql2700_fw.bin"
7644 #define FW_FILE_ISP28XX	"ql2800_fw.bin"
7645 
7646 
7647 static DEFINE_MUTEX(qla_fw_lock);
7648 
7649 static struct fw_blob qla_fw_blobs[] = {
7650 	{ .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
7651 	{ .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
7652 	{ .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
7653 	{ .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
7654 	{ .name = FW_FILE_ISP24XX, },
7655 	{ .name = FW_FILE_ISP25XX, },
7656 	{ .name = FW_FILE_ISP81XX, },
7657 	{ .name = FW_FILE_ISP82XX, },
7658 	{ .name = FW_FILE_ISP2031, },
7659 	{ .name = FW_FILE_ISP8031, },
7660 	{ .name = FW_FILE_ISP27XX, },
7661 	{ .name = FW_FILE_ISP28XX, },
7662 	{ .name = NULL, },
7663 };
7664 
7665 struct fw_blob *
qla2x00_request_firmware(scsi_qla_host_t * vha)7666 qla2x00_request_firmware(scsi_qla_host_t *vha)
7667 {
7668 	struct qla_hw_data *ha = vha->hw;
7669 	struct fw_blob *blob;
7670 
7671 	if (IS_QLA2100(ha)) {
7672 		blob = &qla_fw_blobs[FW_ISP21XX];
7673 	} else if (IS_QLA2200(ha)) {
7674 		blob = &qla_fw_blobs[FW_ISP22XX];
7675 	} else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
7676 		blob = &qla_fw_blobs[FW_ISP2300];
7677 	} else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
7678 		blob = &qla_fw_blobs[FW_ISP2322];
7679 	} else if (IS_QLA24XX_TYPE(ha)) {
7680 		blob = &qla_fw_blobs[FW_ISP24XX];
7681 	} else if (IS_QLA25XX(ha)) {
7682 		blob = &qla_fw_blobs[FW_ISP25XX];
7683 	} else if (IS_QLA81XX(ha)) {
7684 		blob = &qla_fw_blobs[FW_ISP81XX];
7685 	} else if (IS_QLA82XX(ha)) {
7686 		blob = &qla_fw_blobs[FW_ISP82XX];
7687 	} else if (IS_QLA2031(ha)) {
7688 		blob = &qla_fw_blobs[FW_ISP2031];
7689 	} else if (IS_QLA8031(ha)) {
7690 		blob = &qla_fw_blobs[FW_ISP8031];
7691 	} else if (IS_QLA27XX(ha)) {
7692 		blob = &qla_fw_blobs[FW_ISP27XX];
7693 	} else if (IS_QLA28XX(ha)) {
7694 		blob = &qla_fw_blobs[FW_ISP28XX];
7695 	} else {
7696 		return NULL;
7697 	}
7698 
7699 	if (!blob->name)
7700 		return NULL;
7701 
7702 	mutex_lock(&qla_fw_lock);
7703 	if (blob->fw)
7704 		goto out;
7705 
7706 	if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7707 		ql_log(ql_log_warn, vha, 0x0063,
7708 		    "Failed to load firmware image (%s).\n", blob->name);
7709 		blob->fw = NULL;
7710 		blob = NULL;
7711 	}
7712 
7713 out:
7714 	mutex_unlock(&qla_fw_lock);
7715 	return blob;
7716 }
7717 
7718 static void
qla2x00_release_firmware(void)7719 qla2x00_release_firmware(void)
7720 {
7721 	struct fw_blob *blob;
7722 
7723 	mutex_lock(&qla_fw_lock);
7724 	for (blob = qla_fw_blobs; blob->name; blob++)
7725 		release_firmware(blob->fw);
7726 	mutex_unlock(&qla_fw_lock);
7727 }
7728 
qla_pci_error_cleanup(scsi_qla_host_t * vha)7729 static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
7730 {
7731 	struct qla_hw_data *ha = vha->hw;
7732 	scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7733 	struct qla_qpair *qpair = NULL;
7734 	struct scsi_qla_host *vp, *tvp;
7735 	fc_port_t *fcport;
7736 	int i;
7737 	unsigned long flags;
7738 
7739 	ql_dbg(ql_dbg_aer, vha, 0x9000,
7740 	       "%s\n", __func__);
7741 	ha->chip_reset++;
7742 
7743 	ha->base_qpair->chip_reset = ha->chip_reset;
7744 	for (i = 0; i < ha->max_qpairs; i++) {
7745 		if (ha->queue_pair_map[i])
7746 			ha->queue_pair_map[i]->chip_reset =
7747 			    ha->base_qpair->chip_reset;
7748 	}
7749 
7750 	/*
7751 	 * purge mailbox might take a while. Slot Reset/chip reset
7752 	 * will take care of the purge
7753 	 */
7754 
7755 	mutex_lock(&ha->mq_lock);
7756 	ha->base_qpair->online = 0;
7757 	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7758 		qpair->online = 0;
7759 	wmb();
7760 	mutex_unlock(&ha->mq_lock);
7761 
7762 	qla2x00_mark_all_devices_lost(vha);
7763 
7764 	spin_lock_irqsave(&ha->vport_slock, flags);
7765 	list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7766 		atomic_inc(&vp->vref_count);
7767 		spin_unlock_irqrestore(&ha->vport_slock, flags);
7768 		qla2x00_mark_all_devices_lost(vp);
7769 		spin_lock_irqsave(&ha->vport_slock, flags);
7770 		atomic_dec(&vp->vref_count);
7771 	}
7772 	spin_unlock_irqrestore(&ha->vport_slock, flags);
7773 
7774 	/* Clear all async request states across all VPs. */
7775 	list_for_each_entry(fcport, &vha->vp_fcports, list)
7776 		fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7777 
7778 	spin_lock_irqsave(&ha->vport_slock, flags);
7779 	list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
7780 		atomic_inc(&vp->vref_count);
7781 		spin_unlock_irqrestore(&ha->vport_slock, flags);
7782 		list_for_each_entry(fcport, &vp->vp_fcports, list)
7783 			fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7784 		spin_lock_irqsave(&ha->vport_slock, flags);
7785 		atomic_dec(&vp->vref_count);
7786 	}
7787 	spin_unlock_irqrestore(&ha->vport_slock, flags);
7788 }
7789 
7790 
7791 static pci_ers_result_t
qla2xxx_pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)7792 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
7793 {
7794 	scsi_qla_host_t *vha = pci_get_drvdata(pdev);
7795 	struct qla_hw_data *ha = vha->hw;
7796 	pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET;
7797 
7798 	ql_log(ql_log_warn, vha, 0x9000,
7799 	       "PCI error detected, state %x.\n", state);
7800 	ha->pci_error_state = QLA_PCI_ERR_DETECTED;
7801 
7802 	if (!atomic_read(&pdev->enable_cnt)) {
7803 		ql_log(ql_log_info, vha, 0xffff,
7804 			"PCI device is disabled,state %x\n", state);
7805 		ret = PCI_ERS_RESULT_NEED_RESET;
7806 		goto out;
7807 	}
7808 
7809 	switch (state) {
7810 	case pci_channel_io_normal:
7811 		qla_pci_set_eeh_busy(vha);
7812 		if (ql2xmqsupport || ql2xnvmeenable) {
7813 			set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7814 			qla2xxx_wake_dpc(vha);
7815 		}
7816 		ret = PCI_ERS_RESULT_CAN_RECOVER;
7817 		break;
7818 	case pci_channel_io_frozen:
7819 		qla_pci_set_eeh_busy(vha);
7820 		ret = PCI_ERS_RESULT_NEED_RESET;
7821 		break;
7822 	case pci_channel_io_perm_failure:
7823 		ha->flags.pci_channel_io_perm_failure = 1;
7824 		qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
7825 		if (ql2xmqsupport || ql2xnvmeenable) {
7826 			set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7827 			qla2xxx_wake_dpc(vha);
7828 		}
7829 		ret = PCI_ERS_RESULT_DISCONNECT;
7830 	}
7831 out:
7832 	ql_dbg(ql_dbg_aer, vha, 0x600d,
7833 	       "PCI error detected returning [%x].\n", ret);
7834 	return ret;
7835 }
7836 
7837 static pci_ers_result_t
qla2xxx_pci_mmio_enabled(struct pci_dev * pdev)7838 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
7839 {
7840 	int risc_paused = 0;
7841 	uint32_t stat;
7842 	unsigned long flags;
7843 	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7844 	struct qla_hw_data *ha = base_vha->hw;
7845 	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7846 	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
7847 
7848 	ql_log(ql_log_warn, base_vha, 0x9000,
7849 	       "mmio enabled\n");
7850 
7851 	ha->pci_error_state = QLA_PCI_MMIO_ENABLED;
7852 
7853 	if (IS_QLA82XX(ha))
7854 		return PCI_ERS_RESULT_RECOVERED;
7855 
7856 	if (qla2x00_isp_reg_stat(ha)) {
7857 		ql_log(ql_log_info, base_vha, 0x803f,
7858 		    "During mmio enabled, PCI/Register disconnect still detected.\n");
7859 		goto out;
7860 	}
7861 
7862 	spin_lock_irqsave(&ha->hardware_lock, flags);
7863 	if (IS_QLA2100(ha) || IS_QLA2200(ha)){
7864 		stat = rd_reg_word(&reg->hccr);
7865 		if (stat & HCCR_RISC_PAUSE)
7866 			risc_paused = 1;
7867 	} else if (IS_QLA23XX(ha)) {
7868 		stat = rd_reg_dword(&reg->u.isp2300.host_status);
7869 		if (stat & HSR_RISC_PAUSED)
7870 			risc_paused = 1;
7871 	} else if (IS_FWI2_CAPABLE(ha)) {
7872 		stat = rd_reg_dword(&reg24->host_status);
7873 		if (stat & HSRX_RISC_PAUSED)
7874 			risc_paused = 1;
7875 	}
7876 	spin_unlock_irqrestore(&ha->hardware_lock, flags);
7877 
7878 	if (risc_paused) {
7879 		ql_log(ql_log_info, base_vha, 0x9003,
7880 		    "RISC paused -- mmio_enabled, Dumping firmware.\n");
7881 		qla2xxx_dump_fw(base_vha);
7882 	}
7883 out:
7884 	/* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */
7885 	ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7886 	       "mmio enabled returning.\n");
7887 	return PCI_ERS_RESULT_NEED_RESET;
7888 }
7889 
7890 static pci_ers_result_t
qla2xxx_pci_slot_reset(struct pci_dev * pdev)7891 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7892 {
7893 	pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
7894 	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7895 	struct qla_hw_data *ha = base_vha->hw;
7896 	int rc;
7897 	struct qla_qpair *qpair = NULL;
7898 
7899 	ql_log(ql_log_warn, base_vha, 0x9004,
7900 	       "Slot Reset.\n");
7901 
7902 	ha->pci_error_state = QLA_PCI_SLOT_RESET;
7903 	/* Workaround: qla2xxx driver which access hardware earlier
7904 	 * needs error state to be pci_channel_io_online.
7905 	 * Otherwise mailbox command timesout.
7906 	 */
7907 	pdev->error_state = pci_channel_io_normal;
7908 
7909 	pci_restore_state(pdev);
7910 
7911 	/* pci_restore_state() clears the saved_state flag of the device
7912 	 * save restored state which resets saved_state flag
7913 	 */
7914 	pci_save_state(pdev);
7915 
7916 	if (ha->mem_only)
7917 		rc = pci_enable_device_mem(pdev);
7918 	else
7919 		rc = pci_enable_device(pdev);
7920 
7921 	if (rc) {
7922 		ql_log(ql_log_warn, base_vha, 0x9005,
7923 		    "Can't re-enable PCI device after reset.\n");
7924 		goto exit_slot_reset;
7925 	}
7926 
7927 
7928 	if (ha->isp_ops->pci_config(base_vha))
7929 		goto exit_slot_reset;
7930 
7931 	mutex_lock(&ha->mq_lock);
7932 	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7933 		qpair->online = 1;
7934 	mutex_unlock(&ha->mq_lock);
7935 
7936 	ha->flags.eeh_busy = 0;
7937 	base_vha->flags.online = 1;
7938 	set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7939 	ha->isp_ops->abort_isp(base_vha);
7940 	clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7941 
7942 	if (qla2x00_isp_reg_stat(ha)) {
7943 		ha->flags.eeh_busy = 1;
7944 		qla_pci_error_cleanup(base_vha);
7945 		ql_log(ql_log_warn, base_vha, 0x9005,
7946 		       "Device unable to recover from PCI error.\n");
7947 	} else {
7948 		ret =  PCI_ERS_RESULT_RECOVERED;
7949 	}
7950 
7951 exit_slot_reset:
7952 	ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7953 	    "Slot Reset returning %x.\n", ret);
7954 
7955 	return ret;
7956 }
7957 
7958 static void
qla2xxx_pci_resume(struct pci_dev * pdev)7959 qla2xxx_pci_resume(struct pci_dev *pdev)
7960 {
7961 	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7962 	struct qla_hw_data *ha = base_vha->hw;
7963 	int ret;
7964 
7965 	ql_log(ql_log_warn, base_vha, 0x900f,
7966 	       "Pci Resume.\n");
7967 
7968 
7969 	ret = qla2x00_wait_for_hba_online(base_vha);
7970 	if (ret != QLA_SUCCESS) {
7971 		ql_log(ql_log_fatal, base_vha, 0x9002,
7972 		    "The device failed to resume I/O from slot/link_reset.\n");
7973 	}
7974 	ha->pci_error_state = QLA_PCI_RESUME;
7975 	ql_dbg(ql_dbg_aer, base_vha, 0x600d,
7976 	       "Pci Resume returning.\n");
7977 }
7978 
qla_pci_set_eeh_busy(struct scsi_qla_host * vha)7979 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha)
7980 {
7981 	struct qla_hw_data *ha = vha->hw;
7982 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7983 	bool do_cleanup = false;
7984 	unsigned long flags;
7985 
7986 	if (ha->flags.eeh_busy)
7987 		return;
7988 
7989 	spin_lock_irqsave(&base_vha->work_lock, flags);
7990 	if (!ha->flags.eeh_busy) {
7991 		ha->eeh_jif = jiffies;
7992 		ha->flags.eeh_flush = 0;
7993 
7994 		ha->flags.eeh_busy = 1;
7995 		do_cleanup = true;
7996 	}
7997 	spin_unlock_irqrestore(&base_vha->work_lock, flags);
7998 
7999 	if (do_cleanup)
8000 		qla_pci_error_cleanup(base_vha);
8001 }
8002 
8003 /*
8004  * this routine will schedule a task to pause IO from interrupt context
8005  * if caller sees a PCIE error event (register read = 0xf's)
8006  */
qla_schedule_eeh_work(struct scsi_qla_host * vha)8007 void qla_schedule_eeh_work(struct scsi_qla_host *vha)
8008 {
8009 	struct qla_hw_data *ha = vha->hw;
8010 	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
8011 
8012 	if (ha->flags.eeh_busy)
8013 		return;
8014 
8015 	set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags);
8016 	qla2xxx_wake_dpc(base_vha);
8017 }
8018 
8019 static void
qla_pci_reset_prepare(struct pci_dev * pdev)8020 qla_pci_reset_prepare(struct pci_dev *pdev)
8021 {
8022 	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8023 	struct qla_hw_data *ha = base_vha->hw;
8024 	struct qla_qpair *qpair;
8025 
8026 	ql_log(ql_log_warn, base_vha, 0xffff,
8027 	    "%s.\n", __func__);
8028 
8029 	/*
8030 	 * PCI FLR/function reset is about to reset the
8031 	 * slot. Stop the chip to stop all DMA access.
8032 	 * It is assumed that pci_reset_done will be called
8033 	 * after FLR to resume Chip operation.
8034 	 */
8035 	ha->flags.eeh_busy = 1;
8036 	mutex_lock(&ha->mq_lock);
8037 	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8038 		qpair->online = 0;
8039 	mutex_unlock(&ha->mq_lock);
8040 
8041 	set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8042 	qla2x00_abort_isp_cleanup(base_vha);
8043 	qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
8044 }
8045 
8046 static void
qla_pci_reset_done(struct pci_dev * pdev)8047 qla_pci_reset_done(struct pci_dev *pdev)
8048 {
8049 	scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
8050 	struct qla_hw_data *ha = base_vha->hw;
8051 	struct qla_qpair *qpair;
8052 
8053 	ql_log(ql_log_warn, base_vha, 0xffff,
8054 	    "%s.\n", __func__);
8055 
8056 	/*
8057 	 * FLR just completed by PCI layer. Resume adapter
8058 	 */
8059 	ha->flags.eeh_busy = 0;
8060 	mutex_lock(&ha->mq_lock);
8061 	list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
8062 		qpair->online = 1;
8063 	mutex_unlock(&ha->mq_lock);
8064 
8065 	base_vha->flags.online = 1;
8066 	ha->isp_ops->abort_isp(base_vha);
8067 	clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
8068 }
8069 
qla2xxx_map_queues(struct Scsi_Host * shost)8070 static void qla2xxx_map_queues(struct Scsi_Host *shost)
8071 {
8072 	scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
8073 	struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
8074 
8075 	if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
8076 		blk_mq_map_queues(qmap);
8077 	else
8078 		blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
8079 }
8080 
8081 struct scsi_host_template qla2xxx_driver_template = {
8082 	.module			= THIS_MODULE,
8083 	.name			= QLA2XXX_DRIVER_NAME,
8084 	.queuecommand		= qla2xxx_queuecommand,
8085 
8086 	.eh_timed_out		= fc_eh_timed_out,
8087 	.eh_abort_handler	= qla2xxx_eh_abort,
8088 	.eh_should_retry_cmd	= fc_eh_should_retry_cmd,
8089 	.eh_device_reset_handler = qla2xxx_eh_device_reset,
8090 	.eh_target_reset_handler = qla2xxx_eh_target_reset,
8091 	.eh_bus_reset_handler	= qla2xxx_eh_bus_reset,
8092 	.eh_host_reset_handler	= qla2xxx_eh_host_reset,
8093 
8094 	.slave_configure	= qla2xxx_slave_configure,
8095 
8096 	.slave_alloc		= qla2xxx_slave_alloc,
8097 	.slave_destroy		= qla2xxx_slave_destroy,
8098 	.scan_finished		= qla2xxx_scan_finished,
8099 	.scan_start		= qla2xxx_scan_start,
8100 	.change_queue_depth	= scsi_change_queue_depth,
8101 	.map_queues             = qla2xxx_map_queues,
8102 	.this_id		= -1,
8103 	.cmd_per_lun		= 3,
8104 	.sg_tablesize		= SG_ALL,
8105 
8106 	.max_sectors		= 0xFFFF,
8107 	.shost_groups		= qla2x00_host_groups,
8108 
8109 	.supported_mode		= MODE_INITIATOR,
8110 	.track_queue_depth	= 1,
8111 	.cmd_size		= sizeof(srb_t),
8112 };
8113 
8114 static const struct pci_error_handlers qla2xxx_err_handler = {
8115 	.error_detected = qla2xxx_pci_error_detected,
8116 	.mmio_enabled = qla2xxx_pci_mmio_enabled,
8117 	.slot_reset = qla2xxx_pci_slot_reset,
8118 	.resume = qla2xxx_pci_resume,
8119 	.reset_prepare = qla_pci_reset_prepare,
8120 	.reset_done = qla_pci_reset_done,
8121 };
8122 
8123 static struct pci_device_id qla2xxx_pci_tbl[] = {
8124 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
8125 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
8126 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
8127 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
8128 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
8129 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
8130 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
8131 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
8132 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
8133 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
8134 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
8135 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
8136 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
8137 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
8138 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
8139 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
8140 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8141 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
8142 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
8143 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
8144 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
8145 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
8146 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
8147 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
8148 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
8149 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
8150 	{ PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
8151 	{ 0 },
8152 };
8153 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
8154 
8155 static struct pci_driver qla2xxx_pci_driver = {
8156 	.name		= QLA2XXX_DRIVER_NAME,
8157 	.driver		= {
8158 		.owner		= THIS_MODULE,
8159 	},
8160 	.id_table	= qla2xxx_pci_tbl,
8161 	.probe		= qla2x00_probe_one,
8162 	.remove		= qla2x00_remove_one,
8163 	.shutdown	= qla2x00_shutdown,
8164 	.err_handler	= &qla2xxx_err_handler,
8165 };
8166 
8167 static const struct file_operations apidev_fops = {
8168 	.owner = THIS_MODULE,
8169 	.llseek = noop_llseek,
8170 };
8171 
8172 /**
8173  * qla2x00_module_init - Module initialization.
8174  **/
8175 static int __init
qla2x00_module_init(void)8176 qla2x00_module_init(void)
8177 {
8178 	int ret = 0;
8179 
8180 	BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
8181 	BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
8182 	BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
8183 	BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
8184 	BUILD_BUG_ON(sizeof(init_cb_t) != 96);
8185 	BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
8186 	BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
8187 	BUILD_BUG_ON(sizeof(request_t) != 64);
8188 	BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
8189 	BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
8190 	BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
8191 	BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
8192 	BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
8193 	BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
8194 	BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
8195 	BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
8196 	BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
8197 	BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
8198 	BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
8199 	BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
8200 	BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604);
8201 	BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
8202 	BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
8203 	BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
8204 	BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
8205 	BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
8206 	BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
8207 	BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
8208 	BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
8209 	BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
8210 	BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
8211 	BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
8212 	BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
8213 	BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
8214 	BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
8215 	BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
8216 	BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
8217 	BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
8218 	BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
8219 	BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
8220 	BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
8221 	BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
8222 	BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
8223 	BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
8224 	BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
8225 	BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
8226 	BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
8227 	BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
8228 	BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
8229 	BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
8230 	BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
8231 	BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
8232 	BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
8233 	BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
8234 	BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
8235 	BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
8236 	BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
8237 	BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
8238 	BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
8239 	BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
8240 	BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
8241 	BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
8242 	BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
8243 	BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
8244 	BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
8245 	BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
8246 	BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
8247 	BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
8248 	BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
8249 	BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
8250 	BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
8251 	BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
8252 	BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
8253 	BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
8254 	BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
8255 	BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
8256 	BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
8257 	BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
8258 	BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
8259 	BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
8260 	BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
8261 	BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
8262 	BUILD_BUG_ON(sizeof(sw_info_t) != 32);
8263 	BUILD_BUG_ON(sizeof(target_id_t) != 2);
8264 
8265 	qla_trace_init();
8266 
8267 	/* Allocate cache for SRBs. */
8268 	srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
8269 	    SLAB_HWCACHE_ALIGN, NULL);
8270 	if (srb_cachep == NULL) {
8271 		ql_log(ql_log_fatal, NULL, 0x0001,
8272 		    "Unable to allocate SRB cache...Failing load!.\n");
8273 		return -ENOMEM;
8274 	}
8275 
8276 	/* Initialize target kmem_cache and mem_pools */
8277 	ret = qlt_init();
8278 	if (ret < 0) {
8279 		goto destroy_cache;
8280 	} else if (ret > 0) {
8281 		/*
8282 		 * If initiator mode is explictly disabled by qlt_init(),
8283 		 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
8284 		 * performing scsi_scan_target() during LOOP UP event.
8285 		 */
8286 		qla2xxx_transport_functions.disable_target_scan = 1;
8287 		qla2xxx_transport_vport_functions.disable_target_scan = 1;
8288 	}
8289 
8290 	/* Derive version string. */
8291 	strcpy(qla2x00_version_str, QLA2XXX_VERSION);
8292 	if (ql2xextended_error_logging)
8293 		strcat(qla2x00_version_str, "-debug");
8294 	if (ql2xextended_error_logging == 1)
8295 		ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
8296 
8297 	qla2xxx_transport_template =
8298 	    fc_attach_transport(&qla2xxx_transport_functions);
8299 	if (!qla2xxx_transport_template) {
8300 		ql_log(ql_log_fatal, NULL, 0x0002,
8301 		    "fc_attach_transport failed...Failing load!.\n");
8302 		ret = -ENODEV;
8303 		goto qlt_exit;
8304 	}
8305 
8306 	apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
8307 	if (apidev_major < 0) {
8308 		ql_log(ql_log_fatal, NULL, 0x0003,
8309 		    "Unable to register char device %s.\n", QLA2XXX_APIDEV);
8310 	}
8311 
8312 	qla2xxx_transport_vport_template =
8313 	    fc_attach_transport(&qla2xxx_transport_vport_functions);
8314 	if (!qla2xxx_transport_vport_template) {
8315 		ql_log(ql_log_fatal, NULL, 0x0004,
8316 		    "fc_attach_transport vport failed...Failing load!.\n");
8317 		ret = -ENODEV;
8318 		goto unreg_chrdev;
8319 	}
8320 	ql_log(ql_log_info, NULL, 0x0005,
8321 	    "QLogic Fibre Channel HBA Driver: %s.\n",
8322 	    qla2x00_version_str);
8323 	ret = pci_register_driver(&qla2xxx_pci_driver);
8324 	if (ret) {
8325 		ql_log(ql_log_fatal, NULL, 0x0006,
8326 		    "pci_register_driver failed...ret=%d Failing load!.\n",
8327 		    ret);
8328 		goto release_vport_transport;
8329 	}
8330 	return ret;
8331 
8332 release_vport_transport:
8333 	fc_release_transport(qla2xxx_transport_vport_template);
8334 
8335 unreg_chrdev:
8336 	if (apidev_major >= 0)
8337 		unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8338 	fc_release_transport(qla2xxx_transport_template);
8339 
8340 qlt_exit:
8341 	qlt_exit();
8342 
8343 destroy_cache:
8344 	kmem_cache_destroy(srb_cachep);
8345 
8346 	qla_trace_uninit();
8347 	return ret;
8348 }
8349 
8350 /**
8351  * qla2x00_module_exit - Module cleanup.
8352  **/
8353 static void __exit
qla2x00_module_exit(void)8354 qla2x00_module_exit(void)
8355 {
8356 	pci_unregister_driver(&qla2xxx_pci_driver);
8357 	qla2x00_release_firmware();
8358 	kmem_cache_destroy(ctx_cachep);
8359 	fc_release_transport(qla2xxx_transport_vport_template);
8360 	if (apidev_major >= 0)
8361 		unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8362 	fc_release_transport(qla2xxx_transport_template);
8363 	qlt_exit();
8364 	kmem_cache_destroy(srb_cachep);
8365 	qla_trace_uninit();
8366 }
8367 
8368 module_init(qla2x00_module_init);
8369 module_exit(qla2x00_module_exit);
8370 
8371 MODULE_AUTHOR("QLogic Corporation");
8372 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
8373 MODULE_LICENSE("GPL");
8374 MODULE_FIRMWARE(FW_FILE_ISP21XX);
8375 MODULE_FIRMWARE(FW_FILE_ISP22XX);
8376 MODULE_FIRMWARE(FW_FILE_ISP2300);
8377 MODULE_FIRMWARE(FW_FILE_ISP2322);
8378 MODULE_FIRMWARE(FW_FILE_ISP24XX);
8379 MODULE_FIRMWARE(FW_FILE_ISP25XX);
8380