1 /*
2 * linux/drivers/ide/legacy/q40ide.c -- Q40 I/O port IDE Driver
3 *
4 * (c) Richard Zidlicky
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 *
11 */
12
13 #include <linux/types.h>
14 #include <linux/mm.h>
15 #include <linux/interrupt.h>
16 #include <linux/blkdev.h>
17 #include <linux/hdreg.h>
18
19 #include <linux/ide.h>
20
21 /*
22 * Bases of the IDE interfaces
23 */
24
25 #define Q40IDE_NUM_HWIFS 2
26
27 #define PCIDE_BASE1 0x1f0
28 #define PCIDE_BASE2 0x170
29 #define PCIDE_BASE3 0x1e8
30 #define PCIDE_BASE4 0x168
31 #define PCIDE_BASE5 0x1e0
32 #define PCIDE_BASE6 0x160
33
34 static const ide_ioreg_t pcide_bases[Q40IDE_NUM_HWIFS] = {
35 PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4 , PCIDE_BASE5,
36 PCIDE_BASE6 */
37 };
38
39
40 /*
41 * Offsets from one of the above bases
42 */
43
44 /* used to do addr translation here but it is easier to do in setup ports */
45 /*#define IDE_OFF_B(x) ((unsigned long)Q40_ISA_IO_B((IDE_##x##_OFFSET)))*/
46
47 #define IDE_OFF_B(x) ((ide_ioreg_t)((IDE_##x##_OFFSET)))
48 #define IDE_OFF_W(x) ((ide_ioreg_t)((IDE_##x##_OFFSET)))
49
50 static const int pcide_offsets[IDE_NR_PORTS] = {
51 IDE_OFF_W(DATA), IDE_OFF_B(ERROR), IDE_OFF_B(NSECTOR), IDE_OFF_B(SECTOR),
52 IDE_OFF_B(LCYL), IDE_OFF_B(HCYL), 6 /*IDE_OFF_B(CURRENT)*/, IDE_OFF_B(STATUS),
53 518/*IDE_OFF(CMD)*/
54 };
55
q40ide_default_irq(ide_ioreg_t base)56 static int q40ide_default_irq(ide_ioreg_t base)
57 {
58 switch (base) {
59 case 0x1f0: return 14;
60 case 0x170: return 15;
61 case 0x1e8: return 11;
62 default:
63 return 0;
64 }
65 }
66
67
68 /*
69 * This is very similar to ide_setup_ports except that addresses
70 * are pretranslated for q40 ISA access
71 */
q40_ide_setup_ports(hw_regs_t * hw,ide_ioreg_t base,int * offsets,ide_ioreg_t ctrl,ide_ioreg_t intr,ide_ack_intr_t * ack_intr,int irq)72 void q40_ide_setup_ports ( hw_regs_t *hw,
73 ide_ioreg_t base, int *offsets,
74 ide_ioreg_t ctrl, ide_ioreg_t intr,
75 ide_ack_intr_t *ack_intr,
76 /*
77 * ide_io_ops_t *iops,
78 */
79 int irq)
80 {
81 int i;
82
83 for (i = 0; i < IDE_NR_PORTS; i++) {
84 /* BIG FAT WARNING:
85 assumption: only DATA port is ever used in 16 bit mode */
86 if ( i==0 )
87 hw->io_ports[i] = Q40_ISA_IO_W(base + offsets[i]);
88 else
89 hw->io_ports[i] = Q40_ISA_IO_B(base + offsets[i]);
90 }
91
92 hw->irq = irq;
93 hw->dma = NO_DMA;
94 hw->ack_intr = ack_intr;
95 /*
96 * hw->iops = iops;
97 */
98 }
99
100
101
102 /*
103 * the static array is needed to have the name reported in /proc/ioports,
104 * hwif->name unfortunately isn�t available yet
105 */
106 static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
107 "ide0", "ide1"
108 };
109
110 /*
111 * Probe for Q40 IDE interfaces
112 */
113
q40ide_init(void)114 void q40ide_init(void)
115 {
116 int i;
117 ide_hwif_t *hwif;
118 int index;
119 const char *name;
120
121 if (!MACH_IS_Q40)
122 return ;
123
124 for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
125 hw_regs_t hw;
126
127 name = q40_ide_names[i];
128 if (!request_region(pcide_bases[i], 8, name)) {
129 printk("could not reserve ports %lx-%lx for %s\n",
130 pcide_bases[i],pcide_bases[i]+8,name);
131 continue;
132 }
133 if (!request_region(pcide_bases[i]+0x206, 1, name)) {
134 printk("could not reserve port %lx for %s\n",
135 pcide_bases[i]+0x206,name);
136 release_region(pcide_bases[i], 8);
137 continue;
138 }
139 q40_ide_setup_ports(&hw, (ide_ioreg_t)pcide_bases[i],
140 (int *)pcide_offsets,
141 (ide_ioreg_t)pcide_bases[i]+0x206, 0, NULL,
142 // m68kide_iops,
143 q40ide_default_irq(pcide_bases[i]));
144 index = ide_register_hw(&hw, &hwif);
145 // **FIXME**
146 if (index != -1)
147 hwif->mmio = 2;
148 }
149 }
150
151