1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2012 ARM Ltd.
4  */
5 #ifndef __ASM_PGTABLE_H
6 #define __ASM_PGTABLE_H
7 
8 #include <asm/bug.h>
9 #include <asm/proc-fns.h>
10 
11 #include <asm/memory.h>
12 #include <asm/mte.h>
13 #include <asm/pgtable-hwdef.h>
14 #include <asm/pgtable-prot.h>
15 #include <asm/tlbflush.h>
16 
17 /*
18  * VMALLOC range.
19  *
20  * VMALLOC_START: beginning of the kernel vmalloc space
21  * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space
22  *	and fixed mappings
23  */
24 #define VMALLOC_START		(MODULES_END)
25 #define VMALLOC_END		(VMEMMAP_START - SZ_256M)
26 
27 #define vmemmap			((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
28 
29 #ifndef __ASSEMBLY__
30 
31 #include <asm/cmpxchg.h>
32 #include <asm/fixmap.h>
33 #include <linux/mmdebug.h>
34 #include <linux/mm_types.h>
35 #include <linux/sched.h>
36 #include <linux/page_table_check.h>
37 
38 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
39 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
40 
41 /* Set stride and tlb_level in flush_*_tlb_range */
42 #define flush_pmd_tlb_range(vma, addr, end)	\
43 	__flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
44 #define flush_pud_tlb_range(vma, addr, end)	\
45 	__flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
46 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
47 
48 /*
49  * Outside of a few very special situations (e.g. hibernation), we always
50  * use broadcast TLB invalidation instructions, therefore a spurious page
51  * fault on one CPU which has been handled concurrently by another CPU
52  * does not need to perform additional invalidation.
53  */
54 #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0)
55 
56 /*
57  * ZERO_PAGE is a global shared page that is always zero: used
58  * for zero-mapped memory areas etc..
59  */
60 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
61 #define ZERO_PAGE(vaddr)	phys_to_page(__pa_symbol(empty_zero_page))
62 
63 #define pte_ERROR(e)	\
64 	pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
65 
66 /*
67  * Macros to convert between a physical address and its placement in a
68  * page table entry, taking care of 52-bit addresses.
69  */
70 #ifdef CONFIG_ARM64_PA_BITS_52
__pte_to_phys(pte_t pte)71 static inline phys_addr_t __pte_to_phys(pte_t pte)
72 {
73 	return (pte_val(pte) & PTE_ADDR_LOW) |
74 		((pte_val(pte) & PTE_ADDR_HIGH) << 36);
75 }
__phys_to_pte_val(phys_addr_t phys)76 static inline pteval_t __phys_to_pte_val(phys_addr_t phys)
77 {
78 	return (phys | (phys >> 36)) & PTE_ADDR_MASK;
79 }
80 #else
81 #define __pte_to_phys(pte)	(pte_val(pte) & PTE_ADDR_MASK)
82 #define __phys_to_pte_val(phys)	(phys)
83 #endif
84 
85 #define pte_pfn(pte)		(__pte_to_phys(pte) >> PAGE_SHIFT)
86 #define pfn_pte(pfn,prot)	\
87 	__pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
88 
89 #define pte_none(pte)		(!pte_val(pte))
90 #define pte_clear(mm,addr,ptep)	set_pte(ptep, __pte(0))
91 #define pte_page(pte)		(pfn_to_page(pte_pfn(pte)))
92 
93 /*
94  * The following only work if pte_present(). Undefined behaviour otherwise.
95  */
96 #define pte_present(pte)	(!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
97 #define pte_young(pte)		(!!(pte_val(pte) & PTE_AF))
98 #define pte_special(pte)	(!!(pte_val(pte) & PTE_SPECIAL))
99 #define pte_write(pte)		(!!(pte_val(pte) & PTE_WRITE))
100 #define pte_user(pte)		(!!(pte_val(pte) & PTE_USER))
101 #define pte_user_exec(pte)	(!(pte_val(pte) & PTE_UXN))
102 #define pte_cont(pte)		(!!(pte_val(pte) & PTE_CONT))
103 #define pte_devmap(pte)		(!!(pte_val(pte) & PTE_DEVMAP))
104 #define pte_tagged(pte)		((pte_val(pte) & PTE_ATTRINDX_MASK) == \
105 				 PTE_ATTRINDX(MT_NORMAL_TAGGED))
106 
107 #define pte_cont_addr_end(addr, end)						\
108 ({	unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK;	\
109 	(__boundary - 1 < (end) - 1) ? __boundary : (end);			\
110 })
111 
112 #define pmd_cont_addr_end(addr, end)						\
113 ({	unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK;	\
114 	(__boundary - 1 < (end) - 1) ? __boundary : (end);			\
115 })
116 
117 #define pte_hw_dirty(pte)	(pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
118 #define pte_sw_dirty(pte)	(!!(pte_val(pte) & PTE_DIRTY))
119 #define pte_dirty(pte)		(pte_sw_dirty(pte) || pte_hw_dirty(pte))
120 
121 #define pte_valid(pte)		(!!(pte_val(pte) & PTE_VALID))
122 /*
123  * Execute-only user mappings do not have the PTE_USER bit set. All valid
124  * kernel mappings have the PTE_UXN bit set.
125  */
126 #define pte_valid_not_user(pte) \
127 	((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN))
128 /*
129  * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
130  * so that we don't erroneously return false for pages that have been
131  * remapped as PROT_NONE but are yet to be flushed from the TLB.
132  * Note that we can't make any assumptions based on the state of the access
133  * flag, since ptep_clear_flush_young() elides a DSB when invalidating the
134  * TLB.
135  */
136 #define pte_accessible(mm, pte)	\
137 	(mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
138 
139 /*
140  * p??_access_permitted() is true for valid user mappings (PTE_USER
141  * bit set, subject to the write permission check). For execute-only
142  * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits
143  * not set) must return false. PROT_NONE mappings do not have the
144  * PTE_VALID bit set.
145  */
146 #define pte_access_permitted(pte, write) \
147 	(((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte)))
148 #define pmd_access_permitted(pmd, write) \
149 	(pte_access_permitted(pmd_pte(pmd), (write)))
150 #define pud_access_permitted(pud, write) \
151 	(pte_access_permitted(pud_pte(pud), (write)))
152 
clear_pte_bit(pte_t pte,pgprot_t prot)153 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
154 {
155 	pte_val(pte) &= ~pgprot_val(prot);
156 	return pte;
157 }
158 
set_pte_bit(pte_t pte,pgprot_t prot)159 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
160 {
161 	pte_val(pte) |= pgprot_val(prot);
162 	return pte;
163 }
164 
clear_pmd_bit(pmd_t pmd,pgprot_t prot)165 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
166 {
167 	pmd_val(pmd) &= ~pgprot_val(prot);
168 	return pmd;
169 }
170 
set_pmd_bit(pmd_t pmd,pgprot_t prot)171 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
172 {
173 	pmd_val(pmd) |= pgprot_val(prot);
174 	return pmd;
175 }
176 
pte_mkwrite(pte_t pte)177 static inline pte_t pte_mkwrite(pte_t pte)
178 {
179 	pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
180 	pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
181 	return pte;
182 }
183 
pte_mkclean(pte_t pte)184 static inline pte_t pte_mkclean(pte_t pte)
185 {
186 	pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
187 	pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
188 
189 	return pte;
190 }
191 
pte_mkdirty(pte_t pte)192 static inline pte_t pte_mkdirty(pte_t pte)
193 {
194 	pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
195 
196 	if (pte_write(pte))
197 		pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
198 
199 	return pte;
200 }
201 
pte_wrprotect(pte_t pte)202 static inline pte_t pte_wrprotect(pte_t pte)
203 {
204 	/*
205 	 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
206 	 * clear), set the PTE_DIRTY bit.
207 	 */
208 	if (pte_hw_dirty(pte))
209 		pte = pte_mkdirty(pte);
210 
211 	pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
212 	pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
213 	return pte;
214 }
215 
pte_mkold(pte_t pte)216 static inline pte_t pte_mkold(pte_t pte)
217 {
218 	return clear_pte_bit(pte, __pgprot(PTE_AF));
219 }
220 
pte_mkyoung(pte_t pte)221 static inline pte_t pte_mkyoung(pte_t pte)
222 {
223 	return set_pte_bit(pte, __pgprot(PTE_AF));
224 }
225 
pte_mkspecial(pte_t pte)226 static inline pte_t pte_mkspecial(pte_t pte)
227 {
228 	return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
229 }
230 
pte_mkcont(pte_t pte)231 static inline pte_t pte_mkcont(pte_t pte)
232 {
233 	pte = set_pte_bit(pte, __pgprot(PTE_CONT));
234 	return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
235 }
236 
pte_mknoncont(pte_t pte)237 static inline pte_t pte_mknoncont(pte_t pte)
238 {
239 	return clear_pte_bit(pte, __pgprot(PTE_CONT));
240 }
241 
pte_mkpresent(pte_t pte)242 static inline pte_t pte_mkpresent(pte_t pte)
243 {
244 	return set_pte_bit(pte, __pgprot(PTE_VALID));
245 }
246 
pmd_mkcont(pmd_t pmd)247 static inline pmd_t pmd_mkcont(pmd_t pmd)
248 {
249 	return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
250 }
251 
pte_mkdevmap(pte_t pte)252 static inline pte_t pte_mkdevmap(pte_t pte)
253 {
254 	return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
255 }
256 
set_pte(pte_t * ptep,pte_t pte)257 static inline void set_pte(pte_t *ptep, pte_t pte)
258 {
259 	WRITE_ONCE(*ptep, pte);
260 
261 	/*
262 	 * Only if the new pte is valid and kernel, otherwise TLB maintenance
263 	 * or update_mmu_cache() have the necessary barriers.
264 	 */
265 	if (pte_valid_not_user(pte)) {
266 		dsb(ishst);
267 		isb();
268 	}
269 }
270 
271 extern void __sync_icache_dcache(pte_t pteval);
272 
273 /*
274  * PTE bits configuration in the presence of hardware Dirty Bit Management
275  * (PTE_WRITE == PTE_DBM):
276  *
277  * Dirty  Writable | PTE_RDONLY  PTE_WRITE  PTE_DIRTY (sw)
278  *   0      0      |   1           0          0
279  *   0      1      |   1           1          0
280  *   1      0      |   1           0          1
281  *   1      1      |   0           1          x
282  *
283  * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
284  * the page fault mechanism. Checking the dirty status of a pte becomes:
285  *
286  *   PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
287  */
288 
__check_racy_pte_update(struct mm_struct * mm,pte_t * ptep,pte_t pte)289 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep,
290 					   pte_t pte)
291 {
292 	pte_t old_pte;
293 
294 	if (!IS_ENABLED(CONFIG_DEBUG_VM))
295 		return;
296 
297 	old_pte = READ_ONCE(*ptep);
298 
299 	if (!pte_valid(old_pte) || !pte_valid(pte))
300 		return;
301 	if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
302 		return;
303 
304 	/*
305 	 * Check for potential race with hardware updates of the pte
306 	 * (ptep_set_access_flags safely changes valid ptes without going
307 	 * through an invalid entry).
308 	 */
309 	VM_WARN_ONCE(!pte_young(pte),
310 		     "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
311 		     __func__, pte_val(old_pte), pte_val(pte));
312 	VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
313 		     "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
314 		     __func__, pte_val(old_pte), pte_val(pte));
315 }
316 
__set_pte_at(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pte)317 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
318 				pte_t *ptep, pte_t pte)
319 {
320 	if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
321 		__sync_icache_dcache(pte);
322 
323 	/*
324 	 * If the PTE would provide user space access to the tags associated
325 	 * with it then ensure that the MTE tags are synchronised.  Although
326 	 * pte_access_permitted() returns false for exec only mappings, they
327 	 * don't expose tags (instruction fetches don't check tags).
328 	 */
329 	if (system_supports_mte() && pte_access_permitted(pte, false) &&
330 	    !pte_special(pte)) {
331 		pte_t old_pte = READ_ONCE(*ptep);
332 		/*
333 		 * We only need to synchronise if the new PTE has tags enabled
334 		 * or if swapping in (in which case another mapping may have
335 		 * set tags in the past even if this PTE isn't tagged).
336 		 * (!pte_none() && !pte_present()) is an open coded version of
337 		 * is_swap_pte()
338 		 */
339 		if (pte_tagged(pte) || (!pte_none(old_pte) && !pte_present(old_pte)))
340 			mte_sync_tags(old_pte, pte);
341 	}
342 
343 	__check_racy_pte_update(mm, ptep, pte);
344 
345 	set_pte(ptep, pte);
346 }
347 
set_pte_at(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pte)348 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
349 			      pte_t *ptep, pte_t pte)
350 {
351 	page_table_check_pte_set(mm, addr, ptep, pte);
352 	return __set_pte_at(mm, addr, ptep, pte);
353 }
354 
355 /*
356  * Huge pte definitions.
357  */
358 #define pte_mkhuge(pte)		(__pte(pte_val(pte) & ~PTE_TABLE_BIT))
359 
360 /*
361  * Hugetlb definitions.
362  */
363 #define HUGE_MAX_HSTATE		4
364 #define HPAGE_SHIFT		PMD_SHIFT
365 #define HPAGE_SIZE		(_AC(1, UL) << HPAGE_SHIFT)
366 #define HPAGE_MASK		(~(HPAGE_SIZE - 1))
367 #define HUGETLB_PAGE_ORDER	(HPAGE_SHIFT - PAGE_SHIFT)
368 
pgd_pte(pgd_t pgd)369 static inline pte_t pgd_pte(pgd_t pgd)
370 {
371 	return __pte(pgd_val(pgd));
372 }
373 
p4d_pte(p4d_t p4d)374 static inline pte_t p4d_pte(p4d_t p4d)
375 {
376 	return __pte(p4d_val(p4d));
377 }
378 
pud_pte(pud_t pud)379 static inline pte_t pud_pte(pud_t pud)
380 {
381 	return __pte(pud_val(pud));
382 }
383 
pte_pud(pte_t pte)384 static inline pud_t pte_pud(pte_t pte)
385 {
386 	return __pud(pte_val(pte));
387 }
388 
pud_pmd(pud_t pud)389 static inline pmd_t pud_pmd(pud_t pud)
390 {
391 	return __pmd(pud_val(pud));
392 }
393 
pmd_pte(pmd_t pmd)394 static inline pte_t pmd_pte(pmd_t pmd)
395 {
396 	return __pte(pmd_val(pmd));
397 }
398 
pte_pmd(pte_t pte)399 static inline pmd_t pte_pmd(pte_t pte)
400 {
401 	return __pmd(pte_val(pte));
402 }
403 
mk_pud_sect_prot(pgprot_t prot)404 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
405 {
406 	return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT);
407 }
408 
mk_pmd_sect_prot(pgprot_t prot)409 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
410 {
411 	return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT);
412 }
413 
414 #define __HAVE_ARCH_PTE_SWP_EXCLUSIVE
pte_swp_mkexclusive(pte_t pte)415 static inline pte_t pte_swp_mkexclusive(pte_t pte)
416 {
417 	return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE));
418 }
419 
pte_swp_exclusive(pte_t pte)420 static inline int pte_swp_exclusive(pte_t pte)
421 {
422 	return pte_val(pte) & PTE_SWP_EXCLUSIVE;
423 }
424 
pte_swp_clear_exclusive(pte_t pte)425 static inline pte_t pte_swp_clear_exclusive(pte_t pte)
426 {
427 	return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE));
428 }
429 
430 #ifdef CONFIG_NUMA_BALANCING
431 /*
432  * See the comment in include/linux/pgtable.h
433  */
pte_protnone(pte_t pte)434 static inline int pte_protnone(pte_t pte)
435 {
436 	return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
437 }
438 
pmd_protnone(pmd_t pmd)439 static inline int pmd_protnone(pmd_t pmd)
440 {
441 	return pte_protnone(pmd_pte(pmd));
442 }
443 #endif
444 
445 #define pmd_present_invalid(pmd)     (!!(pmd_val(pmd) & PMD_PRESENT_INVALID))
446 
pmd_present(pmd_t pmd)447 static inline int pmd_present(pmd_t pmd)
448 {
449 	return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd);
450 }
451 
452 /*
453  * THP definitions.
454  */
455 
456 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
pmd_trans_huge(pmd_t pmd)457 static inline int pmd_trans_huge(pmd_t pmd)
458 {
459 	return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
460 }
461 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
462 
463 #define pmd_dirty(pmd)		pte_dirty(pmd_pte(pmd))
464 #define pmd_young(pmd)		pte_young(pmd_pte(pmd))
465 #define pmd_valid(pmd)		pte_valid(pmd_pte(pmd))
466 #define pmd_user(pmd)		pte_user(pmd_pte(pmd))
467 #define pmd_user_exec(pmd)	pte_user_exec(pmd_pte(pmd))
468 #define pmd_cont(pmd)		pte_cont(pmd_pte(pmd))
469 #define pmd_wrprotect(pmd)	pte_pmd(pte_wrprotect(pmd_pte(pmd)))
470 #define pmd_mkold(pmd)		pte_pmd(pte_mkold(pmd_pte(pmd)))
471 #define pmd_mkwrite(pmd)	pte_pmd(pte_mkwrite(pmd_pte(pmd)))
472 #define pmd_mkclean(pmd)	pte_pmd(pte_mkclean(pmd_pte(pmd)))
473 #define pmd_mkdirty(pmd)	pte_pmd(pte_mkdirty(pmd_pte(pmd)))
474 #define pmd_mkyoung(pmd)	pte_pmd(pte_mkyoung(pmd_pte(pmd)))
475 
pmd_mkinvalid(pmd_t pmd)476 static inline pmd_t pmd_mkinvalid(pmd_t pmd)
477 {
478 	pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
479 	pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
480 
481 	return pmd;
482 }
483 
484 #define pmd_thp_or_huge(pmd)	(pmd_huge(pmd) || pmd_trans_huge(pmd))
485 
486 #define pmd_write(pmd)		pte_write(pmd_pte(pmd))
487 
488 #define pmd_mkhuge(pmd)		(__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
489 
490 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
491 #define pmd_devmap(pmd)		pte_devmap(pmd_pte(pmd))
492 #endif
pmd_mkdevmap(pmd_t pmd)493 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
494 {
495 	return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
496 }
497 
498 #define __pmd_to_phys(pmd)	__pte_to_phys(pmd_pte(pmd))
499 #define __phys_to_pmd_val(phys)	__phys_to_pte_val(phys)
500 #define pmd_pfn(pmd)		((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
501 #define pfn_pmd(pfn,prot)	__pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
502 #define mk_pmd(page,prot)	pfn_pmd(page_to_pfn(page),prot)
503 
504 #define pud_young(pud)		pte_young(pud_pte(pud))
505 #define pud_mkyoung(pud)	pte_pud(pte_mkyoung(pud_pte(pud)))
506 #define pud_write(pud)		pte_write(pud_pte(pud))
507 
508 #define pud_mkhuge(pud)		(__pud(pud_val(pud) & ~PUD_TABLE_BIT))
509 
510 #define __pud_to_phys(pud)	__pte_to_phys(pud_pte(pud))
511 #define __phys_to_pud_val(phys)	__phys_to_pte_val(phys)
512 #define pud_pfn(pud)		((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
513 #define pfn_pud(pfn,prot)	__pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
514 
set_pmd_at(struct mm_struct * mm,unsigned long addr,pmd_t * pmdp,pmd_t pmd)515 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
516 			      pmd_t *pmdp, pmd_t pmd)
517 {
518 	page_table_check_pmd_set(mm, addr, pmdp, pmd);
519 	return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd));
520 }
521 
set_pud_at(struct mm_struct * mm,unsigned long addr,pud_t * pudp,pud_t pud)522 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr,
523 			      pud_t *pudp, pud_t pud)
524 {
525 	page_table_check_pud_set(mm, addr, pudp, pud);
526 	return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud));
527 }
528 
529 #define __p4d_to_phys(p4d)	__pte_to_phys(p4d_pte(p4d))
530 #define __phys_to_p4d_val(phys)	__phys_to_pte_val(phys)
531 
532 #define __pgd_to_phys(pgd)	__pte_to_phys(pgd_pte(pgd))
533 #define __phys_to_pgd_val(phys)	__phys_to_pte_val(phys)
534 
535 #define __pgprot_modify(prot,mask,bits) \
536 	__pgprot((pgprot_val(prot) & ~(mask)) | (bits))
537 
538 #define pgprot_nx(prot) \
539 	__pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN)
540 
541 /*
542  * Mark the prot value as uncacheable and unbufferable.
543  */
544 #define pgprot_noncached(prot) \
545 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
546 #define pgprot_writecombine(prot) \
547 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
548 #define pgprot_device(prot) \
549 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
550 #define pgprot_tagged(prot) \
551 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED))
552 #define pgprot_mhp	pgprot_tagged
553 /*
554  * DMA allocations for non-coherent devices use what the Arm architecture calls
555  * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
556  * and merging of writes.  This is different from "Device-nGnR[nE]" memory which
557  * is intended for MMIO and thus forbids speculation, preserves access size,
558  * requires strict alignment and can also force write responses to come from the
559  * endpoint.
560  */
561 #define pgprot_dmacoherent(prot) \
562 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, \
563 			PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
564 
565 #define __HAVE_PHYS_MEM_ACCESS_PROT
566 struct file;
567 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
568 				     unsigned long size, pgprot_t vma_prot);
569 
570 #define pmd_none(pmd)		(!pmd_val(pmd))
571 
572 #define pmd_table(pmd)		((pmd_val(pmd) & PMD_TYPE_MASK) == \
573 				 PMD_TYPE_TABLE)
574 #define pmd_sect(pmd)		((pmd_val(pmd) & PMD_TYPE_MASK) == \
575 				 PMD_TYPE_SECT)
576 #define pmd_leaf(pmd)		(pmd_present(pmd) && !pmd_table(pmd))
577 #define pmd_bad(pmd)		(!pmd_table(pmd))
578 
579 #define pmd_leaf_size(pmd)	(pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE)
580 #define pte_leaf_size(pte)	(pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE)
581 
582 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
pud_sect(pud_t pud)583 static inline bool pud_sect(pud_t pud) { return false; }
pud_table(pud_t pud)584 static inline bool pud_table(pud_t pud) { return true; }
585 #else
586 #define pud_sect(pud)		((pud_val(pud) & PUD_TYPE_MASK) == \
587 				 PUD_TYPE_SECT)
588 #define pud_table(pud)		((pud_val(pud) & PUD_TYPE_MASK) == \
589 				 PUD_TYPE_TABLE)
590 #endif
591 
592 extern pgd_t init_pg_dir[PTRS_PER_PGD];
593 extern pgd_t init_pg_end[];
594 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
595 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
596 extern pgd_t idmap_pg_end[];
597 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
598 extern pgd_t reserved_pg_dir[PTRS_PER_PGD];
599 
600 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
601 
in_swapper_pgdir(void * addr)602 static inline bool in_swapper_pgdir(void *addr)
603 {
604 	return ((unsigned long)addr & PAGE_MASK) ==
605 	        ((unsigned long)swapper_pg_dir & PAGE_MASK);
606 }
607 
set_pmd(pmd_t * pmdp,pmd_t pmd)608 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
609 {
610 #ifdef __PAGETABLE_PMD_FOLDED
611 	if (in_swapper_pgdir(pmdp)) {
612 		set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
613 		return;
614 	}
615 #endif /* __PAGETABLE_PMD_FOLDED */
616 
617 	WRITE_ONCE(*pmdp, pmd);
618 
619 	if (pmd_valid(pmd)) {
620 		dsb(ishst);
621 		isb();
622 	}
623 }
624 
pmd_clear(pmd_t * pmdp)625 static inline void pmd_clear(pmd_t *pmdp)
626 {
627 	set_pmd(pmdp, __pmd(0));
628 }
629 
pmd_page_paddr(pmd_t pmd)630 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
631 {
632 	return __pmd_to_phys(pmd);
633 }
634 
pmd_page_vaddr(pmd_t pmd)635 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
636 {
637 	return (unsigned long)__va(pmd_page_paddr(pmd));
638 }
639 
640 /* Find an entry in the third-level page table. */
641 #define pte_offset_phys(dir,addr)	(pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
642 
643 #define pte_set_fixmap(addr)		((pte_t *)set_fixmap_offset(FIX_PTE, addr))
644 #define pte_set_fixmap_offset(pmd, addr)	pte_set_fixmap(pte_offset_phys(pmd, addr))
645 #define pte_clear_fixmap()		clear_fixmap(FIX_PTE)
646 
647 #define pmd_page(pmd)			phys_to_page(__pmd_to_phys(pmd))
648 
649 /* use ONLY for statically allocated translation tables */
650 #define pte_offset_kimg(dir,addr)	((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
651 
652 /*
653  * Conversion functions: convert a page and protection to a page entry,
654  * and a page entry and page directory to the page they refer to.
655  */
656 #define mk_pte(page,prot)	pfn_pte(page_to_pfn(page),prot)
657 
658 #if CONFIG_PGTABLE_LEVELS > 2
659 
660 #define pmd_ERROR(e)	\
661 	pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e))
662 
663 #define pud_none(pud)		(!pud_val(pud))
664 #define pud_bad(pud)		(!pud_table(pud))
665 #define pud_present(pud)	pte_present(pud_pte(pud))
666 #define pud_leaf(pud)		(pud_present(pud) && !pud_table(pud))
667 #define pud_valid(pud)		pte_valid(pud_pte(pud))
668 #define pud_user(pud)		pte_user(pud_pte(pud))
669 
670 
set_pud(pud_t * pudp,pud_t pud)671 static inline void set_pud(pud_t *pudp, pud_t pud)
672 {
673 #ifdef __PAGETABLE_PUD_FOLDED
674 	if (in_swapper_pgdir(pudp)) {
675 		set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
676 		return;
677 	}
678 #endif /* __PAGETABLE_PUD_FOLDED */
679 
680 	WRITE_ONCE(*pudp, pud);
681 
682 	if (pud_valid(pud)) {
683 		dsb(ishst);
684 		isb();
685 	}
686 }
687 
pud_clear(pud_t * pudp)688 static inline void pud_clear(pud_t *pudp)
689 {
690 	set_pud(pudp, __pud(0));
691 }
692 
pud_page_paddr(pud_t pud)693 static inline phys_addr_t pud_page_paddr(pud_t pud)
694 {
695 	return __pud_to_phys(pud);
696 }
697 
pud_pgtable(pud_t pud)698 static inline pmd_t *pud_pgtable(pud_t pud)
699 {
700 	return (pmd_t *)__va(pud_page_paddr(pud));
701 }
702 
703 /* Find an entry in the second-level page table. */
704 #define pmd_offset_phys(dir, addr)	(pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
705 
706 #define pmd_set_fixmap(addr)		((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
707 #define pmd_set_fixmap_offset(pud, addr)	pmd_set_fixmap(pmd_offset_phys(pud, addr))
708 #define pmd_clear_fixmap()		clear_fixmap(FIX_PMD)
709 
710 #define pud_page(pud)			phys_to_page(__pud_to_phys(pud))
711 
712 /* use ONLY for statically allocated translation tables */
713 #define pmd_offset_kimg(dir,addr)	((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
714 
715 #else
716 
717 #define pud_page_paddr(pud)	({ BUILD_BUG(); 0; })
718 
719 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
720 #define pmd_set_fixmap(addr)		NULL
721 #define pmd_set_fixmap_offset(pudp, addr)	((pmd_t *)pudp)
722 #define pmd_clear_fixmap()
723 
724 #define pmd_offset_kimg(dir,addr)	((pmd_t *)dir)
725 
726 #endif	/* CONFIG_PGTABLE_LEVELS > 2 */
727 
728 #if CONFIG_PGTABLE_LEVELS > 3
729 
730 #define pud_ERROR(e)	\
731 	pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e))
732 
733 #define p4d_none(p4d)		(!p4d_val(p4d))
734 #define p4d_bad(p4d)		(!(p4d_val(p4d) & 2))
735 #define p4d_present(p4d)	(p4d_val(p4d))
736 
set_p4d(p4d_t * p4dp,p4d_t p4d)737 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
738 {
739 	if (in_swapper_pgdir(p4dp)) {
740 		set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d)));
741 		return;
742 	}
743 
744 	WRITE_ONCE(*p4dp, p4d);
745 	dsb(ishst);
746 	isb();
747 }
748 
p4d_clear(p4d_t * p4dp)749 static inline void p4d_clear(p4d_t *p4dp)
750 {
751 	set_p4d(p4dp, __p4d(0));
752 }
753 
p4d_page_paddr(p4d_t p4d)754 static inline phys_addr_t p4d_page_paddr(p4d_t p4d)
755 {
756 	return __p4d_to_phys(p4d);
757 }
758 
p4d_pgtable(p4d_t p4d)759 static inline pud_t *p4d_pgtable(p4d_t p4d)
760 {
761 	return (pud_t *)__va(p4d_page_paddr(p4d));
762 }
763 
764 /* Find an entry in the first-level page table. */
765 #define pud_offset_phys(dir, addr)	(p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
766 
767 #define pud_set_fixmap(addr)		((pud_t *)set_fixmap_offset(FIX_PUD, addr))
768 #define pud_set_fixmap_offset(p4d, addr)	pud_set_fixmap(pud_offset_phys(p4d, addr))
769 #define pud_clear_fixmap()		clear_fixmap(FIX_PUD)
770 
771 #define p4d_page(p4d)		pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d)))
772 
773 /* use ONLY for statically allocated translation tables */
774 #define pud_offset_kimg(dir,addr)	((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
775 
776 #else
777 
778 #define p4d_page_paddr(p4d)	({ BUILD_BUG(); 0;})
779 #define pgd_page_paddr(pgd)	({ BUILD_BUG(); 0;})
780 
781 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
782 #define pud_set_fixmap(addr)		NULL
783 #define pud_set_fixmap_offset(pgdp, addr)	((pud_t *)pgdp)
784 #define pud_clear_fixmap()
785 
786 #define pud_offset_kimg(dir,addr)	((pud_t *)dir)
787 
788 #endif  /* CONFIG_PGTABLE_LEVELS > 3 */
789 
790 #define pgd_ERROR(e)	\
791 	pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
792 
793 #define pgd_set_fixmap(addr)	((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
794 #define pgd_clear_fixmap()	clear_fixmap(FIX_PGD)
795 
pte_modify(pte_t pte,pgprot_t newprot)796 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
797 {
798 	/*
799 	 * Normal and Normal-Tagged are two different memory types and indices
800 	 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK.
801 	 */
802 	const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
803 			      PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP |
804 			      PTE_ATTRINDX_MASK;
805 	/* preserve the hardware dirty information */
806 	if (pte_hw_dirty(pte))
807 		pte = pte_mkdirty(pte);
808 	pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
809 	return pte;
810 }
811 
pmd_modify(pmd_t pmd,pgprot_t newprot)812 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
813 {
814 	return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
815 }
816 
817 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
818 extern int ptep_set_access_flags(struct vm_area_struct *vma,
819 				 unsigned long address, pte_t *ptep,
820 				 pte_t entry, int dirty);
821 
822 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
823 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
pmdp_set_access_flags(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp,pmd_t entry,int dirty)824 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
825 					unsigned long address, pmd_t *pmdp,
826 					pmd_t entry, int dirty)
827 {
828 	return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
829 }
830 
pud_devmap(pud_t pud)831 static inline int pud_devmap(pud_t pud)
832 {
833 	return 0;
834 }
835 
pgd_devmap(pgd_t pgd)836 static inline int pgd_devmap(pgd_t pgd)
837 {
838 	return 0;
839 }
840 #endif
841 
842 #ifdef CONFIG_PAGE_TABLE_CHECK
pte_user_accessible_page(pte_t pte)843 static inline bool pte_user_accessible_page(pte_t pte)
844 {
845 	return pte_present(pte) && (pte_user(pte) || pte_user_exec(pte));
846 }
847 
pmd_user_accessible_page(pmd_t pmd)848 static inline bool pmd_user_accessible_page(pmd_t pmd)
849 {
850 	return pmd_present(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd));
851 }
852 
pud_user_accessible_page(pud_t pud)853 static inline bool pud_user_accessible_page(pud_t pud)
854 {
855 	return pud_present(pud) && pud_user(pud);
856 }
857 #endif
858 
859 /*
860  * Atomic pte/pmd modifications.
861  */
862 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
__ptep_test_and_clear_young(pte_t * ptep)863 static inline int __ptep_test_and_clear_young(pte_t *ptep)
864 {
865 	pte_t old_pte, pte;
866 
867 	pte = READ_ONCE(*ptep);
868 	do {
869 		old_pte = pte;
870 		pte = pte_mkold(pte);
871 		pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
872 					       pte_val(old_pte), pte_val(pte));
873 	} while (pte_val(pte) != pte_val(old_pte));
874 
875 	return pte_young(pte);
876 }
877 
ptep_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)878 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
879 					    unsigned long address,
880 					    pte_t *ptep)
881 {
882 	return __ptep_test_and_clear_young(ptep);
883 }
884 
885 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
ptep_clear_flush_young(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)886 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
887 					 unsigned long address, pte_t *ptep)
888 {
889 	int young = ptep_test_and_clear_young(vma, address, ptep);
890 
891 	if (young) {
892 		/*
893 		 * We can elide the trailing DSB here since the worst that can
894 		 * happen is that a CPU continues to use the young entry in its
895 		 * TLB and we mistakenly reclaim the associated page. The
896 		 * window for such an event is bounded by the next
897 		 * context-switch, which provides a DSB to complete the TLB
898 		 * invalidation.
899 		 */
900 		flush_tlb_page_nosync(vma, address);
901 	}
902 
903 	return young;
904 }
905 
906 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
907 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
pmdp_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp)908 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
909 					    unsigned long address,
910 					    pmd_t *pmdp)
911 {
912 	return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
913 }
914 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
915 
916 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
ptep_get_and_clear(struct mm_struct * mm,unsigned long address,pte_t * ptep)917 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
918 				       unsigned long address, pte_t *ptep)
919 {
920 	pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0));
921 
922 	page_table_check_pte_clear(mm, address, pte);
923 
924 	return pte;
925 }
926 
927 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
928 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
pmdp_huge_get_and_clear(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)929 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
930 					    unsigned long address, pmd_t *pmdp)
931 {
932 	pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0));
933 
934 	page_table_check_pmd_clear(mm, address, pmd);
935 
936 	return pmd;
937 }
938 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
939 
940 /*
941  * ptep_set_wrprotect - mark read-only while trasferring potential hardware
942  * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
943  */
944 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
ptep_set_wrprotect(struct mm_struct * mm,unsigned long address,pte_t * ptep)945 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
946 {
947 	pte_t old_pte, pte;
948 
949 	pte = READ_ONCE(*ptep);
950 	do {
951 		old_pte = pte;
952 		pte = pte_wrprotect(pte);
953 		pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
954 					       pte_val(old_pte), pte_val(pte));
955 	} while (pte_val(pte) != pte_val(old_pte));
956 }
957 
958 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
959 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
pmdp_set_wrprotect(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)960 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
961 				      unsigned long address, pmd_t *pmdp)
962 {
963 	ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
964 }
965 
966 #define pmdp_establish pmdp_establish
pmdp_establish(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp,pmd_t pmd)967 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
968 		unsigned long address, pmd_t *pmdp, pmd_t pmd)
969 {
970 	page_table_check_pmd_set(vma->vm_mm, address, pmdp, pmd);
971 	return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
972 }
973 #endif
974 
975 /*
976  * Encode and decode a swap entry:
977  *	bits 0-1:	present (must be zero)
978  *	bits 2:		remember PG_anon_exclusive
979  *	bits 3-7:	swap type
980  *	bits 8-57:	swap offset
981  *	bit  58:	PTE_PROT_NONE (must be zero)
982  */
983 #define __SWP_TYPE_SHIFT	3
984 #define __SWP_TYPE_BITS		5
985 #define __SWP_OFFSET_BITS	50
986 #define __SWP_TYPE_MASK		((1 << __SWP_TYPE_BITS) - 1)
987 #define __SWP_OFFSET_SHIFT	(__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
988 #define __SWP_OFFSET_MASK	((1UL << __SWP_OFFSET_BITS) - 1)
989 
990 #define __swp_type(x)		(((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
991 #define __swp_offset(x)		(((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
992 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
993 
994 #define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
995 #define __swp_entry_to_pte(swp)	((pte_t) { (swp).val })
996 
997 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
998 #define __pmd_to_swp_entry(pmd)		((swp_entry_t) { pmd_val(pmd) })
999 #define __swp_entry_to_pmd(swp)		__pmd((swp).val)
1000 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
1001 
1002 /*
1003  * Ensure that there are not more swap files than can be encoded in the kernel
1004  * PTEs.
1005  */
1006 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
1007 
1008 extern int kern_addr_valid(unsigned long addr);
1009 
1010 #ifdef CONFIG_ARM64_MTE
1011 
1012 #define __HAVE_ARCH_PREPARE_TO_SWAP
arch_prepare_to_swap(struct page * page)1013 static inline int arch_prepare_to_swap(struct page *page)
1014 {
1015 	if (system_supports_mte())
1016 		return mte_save_tags(page);
1017 	return 0;
1018 }
1019 
1020 #define __HAVE_ARCH_SWAP_INVALIDATE
arch_swap_invalidate_page(int type,pgoff_t offset)1021 static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
1022 {
1023 	if (system_supports_mte())
1024 		mte_invalidate_tags(type, offset);
1025 }
1026 
arch_swap_invalidate_area(int type)1027 static inline void arch_swap_invalidate_area(int type)
1028 {
1029 	if (system_supports_mte())
1030 		mte_invalidate_tags_area(type);
1031 }
1032 
1033 #define __HAVE_ARCH_SWAP_RESTORE
arch_swap_restore(swp_entry_t entry,struct folio * folio)1034 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio)
1035 {
1036 	if (system_supports_mte() && mte_restore_tags(entry, &folio->page))
1037 		set_bit(PG_mte_tagged, &folio->flags);
1038 }
1039 
1040 #endif /* CONFIG_ARM64_MTE */
1041 
1042 /*
1043  * On AArch64, the cache coherency is handled via the set_pte_at() function.
1044  */
update_mmu_cache(struct vm_area_struct * vma,unsigned long addr,pte_t * ptep)1045 static inline void update_mmu_cache(struct vm_area_struct *vma,
1046 				    unsigned long addr, pte_t *ptep)
1047 {
1048 	/*
1049 	 * We don't do anything here, so there's a very small chance of
1050 	 * us retaking a user fault which we just fixed up. The alternative
1051 	 * is doing a dsb(ishst), but that penalises the fastpath.
1052 	 */
1053 }
1054 
1055 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
1056 
1057 #ifdef CONFIG_ARM64_PA_BITS_52
1058 #define phys_to_ttbr(addr)	(((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
1059 #else
1060 #define phys_to_ttbr(addr)	(addr)
1061 #endif
1062 
1063 /*
1064  * On arm64 without hardware Access Flag, copying from user will fail because
1065  * the pte is old and cannot be marked young. So we always end up with zeroed
1066  * page after fork() + CoW for pfn mappings. We don't always have a
1067  * hardware-managed access flag on arm64.
1068  */
arch_faults_on_old_pte(void)1069 static inline bool arch_faults_on_old_pte(void)
1070 {
1071 	/* The register read below requires a stable CPU to make any sense */
1072 	cant_migrate();
1073 
1074 	return !cpu_has_hw_af();
1075 }
1076 #define arch_faults_on_old_pte		arch_faults_on_old_pte
1077 
1078 /*
1079  * Experimentally, it's cheap to set the access flag in hardware and we
1080  * benefit from prefaulting mappings as 'old' to start with.
1081  */
arch_wants_old_prefaulted_pte(void)1082 static inline bool arch_wants_old_prefaulted_pte(void)
1083 {
1084 	return !arch_faults_on_old_pte();
1085 }
1086 #define arch_wants_old_prefaulted_pte	arch_wants_old_prefaulted_pte
1087 
pud_sect_supported(void)1088 static inline bool pud_sect_supported(void)
1089 {
1090 	return PAGE_SIZE == SZ_4K;
1091 }
1092 
1093 
1094 #endif /* !__ASSEMBLY__ */
1095 
1096 #endif /* __ASM_PGTABLE_H */
1097