1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dc_features.h" 27 #include "display_mode_enums.h" 28 29 /** 30 * DOC: overview 31 * 32 * Most of the DML code is automatically generated and tested via hardware 33 * description language. Usually, we use the reference _vcs_dpi in the code 34 * where VCS means "Verilog Compiled Simulator" and DPI stands for "Direct 35 * Programmer Interface". In other words, those structs can be used to 36 * interface with Verilog with other languages such as C. 37 */ 38 39 #ifndef __DISPLAY_MODE_STRUCTS_H__ 40 #define __DISPLAY_MODE_STRUCTS_H__ 41 42 typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st; 43 typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st; 44 typedef struct _vcs_dpi_ip_params_st ip_params_st; 45 typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st; 46 typedef struct _vcs_dpi_display_output_params_st display_output_params_st; 47 typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st; 48 typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st; 49 typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st; 50 typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st; 51 typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st; 52 typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st; 53 typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st; 54 typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st; 55 typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st; 56 typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st; 57 typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st; 58 typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st; 59 typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st; 60 typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st; 61 typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st; 62 typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st; 63 typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st; 64 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st; 65 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st; 66 67 typedef struct { 68 double UrgentWatermark; 69 double WritebackUrgentWatermark; 70 double DRAMClockChangeWatermark; 71 double FCLKChangeWatermark; 72 double WritebackDRAMClockChangeWatermark; 73 double WritebackFCLKChangeWatermark; 74 double StutterExitWatermark; 75 double StutterEnterPlusExitWatermark; 76 double Z8StutterExitWatermark; 77 double Z8StutterEnterPlusExitWatermark; 78 double USRRetrainingWatermark; 79 } Watermarks; 80 81 typedef struct { 82 double UrgentLatency; 83 double ExtraLatency; 84 double WritebackLatency; 85 double DRAMClockChangeLatency; 86 double FCLKChangeLatency; 87 double SRExitTime; 88 double SREnterPlusExitTime; 89 double SRExitZ8Time; 90 double SREnterPlusExitZ8Time; 91 double USRRetrainingLatencyPlusSMNLatency; 92 } Latencies; 93 94 typedef struct { 95 double Dppclk; 96 double Dispclk; 97 double PixelClock; 98 double DCFClkDeepSleep; 99 unsigned int DPPPerSurface; 100 bool ScalerEnabled; 101 enum dm_rotation_angle SourceRotation; 102 unsigned int ViewportHeight; 103 unsigned int ViewportHeightChroma; 104 unsigned int BlockWidth256BytesY; 105 unsigned int BlockHeight256BytesY; 106 unsigned int BlockWidth256BytesC; 107 unsigned int BlockHeight256BytesC; 108 unsigned int BlockWidthY; 109 unsigned int BlockHeightY; 110 unsigned int BlockWidthC; 111 unsigned int BlockHeightC; 112 unsigned int InterlaceEnable; 113 unsigned int NumberOfCursors; 114 unsigned int VBlank; 115 unsigned int HTotal; 116 unsigned int HActive; 117 bool DCCEnable; 118 enum odm_combine_mode ODMMode; 119 enum source_format_class SourcePixelFormat; 120 enum dm_swizzle_mode SurfaceTiling; 121 unsigned int BytePerPixelY; 122 unsigned int BytePerPixelC; 123 bool ProgressiveToInterlaceUnitInOPP; 124 double VRatio; 125 double VRatioChroma; 126 unsigned int VTaps; 127 unsigned int VTapsChroma; 128 unsigned int PitchY; 129 unsigned int DCCMetaPitchY; 130 unsigned int PitchC; 131 unsigned int DCCMetaPitchC; 132 bool ViewportStationary; 133 unsigned int ViewportXStart; 134 unsigned int ViewportYStart; 135 unsigned int ViewportXStartC; 136 unsigned int ViewportYStartC; 137 bool FORCE_ONE_ROW_FOR_FRAME; 138 unsigned int SwathHeightY; 139 unsigned int SwathHeightC; 140 } DmlPipe; 141 142 typedef struct { 143 double UrgentLatency; 144 double ExtraLatency; 145 double WritebackLatency; 146 double DRAMClockChangeLatency; 147 double FCLKChangeLatency; 148 double SRExitTime; 149 double SREnterPlusExitTime; 150 double SRExitZ8Time; 151 double SREnterPlusExitZ8Time; 152 double USRRetrainingLatency; 153 double SMNLatency; 154 } SOCParametersList; 155 156 struct _vcs_dpi_voltage_scaling_st { 157 int state; 158 double dscclk_mhz; 159 double dcfclk_mhz; 160 double socclk_mhz; 161 double phyclk_d18_mhz; 162 double phyclk_d32_mhz; 163 double dram_speed_mts; 164 double fabricclk_mhz; 165 double dispclk_mhz; 166 double dram_bw_per_chan_gbps; 167 double phyclk_mhz; 168 double dppclk_mhz; 169 double dtbclk_mhz; 170 }; 171 172 /** 173 * _vcs_dpi_soc_bounding_box_st: SOC definitions 174 * 175 * This struct maintains the SOC Bounding Box information for the ASIC; it 176 * defines things such as clock, voltage, performance, etc. Usually, we load 177 * these values from VBIOS; if something goes wrong, we use some hard-coded 178 * values, which will enable the ASIC to light up with limitations. 179 */ 180 struct _vcs_dpi_soc_bounding_box_st { 181 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 182 /** 183 * @num_states: It represents the total of Display Power Management 184 * (DPM) supported by the specific ASIC. 185 */ 186 unsigned int num_states; 187 double sr_exit_time_us; 188 double sr_enter_plus_exit_time_us; 189 double sr_exit_z8_time_us; 190 double sr_enter_plus_exit_z8_time_us; 191 double urgent_latency_us; 192 double urgent_latency_pixel_data_only_us; 193 double urgent_latency_pixel_mixed_with_vm_data_us; 194 double urgent_latency_vm_data_only_us; 195 double usr_retraining_latency_us; 196 double smn_latency_us; 197 double fclk_change_latency_us; 198 double mall_allocated_for_dcn_mbytes; 199 double pct_ideal_fabric_bw_after_urgent; 200 double pct_ideal_dram_bw_after_urgent_strobe; 201 double max_avg_fabric_bw_use_normal_percent; 202 double max_avg_dram_bw_use_normal_strobe_percent; 203 enum dm_prefetch_modes allow_for_pstate_or_stutter_in_vblank_final; 204 bool dram_clock_change_requirement_final; 205 double writeback_latency_us; 206 double ideal_dram_bw_after_urgent_percent; 207 double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly 208 double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; 209 double pct_ideal_dram_sdp_bw_after_urgent_vm_only; 210 double pct_ideal_sdp_bw_after_urgent; 211 double max_avg_sdp_bw_use_normal_percent; 212 double max_avg_dram_bw_use_normal_percent; 213 unsigned int max_request_size_bytes; 214 double downspread_percent; 215 double dram_page_open_time_ns; 216 double dram_rw_turnaround_time_ns; 217 double dram_return_buffer_per_channel_bytes; 218 double dram_channel_width_bytes; 219 double fabric_datapath_to_dcn_data_return_bytes; 220 double dcn_downspread_percent; 221 double dispclk_dppclk_vco_speed_mhz; 222 double dfs_vco_period_ps; 223 unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes; 224 unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; 225 unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes; 226 unsigned int round_trip_ping_latency_dcfclk_cycles; 227 unsigned int urgent_out_of_order_return_per_channel_bytes; 228 unsigned int channel_interleave_bytes; 229 unsigned int num_banks; 230 unsigned int num_chans; 231 unsigned int vmm_page_size_bytes; 232 unsigned int hostvm_min_page_size_bytes; 233 unsigned int gpuvm_min_page_size_bytes; 234 double dram_clock_change_latency_us; 235 double dummy_pstate_latency_us; 236 double writeback_dram_clock_change_latency_us; 237 unsigned int return_bus_width_bytes; 238 unsigned int voltage_override; 239 double xfc_bus_transport_time_us; 240 double xfc_xbuf_latency_tolerance_us; 241 int use_urgent_burst_bw; 242 double min_dcfclk; 243 bool do_urgent_latency_adjustment; 244 double urgent_latency_adjustment_fabric_clock_component_us; 245 double urgent_latency_adjustment_fabric_clock_reference_mhz; 246 bool disable_dram_clock_change_vactive_support; 247 bool allow_dram_clock_one_display_vactive; 248 enum self_refresh_affinity allow_dram_self_refresh_or_dram_clock_change_in_vblank; 249 }; 250 251 /** 252 * @_vcs_dpi_ip_params_st: IP configuraion for DCN blocks 253 * 254 * In this struct you can find the DCN configuration associated to the specific 255 * ASIC. For example, here we can save how many DPPs the ASIC is using and it 256 * is available. 257 * 258 */ 259 struct _vcs_dpi_ip_params_st { 260 bool use_min_dcfclk; 261 bool clamp_min_dcfclk; 262 bool gpuvm_enable; 263 bool hostvm_enable; 264 bool dsc422_native_support; 265 unsigned int gpuvm_max_page_table_levels; 266 unsigned int hostvm_max_page_table_levels; 267 unsigned int hostvm_cached_page_table_levels; 268 unsigned int pte_group_size_bytes; 269 unsigned int max_inter_dcn_tile_repeaters; 270 unsigned int num_dsc; 271 unsigned int odm_capable; 272 unsigned int rob_buffer_size_kbytes; 273 unsigned int det_buffer_size_kbytes; 274 unsigned int min_comp_buffer_size_kbytes; 275 unsigned int dpte_buffer_size_in_pte_reqs_luma; 276 unsigned int dpte_buffer_size_in_pte_reqs_chroma; 277 unsigned int pde_proc_buffer_size_64k_reqs; 278 unsigned int dpp_output_buffer_pixels; 279 unsigned int opp_output_buffer_lines; 280 unsigned int pixel_chunk_size_kbytes; 281 unsigned int alpha_pixel_chunk_size_kbytes; 282 unsigned int min_pixel_chunk_size_bytes; 283 unsigned int dcc_meta_buffer_size_bytes; 284 unsigned char pte_enable; 285 unsigned int pte_chunk_size_kbytes; 286 unsigned int meta_chunk_size_kbytes; 287 unsigned int min_meta_chunk_size_bytes; 288 unsigned int writeback_chunk_size_kbytes; 289 unsigned int line_buffer_size_bits; 290 unsigned int max_line_buffer_lines; 291 unsigned int writeback_luma_buffer_size_kbytes; 292 unsigned int writeback_chroma_buffer_size_kbytes; 293 unsigned int writeback_chroma_line_buffer_width_pixels; 294 295 unsigned int writeback_interface_buffer_size_kbytes; 296 unsigned int writeback_line_buffer_buffer_size; 297 298 unsigned int writeback_10bpc420_supported; 299 double writeback_max_hscl_ratio; 300 double writeback_max_vscl_ratio; 301 double writeback_min_hscl_ratio; 302 double writeback_min_vscl_ratio; 303 unsigned int maximum_dsc_bits_per_component; 304 unsigned int maximum_pixels_per_line_per_dsc_unit; 305 unsigned int writeback_max_hscl_taps; 306 unsigned int writeback_max_vscl_taps; 307 unsigned int writeback_line_buffer_luma_buffer_size; 308 unsigned int writeback_line_buffer_chroma_buffer_size; 309 310 unsigned int max_page_table_levels; 311 /** 312 * @max_num_dpp: Maximum number of DPP supported in the target ASIC. 313 */ 314 unsigned int max_num_dpp; 315 unsigned int max_num_otg; 316 unsigned int cursor_chunk_size; 317 unsigned int cursor_buffer_size; 318 unsigned int max_num_wb; 319 unsigned int max_dchub_pscl_bw_pix_per_clk; 320 unsigned int max_pscl_lb_bw_pix_per_clk; 321 unsigned int max_lb_vscl_bw_pix_per_clk; 322 unsigned int max_vscl_hscl_bw_pix_per_clk; 323 double max_hscl_ratio; 324 double max_vscl_ratio; 325 unsigned int hscl_mults; 326 unsigned int vscl_mults; 327 unsigned int max_hscl_taps; 328 unsigned int max_vscl_taps; 329 unsigned int xfc_supported; 330 unsigned int ptoi_supported; 331 unsigned int gfx7_compat_tiling_supported; 332 333 bool odm_combine_4to1_supported; 334 bool dynamic_metadata_vm_enabled; 335 unsigned int max_num_hdmi_frl_outputs; 336 337 unsigned int xfc_fill_constant_bytes; 338 double dispclk_ramp_margin_percent; 339 double xfc_fill_bw_overhead_percent; 340 double underscan_factor; 341 unsigned int min_vblank_lines; 342 unsigned int dppclk_delay_subtotal; 343 unsigned int dispclk_delay_subtotal; 344 double dcfclk_cstate_latency; 345 unsigned int dppclk_delay_scl; 346 unsigned int dppclk_delay_scl_lb_only; 347 unsigned int dppclk_delay_cnvc_formatter; 348 unsigned int dppclk_delay_cnvc_cursor; 349 unsigned int is_line_buffer_bpp_fixed; 350 unsigned int line_buffer_fixed_bpp; 351 unsigned int dcc_supported; 352 unsigned int config_return_buffer_size_in_kbytes; 353 unsigned int compressed_buffer_segment_size_in_kbytes; 354 unsigned int meta_fifo_size_in_kentries; 355 unsigned int zero_size_buffer_entries; 356 unsigned int compbuf_reserved_space_64b; 357 unsigned int compbuf_reserved_space_zs; 358 359 unsigned int IsLineBufferBppFixed; 360 unsigned int LineBufferFixedBpp; 361 unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 362 unsigned int bug_forcing_LC_req_same_size_fixed; 363 unsigned int number_of_cursors; 364 unsigned int max_num_dp2p0_outputs; 365 unsigned int max_num_dp2p0_streams; 366 unsigned int VBlankNomDefaultUS; 367 368 /* DM workarounds */ 369 double dsc_delay_factor_wa; // TODO: Remove after implementing root cause fix 370 double min_prefetch_in_strobe_us; 371 }; 372 373 struct _vcs_dpi_display_xfc_params_st { 374 double xfc_tslv_vready_offset_us; 375 double xfc_tslv_vupdate_width_us; 376 double xfc_tslv_vupdate_offset_us; 377 int xfc_slv_chunk_size_bytes; 378 }; 379 380 struct _vcs_dpi_display_pipe_source_params_st { 381 int source_format; 382 double dcc_fraction_of_zs_req_luma; 383 double dcc_fraction_of_zs_req_chroma; 384 unsigned char dcc; 385 unsigned int dcc_rate; 386 unsigned int dcc_rate_chroma; 387 unsigned char dcc_use_global; 388 unsigned char vm; 389 bool unbounded_req_mode; 390 bool gpuvm; // gpuvm enabled 391 bool hostvm; // hostvm enabled 392 bool gpuvm_levels_force_en; 393 unsigned int gpuvm_levels_force; 394 bool hostvm_levels_force_en; 395 unsigned int hostvm_levels_force; 396 int source_scan; 397 int source_rotation; // new in dml32 398 unsigned int det_size_override; // use to populate DETSizeOverride in vba struct 399 int sw_mode; 400 int macro_tile_size; 401 unsigned int surface_width_y; 402 unsigned int surface_height_y; 403 unsigned int surface_width_c; 404 unsigned int surface_height_c; 405 unsigned int viewport_width; 406 unsigned int viewport_height; 407 unsigned int viewport_y_y; 408 unsigned int viewport_y_c; 409 unsigned int viewport_width_c; 410 unsigned int viewport_height_c; 411 unsigned int viewport_width_max; 412 unsigned int viewport_height_max; 413 unsigned int viewport_x_y; 414 unsigned int viewport_x_c; 415 bool viewport_stationary; 416 unsigned int dcc_rate_luma; 417 unsigned int gpuvm_min_page_size_kbytes; 418 unsigned int use_mall_for_pstate_change; 419 unsigned int use_mall_for_static_screen; 420 bool force_one_row_for_frame; 421 bool pte_buffer_mode; 422 unsigned int data_pitch; 423 unsigned int data_pitch_c; 424 unsigned int meta_pitch; 425 unsigned int meta_pitch_c; 426 unsigned int cur0_src_width; 427 int cur0_bpp; 428 unsigned int cur1_src_width; 429 int cur1_bpp; 430 int num_cursors; 431 unsigned char is_hsplit; 432 unsigned char dynamic_metadata_enable; 433 unsigned int dynamic_metadata_lines_before_active; 434 unsigned int dynamic_metadata_xmit_bytes; 435 unsigned int hsplit_grp; 436 unsigned char xfc_enable; 437 unsigned char xfc_slave; 438 unsigned char immediate_flip; 439 struct _vcs_dpi_display_xfc_params_st xfc_params; 440 //for vstartuplines calculation freesync 441 unsigned char v_total_min; 442 unsigned char v_total_max; 443 }; 444 struct writeback_st { 445 int wb_src_height; 446 int wb_src_width; 447 int wb_dst_width; 448 int wb_dst_height; 449 int wb_pixel_format; 450 int wb_htaps_luma; 451 int wb_vtaps_luma; 452 int wb_htaps_chroma; 453 int wb_vtaps_chroma; 454 unsigned int wb_htaps; 455 unsigned int wb_vtaps; 456 double wb_hratio; 457 double wb_vratio; 458 }; 459 460 struct display_audio_params_st { 461 unsigned int audio_sample_rate_khz; 462 int audio_sample_layout; 463 }; 464 465 struct _vcs_dpi_display_output_params_st { 466 int dp_lanes; 467 double output_bpp; 468 unsigned int dsc_input_bpc; 469 int dsc_enable; 470 int wb_enable; 471 int num_active_wb; 472 int output_type; 473 int is_virtual; 474 int output_format; 475 int dsc_slices; 476 int max_audio_sample_rate; 477 struct writeback_st wb; 478 struct display_audio_params_st audio; 479 unsigned int output_bpc; 480 int dp_rate; 481 unsigned int dp_multistream_id; 482 bool dp_multistream_en; 483 }; 484 485 struct _vcs_dpi_scaler_ratio_depth_st { 486 double hscl_ratio; 487 double vscl_ratio; 488 double hscl_ratio_c; 489 double vscl_ratio_c; 490 double vinit; 491 double vinit_c; 492 double vinit_bot; 493 double vinit_bot_c; 494 int lb_depth; 495 int scl_enable; 496 }; 497 498 struct _vcs_dpi_scaler_taps_st { 499 unsigned int htaps; 500 unsigned int vtaps; 501 unsigned int htaps_c; 502 unsigned int vtaps_c; 503 }; 504 505 struct _vcs_dpi_display_pipe_dest_params_st { 506 unsigned int recout_width; 507 unsigned int recout_height; 508 unsigned int full_recout_width; 509 unsigned int full_recout_height; 510 unsigned int hblank_start; 511 unsigned int hblank_end; 512 unsigned int vblank_start; 513 unsigned int vblank_end; 514 unsigned int htotal; 515 unsigned int vtotal; 516 unsigned int vfront_porch; 517 unsigned int vblank_nom; 518 unsigned int vactive; 519 unsigned int hactive; 520 unsigned int vstartup_start; 521 unsigned int vupdate_offset; 522 unsigned int vupdate_width; 523 unsigned int vready_offset; 524 unsigned char interlaced; 525 double pixel_rate_mhz; 526 unsigned char synchronized_vblank_all_planes; 527 unsigned char otg_inst; 528 unsigned int odm_combine; 529 unsigned char use_maximum_vstartup; 530 unsigned int vtotal_max; 531 unsigned int vtotal_min; 532 unsigned int refresh_rate; 533 bool synchronize_timings; 534 unsigned int odm_combine_policy; 535 bool drr_display; 536 }; 537 538 struct _vcs_dpi_display_pipe_params_st { 539 display_pipe_source_params_st src; 540 display_pipe_dest_params_st dest; 541 scaler_ratio_depth_st scale_ratio_depth; 542 scaler_taps_st scale_taps; 543 }; 544 545 struct _vcs_dpi_display_clocks_and_cfg_st { 546 int voltage; 547 double dppclk_mhz; 548 double refclk_mhz; 549 double dispclk_mhz; 550 double dcfclk_mhz; 551 double socclk_mhz; 552 }; 553 554 struct _vcs_dpi_display_e2e_pipe_params_st { 555 display_pipe_params_st pipe; 556 display_output_params_st dout; 557 display_clocks_and_cfg_st clks_cfg; 558 }; 559 560 struct _vcs_dpi_display_data_rq_misc_params_st { 561 unsigned int full_swath_bytes; 562 unsigned int stored_swath_bytes; 563 unsigned int blk256_height; 564 unsigned int blk256_width; 565 unsigned int req_height; 566 unsigned int req_width; 567 }; 568 569 struct _vcs_dpi_display_data_rq_sizing_params_st { 570 unsigned int chunk_bytes; 571 unsigned int min_chunk_bytes; 572 unsigned int meta_chunk_bytes; 573 unsigned int min_meta_chunk_bytes; 574 unsigned int mpte_group_bytes; 575 unsigned int dpte_group_bytes; 576 }; 577 578 struct _vcs_dpi_display_data_rq_dlg_params_st { 579 unsigned int swath_width_ub; 580 unsigned int swath_height; 581 unsigned int req_per_swath_ub; 582 unsigned int meta_pte_bytes_per_frame_ub; 583 unsigned int dpte_req_per_row_ub; 584 unsigned int dpte_groups_per_row_ub; 585 unsigned int dpte_row_height; 586 unsigned int dpte_bytes_per_row_ub; 587 unsigned int meta_chunks_per_row_ub; 588 unsigned int meta_req_per_row_ub; 589 unsigned int meta_row_height; 590 unsigned int meta_bytes_per_row_ub; 591 }; 592 593 struct _vcs_dpi_display_rq_dlg_params_st { 594 display_data_rq_dlg_params_st rq_l; 595 display_data_rq_dlg_params_st rq_c; 596 }; 597 598 struct _vcs_dpi_display_rq_sizing_params_st { 599 display_data_rq_sizing_params_st rq_l; 600 display_data_rq_sizing_params_st rq_c; 601 }; 602 603 struct _vcs_dpi_display_rq_misc_params_st { 604 display_data_rq_misc_params_st rq_l; 605 display_data_rq_misc_params_st rq_c; 606 }; 607 608 struct _vcs_dpi_display_rq_params_st { 609 unsigned char yuv420; 610 unsigned char yuv420_10bpc; 611 unsigned char rgbe_alpha; 612 display_rq_misc_params_st misc; 613 display_rq_sizing_params_st sizing; 614 display_rq_dlg_params_st dlg; 615 }; 616 617 struct _vcs_dpi_display_dlg_regs_st { 618 unsigned int refcyc_h_blank_end; 619 unsigned int dlg_vblank_end; 620 unsigned int min_dst_y_next_start; 621 unsigned int optimized_min_dst_y_next_start; 622 unsigned int optimized_min_dst_y_next_start_us; 623 unsigned int refcyc_per_htotal; 624 unsigned int refcyc_x_after_scaler; 625 unsigned int dst_y_after_scaler; 626 unsigned int dst_y_prefetch; 627 unsigned int dst_y_per_vm_vblank; 628 unsigned int dst_y_per_row_vblank; 629 unsigned int dst_y_per_vm_flip; 630 unsigned int dst_y_per_row_flip; 631 unsigned int ref_freq_to_pix_freq; 632 unsigned int vratio_prefetch; 633 unsigned int vratio_prefetch_c; 634 unsigned int refcyc_per_pte_group_vblank_l; 635 unsigned int refcyc_per_pte_group_vblank_c; 636 unsigned int refcyc_per_meta_chunk_vblank_l; 637 unsigned int refcyc_per_meta_chunk_vblank_c; 638 unsigned int refcyc_per_pte_group_flip_l; 639 unsigned int refcyc_per_pte_group_flip_c; 640 unsigned int refcyc_per_meta_chunk_flip_l; 641 unsigned int refcyc_per_meta_chunk_flip_c; 642 unsigned int dst_y_per_pte_row_nom_l; 643 unsigned int dst_y_per_pte_row_nom_c; 644 unsigned int refcyc_per_pte_group_nom_l; 645 unsigned int refcyc_per_pte_group_nom_c; 646 unsigned int dst_y_per_meta_row_nom_l; 647 unsigned int dst_y_per_meta_row_nom_c; 648 unsigned int refcyc_per_meta_chunk_nom_l; 649 unsigned int refcyc_per_meta_chunk_nom_c; 650 unsigned int refcyc_per_line_delivery_pre_l; 651 unsigned int refcyc_per_line_delivery_pre_c; 652 unsigned int refcyc_per_line_delivery_l; 653 unsigned int refcyc_per_line_delivery_c; 654 unsigned int chunk_hdl_adjust_cur0; 655 unsigned int chunk_hdl_adjust_cur1; 656 unsigned int vready_after_vcount0; 657 unsigned int dst_y_offset_cur0; 658 unsigned int dst_y_offset_cur1; 659 unsigned int xfc_reg_transfer_delay; 660 unsigned int xfc_reg_precharge_delay; 661 unsigned int xfc_reg_remote_surface_flip_latency; 662 unsigned int xfc_reg_prefetch_margin; 663 unsigned int dst_y_delta_drq_limit; 664 unsigned int refcyc_per_vm_group_vblank; 665 unsigned int refcyc_per_vm_group_flip; 666 unsigned int refcyc_per_vm_req_vblank; 667 unsigned int refcyc_per_vm_req_flip; 668 unsigned int refcyc_per_vm_dmdata; 669 unsigned int dmdata_dl_delta; 670 }; 671 672 struct _vcs_dpi_display_ttu_regs_st { 673 unsigned int qos_level_low_wm; 674 unsigned int qos_level_high_wm; 675 unsigned int min_ttu_vblank; 676 unsigned int qos_level_flip; 677 unsigned int refcyc_per_req_delivery_l; 678 unsigned int refcyc_per_req_delivery_c; 679 unsigned int refcyc_per_req_delivery_cur0; 680 unsigned int refcyc_per_req_delivery_cur1; 681 unsigned int refcyc_per_req_delivery_pre_l; 682 unsigned int refcyc_per_req_delivery_pre_c; 683 unsigned int refcyc_per_req_delivery_pre_cur0; 684 unsigned int refcyc_per_req_delivery_pre_cur1; 685 unsigned int qos_level_fixed_l; 686 unsigned int qos_level_fixed_c; 687 unsigned int qos_level_fixed_cur0; 688 unsigned int qos_level_fixed_cur1; 689 unsigned int qos_ramp_disable_l; 690 unsigned int qos_ramp_disable_c; 691 unsigned int qos_ramp_disable_cur0; 692 unsigned int qos_ramp_disable_cur1; 693 }; 694 695 struct _vcs_dpi_display_data_rq_regs_st { 696 unsigned int chunk_size; 697 unsigned int min_chunk_size; 698 unsigned int meta_chunk_size; 699 unsigned int min_meta_chunk_size; 700 unsigned int dpte_group_size; 701 unsigned int mpte_group_size; 702 unsigned int swath_height; 703 unsigned int pte_row_height_linear; 704 }; 705 706 struct _vcs_dpi_display_rq_regs_st { 707 display_data_rq_regs_st rq_regs_l; 708 display_data_rq_regs_st rq_regs_c; 709 unsigned int drq_expansion_mode; 710 unsigned int prq_expansion_mode; 711 unsigned int mrq_expansion_mode; 712 unsigned int crq_expansion_mode; 713 unsigned int plane1_base_address; 714 unsigned int aperture_low_addr; // bits [47:18] 715 unsigned int aperture_high_addr; // bits [47:18] 716 }; 717 718 struct _vcs_dpi_display_dlg_sys_params_st { 719 double t_mclk_wm_us; 720 double t_urg_wm_us; 721 double t_sr_wm_us; 722 double t_extra_us; 723 double mem_trip_us; 724 double deepsleep_dcfclk_mhz; 725 double total_flip_bw; 726 unsigned int total_flip_bytes; 727 }; 728 729 struct _vcs_dpi_display_arb_params_st { 730 int max_req_outstanding; 731 int min_req_outstanding; 732 int sat_level_us; 733 int hvm_min_req_outstand_commit_threshold; 734 int hvm_max_qos_commit_threshold; 735 int compbuf_reserved_space_kbytes; 736 }; 737 738 #endif /*__DISPLAY_MODE_STRUCTS_H__*/ 739