1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5 #ifndef __ASM_PGTABLE_H
6 #define __ASM_PGTABLE_H
7
8 #include <asm/bug.h>
9 #include <asm/proc-fns.h>
10
11 #include <asm/memory.h>
12 #include <asm/mte.h>
13 #include <asm/pgtable-hwdef.h>
14 #include <asm/pgtable-prot.h>
15 #include <asm/tlbflush.h>
16
17 /*
18 * VMALLOC range.
19 *
20 * VMALLOC_START: beginning of the kernel vmalloc space
21 * VMALLOC_END: extends to the available space below vmemmap, PCI I/O space
22 * and fixed mappings
23 */
24 #define VMALLOC_START (MODULES_END)
25 #define VMALLOC_END (VMEMMAP_START - SZ_256M)
26
27 #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
28
29 #ifndef __ASSEMBLY__
30
31 #include <asm/cmpxchg.h>
32 #include <asm/fixmap.h>
33 #include <linux/mmdebug.h>
34 #include <linux/mm_types.h>
35 #include <linux/sched.h>
36 #include <linux/page_table_check.h>
37
38 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
39 #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
40
41 /* Set stride and tlb_level in flush_*_tlb_range */
42 #define flush_pmd_tlb_range(vma, addr, end) \
43 __flush_tlb_range(vma, addr, end, PMD_SIZE, false, 2)
44 #define flush_pud_tlb_range(vma, addr, end) \
45 __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
46 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
47
arch_thp_swp_supported(void)48 static inline bool arch_thp_swp_supported(void)
49 {
50 return !system_supports_mte();
51 }
52 #define arch_thp_swp_supported arch_thp_swp_supported
53
54 /*
55 * Outside of a few very special situations (e.g. hibernation), we always
56 * use broadcast TLB invalidation instructions, therefore a spurious page
57 * fault on one CPU which has been handled concurrently by another CPU
58 * does not need to perform additional invalidation.
59 */
60 #define flush_tlb_fix_spurious_fault(vma, address) do { } while (0)
61
62 /*
63 * ZERO_PAGE is a global shared page that is always zero: used
64 * for zero-mapped memory areas etc..
65 */
66 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
67 #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page))
68
69 #define pte_ERROR(e) \
70 pr_err("%s:%d: bad pte %016llx.\n", __FILE__, __LINE__, pte_val(e))
71
72 /*
73 * Macros to convert between a physical address and its placement in a
74 * page table entry, taking care of 52-bit addresses.
75 */
76 #ifdef CONFIG_ARM64_PA_BITS_52
__pte_to_phys(pte_t pte)77 static inline phys_addr_t __pte_to_phys(pte_t pte)
78 {
79 return (pte_val(pte) & PTE_ADDR_LOW) |
80 ((pte_val(pte) & PTE_ADDR_HIGH) << 36);
81 }
__phys_to_pte_val(phys_addr_t phys)82 static inline pteval_t __phys_to_pte_val(phys_addr_t phys)
83 {
84 return (phys | (phys >> 36)) & PTE_ADDR_MASK;
85 }
86 #else
87 #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK)
88 #define __phys_to_pte_val(phys) (phys)
89 #endif
90
91 #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT)
92 #define pfn_pte(pfn,prot) \
93 __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
94
95 #define pte_none(pte) (!pte_val(pte))
96 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
97 #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
98
99 /*
100 * The following only work if pte_present(). Undefined behaviour otherwise.
101 */
102 #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
103 #define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
104 #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
105 #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
106 #define pte_user(pte) (!!(pte_val(pte) & PTE_USER))
107 #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN))
108 #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
109 #define pte_devmap(pte) (!!(pte_val(pte) & PTE_DEVMAP))
110 #define pte_tagged(pte) ((pte_val(pte) & PTE_ATTRINDX_MASK) == \
111 PTE_ATTRINDX(MT_NORMAL_TAGGED))
112
113 #define pte_cont_addr_end(addr, end) \
114 ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \
115 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
116 })
117
118 #define pmd_cont_addr_end(addr, end) \
119 ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \
120 (__boundary - 1 < (end) - 1) ? __boundary : (end); \
121 })
122
123 #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
124 #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
125 #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
126
127 #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
128 /*
129 * Execute-only user mappings do not have the PTE_USER bit set. All valid
130 * kernel mappings have the PTE_UXN bit set.
131 */
132 #define pte_valid_not_user(pte) \
133 ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN))
134 /*
135 * Could the pte be present in the TLB? We must check mm_tlb_flush_pending
136 * so that we don't erroneously return false for pages that have been
137 * remapped as PROT_NONE but are yet to be flushed from the TLB.
138 * Note that we can't make any assumptions based on the state of the access
139 * flag, since ptep_clear_flush_young() elides a DSB when invalidating the
140 * TLB.
141 */
142 #define pte_accessible(mm, pte) \
143 (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid(pte))
144
145 /*
146 * p??_access_permitted() is true for valid user mappings (PTE_USER
147 * bit set, subject to the write permission check). For execute-only
148 * mappings, like PROT_EXEC with EPAN (both PTE_USER and PTE_UXN bits
149 * not set) must return false. PROT_NONE mappings do not have the
150 * PTE_VALID bit set.
151 */
152 #define pte_access_permitted(pte, write) \
153 (((pte_val(pte) & (PTE_VALID | PTE_USER)) == (PTE_VALID | PTE_USER)) && (!(write) || pte_write(pte)))
154 #define pmd_access_permitted(pmd, write) \
155 (pte_access_permitted(pmd_pte(pmd), (write)))
156 #define pud_access_permitted(pud, write) \
157 (pte_access_permitted(pud_pte(pud), (write)))
158
clear_pte_bit(pte_t pte,pgprot_t prot)159 static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
160 {
161 pte_val(pte) &= ~pgprot_val(prot);
162 return pte;
163 }
164
set_pte_bit(pte_t pte,pgprot_t prot)165 static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
166 {
167 pte_val(pte) |= pgprot_val(prot);
168 return pte;
169 }
170
clear_pmd_bit(pmd_t pmd,pgprot_t prot)171 static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
172 {
173 pmd_val(pmd) &= ~pgprot_val(prot);
174 return pmd;
175 }
176
set_pmd_bit(pmd_t pmd,pgprot_t prot)177 static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
178 {
179 pmd_val(pmd) |= pgprot_val(prot);
180 return pmd;
181 }
182
pte_mkwrite(pte_t pte)183 static inline pte_t pte_mkwrite(pte_t pte)
184 {
185 pte = set_pte_bit(pte, __pgprot(PTE_WRITE));
186 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
187 return pte;
188 }
189
pte_mkclean(pte_t pte)190 static inline pte_t pte_mkclean(pte_t pte)
191 {
192 pte = clear_pte_bit(pte, __pgprot(PTE_DIRTY));
193 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
194
195 return pte;
196 }
197
pte_mkdirty(pte_t pte)198 static inline pte_t pte_mkdirty(pte_t pte)
199 {
200 pte = set_pte_bit(pte, __pgprot(PTE_DIRTY));
201
202 if (pte_write(pte))
203 pte = clear_pte_bit(pte, __pgprot(PTE_RDONLY));
204
205 return pte;
206 }
207
pte_wrprotect(pte_t pte)208 static inline pte_t pte_wrprotect(pte_t pte)
209 {
210 /*
211 * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY
212 * clear), set the PTE_DIRTY bit.
213 */
214 if (pte_hw_dirty(pte))
215 pte = pte_mkdirty(pte);
216
217 pte = clear_pte_bit(pte, __pgprot(PTE_WRITE));
218 pte = set_pte_bit(pte, __pgprot(PTE_RDONLY));
219 return pte;
220 }
221
pte_mkold(pte_t pte)222 static inline pte_t pte_mkold(pte_t pte)
223 {
224 return clear_pte_bit(pte, __pgprot(PTE_AF));
225 }
226
pte_mkyoung(pte_t pte)227 static inline pte_t pte_mkyoung(pte_t pte)
228 {
229 return set_pte_bit(pte, __pgprot(PTE_AF));
230 }
231
pte_mkspecial(pte_t pte)232 static inline pte_t pte_mkspecial(pte_t pte)
233 {
234 return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
235 }
236
pte_mkcont(pte_t pte)237 static inline pte_t pte_mkcont(pte_t pte)
238 {
239 pte = set_pte_bit(pte, __pgprot(PTE_CONT));
240 return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
241 }
242
pte_mknoncont(pte_t pte)243 static inline pte_t pte_mknoncont(pte_t pte)
244 {
245 return clear_pte_bit(pte, __pgprot(PTE_CONT));
246 }
247
pte_mkpresent(pte_t pte)248 static inline pte_t pte_mkpresent(pte_t pte)
249 {
250 return set_pte_bit(pte, __pgprot(PTE_VALID));
251 }
252
pmd_mkcont(pmd_t pmd)253 static inline pmd_t pmd_mkcont(pmd_t pmd)
254 {
255 return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
256 }
257
pte_mkdevmap(pte_t pte)258 static inline pte_t pte_mkdevmap(pte_t pte)
259 {
260 return set_pte_bit(pte, __pgprot(PTE_DEVMAP | PTE_SPECIAL));
261 }
262
set_pte(pte_t * ptep,pte_t pte)263 static inline void set_pte(pte_t *ptep, pte_t pte)
264 {
265 WRITE_ONCE(*ptep, pte);
266
267 /*
268 * Only if the new pte is valid and kernel, otherwise TLB maintenance
269 * or update_mmu_cache() have the necessary barriers.
270 */
271 if (pte_valid_not_user(pte)) {
272 dsb(ishst);
273 isb();
274 }
275 }
276
277 extern void __sync_icache_dcache(pte_t pteval);
278
279 /*
280 * PTE bits configuration in the presence of hardware Dirty Bit Management
281 * (PTE_WRITE == PTE_DBM):
282 *
283 * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
284 * 0 0 | 1 0 0
285 * 0 1 | 1 1 0
286 * 1 0 | 1 0 1
287 * 1 1 | 0 1 x
288 *
289 * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
290 * the page fault mechanism. Checking the dirty status of a pte becomes:
291 *
292 * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
293 */
294
__check_racy_pte_update(struct mm_struct * mm,pte_t * ptep,pte_t pte)295 static inline void __check_racy_pte_update(struct mm_struct *mm, pte_t *ptep,
296 pte_t pte)
297 {
298 pte_t old_pte;
299
300 if (!IS_ENABLED(CONFIG_DEBUG_VM))
301 return;
302
303 old_pte = READ_ONCE(*ptep);
304
305 if (!pte_valid(old_pte) || !pte_valid(pte))
306 return;
307 if (mm != current->active_mm && atomic_read(&mm->mm_users) <= 1)
308 return;
309
310 /*
311 * Check for potential race with hardware updates of the pte
312 * (ptep_set_access_flags safely changes valid ptes without going
313 * through an invalid entry).
314 */
315 VM_WARN_ONCE(!pte_young(pte),
316 "%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
317 __func__, pte_val(old_pte), pte_val(pte));
318 VM_WARN_ONCE(pte_write(old_pte) && !pte_dirty(pte),
319 "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
320 __func__, pte_val(old_pte), pte_val(pte));
321 }
322
__set_pte_at(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pte)323 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
324 pte_t *ptep, pte_t pte)
325 {
326 if (pte_present(pte) && pte_user_exec(pte) && !pte_special(pte))
327 __sync_icache_dcache(pte);
328
329 /*
330 * If the PTE would provide user space access to the tags associated
331 * with it then ensure that the MTE tags are synchronised. Although
332 * pte_access_permitted() returns false for exec only mappings, they
333 * don't expose tags (instruction fetches don't check tags).
334 */
335 if (system_supports_mte() && pte_access_permitted(pte, false) &&
336 !pte_special(pte)) {
337 pte_t old_pte = READ_ONCE(*ptep);
338 /*
339 * We only need to synchronise if the new PTE has tags enabled
340 * or if swapping in (in which case another mapping may have
341 * set tags in the past even if this PTE isn't tagged).
342 * (!pte_none() && !pte_present()) is an open coded version of
343 * is_swap_pte()
344 */
345 if (pte_tagged(pte) || (!pte_none(old_pte) && !pte_present(old_pte)))
346 mte_sync_tags(old_pte, pte);
347 }
348
349 __check_racy_pte_update(mm, ptep, pte);
350
351 set_pte(ptep, pte);
352 }
353
set_pte_at(struct mm_struct * mm,unsigned long addr,pte_t * ptep,pte_t pte)354 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
355 pte_t *ptep, pte_t pte)
356 {
357 page_table_check_pte_set(mm, addr, ptep, pte);
358 return __set_pte_at(mm, addr, ptep, pte);
359 }
360
361 /*
362 * Huge pte definitions.
363 */
364 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
365
366 /*
367 * Hugetlb definitions.
368 */
369 #define HUGE_MAX_HSTATE 4
370 #define HPAGE_SHIFT PMD_SHIFT
371 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
372 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
373 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
374
pgd_pte(pgd_t pgd)375 static inline pte_t pgd_pte(pgd_t pgd)
376 {
377 return __pte(pgd_val(pgd));
378 }
379
p4d_pte(p4d_t p4d)380 static inline pte_t p4d_pte(p4d_t p4d)
381 {
382 return __pte(p4d_val(p4d));
383 }
384
pud_pte(pud_t pud)385 static inline pte_t pud_pte(pud_t pud)
386 {
387 return __pte(pud_val(pud));
388 }
389
pte_pud(pte_t pte)390 static inline pud_t pte_pud(pte_t pte)
391 {
392 return __pud(pte_val(pte));
393 }
394
pud_pmd(pud_t pud)395 static inline pmd_t pud_pmd(pud_t pud)
396 {
397 return __pmd(pud_val(pud));
398 }
399
pmd_pte(pmd_t pmd)400 static inline pte_t pmd_pte(pmd_t pmd)
401 {
402 return __pte(pmd_val(pmd));
403 }
404
pte_pmd(pte_t pte)405 static inline pmd_t pte_pmd(pte_t pte)
406 {
407 return __pmd(pte_val(pte));
408 }
409
mk_pud_sect_prot(pgprot_t prot)410 static inline pgprot_t mk_pud_sect_prot(pgprot_t prot)
411 {
412 return __pgprot((pgprot_val(prot) & ~PUD_TABLE_BIT) | PUD_TYPE_SECT);
413 }
414
mk_pmd_sect_prot(pgprot_t prot)415 static inline pgprot_t mk_pmd_sect_prot(pgprot_t prot)
416 {
417 return __pgprot((pgprot_val(prot) & ~PMD_TABLE_BIT) | PMD_TYPE_SECT);
418 }
419
420 #define __HAVE_ARCH_PTE_SWP_EXCLUSIVE
pte_swp_mkexclusive(pte_t pte)421 static inline pte_t pte_swp_mkexclusive(pte_t pte)
422 {
423 return set_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE));
424 }
425
pte_swp_exclusive(pte_t pte)426 static inline int pte_swp_exclusive(pte_t pte)
427 {
428 return pte_val(pte) & PTE_SWP_EXCLUSIVE;
429 }
430
pte_swp_clear_exclusive(pte_t pte)431 static inline pte_t pte_swp_clear_exclusive(pte_t pte)
432 {
433 return clear_pte_bit(pte, __pgprot(PTE_SWP_EXCLUSIVE));
434 }
435
436 /*
437 * Select all bits except the pfn
438 */
pte_pgprot(pte_t pte)439 static inline pgprot_t pte_pgprot(pte_t pte)
440 {
441 unsigned long pfn = pte_pfn(pte);
442
443 return __pgprot(pte_val(pfn_pte(pfn, __pgprot(0))) ^ pte_val(pte));
444 }
445
446 #ifdef CONFIG_NUMA_BALANCING
447 /*
448 * See the comment in include/linux/pgtable.h
449 */
pte_protnone(pte_t pte)450 static inline int pte_protnone(pte_t pte)
451 {
452 return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE;
453 }
454
pmd_protnone(pmd_t pmd)455 static inline int pmd_protnone(pmd_t pmd)
456 {
457 return pte_protnone(pmd_pte(pmd));
458 }
459 #endif
460
461 #define pmd_present_invalid(pmd) (!!(pmd_val(pmd) & PMD_PRESENT_INVALID))
462
pmd_present(pmd_t pmd)463 static inline int pmd_present(pmd_t pmd)
464 {
465 return pte_present(pmd_pte(pmd)) || pmd_present_invalid(pmd);
466 }
467
468 /*
469 * THP definitions.
470 */
471
472 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
pmd_trans_huge(pmd_t pmd)473 static inline int pmd_trans_huge(pmd_t pmd)
474 {
475 return pmd_val(pmd) && pmd_present(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
476 }
477 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
478
479 #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
480 #define pmd_young(pmd) pte_young(pmd_pte(pmd))
481 #define pmd_valid(pmd) pte_valid(pmd_pte(pmd))
482 #define pmd_user(pmd) pte_user(pmd_pte(pmd))
483 #define pmd_user_exec(pmd) pte_user_exec(pmd_pte(pmd))
484 #define pmd_cont(pmd) pte_cont(pmd_pte(pmd))
485 #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
486 #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
487 #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
488 #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
489 #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
490 #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
491
pmd_mkinvalid(pmd_t pmd)492 static inline pmd_t pmd_mkinvalid(pmd_t pmd)
493 {
494 pmd = set_pmd_bit(pmd, __pgprot(PMD_PRESENT_INVALID));
495 pmd = clear_pmd_bit(pmd, __pgprot(PMD_SECT_VALID));
496
497 return pmd;
498 }
499
500 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
501
502 #define pmd_write(pmd) pte_write(pmd_pte(pmd))
503
504 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
505
506 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
507 #define pmd_devmap(pmd) pte_devmap(pmd_pte(pmd))
508 #endif
pmd_mkdevmap(pmd_t pmd)509 static inline pmd_t pmd_mkdevmap(pmd_t pmd)
510 {
511 return pte_pmd(set_pte_bit(pmd_pte(pmd), __pgprot(PTE_DEVMAP)));
512 }
513
514 #define __pmd_to_phys(pmd) __pte_to_phys(pmd_pte(pmd))
515 #define __phys_to_pmd_val(phys) __phys_to_pte_val(phys)
516 #define pmd_pfn(pmd) ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT)
517 #define pfn_pmd(pfn,prot) __pmd(__phys_to_pmd_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
518 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
519
520 #define pud_young(pud) pte_young(pud_pte(pud))
521 #define pud_mkyoung(pud) pte_pud(pte_mkyoung(pud_pte(pud)))
522 #define pud_write(pud) pte_write(pud_pte(pud))
523
524 #define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
525
526 #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
527 #define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
528 #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
529 #define pfn_pud(pfn,prot) __pud(__phys_to_pud_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
530
set_pmd_at(struct mm_struct * mm,unsigned long addr,pmd_t * pmdp,pmd_t pmd)531 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
532 pmd_t *pmdp, pmd_t pmd)
533 {
534 page_table_check_pmd_set(mm, addr, pmdp, pmd);
535 return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd));
536 }
537
set_pud_at(struct mm_struct * mm,unsigned long addr,pud_t * pudp,pud_t pud)538 static inline void set_pud_at(struct mm_struct *mm, unsigned long addr,
539 pud_t *pudp, pud_t pud)
540 {
541 page_table_check_pud_set(mm, addr, pudp, pud);
542 return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud));
543 }
544
545 #define __p4d_to_phys(p4d) __pte_to_phys(p4d_pte(p4d))
546 #define __phys_to_p4d_val(phys) __phys_to_pte_val(phys)
547
548 #define __pgd_to_phys(pgd) __pte_to_phys(pgd_pte(pgd))
549 #define __phys_to_pgd_val(phys) __phys_to_pte_val(phys)
550
551 #define __pgprot_modify(prot,mask,bits) \
552 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
553
554 #define pgprot_nx(prot) \
555 __pgprot_modify(prot, PTE_MAYBE_GP, PTE_PXN)
556
557 /*
558 * Mark the prot value as uncacheable and unbufferable.
559 */
560 #define pgprot_noncached(prot) \
561 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
562 #define pgprot_writecombine(prot) \
563 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
564 #define pgprot_device(prot) \
565 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
566 #define pgprot_tagged(prot) \
567 __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_TAGGED))
568 #define pgprot_mhp pgprot_tagged
569 /*
570 * DMA allocations for non-coherent devices use what the Arm architecture calls
571 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses
572 * and merging of writes. This is different from "Device-nGnR[nE]" memory which
573 * is intended for MMIO and thus forbids speculation, preserves access size,
574 * requires strict alignment and can also force write responses to come from the
575 * endpoint.
576 */
577 #define pgprot_dmacoherent(prot) \
578 __pgprot_modify(prot, PTE_ATTRINDX_MASK, \
579 PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
580
581 #define __HAVE_PHYS_MEM_ACCESS_PROT
582 struct file;
583 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
584 unsigned long size, pgprot_t vma_prot);
585
586 #define pmd_none(pmd) (!pmd_val(pmd))
587
588 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
589 PMD_TYPE_TABLE)
590 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
591 PMD_TYPE_SECT)
592 #define pmd_leaf(pmd) (pmd_present(pmd) && !pmd_table(pmd))
593 #define pmd_bad(pmd) (!pmd_table(pmd))
594
595 #define pmd_leaf_size(pmd) (pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE)
596 #define pte_leaf_size(pte) (pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE)
597
598 #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3
pud_sect(pud_t pud)599 static inline bool pud_sect(pud_t pud) { return false; }
pud_table(pud_t pud)600 static inline bool pud_table(pud_t pud) { return true; }
601 #else
602 #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
603 PUD_TYPE_SECT)
604 #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
605 PUD_TYPE_TABLE)
606 #endif
607
608 extern pgd_t init_pg_dir[PTRS_PER_PGD];
609 extern pgd_t init_pg_end[];
610 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
611 extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
612 extern pgd_t idmap_pg_end[];
613 extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
614 extern pgd_t reserved_pg_dir[PTRS_PER_PGD];
615
616 extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd);
617
in_swapper_pgdir(void * addr)618 static inline bool in_swapper_pgdir(void *addr)
619 {
620 return ((unsigned long)addr & PAGE_MASK) ==
621 ((unsigned long)swapper_pg_dir & PAGE_MASK);
622 }
623
set_pmd(pmd_t * pmdp,pmd_t pmd)624 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
625 {
626 #ifdef __PAGETABLE_PMD_FOLDED
627 if (in_swapper_pgdir(pmdp)) {
628 set_swapper_pgd((pgd_t *)pmdp, __pgd(pmd_val(pmd)));
629 return;
630 }
631 #endif /* __PAGETABLE_PMD_FOLDED */
632
633 WRITE_ONCE(*pmdp, pmd);
634
635 if (pmd_valid(pmd)) {
636 dsb(ishst);
637 isb();
638 }
639 }
640
pmd_clear(pmd_t * pmdp)641 static inline void pmd_clear(pmd_t *pmdp)
642 {
643 set_pmd(pmdp, __pmd(0));
644 }
645
pmd_page_paddr(pmd_t pmd)646 static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
647 {
648 return __pmd_to_phys(pmd);
649 }
650
pmd_page_vaddr(pmd_t pmd)651 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
652 {
653 return (unsigned long)__va(pmd_page_paddr(pmd));
654 }
655
656 /* Find an entry in the third-level page table. */
657 #define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
658
659 #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr))
660 #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr))
661 #define pte_clear_fixmap() clear_fixmap(FIX_PTE)
662
663 #define pmd_page(pmd) phys_to_page(__pmd_to_phys(pmd))
664
665 /* use ONLY for statically allocated translation tables */
666 #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr))))
667
668 /*
669 * Conversion functions: convert a page and protection to a page entry,
670 * and a page entry and page directory to the page they refer to.
671 */
672 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
673
674 #if CONFIG_PGTABLE_LEVELS > 2
675
676 #define pmd_ERROR(e) \
677 pr_err("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e))
678
679 #define pud_none(pud) (!pud_val(pud))
680 #define pud_bad(pud) (!pud_table(pud))
681 #define pud_present(pud) pte_present(pud_pte(pud))
682 #define pud_leaf(pud) (pud_present(pud) && !pud_table(pud))
683 #define pud_valid(pud) pte_valid(pud_pte(pud))
684 #define pud_user(pud) pte_user(pud_pte(pud))
685 #define pud_user_exec(pud) pte_user_exec(pud_pte(pud))
686
set_pud(pud_t * pudp,pud_t pud)687 static inline void set_pud(pud_t *pudp, pud_t pud)
688 {
689 #ifdef __PAGETABLE_PUD_FOLDED
690 if (in_swapper_pgdir(pudp)) {
691 set_swapper_pgd((pgd_t *)pudp, __pgd(pud_val(pud)));
692 return;
693 }
694 #endif /* __PAGETABLE_PUD_FOLDED */
695
696 WRITE_ONCE(*pudp, pud);
697
698 if (pud_valid(pud)) {
699 dsb(ishst);
700 isb();
701 }
702 }
703
pud_clear(pud_t * pudp)704 static inline void pud_clear(pud_t *pudp)
705 {
706 set_pud(pudp, __pud(0));
707 }
708
pud_page_paddr(pud_t pud)709 static inline phys_addr_t pud_page_paddr(pud_t pud)
710 {
711 return __pud_to_phys(pud);
712 }
713
pud_pgtable(pud_t pud)714 static inline pmd_t *pud_pgtable(pud_t pud)
715 {
716 return (pmd_t *)__va(pud_page_paddr(pud));
717 }
718
719 /* Find an entry in the second-level page table. */
720 #define pmd_offset_phys(dir, addr) (pud_page_paddr(READ_ONCE(*(dir))) + pmd_index(addr) * sizeof(pmd_t))
721
722 #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr))
723 #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr))
724 #define pmd_clear_fixmap() clear_fixmap(FIX_PMD)
725
726 #define pud_page(pud) phys_to_page(__pud_to_phys(pud))
727
728 /* use ONLY for statically allocated translation tables */
729 #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr))))
730
731 #else
732
733 #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; })
734
735 /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */
736 #define pmd_set_fixmap(addr) NULL
737 #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp)
738 #define pmd_clear_fixmap()
739
740 #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir)
741
742 #endif /* CONFIG_PGTABLE_LEVELS > 2 */
743
744 #if CONFIG_PGTABLE_LEVELS > 3
745
746 #define pud_ERROR(e) \
747 pr_err("%s:%d: bad pud %016llx.\n", __FILE__, __LINE__, pud_val(e))
748
749 #define p4d_none(p4d) (!p4d_val(p4d))
750 #define p4d_bad(p4d) (!(p4d_val(p4d) & 2))
751 #define p4d_present(p4d) (p4d_val(p4d))
752
set_p4d(p4d_t * p4dp,p4d_t p4d)753 static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
754 {
755 if (in_swapper_pgdir(p4dp)) {
756 set_swapper_pgd((pgd_t *)p4dp, __pgd(p4d_val(p4d)));
757 return;
758 }
759
760 WRITE_ONCE(*p4dp, p4d);
761 dsb(ishst);
762 isb();
763 }
764
p4d_clear(p4d_t * p4dp)765 static inline void p4d_clear(p4d_t *p4dp)
766 {
767 set_p4d(p4dp, __p4d(0));
768 }
769
p4d_page_paddr(p4d_t p4d)770 static inline phys_addr_t p4d_page_paddr(p4d_t p4d)
771 {
772 return __p4d_to_phys(p4d);
773 }
774
p4d_pgtable(p4d_t p4d)775 static inline pud_t *p4d_pgtable(p4d_t p4d)
776 {
777 return (pud_t *)__va(p4d_page_paddr(p4d));
778 }
779
780 /* Find an entry in the first-level page table. */
781 #define pud_offset_phys(dir, addr) (p4d_page_paddr(READ_ONCE(*(dir))) + pud_index(addr) * sizeof(pud_t))
782
783 #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr))
784 #define pud_set_fixmap_offset(p4d, addr) pud_set_fixmap(pud_offset_phys(p4d, addr))
785 #define pud_clear_fixmap() clear_fixmap(FIX_PUD)
786
787 #define p4d_page(p4d) pfn_to_page(__phys_to_pfn(__p4d_to_phys(p4d)))
788
789 /* use ONLY for statically allocated translation tables */
790 #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr))))
791
792 #else
793
794 #define p4d_page_paddr(p4d) ({ BUILD_BUG(); 0;})
795 #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;})
796
797 /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */
798 #define pud_set_fixmap(addr) NULL
799 #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp)
800 #define pud_clear_fixmap()
801
802 #define pud_offset_kimg(dir,addr) ((pud_t *)dir)
803
804 #endif /* CONFIG_PGTABLE_LEVELS > 3 */
805
806 #define pgd_ERROR(e) \
807 pr_err("%s:%d: bad pgd %016llx.\n", __FILE__, __LINE__, pgd_val(e))
808
809 #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr))
810 #define pgd_clear_fixmap() clear_fixmap(FIX_PGD)
811
pte_modify(pte_t pte,pgprot_t newprot)812 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
813 {
814 /*
815 * Normal and Normal-Tagged are two different memory types and indices
816 * in MAIR_EL1. The mask below has to include PTE_ATTRINDX_MASK.
817 */
818 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
819 PTE_PROT_NONE | PTE_VALID | PTE_WRITE | PTE_GP |
820 PTE_ATTRINDX_MASK;
821 /* preserve the hardware dirty information */
822 if (pte_hw_dirty(pte))
823 pte = pte_mkdirty(pte);
824 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
825 return pte;
826 }
827
pmd_modify(pmd_t pmd,pgprot_t newprot)828 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
829 {
830 return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
831 }
832
833 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
834 extern int ptep_set_access_flags(struct vm_area_struct *vma,
835 unsigned long address, pte_t *ptep,
836 pte_t entry, int dirty);
837
838 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
839 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
pmdp_set_access_flags(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp,pmd_t entry,int dirty)840 static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
841 unsigned long address, pmd_t *pmdp,
842 pmd_t entry, int dirty)
843 {
844 return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty);
845 }
846
pud_devmap(pud_t pud)847 static inline int pud_devmap(pud_t pud)
848 {
849 return 0;
850 }
851
pgd_devmap(pgd_t pgd)852 static inline int pgd_devmap(pgd_t pgd)
853 {
854 return 0;
855 }
856 #endif
857
858 #ifdef CONFIG_PAGE_TABLE_CHECK
pte_user_accessible_page(pte_t pte)859 static inline bool pte_user_accessible_page(pte_t pte)
860 {
861 return pte_present(pte) && (pte_user(pte) || pte_user_exec(pte));
862 }
863
pmd_user_accessible_page(pmd_t pmd)864 static inline bool pmd_user_accessible_page(pmd_t pmd)
865 {
866 return pmd_leaf(pmd) && !pmd_present_invalid(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd));
867 }
868
pud_user_accessible_page(pud_t pud)869 static inline bool pud_user_accessible_page(pud_t pud)
870 {
871 return pud_leaf(pud) && (pud_user(pud) || pud_user_exec(pud));
872 }
873 #endif
874
875 /*
876 * Atomic pte/pmd modifications.
877 */
878 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
__ptep_test_and_clear_young(pte_t * ptep)879 static inline int __ptep_test_and_clear_young(pte_t *ptep)
880 {
881 pte_t old_pte, pte;
882
883 pte = READ_ONCE(*ptep);
884 do {
885 old_pte = pte;
886 pte = pte_mkold(pte);
887 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
888 pte_val(old_pte), pte_val(pte));
889 } while (pte_val(pte) != pte_val(old_pte));
890
891 return pte_young(pte);
892 }
893
ptep_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)894 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
895 unsigned long address,
896 pte_t *ptep)
897 {
898 return __ptep_test_and_clear_young(ptep);
899 }
900
901 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
ptep_clear_flush_young(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)902 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
903 unsigned long address, pte_t *ptep)
904 {
905 int young = ptep_test_and_clear_young(vma, address, ptep);
906
907 if (young) {
908 /*
909 * We can elide the trailing DSB here since the worst that can
910 * happen is that a CPU continues to use the young entry in its
911 * TLB and we mistakenly reclaim the associated page. The
912 * window for such an event is bounded by the next
913 * context-switch, which provides a DSB to complete the TLB
914 * invalidation.
915 */
916 flush_tlb_page_nosync(vma, address);
917 }
918
919 return young;
920 }
921
922 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
923 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
pmdp_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp)924 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
925 unsigned long address,
926 pmd_t *pmdp)
927 {
928 return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
929 }
930 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
931
932 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
ptep_get_and_clear(struct mm_struct * mm,unsigned long address,pte_t * ptep)933 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
934 unsigned long address, pte_t *ptep)
935 {
936 pte_t pte = __pte(xchg_relaxed(&pte_val(*ptep), 0));
937
938 page_table_check_pte_clear(mm, address, pte);
939
940 return pte;
941 }
942
943 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
944 #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
pmdp_huge_get_and_clear(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)945 static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
946 unsigned long address, pmd_t *pmdp)
947 {
948 pmd_t pmd = __pmd(xchg_relaxed(&pmd_val(*pmdp), 0));
949
950 page_table_check_pmd_clear(mm, address, pmd);
951
952 return pmd;
953 }
954 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
955
956 /*
957 * ptep_set_wrprotect - mark read-only while trasferring potential hardware
958 * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
959 */
960 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
ptep_set_wrprotect(struct mm_struct * mm,unsigned long address,pte_t * ptep)961 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
962 {
963 pte_t old_pte, pte;
964
965 pte = READ_ONCE(*ptep);
966 do {
967 old_pte = pte;
968 pte = pte_wrprotect(pte);
969 pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep),
970 pte_val(old_pte), pte_val(pte));
971 } while (pte_val(pte) != pte_val(old_pte));
972 }
973
974 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
975 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
pmdp_set_wrprotect(struct mm_struct * mm,unsigned long address,pmd_t * pmdp)976 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
977 unsigned long address, pmd_t *pmdp)
978 {
979 ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
980 }
981
982 #define pmdp_establish pmdp_establish
pmdp_establish(struct vm_area_struct * vma,unsigned long address,pmd_t * pmdp,pmd_t pmd)983 static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
984 unsigned long address, pmd_t *pmdp, pmd_t pmd)
985 {
986 page_table_check_pmd_set(vma->vm_mm, address, pmdp, pmd);
987 return __pmd(xchg_relaxed(&pmd_val(*pmdp), pmd_val(pmd)));
988 }
989 #endif
990
991 /*
992 * Encode and decode a swap entry:
993 * bits 0-1: present (must be zero)
994 * bits 2: remember PG_anon_exclusive
995 * bits 3-7: swap type
996 * bits 8-57: swap offset
997 * bit 58: PTE_PROT_NONE (must be zero)
998 */
999 #define __SWP_TYPE_SHIFT 3
1000 #define __SWP_TYPE_BITS 5
1001 #define __SWP_OFFSET_BITS 50
1002 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
1003 #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
1004 #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
1005
1006 #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
1007 #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
1008 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
1009
1010 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1011 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
1012
1013 #ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
1014 #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val(pmd) })
1015 #define __swp_entry_to_pmd(swp) __pmd((swp).val)
1016 #endif /* CONFIG_ARCH_ENABLE_THP_MIGRATION */
1017
1018 /*
1019 * Ensure that there are not more swap files than can be encoded in the kernel
1020 * PTEs.
1021 */
1022 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
1023
1024 extern int kern_addr_valid(unsigned long addr);
1025
1026 #ifdef CONFIG_ARM64_MTE
1027
1028 #define __HAVE_ARCH_PREPARE_TO_SWAP
arch_prepare_to_swap(struct page * page)1029 static inline int arch_prepare_to_swap(struct page *page)
1030 {
1031 if (system_supports_mte())
1032 return mte_save_tags(page);
1033 return 0;
1034 }
1035
1036 #define __HAVE_ARCH_SWAP_INVALIDATE
arch_swap_invalidate_page(int type,pgoff_t offset)1037 static inline void arch_swap_invalidate_page(int type, pgoff_t offset)
1038 {
1039 if (system_supports_mte())
1040 mte_invalidate_tags(type, offset);
1041 }
1042
arch_swap_invalidate_area(int type)1043 static inline void arch_swap_invalidate_area(int type)
1044 {
1045 if (system_supports_mte())
1046 mte_invalidate_tags_area(type);
1047 }
1048
1049 #define __HAVE_ARCH_SWAP_RESTORE
arch_swap_restore(swp_entry_t entry,struct folio * folio)1050 static inline void arch_swap_restore(swp_entry_t entry, struct folio *folio)
1051 {
1052 if (system_supports_mte() && mte_restore_tags(entry, &folio->page))
1053 set_bit(PG_mte_tagged, &folio->flags);
1054 }
1055
1056 #endif /* CONFIG_ARM64_MTE */
1057
1058 /*
1059 * On AArch64, the cache coherency is handled via the set_pte_at() function.
1060 */
update_mmu_cache(struct vm_area_struct * vma,unsigned long addr,pte_t * ptep)1061 static inline void update_mmu_cache(struct vm_area_struct *vma,
1062 unsigned long addr, pte_t *ptep)
1063 {
1064 /*
1065 * We don't do anything here, so there's a very small chance of
1066 * us retaking a user fault which we just fixed up. The alternative
1067 * is doing a dsb(ishst), but that penalises the fastpath.
1068 */
1069 }
1070
1071 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
1072
1073 #ifdef CONFIG_ARM64_PA_BITS_52
1074 #define phys_to_ttbr(addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52)
1075 #else
1076 #define phys_to_ttbr(addr) (addr)
1077 #endif
1078
1079 /*
1080 * On arm64 without hardware Access Flag, copying from user will fail because
1081 * the pte is old and cannot be marked young. So we always end up with zeroed
1082 * page after fork() + CoW for pfn mappings. We don't always have a
1083 * hardware-managed access flag on arm64.
1084 */
1085 #define arch_has_hw_pte_young cpu_has_hw_af
1086
1087 /*
1088 * Experimentally, it's cheap to set the access flag in hardware and we
1089 * benefit from prefaulting mappings as 'old' to start with.
1090 */
1091 #define arch_wants_old_prefaulted_pte cpu_has_hw_af
1092
pud_sect_supported(void)1093 static inline bool pud_sect_supported(void)
1094 {
1095 return PAGE_SIZE == SZ_4K;
1096 }
1097
1098
1099 #endif /* !__ASSEMBLY__ */
1100
1101 #endif /* __ASM_PGTABLE_H */
1102