1 /* $Id: pci_psycho.c,v 1.30.2.3 2002/03/03 10:31:56 davem Exp $
2 * pci_psycho.c: PSYCHO/U2P specific PCI controller support.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/init.h>
13 #include <linux/slab.h>
14
15 #include <asm/pbm.h>
16 #include <asm/iommu.h>
17 #include <asm/irq.h>
18 #include <asm/starfire.h>
19
20 #include "pci_impl.h"
21 #include "iommu_common.h"
22
23 /* All PSYCHO registers are 64-bits. The following accessor
24 * routines are how they are accessed. The REG parameter
25 * is a physical address.
26 */
27 #define psycho_read(__reg) \
28 ({ u64 __ret; \
29 __asm__ __volatile__("ldxa [%1] %2, %0" \
30 : "=r" (__ret) \
31 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
32 : "memory"); \
33 __ret; \
34 })
35 #define psycho_write(__reg, __val) \
36 __asm__ __volatile__("stxa %0, [%1] %2" \
37 : /* no outputs */ \
38 : "r" (__val), "r" (__reg), \
39 "i" (ASI_PHYS_BYPASS_EC_E) \
40 : "memory")
41
42 /* Misc. PSYCHO PCI controller register offsets and definitions. */
43 #define PSYCHO_CONTROL 0x0010UL
44 #define PSYCHO_CONTROL_IMPL 0xf000000000000000 /* Implementation of this PSYCHO*/
45 #define PSYCHO_CONTROL_VER 0x0f00000000000000 /* Version of this PSYCHO */
46 #define PSYCHO_CONTROL_MID 0x00f8000000000000 /* UPA Module ID of PSYCHO */
47 #define PSYCHO_CONTROL_IGN 0x0007c00000000000 /* Interrupt Group Number */
48 #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0 /* Reserved */
49 #define PSYCHO_CONTROL_APCKEN 0x0000000000000008 /* Address Parity Check Enable */
50 #define PSYCHO_CONTROL_APERR 0x0000000000000004 /* Incoming System Addr Parerr */
51 #define PSYCHO_CONTROL_IAP 0x0000000000000002 /* Invert UPA Parity */
52 #define PSYCHO_CONTROL_MODE 0x0000000000000001 /* PSYCHO clock mode */
53 #define PSYCHO_PCIA_CTRL 0x2000UL
54 #define PSYCHO_PCIB_CTRL 0x4000UL
55 #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000 /* Reserved */
56 #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000 /* Streaming byte hole error */
57 #define PSYCHO_PCICTRL_SERR 0x0000000400000000 /* SERR signal asserted */
58 #define PSYCHO_PCICTRL_SPEED 0x0000000200000000 /* PCI speed (1 is U2P clock) */
59 #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000 /* Reserved */
60 #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000 /* PCI arbitration parking */
61 #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800 /* Reserved */
62 #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400 /* Streaming byte hole int enab */
63 #define PSYCHO_PCICTRL_WEN 0x0000000000000200 /* Power Mgmt Wake Enable */
64 #define PSYCHO_PCICTRL_EEN 0x0000000000000100 /* PCI Error Interrupt Enable */
65 #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0 /* Reserved */
66 #define PSYCHO_PCICTRL_AEN 0x000000000000003f /* PCI DVMA Arbitration Enable */
67
68 /* U2P Programmer's Manual, page 13-55, configuration space
69 * address format:
70 *
71 * 32 24 23 16 15 11 10 8 7 2 1 0
72 * ---------------------------------------------------------
73 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
74 * ---------------------------------------------------------
75 */
76 #define PSYCHO_CONFIG_BASE(PBM) \
77 ((PBM)->config_space | (1UL << 24))
78 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
79 (((unsigned long)(BUS) << 16) | \
80 ((unsigned long)(DEVFN) << 8) | \
81 ((unsigned long)(REG)))
82
psycho_pci_config_mkaddr(struct pci_pbm_info * pbm,unsigned char bus,unsigned int devfn,int where)83 static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
84 unsigned char bus,
85 unsigned int devfn,
86 int where)
87 {
88 if (!pbm)
89 return NULL;
90 return (void *)
91 (PSYCHO_CONFIG_BASE(pbm) |
92 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
93 }
94
psycho_out_of_range(struct pci_pbm_info * pbm,unsigned char bus,unsigned char devfn)95 static int psycho_out_of_range(struct pci_pbm_info *pbm,
96 unsigned char bus,
97 unsigned char devfn)
98 {
99 return ((pbm->parent == 0) ||
100 ((pbm == &pbm->parent->pbm_B) &&
101 (bus == pbm->pci_first_busno) &&
102 PCI_SLOT(devfn) > 8) ||
103 ((pbm == &pbm->parent->pbm_A) &&
104 (bus == pbm->pci_first_busno) &&
105 PCI_SLOT(devfn) > 8));
106 }
107
108 /* PSYCHO PCI configuration space accessors. */
109
psycho_read_byte(struct pci_dev * dev,int where,u8 * value)110 static int psycho_read_byte(struct pci_dev *dev, int where, u8 *value)
111 {
112 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
113 unsigned char bus = dev->bus->number;
114 unsigned int devfn = dev->devfn;
115 u8 *addr;
116
117 *value = 0xff;
118 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
119 if (!addr)
120 return PCIBIOS_SUCCESSFUL;
121
122 if (psycho_out_of_range(pbm, bus, devfn))
123 return PCIBIOS_SUCCESSFUL;
124 pci_config_read8(addr, value);
125 return PCIBIOS_SUCCESSFUL;
126 }
127
psycho_read_word(struct pci_dev * dev,int where,u16 * value)128 static int psycho_read_word(struct pci_dev *dev, int where, u16 *value)
129 {
130 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
131 unsigned char bus = dev->bus->number;
132 unsigned int devfn = dev->devfn;
133 u16 *addr;
134
135 *value = 0xffff;
136 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
137 if (!addr)
138 return PCIBIOS_SUCCESSFUL;
139
140 if (psycho_out_of_range(pbm, bus, devfn))
141 return PCIBIOS_SUCCESSFUL;
142
143 if (where & 0x01) {
144 printk("pcibios_read_config_word: misaligned reg [%x]\n",
145 where);
146 return PCIBIOS_SUCCESSFUL;
147 }
148 pci_config_read16(addr, value);
149 return PCIBIOS_SUCCESSFUL;
150 }
151
psycho_read_dword(struct pci_dev * dev,int where,u32 * value)152 static int psycho_read_dword(struct pci_dev *dev, int where, u32 *value)
153 {
154 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
155 unsigned char bus = dev->bus->number;
156 unsigned int devfn = dev->devfn;
157 u32 *addr;
158
159 *value = 0xffffffff;
160 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
161 if (!addr)
162 return PCIBIOS_SUCCESSFUL;
163
164 if (psycho_out_of_range(pbm, bus, devfn))
165 return PCIBIOS_SUCCESSFUL;
166
167 if (where & 0x03) {
168 printk("pcibios_read_config_dword: misaligned reg [%x]\n",
169 where);
170 return PCIBIOS_SUCCESSFUL;
171 }
172
173 pci_config_read32(addr, value);
174 return PCIBIOS_SUCCESSFUL;
175 }
176
psycho_write_byte(struct pci_dev * dev,int where,u8 value)177 static int psycho_write_byte(struct pci_dev *dev, int where, u8 value)
178 {
179 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
180 unsigned char bus = dev->bus->number;
181 unsigned int devfn = dev->devfn;
182 u8 *addr;
183
184 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
185 if (!addr)
186 return PCIBIOS_SUCCESSFUL;
187
188 if (psycho_out_of_range(pbm, bus, devfn))
189 return PCIBIOS_SUCCESSFUL;
190
191 pci_config_write8(addr, value);
192 return PCIBIOS_SUCCESSFUL;
193 }
194
psycho_write_word(struct pci_dev * dev,int where,u16 value)195 static int psycho_write_word(struct pci_dev *dev, int where, u16 value)
196 {
197 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
198 unsigned char bus = dev->bus->number;
199 unsigned int devfn = dev->devfn;
200 u16 *addr;
201
202 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
203 if (!addr)
204 return PCIBIOS_SUCCESSFUL;
205
206 if (psycho_out_of_range(pbm, bus, devfn))
207 return PCIBIOS_SUCCESSFUL;
208
209 if (where & 0x01) {
210 printk("pcibios_write_config_word: misaligned reg [%x]\n",
211 where);
212 return PCIBIOS_SUCCESSFUL;
213 }
214 pci_config_write16(addr, value);
215 return PCIBIOS_SUCCESSFUL;
216 }
217
psycho_write_dword(struct pci_dev * dev,int where,u32 value)218 static int psycho_write_dword(struct pci_dev *dev, int where, u32 value)
219 {
220 struct pci_pbm_info *pbm = pci_bus2pbm[dev->bus->number];
221 unsigned char bus = dev->bus->number;
222 unsigned int devfn = dev->devfn;
223 u32 *addr;
224
225 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
226 if (!addr)
227 return PCIBIOS_SUCCESSFUL;
228
229 if (psycho_out_of_range(pbm, bus, devfn))
230 return PCIBIOS_SUCCESSFUL;
231
232 if (where & 0x03) {
233 printk("pcibios_write_config_dword: misaligned reg [%x]\n",
234 where);
235 return PCIBIOS_SUCCESSFUL;
236 }
237 pci_config_write32(addr, value);
238 return PCIBIOS_SUCCESSFUL;
239 }
240
241 static struct pci_ops psycho_ops = {
242 psycho_read_byte,
243 psycho_read_word,
244 psycho_read_dword,
245 psycho_write_byte,
246 psycho_write_word,
247 psycho_write_dword
248 };
249
250 /* PSYCHO interrupt mapping support. */
251 #define PSYCHO_IMAP_A_SLOT0 0x0c00UL
252 #define PSYCHO_IMAP_B_SLOT0 0x0c20UL
psycho_pcislot_imap_offset(unsigned long ino)253 static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
254 {
255 unsigned int bus = (ino & 0x10) >> 4;
256 unsigned int slot = (ino & 0x0c) >> 2;
257
258 if (bus == 0)
259 return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
260 else
261 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
262 }
263
264 #define PSYCHO_IMAP_SCSI 0x1000UL
265 #define PSYCHO_IMAP_ETH 0x1008UL
266 #define PSYCHO_IMAP_BPP 0x1010UL
267 #define PSYCHO_IMAP_AU_REC 0x1018UL
268 #define PSYCHO_IMAP_AU_PLAY 0x1020UL
269 #define PSYCHO_IMAP_PFAIL 0x1028UL
270 #define PSYCHO_IMAP_KMS 0x1030UL
271 #define PSYCHO_IMAP_FLPY 0x1038UL
272 #define PSYCHO_IMAP_SHW 0x1040UL
273 #define PSYCHO_IMAP_KBD 0x1048UL
274 #define PSYCHO_IMAP_MS 0x1050UL
275 #define PSYCHO_IMAP_SER 0x1058UL
276 #define PSYCHO_IMAP_TIM0 0x1060UL
277 #define PSYCHO_IMAP_TIM1 0x1068UL
278 #define PSYCHO_IMAP_UE 0x1070UL
279 #define PSYCHO_IMAP_CE 0x1078UL
280 #define PSYCHO_IMAP_A_ERR 0x1080UL
281 #define PSYCHO_IMAP_B_ERR 0x1088UL
282 #define PSYCHO_IMAP_PMGMT 0x1090UL
283 #define PSYCHO_IMAP_GFX 0x1098UL
284 #define PSYCHO_IMAP_EUPA 0x10a0UL
285
286 static unsigned long __onboard_imap_off[] = {
287 /*0x20*/ PSYCHO_IMAP_SCSI,
288 /*0x21*/ PSYCHO_IMAP_ETH,
289 /*0x22*/ PSYCHO_IMAP_BPP,
290 /*0x23*/ PSYCHO_IMAP_AU_REC,
291 /*0x24*/ PSYCHO_IMAP_AU_PLAY,
292 /*0x25*/ PSYCHO_IMAP_PFAIL,
293 /*0x26*/ PSYCHO_IMAP_KMS,
294 /*0x27*/ PSYCHO_IMAP_FLPY,
295 /*0x28*/ PSYCHO_IMAP_SHW,
296 /*0x29*/ PSYCHO_IMAP_KBD,
297 /*0x2a*/ PSYCHO_IMAP_MS,
298 /*0x2b*/ PSYCHO_IMAP_SER,
299 /*0x2c*/ PSYCHO_IMAP_TIM0,
300 /*0x2d*/ PSYCHO_IMAP_TIM1,
301 /*0x2e*/ PSYCHO_IMAP_UE,
302 /*0x2f*/ PSYCHO_IMAP_CE,
303 /*0x30*/ PSYCHO_IMAP_A_ERR,
304 /*0x31*/ PSYCHO_IMAP_B_ERR,
305 /*0x32*/ PSYCHO_IMAP_PMGMT
306 };
307 #define PSYCHO_ONBOARD_IRQ_BASE 0x20
308 #define PSYCHO_ONBOARD_IRQ_LAST 0x32
309 #define psycho_onboard_imap_offset(__ino) \
310 __onboard_imap_off[(__ino) - PSYCHO_ONBOARD_IRQ_BASE]
311
312 #define PSYCHO_ICLR_A_SLOT0 0x1400UL
313 #define PSYCHO_ICLR_SCSI 0x1800UL
314
315 #define psycho_iclr_offset(ino) \
316 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
317 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
318
319 /* PCI PSYCHO INO number to Sparc PIL level. */
320 static unsigned char psycho_pil_table[] = {
321 /*0x00*/0, 0, 0, 0, /* PCI A slot 0 Int A, B, C, D */
322 /*0x04*/0, 0, 0, 0, /* PCI A slot 1 Int A, B, C, D */
323 /*0x08*/0, 0, 0, 0, /* PCI A slot 2 Int A, B, C, D */
324 /*0x0c*/0, 0, 0, 0, /* PCI A slot 3 Int A, B, C, D */
325 /*0x10*/0, 0, 0, 0, /* PCI B slot 0 Int A, B, C, D */
326 /*0x14*/0, 0, 0, 0, /* PCI B slot 1 Int A, B, C, D */
327 /*0x18*/0, 0, 0, 0, /* PCI B slot 2 Int A, B, C, D */
328 /*0x1c*/0, 0, 0, 0, /* PCI B slot 3 Int A, B, C, D */
329 /*0x20*/4, /* SCSI */
330 /*0x21*/5, /* Ethernet */
331 /*0x22*/8, /* Parallel Port */
332 /*0x23*/13, /* Audio Record */
333 /*0x24*/14, /* Audio Playback */
334 /*0x25*/15, /* PowerFail */
335 /*0x26*/4, /* second SCSI */
336 /*0x27*/11, /* Floppy */
337 /*0x28*/4, /* Spare Hardware */
338 /*0x29*/9, /* Keyboard */
339 /*0x2a*/4, /* Mouse */
340 /*0x2b*/12, /* Serial */
341 /*0x2c*/10, /* Timer 0 */
342 /*0x2d*/11, /* Timer 1 */
343 /*0x2e*/15, /* Uncorrectable ECC */
344 /*0x2f*/15, /* Correctable ECC */
345 /*0x30*/15, /* PCI Bus A Error */
346 /*0x31*/15, /* PCI Bus B Error */
347 /*0x32*/15, /* Power Management */
348 };
349
psycho_ino_to_pil(struct pci_dev * pdev,unsigned int ino)350 static int __init psycho_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
351 {
352 int ret;
353
354 ret = psycho_pil_table[ino];
355 if (ret == 0 && pdev == NULL) {
356 ret = 4;
357 } else if (ret == 0) {
358 switch ((pdev->class >> 16) & 0xff) {
359 case PCI_BASE_CLASS_STORAGE:
360 ret = 4;
361 break;
362
363 case PCI_BASE_CLASS_NETWORK:
364 ret = 6;
365 break;
366
367 case PCI_BASE_CLASS_DISPLAY:
368 ret = 9;
369 break;
370
371 case PCI_BASE_CLASS_MULTIMEDIA:
372 case PCI_BASE_CLASS_MEMORY:
373 case PCI_BASE_CLASS_BRIDGE:
374 case PCI_BASE_CLASS_SERIAL:
375 ret = 10;
376 break;
377
378 default:
379 ret = 4;
380 break;
381 };
382 }
383
384 return ret;
385 }
386
psycho_irq_build(struct pci_pbm_info * pbm,struct pci_dev * pdev,unsigned int ino)387 static unsigned int __init psycho_irq_build(struct pci_pbm_info *pbm,
388 struct pci_dev *pdev,
389 unsigned int ino)
390 {
391 struct ino_bucket *bucket;
392 unsigned long imap, iclr;
393 unsigned long imap_off, iclr_off;
394 int pil, inofixup = 0;
395
396 ino &= PCI_IRQ_INO;
397 if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
398 /* PCI slot */
399 imap_off = psycho_pcislot_imap_offset(ino);
400 } else {
401 /* Onboard device */
402 if (ino > PSYCHO_ONBOARD_IRQ_LAST) {
403 prom_printf("psycho_irq_build: Wacky INO [%x]\n", ino);
404 prom_halt();
405 }
406 imap_off = psycho_onboard_imap_offset(ino);
407 }
408
409 /* Now build the IRQ bucket. */
410 pil = psycho_ino_to_pil(pdev, ino);
411
412 if (PIL_RESERVED(pil))
413 BUG();
414
415 imap = pbm->controller_regs + imap_off;
416 imap += 4;
417
418 iclr_off = psycho_iclr_offset(ino);
419 iclr = pbm->controller_regs + iclr_off;
420 iclr += 4;
421
422 if ((ino & 0x20) == 0)
423 inofixup = ino & 0x03;
424
425 bucket = __bucket(build_irq(pil, inofixup, iclr, imap));
426 bucket->flags |= IBF_PCI;
427
428 return __irq(bucket);
429 }
430
431 /* PSYCHO error handling support. */
432 enum psycho_error_type {
433 UE_ERR, CE_ERR, PCI_ERR
434 };
435
436 /* Helper function of IOMMU error checking, which checks out
437 * the state of the streaming buffers. The IOMMU lock is
438 * held when this is called.
439 *
440 * For the PCI error case we know which PBM (and thus which
441 * streaming buffer) caused the error, but for the uncorrectable
442 * error case we do not. So we always check both streaming caches.
443 */
444 #define PSYCHO_STRBUF_CONTROL_A 0x2800UL
445 #define PSYCHO_STRBUF_CONTROL_B 0x4800UL
446 #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0 /* LRU Lock Pointer */
447 #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008 /* LRU Lock Enable */
448 #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004 /* Rerun Disable */
449 #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002 /* Diagnostic Mode Enable */
450 #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001 /* Streaming Buffer Enable */
451 #define PSYCHO_STRBUF_FLUSH_A 0x2808UL
452 #define PSYCHO_STRBUF_FLUSH_B 0x4808UL
453 #define PSYCHO_STRBUF_FSYNC_A 0x2810UL
454 #define PSYCHO_STRBUF_FSYNC_B 0x4810UL
455 #define PSYCHO_STC_DATA_A 0xb000UL
456 #define PSYCHO_STC_DATA_B 0xc000UL
457 #define PSYCHO_STC_ERR_A 0xb400UL
458 #define PSYCHO_STC_ERR_B 0xc400UL
459 #define PSYCHO_STCERR_WRITE 0x0000000000000002 /* Write Error */
460 #define PSYCHO_STCERR_READ 0x0000000000000001 /* Read Error */
461 #define PSYCHO_STC_TAG_A 0xb800UL
462 #define PSYCHO_STC_TAG_B 0xc800UL
463 #define PSYCHO_STCTAG_PPN 0x0fffffff00000000 /* Physical Page Number */
464 #define PSYCHO_STCTAG_VPN 0x00000000ffffe000 /* Virtual Page Number */
465 #define PSYCHO_STCTAG_VALID 0x0000000000000002 /* Valid */
466 #define PSYCHO_STCTAG_WRITE 0x0000000000000001 /* Writable */
467 #define PSYCHO_STC_LINE_A 0xb900UL
468 #define PSYCHO_STC_LINE_B 0xc900UL
469 #define PSYCHO_STCLINE_LINDX 0x0000000001e00000 /* LRU Index */
470 #define PSYCHO_STCLINE_SPTR 0x00000000001f8000 /* Dirty Data Start Pointer */
471 #define PSYCHO_STCLINE_LADDR 0x0000000000007f00 /* Line Address */
472 #define PSYCHO_STCLINE_EPTR 0x00000000000000fc /* Dirty Data End Pointer */
473 #define PSYCHO_STCLINE_VALID 0x0000000000000002 /* Valid */
474 #define PSYCHO_STCLINE_FOFN 0x0000000000000001 /* Fetch Outstanding / Flush Necessary */
475
476 static spinlock_t stc_buf_lock = SPIN_LOCK_UNLOCKED;
477 static unsigned long stc_error_buf[128];
478 static unsigned long stc_tag_buf[16];
479 static unsigned long stc_line_buf[16];
480
__psycho_check_one_stc(struct pci_controller_info * p,struct pci_pbm_info * pbm,int is_pbm_a)481 static void __psycho_check_one_stc(struct pci_controller_info *p,
482 struct pci_pbm_info *pbm,
483 int is_pbm_a)
484 {
485 struct pci_strbuf *strbuf = &pbm->stc;
486 unsigned long regbase = p->pbm_A.controller_regs;
487 unsigned long err_base, tag_base, line_base;
488 u64 control;
489 int i;
490
491 if (is_pbm_a) {
492 err_base = regbase + PSYCHO_STC_ERR_A;
493 tag_base = regbase + PSYCHO_STC_TAG_A;
494 line_base = regbase + PSYCHO_STC_LINE_A;
495 } else {
496 err_base = regbase + PSYCHO_STC_ERR_A;
497 tag_base = regbase + PSYCHO_STC_TAG_A;
498 line_base = regbase + PSYCHO_STC_LINE_A;
499 }
500
501 spin_lock(&stc_buf_lock);
502
503 /* This is __REALLY__ dangerous. When we put the
504 * streaming buffer into diagnostic mode to probe
505 * it's tags and error status, we _must_ clear all
506 * of the line tag valid bits before re-enabling
507 * the streaming buffer. If any dirty data lives
508 * in the STC when we do this, we will end up
509 * invalidating it before it has a chance to reach
510 * main memory.
511 */
512 control = psycho_read(strbuf->strbuf_control);
513 psycho_write(strbuf->strbuf_control,
514 (control | PSYCHO_STRBUF_CTRL_DENAB));
515 for (i = 0; i < 128; i++) {
516 unsigned long val;
517
518 val = psycho_read(err_base + (i * 8UL));
519 psycho_write(err_base + (i * 8UL), 0UL);
520 stc_error_buf[i] = val;
521 }
522 for (i = 0; i < 16; i++) {
523 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
524 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
525 psycho_write(tag_base + (i * 8UL), 0UL);
526 psycho_write(line_base + (i * 8UL), 0UL);
527 }
528
529 /* OK, state is logged, exit diagnostic mode. */
530 psycho_write(strbuf->strbuf_control, control);
531
532 for (i = 0; i < 16; i++) {
533 int j, saw_error, first, last;
534
535 saw_error = 0;
536 first = i * 8;
537 last = first + 8;
538 for (j = first; j < last; j++) {
539 unsigned long errval = stc_error_buf[j];
540 if (errval != 0) {
541 saw_error++;
542 printk("PSYCHO%d(PBM%c): STC_ERR(%d)[wr(%d)rd(%d)]\n",
543 p->index,
544 (is_pbm_a ? 'A' : 'B'),
545 j,
546 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
547 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
548 }
549 }
550 if (saw_error != 0) {
551 unsigned long tagval = stc_tag_buf[i];
552 unsigned long lineval = stc_line_buf[i];
553 printk("PSYCHO%d(PBM%c): STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
554 p->index,
555 (is_pbm_a ? 'A' : 'B'),
556 i,
557 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
558 (tagval & PSYCHO_STCTAG_VPN),
559 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
560 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
561 printk("PSYCHO%d(PBM%c): STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
562 "V(%d)FOFN(%d)]\n",
563 p->index,
564 (is_pbm_a ? 'A' : 'B'),
565 i,
566 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
567 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
568 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
569 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
570 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
571 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
572 }
573 }
574
575 spin_unlock(&stc_buf_lock);
576 }
577
__psycho_check_stc_error(struct pci_controller_info * p,unsigned long afsr,unsigned long afar,enum psycho_error_type type)578 static void __psycho_check_stc_error(struct pci_controller_info *p,
579 unsigned long afsr,
580 unsigned long afar,
581 enum psycho_error_type type)
582 {
583 struct pci_pbm_info *pbm;
584
585 pbm = &p->pbm_A;
586 if (pbm->stc.strbuf_enabled)
587 __psycho_check_one_stc(p, pbm, 1);
588
589 pbm = &p->pbm_B;
590 if (pbm->stc.strbuf_enabled)
591 __psycho_check_one_stc(p, pbm, 0);
592 }
593
594 /* When an Uncorrectable Error or a PCI Error happens, we
595 * interrogate the IOMMU state to see if it is the cause.
596 */
597 #define PSYCHO_IOMMU_CONTROL 0x0200UL
598 #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000 /* Reserved */
599 #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000 /* Translation Error Status */
600 #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000 /* Translation Error encountered */
601 #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000 /* Enable translation locking */
602 #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000 /* Translation lock pointer */
603 #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000 /* TSB Size */
604 #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000 /* TSB Table 1024 8-byte entries */
605 #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000 /* TSB Table 2048 8-byte entries */
606 #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000 /* TSB Table 4096 8-byte entries */
607 #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000 /* TSB Table 8192 8-byte entries */
608 #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000 /* TSB Table 16k 8-byte entries */
609 #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000 /* TSB Table 32k 8-byte entries */
610 #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000 /* TSB Table 64k 8-byte entries */
611 #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000 /* TSB Table 128k 8-byte entries */
612 #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8 /* Reserved */
613 #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004 /* Assumed page size, 0=8k 1=64k */
614 #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002 /* Diagnostic mode enable */
615 #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001 /* IOMMU Enable */
616 #define PSYCHO_IOMMU_TSBBASE 0x0208UL
617 #define PSYCHO_IOMMU_FLUSH 0x0210UL
618 #define PSYCHO_IOMMU_TAG 0xa580UL
619 #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
620 #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
621 #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
622 #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
623 #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
624 #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
625 #define PSYCHO_IOMMU_DATA 0xa600UL
626 #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
627 #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
628 #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
psycho_check_iommu_error(struct pci_controller_info * p,unsigned long afsr,unsigned long afar,enum psycho_error_type type)629 static void psycho_check_iommu_error(struct pci_controller_info *p,
630 unsigned long afsr,
631 unsigned long afar,
632 enum psycho_error_type type)
633 {
634 struct pci_iommu *iommu = p->pbm_A.iommu;
635 unsigned long iommu_tag[16];
636 unsigned long iommu_data[16];
637 unsigned long flags;
638 u64 control;
639 int i;
640
641 spin_lock_irqsave(&iommu->lock, flags);
642 control = psycho_read(iommu->iommu_control);
643 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
644 char *type_string;
645
646 /* Clear the error encountered bit. */
647 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
648 psycho_write(iommu->iommu_control, control);
649
650 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
651 case 0:
652 type_string = "Protection Error";
653 break;
654 case 1:
655 type_string = "Invalid Error";
656 break;
657 case 2:
658 type_string = "TimeOut Error";
659 break;
660 case 3:
661 default:
662 type_string = "ECC Error";
663 break;
664 };
665 printk("PSYCHO%d: IOMMU Error, type[%s]\n",
666 p->index, type_string);
667
668 /* Put the IOMMU into diagnostic mode and probe
669 * it's TLB for entries with error status.
670 *
671 * It is very possible for another DVMA to occur
672 * while we do this probe, and corrupt the system
673 * further. But we are so screwed at this point
674 * that we are likely to crash hard anyways, so
675 * get as much diagnostic information to the
676 * console as we can.
677 */
678 psycho_write(iommu->iommu_control,
679 control | PSYCHO_IOMMU_CTRL_DENAB);
680 for (i = 0; i < 16; i++) {
681 unsigned long base = p->pbm_A.controller_regs;
682
683 iommu_tag[i] =
684 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
685 iommu_data[i] =
686 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
687
688 /* Now clear out the entry. */
689 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
690 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
691 }
692
693 /* Leave diagnostic mode. */
694 psycho_write(iommu->iommu_control, control);
695
696 for (i = 0; i < 16; i++) {
697 unsigned long tag, data;
698
699 tag = iommu_tag[i];
700 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
701 continue;
702
703 data = iommu_data[i];
704 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
705 case 0:
706 type_string = "Protection Error";
707 break;
708 case 1:
709 type_string = "Invalid Error";
710 break;
711 case 2:
712 type_string = "TimeOut Error";
713 break;
714 case 3:
715 default:
716 type_string = "ECC Error";
717 break;
718 };
719 printk("PSYCHO%d: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
720 p->index, i, type_string,
721 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
722 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
723 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
724 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
725 printk("PSYCHO%d: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
726 p->index, i,
727 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
728 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
729 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
730 }
731 }
732 __psycho_check_stc_error(p, afsr, afar, type);
733 spin_unlock_irqrestore(&iommu->lock, flags);
734 }
735
736 /* Uncorrectable Errors. Cause of the error and the address are
737 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
738 * relating to UPA interface transactions.
739 */
740 #define PSYCHO_UE_AFSR 0x0030UL
741 #define PSYCHO_UEAFSR_PPIO 0x8000000000000000 /* Primary PIO is cause */
742 #define PSYCHO_UEAFSR_PDRD 0x4000000000000000 /* Primary DVMA read is cause */
743 #define PSYCHO_UEAFSR_PDWR 0x2000000000000000 /* Primary DVMA write is cause */
744 #define PSYCHO_UEAFSR_SPIO 0x1000000000000000 /* Secondary PIO is cause */
745 #define PSYCHO_UEAFSR_SDRD 0x0800000000000000 /* Secondary DVMA read is cause */
746 #define PSYCHO_UEAFSR_SDWR 0x0400000000000000 /* Secondary DVMA write is cause*/
747 #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000 /* Reserved */
748 #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000 /* Bytemask of failed transfer */
749 #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000 /* Doubleword Offset */
750 #define PSYCHO_UEAFSR_MID 0x000000001f000000 /* UPA MID causing the fault */
751 #define PSYCHO_UEAFSR_BLK 0x0000000000800000 /* Trans was block operation */
752 #define PSYCHO_UEAFSR_RESV2 0x00000000007fffff /* Reserved */
753 #define PSYCHO_UE_AFAR 0x0038UL
754
psycho_ue_intr(int irq,void * dev_id,struct pt_regs * regs)755 static void psycho_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
756 {
757 struct pci_controller_info *p = dev_id;
758 unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFSR;
759 unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFAR;
760 unsigned long afsr, afar, error_bits;
761 int reported;
762
763 /* Latch uncorrectable error status. */
764 afar = psycho_read(afar_reg);
765 afsr = psycho_read(afsr_reg);
766
767 /* Clear the primary/secondary error status bits. */
768 error_bits = afsr &
769 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
770 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
771 if (!error_bits)
772 return;
773 psycho_write(afsr_reg, error_bits);
774
775 /* Log the error. */
776 printk("PSYCHO%d: Uncorrectable Error, primary error type[%s]\n",
777 p->index,
778 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
779 "PIO" :
780 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
781 "DMA Read" :
782 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
783 "DMA Write" : "???")))));
784 printk("PSYCHO%d: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
785 p->index,
786 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
787 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
788 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
789 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
790 printk("PSYCHO%d: UE AFAR [%016lx]\n", p->index, afar);
791 printk("PSYCHO%d: UE Secondary errors [", p->index);
792 reported = 0;
793 if (afsr & PSYCHO_UEAFSR_SPIO) {
794 reported++;
795 printk("(PIO)");
796 }
797 if (afsr & PSYCHO_UEAFSR_SDRD) {
798 reported++;
799 printk("(DMA Read)");
800 }
801 if (afsr & PSYCHO_UEAFSR_SDWR) {
802 reported++;
803 printk("(DMA Write)");
804 }
805 if (!reported)
806 printk("(none)");
807 printk("]\n");
808
809 /* Interrogate IOMMU for error status. */
810 psycho_check_iommu_error(p, afsr, afar, UE_ERR);
811 }
812
813 /* Correctable Errors. */
814 #define PSYCHO_CE_AFSR 0x0040UL
815 #define PSYCHO_CEAFSR_PPIO 0x8000000000000000 /* Primary PIO is cause */
816 #define PSYCHO_CEAFSR_PDRD 0x4000000000000000 /* Primary DVMA read is cause */
817 #define PSYCHO_CEAFSR_PDWR 0x2000000000000000 /* Primary DVMA write is cause */
818 #define PSYCHO_CEAFSR_SPIO 0x1000000000000000 /* Secondary PIO is cause */
819 #define PSYCHO_CEAFSR_SDRD 0x0800000000000000 /* Secondary DVMA read is cause */
820 #define PSYCHO_CEAFSR_SDWR 0x0400000000000000 /* Secondary DVMA write is cause*/
821 #define PSYCHO_CEAFSR_RESV1 0x0300000000000000 /* Reserved */
822 #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000 /* Syndrome Bits */
823 #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000 /* Bytemask of failed transfer */
824 #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000 /* Double Offset */
825 #define PSYCHO_CEAFSR_MID 0x000000001f000000 /* UPA MID causing the fault */
826 #define PSYCHO_CEAFSR_BLK 0x0000000000800000 /* Trans was block operation */
827 #define PSYCHO_CEAFSR_RESV2 0x00000000007fffff /* Reserved */
828 #define PSYCHO_CE_AFAR 0x0040UL
829
psycho_ce_intr(int irq,void * dev_id,struct pt_regs * regs)830 static void psycho_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
831 {
832 struct pci_controller_info *p = dev_id;
833 unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFSR;
834 unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFAR;
835 unsigned long afsr, afar, error_bits;
836 int reported;
837
838 /* Latch error status. */
839 afar = psycho_read(afar_reg);
840 afsr = psycho_read(afsr_reg);
841
842 /* Clear primary/secondary error status bits. */
843 error_bits = afsr &
844 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
845 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
846 if (!error_bits)
847 return;
848 psycho_write(afsr_reg, error_bits);
849
850 /* Log the error. */
851 printk("PSYCHO%d: Correctable Error, primary error type[%s]\n",
852 p->index,
853 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
854 "PIO" :
855 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
856 "DMA Read" :
857 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
858 "DMA Write" : "???")))));
859
860 /* XXX Use syndrome and afar to print out module string just like
861 * XXX UDB CE trap handler does... -DaveM
862 */
863 printk("PSYCHO%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
864 "UPA_MID[%02lx] was_block(%d)\n",
865 p->index,
866 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
867 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
868 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
869 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
870 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
871 printk("PSYCHO%d: CE AFAR [%016lx]\n", p->index, afar);
872 printk("PSYCHO%d: CE Secondary errors [", p->index);
873 reported = 0;
874 if (afsr & PSYCHO_CEAFSR_SPIO) {
875 reported++;
876 printk("(PIO)");
877 }
878 if (afsr & PSYCHO_CEAFSR_SDRD) {
879 reported++;
880 printk("(DMA Read)");
881 }
882 if (afsr & PSYCHO_CEAFSR_SDWR) {
883 reported++;
884 printk("(DMA Write)");
885 }
886 if (!reported)
887 printk("(none)");
888 printk("]\n");
889 }
890
891 /* PCI Errors. They are signalled by the PCI bus module since they
892 * are assosciated with a specific bus segment.
893 */
894 #define PSYCHO_PCI_AFSR_A 0x2010UL
895 #define PSYCHO_PCI_AFSR_B 0x4010UL
896 #define PSYCHO_PCIAFSR_PMA 0x8000000000000000 /* Primary Master Abort Error */
897 #define PSYCHO_PCIAFSR_PTA 0x4000000000000000 /* Primary Target Abort Error */
898 #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000 /* Primary Excessive Retries */
899 #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000 /* Primary Parity Error */
900 #define PSYCHO_PCIAFSR_SMA 0x0800000000000000 /* Secondary Master Abort Error */
901 #define PSYCHO_PCIAFSR_STA 0x0400000000000000 /* Secondary Target Abort Error */
902 #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000 /* Secondary Excessive Retries */
903 #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000 /* Secondary Parity Error */
904 #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000 /* Reserved */
905 #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000 /* Bytemask of failed transfer */
906 #define PSYCHO_PCIAFSR_BLK 0x0000000080000000 /* Trans was block operation */
907 #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000 /* Reserved */
908 #define PSYCHO_PCIAFSR_MID 0x000000003e000000 /* MID causing the error */
909 #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffff /* Reserved */
910 #define PSYCHO_PCI_AFAR_A 0x2018UL
911 #define PSYCHO_PCI_AFAR_B 0x4018UL
912
psycho_pcierr_intr_other(struct pci_pbm_info * pbm,int is_pbm_a)913 static void psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a)
914 {
915 unsigned long csr_reg, csr, csr_error_bits;
916 u16 stat;
917
918 if (is_pbm_a) {
919 csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL;
920 } else {
921 csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL;
922 }
923 csr = psycho_read(csr_reg);
924 csr_error_bits =
925 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
926 if (csr_error_bits) {
927 /* Clear the errors. */
928 psycho_write(csr_reg, csr);
929
930 /* Log 'em. */
931 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
932 printk("%s: PCI streaming byte hole error asserted.\n",
933 pbm->name);
934 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
935 printk("%s: PCI SERR signal asserted.\n", pbm->name);
936 }
937 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
938 if (stat & (PCI_STATUS_PARITY |
939 PCI_STATUS_SIG_TARGET_ABORT |
940 PCI_STATUS_REC_TARGET_ABORT |
941 PCI_STATUS_REC_MASTER_ABORT |
942 PCI_STATUS_SIG_SYSTEM_ERROR)) {
943 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
944 pbm->name, stat);
945 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
946 }
947 }
948
psycho_pcierr_intr(int irq,void * dev_id,struct pt_regs * regs)949 static void psycho_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
950 {
951 struct pci_pbm_info *pbm = dev_id;
952 struct pci_controller_info *p = pbm->parent;
953 unsigned long afsr_reg, afar_reg;
954 unsigned long afsr, afar, error_bits;
955 int is_pbm_a, reported;
956
957 is_pbm_a = (pbm == &pbm->parent->pbm_A);
958 if (is_pbm_a) {
959 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A;
960 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A;
961 } else {
962 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B;
963 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B;
964 }
965
966 /* Latch error status. */
967 afar = psycho_read(afar_reg);
968 afsr = psycho_read(afsr_reg);
969
970 /* Clear primary/secondary error status bits. */
971 error_bits = afsr &
972 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
973 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
974 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
975 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
976 if (!error_bits)
977 return psycho_pcierr_intr_other(pbm, is_pbm_a);
978 psycho_write(afsr_reg, error_bits);
979
980 /* Log the error. */
981 printk("PSYCHO%d(PBM%c): PCI Error, primary error type[%s]\n",
982 p->index, (is_pbm_a ? 'A' : 'B'),
983 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
984 "Master Abort" :
985 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
986 "Target Abort" :
987 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
988 "Excessive Retries" :
989 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
990 "Parity Error" : "???"))))));
991 printk("PSYCHO%d(PBM%c): bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
992 p->index, (is_pbm_a ? 'A' : 'B'),
993 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
994 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
995 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
996 printk("PSYCHO%d(PBM%c): PCI AFAR [%016lx]\n",
997 p->index, (is_pbm_a ? 'A' : 'B'), afar);
998 printk("PSYCHO%d(PBM%c): PCI Secondary errors [",
999 p->index, (is_pbm_a ? 'A' : 'B'));
1000 reported = 0;
1001 if (afsr & PSYCHO_PCIAFSR_SMA) {
1002 reported++;
1003 printk("(Master Abort)");
1004 }
1005 if (afsr & PSYCHO_PCIAFSR_STA) {
1006 reported++;
1007 printk("(Target Abort)");
1008 }
1009 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
1010 reported++;
1011 printk("(Excessive Retries)");
1012 }
1013 if (afsr & PSYCHO_PCIAFSR_SPERR) {
1014 reported++;
1015 printk("(Parity Error)");
1016 }
1017 if (!reported)
1018 printk("(none)");
1019 printk("]\n");
1020
1021 /* For the error types shown, scan PBM's PCI bus for devices
1022 * which have logged that error type.
1023 */
1024
1025 /* If we see a Target Abort, this could be the result of an
1026 * IOMMU translation error of some sort. It is extremely
1027 * useful to log this information as usually it indicates
1028 * a bug in the IOMMU support code or a PCI device driver.
1029 */
1030 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
1031 psycho_check_iommu_error(p, afsr, afar, PCI_ERR);
1032 pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
1033 }
1034 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
1035 pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
1036
1037 /* For excessive retries, PSYCHO/PBM will abort the device
1038 * and there is no way to specifically check for excessive
1039 * retries in the config space status registers. So what
1040 * we hope is that we'll catch it via the master/target
1041 * abort events.
1042 */
1043
1044 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
1045 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
1046 }
1047
1048 /* XXX What about PowerFail/PowerManagement??? -DaveM */
1049 #define PSYCHO_ECC_CTRL 0x0020
1050 #define PSYCHO_ECCCTRL_EE 0x8000000000000000 /* Enable ECC Checking */
1051 #define PSYCHO_ECCCTRL_UE 0x4000000000000000 /* Enable UE Interrupts */
1052 #define PSYCHO_ECCCTRL_CE 0x2000000000000000 /* Enable CE INterrupts */
1053 #define PSYCHO_UE_INO 0x2e
1054 #define PSYCHO_CE_INO 0x2f
1055 #define PSYCHO_PCIERR_A_INO 0x30
1056 #define PSYCHO_PCIERR_B_INO 0x31
psycho_register_error_handlers(struct pci_controller_info * p)1057 static void __init psycho_register_error_handlers(struct pci_controller_info *p)
1058 {
1059 struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
1060 unsigned long base = p->pbm_A.controller_regs;
1061 unsigned int irq, portid = pbm->portid;
1062 u64 tmp;
1063
1064 /* Build IRQs and register handlers. */
1065 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_UE_INO);
1066 if (request_irq(irq, psycho_ue_intr,
1067 SA_SHIRQ, "PSYCHO UE", p) < 0) {
1068 prom_printf("PSYCHO%d: Cannot register UE interrupt.\n",
1069 p->index);
1070 prom_halt();
1071 }
1072
1073 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_CE_INO);
1074 if (request_irq(irq, psycho_ce_intr,
1075 SA_SHIRQ, "PSYCHO CE", p) < 0) {
1076 prom_printf("PSYCHO%d: Cannot register CE interrupt.\n",
1077 p->index);
1078 prom_halt();
1079 }
1080
1081 pbm = &p->pbm_A;
1082 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_PCIERR_A_INO);
1083 if (request_irq(irq, psycho_pcierr_intr,
1084 SA_SHIRQ, "PSYCHO PCIERR", &p->pbm_A) < 0) {
1085 prom_printf("PSYCHO%d(PBMA): Cannot register PciERR interrupt.\n",
1086 p->index);
1087 prom_halt();
1088 }
1089
1090 pbm = &p->pbm_B;
1091 irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_PCIERR_B_INO);
1092 if (request_irq(irq, psycho_pcierr_intr,
1093 SA_SHIRQ, "PSYCHO PCIERR", &p->pbm_B) < 0) {
1094 prom_printf("PSYCHO%d(PBMB): Cannot register PciERR interrupt.\n",
1095 p->index);
1096 prom_halt();
1097 }
1098
1099 /* Enable UE and CE interrupts for controller. */
1100 psycho_write(base + PSYCHO_ECC_CTRL,
1101 (PSYCHO_ECCCTRL_EE |
1102 PSYCHO_ECCCTRL_UE |
1103 PSYCHO_ECCCTRL_CE));
1104
1105 /* Enable PCI Error interrupts and clear error
1106 * bits for each PBM.
1107 */
1108 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
1109 tmp |= (PSYCHO_PCICTRL_SERR |
1110 PSYCHO_PCICTRL_SBH_ERR |
1111 PSYCHO_PCICTRL_EEN);
1112 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
1113 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
1114
1115 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
1116 tmp |= (PSYCHO_PCICTRL_SERR |
1117 PSYCHO_PCICTRL_SBH_ERR |
1118 PSYCHO_PCICTRL_EEN);
1119 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
1120 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
1121 }
1122
1123 /* PSYCHO boot time probing and initialization. */
psycho_resource_adjust(struct pci_dev * pdev,struct resource * res,struct resource * root)1124 static void __init psycho_resource_adjust(struct pci_dev *pdev,
1125 struct resource *res,
1126 struct resource *root)
1127 {
1128 res->start += root->start;
1129 res->end += root->start;
1130 }
1131
psycho_base_address_update(struct pci_dev * pdev,int resource)1132 static void __init psycho_base_address_update(struct pci_dev *pdev, int resource)
1133 {
1134 struct pcidev_cookie *pcp = pdev->sysdata;
1135 struct pci_pbm_info *pbm = pcp->pbm;
1136 struct resource *res, *root;
1137 u32 reg;
1138 int where, size, is_64bit;
1139
1140 res = &pdev->resource[resource];
1141 if (resource < 6) {
1142 where = PCI_BASE_ADDRESS_0 + (resource * 4);
1143 } else if (resource == PCI_ROM_RESOURCE) {
1144 where = pdev->rom_base_reg;
1145 } else {
1146 /* Somebody might have asked allocation of a non-standard resource */
1147 return;
1148 }
1149
1150 is_64bit = 0;
1151 if (res->flags & IORESOURCE_IO)
1152 root = &pbm->io_space;
1153 else {
1154 root = &pbm->mem_space;
1155 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
1156 == PCI_BASE_ADDRESS_MEM_TYPE_64)
1157 is_64bit = 1;
1158 }
1159
1160 size = res->end - res->start;
1161 pci_read_config_dword(pdev, where, ®);
1162 reg = ((reg & size) |
1163 (((u32)(res->start - root->start)) & ~size));
1164 if (resource == PCI_ROM_RESOURCE) {
1165 reg |= PCI_ROM_ADDRESS_ENABLE;
1166 res->flags |= PCI_ROM_ADDRESS_ENABLE;
1167 }
1168 pci_write_config_dword(pdev, where, reg);
1169
1170 /* This knows that the upper 32-bits of the address
1171 * must be zero. Our PCI common layer enforces this.
1172 */
1173 if (is_64bit)
1174 pci_write_config_dword(pdev, where + 4, 0);
1175 }
1176
1177 /* We have to do the config space accesses by hand, thus... */
1178 #define PBM_BRIDGE_BUS 0x40
1179 #define PBM_BRIDGE_SUBORDINATE 0x41
pbm_renumber(struct pci_pbm_info * pbm,u8 orig_busno)1180 static void __init pbm_renumber(struct pci_pbm_info *pbm, u8 orig_busno)
1181 {
1182 u8 *addr, busno;
1183 int nbus;
1184
1185 busno = pci_highest_busnum;
1186 nbus = pbm->pci_last_busno - pbm->pci_first_busno;
1187
1188 addr = psycho_pci_config_mkaddr(pbm, orig_busno,
1189 0, PBM_BRIDGE_BUS);
1190 pci_config_write8(addr, busno);
1191 addr = psycho_pci_config_mkaddr(pbm, busno,
1192 0, PBM_BRIDGE_SUBORDINATE);
1193 pci_config_write8(addr, busno + nbus);
1194
1195 pbm->pci_first_busno = busno;
1196 pbm->pci_last_busno = busno + nbus;
1197 pci_highest_busnum = busno + nbus + 1;
1198
1199 do {
1200 pci_bus2pbm[busno++] = pbm;
1201 } while (nbus--);
1202 }
1203
1204 /* We have to do the config space accesses by hand here since
1205 * the pci_bus2pbm array is not ready yet.
1206 */
pbm_pci_bridge_renumber(struct pci_pbm_info * pbm,u8 busno)1207 static void __init pbm_pci_bridge_renumber(struct pci_pbm_info *pbm,
1208 u8 busno)
1209 {
1210 u32 devfn, l, class;
1211 u8 hdr_type;
1212 int is_multi = 0;
1213
1214 for(devfn = 0; devfn < 0xff; ++devfn) {
1215 u32 *dwaddr;
1216 u8 *baddr;
1217
1218 if (PCI_FUNC(devfn) != 0 && is_multi == 0)
1219 continue;
1220
1221 /* Anything there? */
1222 dwaddr = psycho_pci_config_mkaddr(pbm, busno, devfn, PCI_VENDOR_ID);
1223 l = 0xffffffff;
1224 pci_config_read32(dwaddr, &l);
1225 if (l == 0xffffffff || l == 0x00000000 ||
1226 l == 0x0000ffff || l == 0xffff0000) {
1227 is_multi = 0;
1228 continue;
1229 }
1230
1231 baddr = psycho_pci_config_mkaddr(pbm, busno, devfn, PCI_HEADER_TYPE);
1232 pci_config_read8(baddr, &hdr_type);
1233 if (PCI_FUNC(devfn) == 0)
1234 is_multi = hdr_type & 0x80;
1235
1236 dwaddr = psycho_pci_config_mkaddr(pbm, busno, devfn, PCI_CLASS_REVISION);
1237 class = 0xffffffff;
1238 pci_config_read32(dwaddr, &class);
1239 if ((class >> 16) == PCI_CLASS_BRIDGE_PCI) {
1240 u32 buses = 0xffffffff;
1241
1242 dwaddr = psycho_pci_config_mkaddr(pbm, busno, devfn,
1243 PCI_PRIMARY_BUS);
1244 pci_config_read32(dwaddr, &buses);
1245 pbm_pci_bridge_renumber(pbm, (buses >> 8) & 0xff);
1246 buses &= 0xff000000;
1247 pci_config_write32(dwaddr, buses);
1248 }
1249 }
1250 }
1251
pbm_bridge_reconfigure(struct pci_controller_info * p)1252 static void __init pbm_bridge_reconfigure(struct pci_controller_info *p)
1253 {
1254 struct pci_pbm_info *pbm;
1255 u8 *addr;
1256
1257 /* Clear out primary/secondary/subordinate bus numbers on
1258 * all PCI-to-PCI bridges under each PBM. The generic bus
1259 * probing will fix them up.
1260 */
1261 pbm_pci_bridge_renumber(&p->pbm_B, p->pbm_B.pci_first_busno);
1262 pbm_pci_bridge_renumber(&p->pbm_A, p->pbm_A.pci_first_busno);
1263
1264 /* Move PBM A out of the way. */
1265 pbm = &p->pbm_A;
1266 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1267 0, PBM_BRIDGE_BUS);
1268 pci_config_write8(addr, 0xff);
1269 addr = psycho_pci_config_mkaddr(pbm, 0xff,
1270 0, PBM_BRIDGE_SUBORDINATE);
1271 pci_config_write8(addr, 0xff);
1272
1273 /* Now we can safely renumber both PBMs. */
1274 pbm_renumber(&p->pbm_B, p->pbm_B.pci_first_busno);
1275 pbm_renumber(&p->pbm_A, 0xff);
1276 }
1277
pbm_config_busmastering(struct pci_pbm_info * pbm)1278 static void __init pbm_config_busmastering(struct pci_pbm_info *pbm)
1279 {
1280 u8 *addr;
1281
1282 /* Set cache-line size to 64 bytes, this is actually
1283 * a nop but I do it for completeness.
1284 */
1285 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1286 0, PCI_CACHE_LINE_SIZE);
1287 pci_config_write8(addr, 64 / sizeof(u32));
1288
1289 /* Set PBM latency timer to 64 PCI clocks. */
1290 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1291 0, PCI_LATENCY_TIMER);
1292 pci_config_write8(addr, 64);
1293 }
1294
pbm_scan_bus(struct pci_controller_info * p,struct pci_pbm_info * pbm)1295 static void __init pbm_scan_bus(struct pci_controller_info *p,
1296 struct pci_pbm_info *pbm)
1297 {
1298 struct pcidev_cookie *cookie = kmalloc(sizeof(*cookie), GFP_KERNEL);
1299
1300 if (!cookie) {
1301 prom_printf("PSYCHO: Critical allocation failure.\n");
1302 prom_halt();
1303 }
1304
1305 /* All we care about is the PBM. */
1306 memset(cookie, 0, sizeof(*cookie));
1307 cookie->pbm = pbm;
1308
1309 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
1310 p->pci_ops,
1311 pbm);
1312 pci_fixup_host_bridge_self(pbm->pci_bus);
1313 pbm->pci_bus->self->sysdata = cookie;
1314
1315 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
1316 pci_record_assignments(pbm, pbm->pci_bus);
1317 pci_assign_unassigned(pbm, pbm->pci_bus);
1318 pci_fixup_irq(pbm, pbm->pci_bus);
1319 pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
1320 pci_setup_busmastering(pbm, pbm->pci_bus);
1321 }
1322
psycho_scan_bus(struct pci_controller_info * p)1323 static void __init psycho_scan_bus(struct pci_controller_info *p)
1324 {
1325 pbm_bridge_reconfigure(p);
1326 pbm_config_busmastering(&p->pbm_B);
1327 p->pbm_B.is_66mhz_capable = 0;
1328 pbm_config_busmastering(&p->pbm_A);
1329 p->pbm_A.is_66mhz_capable = 1;
1330 pbm_scan_bus(p, &p->pbm_B);
1331 pbm_scan_bus(p, &p->pbm_A);
1332
1333 /* After the PCI bus scan is complete, we can register
1334 * the error interrupt handlers.
1335 */
1336 psycho_register_error_handlers(p);
1337 }
1338
psycho_iommu_init(struct pci_controller_info * p)1339 static void __init psycho_iommu_init(struct pci_controller_info *p)
1340 {
1341 struct pci_iommu *iommu = p->pbm_A.iommu;
1342 unsigned long tsbbase, i;
1343 u64 control;
1344
1345 /* Setup initial software IOMMU state. */
1346 spin_lock_init(&iommu->lock);
1347 iommu->iommu_cur_ctx = 0;
1348
1349 /* Register addresses. */
1350 iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;
1351 iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE;
1352 iommu->iommu_flush = p->pbm_A.controller_regs + PSYCHO_IOMMU_FLUSH;
1353 /* PSYCHO's IOMMU lacks ctx flushing. */
1354 iommu->iommu_ctxflush = 0;
1355
1356 /* We use the main control register of PSYCHO as the write
1357 * completion register.
1358 */
1359 iommu->write_complete_reg = p->pbm_A.controller_regs + PSYCHO_CONTROL;
1360
1361 /*
1362 * Invalidate TLB Entries.
1363 */
1364 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
1365 control |= PSYCHO_IOMMU_CTRL_DENAB;
1366 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
1367 for(i = 0; i < 16; i++) {
1368 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
1369 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
1370 }
1371
1372 /* Leave diag mode enabled for full-flushing done
1373 * in pci_iommu.c
1374 */
1375
1376 iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
1377 if (!iommu->dummy_page) {
1378 prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n");
1379 prom_halt();
1380 }
1381 memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
1382 iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
1383
1384 /* Using assumed page size 8K with 128K entries we need 1MB iommu page
1385 * table (128K ioptes * 8 bytes per iopte). This is
1386 * page order 7 on UltraSparc.
1387 */
1388 tsbbase = __get_free_pages(GFP_KERNEL, get_order(IO_TSB_SIZE));
1389 if (!tsbbase) {
1390 prom_printf("PSYCHO_IOMMU: Error, gfp(tsb) failed.\n");
1391 prom_halt();
1392 }
1393 iommu->page_table = (iopte_t *)tsbbase;
1394 iommu->page_table_sz_bits = 17;
1395 iommu->page_table_map_base = 0xc0000000;
1396 iommu->dma_addr_mask = 0xffffffff;
1397 pci_iommu_table_init(iommu, IO_TSB_SIZE);
1398
1399 /* We start with no consistent mappings. */
1400 iommu->lowest_consistent_map =
1401 1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
1402
1403 for (i = 0; i < PBM_NCLUSTERS; i++) {
1404 iommu->alloc_info[i].flush = 0;
1405 iommu->alloc_info[i].next = 0;
1406 }
1407
1408 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE, __pa(tsbbase));
1409
1410 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
1411 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
1412 control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
1413 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
1414
1415 /* If necessary, hook us up for starfire IRQ translations. */
1416 if(this_is_starfire)
1417 p->starfire_cookie = starfire_hookup(p->pbm_A.portid);
1418 else
1419 p->starfire_cookie = NULL;
1420 }
1421
1422 #define PSYCHO_IRQ_RETRY 0x1a00UL
1423 #define PSYCHO_PCIA_DIAG 0x2020UL
1424 #define PSYCHO_PCIB_DIAG 0x4020UL
1425 #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80 /* Reserved */
1426 #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040 /* Disable retry limit */
1427 #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020 /* Disable DMA wr / irq sync */
1428 #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010 /* Disable DMA wr / PIO rd sync */
1429 #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008 /* Invert DMA data parity */
1430 #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004 /* Invert PIO data parity */
1431 #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002 /* Invert PIO address parity */
1432 #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001 /* Enable loopback mode */
1433
psycho_controller_hwinit(struct pci_controller_info * p)1434 static void psycho_controller_hwinit(struct pci_controller_info *p)
1435 {
1436 u64 tmp;
1437
1438 /* PROM sets the IRQ retry value too low, increase it. */
1439 psycho_write(p->pbm_A.controller_regs + PSYCHO_IRQ_RETRY, 0xff);
1440
1441 /* Enable arbiter for all PCI slots. */
1442 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL);
1443 tmp |= PSYCHO_PCICTRL_AEN;
1444 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL, tmp);
1445
1446 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL);
1447 tmp |= PSYCHO_PCICTRL_AEN;
1448 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL, tmp);
1449
1450 /* Disable DMA write / PIO read synchronization on
1451 * both PCI bus segments.
1452 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
1453 */
1454 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG);
1455 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1456 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG, tmp);
1457
1458 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG);
1459 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1460 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG, tmp);
1461 }
1462
pbm_register_toplevel_resources(struct pci_controller_info * p,struct pci_pbm_info * pbm)1463 static void __init pbm_register_toplevel_resources(struct pci_controller_info *p,
1464 struct pci_pbm_info *pbm)
1465 {
1466 char *name = pbm->name;
1467
1468 sprintf(name, "PSYCHO%d PBM%c",
1469 p->index,
1470 (pbm == &p->pbm_A ? 'A' : 'B'));
1471 pbm->io_space.name = pbm->mem_space.name = name;
1472
1473 request_resource(&ioport_resource, &pbm->io_space);
1474 request_resource(&iomem_resource, &pbm->mem_space);
1475 pci_register_legacy_regions(&pbm->io_space,
1476 &pbm->mem_space);
1477 }
1478
psycho_pbm_strbuf_init(struct pci_controller_info * p,struct pci_pbm_info * pbm,int is_pbm_a)1479 static void psycho_pbm_strbuf_init(struct pci_controller_info *p,
1480 struct pci_pbm_info *pbm,
1481 int is_pbm_a)
1482 {
1483 unsigned long base = pbm->controller_regs;
1484 u64 control;
1485
1486 if (is_pbm_a) {
1487 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
1488 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
1489 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
1490 } else {
1491 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
1492 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
1493 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
1494 }
1495 /* PSYCHO's streaming buffer lacks ctx flushing. */
1496 pbm->stc.strbuf_ctxflush = 0;
1497 pbm->stc.strbuf_ctxmatch_base = 0;
1498
1499 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1500 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1501 + 63UL)
1502 & ~63UL);
1503 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1504 __pa(pbm->stc.strbuf_flushflag);
1505
1506 /* Enable the streaming buffer. We have to be careful
1507 * just in case OBP left it with LRU locking enabled.
1508 *
1509 * It is possible to control if PBM will be rerun on
1510 * line misses. Currently I just retain whatever setting
1511 * OBP left us with. All checks so far show it having
1512 * a value of zero.
1513 */
1514 #undef PSYCHO_STRBUF_RERUN_ENABLE
1515 #undef PSYCHO_STRBUF_RERUN_DISABLE
1516 control = psycho_read(pbm->stc.strbuf_control);
1517 control |= PSYCHO_STRBUF_CTRL_ENAB;
1518 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
1519 #ifdef PSYCHO_STRBUF_RERUN_ENABLE
1520 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
1521 #else
1522 #ifdef PSYCHO_STRBUF_RERUN_DISABLE
1523 control |= PSYCHO_STRBUF_CTRL_RRDIS;
1524 #endif
1525 #endif
1526 psycho_write(pbm->stc.strbuf_control, control);
1527
1528 pbm->stc.strbuf_enabled = 1;
1529 }
1530
1531 #define PSYCHO_IOSPACE_A 0x002000000UL
1532 #define PSYCHO_IOSPACE_B 0x002010000UL
1533 #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
1534 #define PSYCHO_MEMSPACE_A 0x100000000UL
1535 #define PSYCHO_MEMSPACE_B 0x180000000UL
1536 #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
1537
psycho_pbm_init(struct pci_controller_info * p,int prom_node,int is_pbm_a)1538 static void psycho_pbm_init(struct pci_controller_info *p,
1539 int prom_node, int is_pbm_a)
1540 {
1541 unsigned int busrange[2];
1542 struct pci_pbm_info *pbm;
1543 int err;
1544
1545 if (is_pbm_a) {
1546 pbm = &p->pbm_A;
1547 pbm->pci_first_slot = 1;
1548 pbm->io_space.start = pbm->controller_regs + PSYCHO_IOSPACE_A;
1549 pbm->mem_space.start = pbm->controller_regs + PSYCHO_MEMSPACE_A;
1550 } else {
1551 pbm = &p->pbm_B;
1552 pbm->pci_first_slot = 2;
1553 pbm->io_space.start = pbm->controller_regs + PSYCHO_IOSPACE_B;
1554 pbm->mem_space.start = pbm->controller_regs + PSYCHO_MEMSPACE_B;
1555 }
1556
1557 pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
1558 pbm->chip_version =
1559 prom_getintdefault(prom_node, "version#", 0);
1560 pbm->chip_revision =
1561 prom_getintdefault(prom_node, "module-revision#", 0);
1562
1563 pbm->io_space.end = pbm->io_space.start + PSYCHO_IOSPACE_SIZE;
1564 pbm->io_space.flags = IORESOURCE_IO;
1565 pbm->mem_space.end = pbm->mem_space.start + PSYCHO_MEMSPACE_SIZE;
1566 pbm->mem_space.flags = IORESOURCE_MEM;
1567 pbm_register_toplevel_resources(p, pbm);
1568
1569 pbm->parent = p;
1570 pbm->prom_node = prom_node;
1571 prom_getstring(prom_node, "name",
1572 pbm->prom_name,
1573 sizeof(pbm->prom_name));
1574
1575 err = prom_getproperty(prom_node, "ranges",
1576 (char *)pbm->pbm_ranges,
1577 sizeof(pbm->pbm_ranges));
1578 if (err != -1)
1579 pbm->num_pbm_ranges =
1580 (err / sizeof(struct linux_prom_pci_ranges));
1581 else
1582 pbm->num_pbm_ranges = 0;
1583
1584 err = prom_getproperty(prom_node, "interrupt-map",
1585 (char *)pbm->pbm_intmap,
1586 sizeof(pbm->pbm_intmap));
1587 if (err != -1) {
1588 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
1589 err = prom_getproperty(prom_node, "interrupt-map-mask",
1590 (char *)&pbm->pbm_intmask,
1591 sizeof(pbm->pbm_intmask));
1592 if (err == -1) {
1593 prom_printf("PSYCHO-PBM: Fatal error, no "
1594 "interrupt-map-mask.\n");
1595 prom_halt();
1596 }
1597 } else {
1598 pbm->num_pbm_intmap = 0;
1599 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
1600 }
1601
1602 err = prom_getproperty(prom_node, "bus-range",
1603 (char *)&busrange[0],
1604 sizeof(busrange));
1605 if (err == 0 || err == -1) {
1606 prom_printf("PSYCHO-PBM: Fatal error, no bus-range.\n");
1607 prom_halt();
1608 }
1609 pbm->pci_first_busno = busrange[0];
1610 pbm->pci_last_busno = busrange[1];
1611
1612 psycho_pbm_strbuf_init(p, pbm, is_pbm_a);
1613 }
1614
1615 #define PSYCHO_CONFIGSPACE 0x001000000UL
1616
psycho_init(int node,char * model_name)1617 void __init psycho_init(int node, char *model_name)
1618 {
1619 struct linux_prom64_registers pr_regs[3];
1620 struct pci_controller_info *p;
1621 struct pci_iommu *iommu;
1622 unsigned long flags;
1623 u32 upa_portid;
1624 int is_pbm_a, err;
1625
1626 upa_portid = prom_getintdefault(node, "upa-portid", 0xff);
1627
1628 spin_lock_irqsave(&pci_controller_lock, flags);
1629 for(p = pci_controller_root; p; p = p->next) {
1630 if (p->pbm_A.portid == upa_portid) {
1631 spin_unlock_irqrestore(&pci_controller_lock, flags);
1632 is_pbm_a = (p->pbm_A.prom_node == 0);
1633 psycho_pbm_init(p, node, is_pbm_a);
1634 return;
1635 }
1636 }
1637 spin_unlock_irqrestore(&pci_controller_lock, flags);
1638
1639 p = kmalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1640 if (!p) {
1641 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1642 prom_halt();
1643 }
1644 memset(p, 0, sizeof(*p));
1645 iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
1646 if (!iommu) {
1647 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1648 prom_halt();
1649 }
1650 memset(iommu, 0, sizeof(*iommu));
1651 p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1652
1653 spin_lock_irqsave(&pci_controller_lock, flags);
1654 p->next = pci_controller_root;
1655 pci_controller_root = p;
1656 spin_unlock_irqrestore(&pci_controller_lock, flags);
1657
1658 p->pbm_A.portid = upa_portid;
1659 p->pbm_B.portid = upa_portid;
1660 p->index = pci_num_controllers++;
1661 p->pbms_same_domain = 0;
1662 p->scan_bus = psycho_scan_bus;
1663 p->irq_build = psycho_irq_build;
1664 p->base_address_update = psycho_base_address_update;
1665 p->resource_adjust = psycho_resource_adjust;
1666 p->pci_ops = &psycho_ops;
1667
1668 err = prom_getproperty(node, "reg",
1669 (char *)&pr_regs[0],
1670 sizeof(pr_regs));
1671 if (err == 0 || err == -1) {
1672 prom_printf("PSYCHO: Fatal error, no reg property.\n");
1673 prom_halt();
1674 }
1675
1676 p->pbm_A.controller_regs = pr_regs[2].phys_addr;
1677 p->pbm_B.controller_regs = pr_regs[2].phys_addr;
1678 printk("PCI: Found PSYCHO, control regs at %016lx\n",
1679 p->pbm_A.controller_regs);
1680
1681 p->pbm_A.config_space = p->pbm_B.config_space =
1682 (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1683 printk("PSYCHO: Shared PCI config space at %016lx\n",
1684 p->pbm_A.config_space);
1685
1686 /*
1687 * Psycho's PCI MEM space is mapped to a 2GB aligned area, so
1688 * we need to adjust our MEM space mask.
1689 */
1690 pci_memspace_mask = 0x7fffffffUL;
1691
1692 psycho_controller_hwinit(p);
1693
1694 psycho_iommu_init(p);
1695
1696 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
1697 psycho_pbm_init(p, node, is_pbm_a);
1698 }
1699