1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25
26 #include <linux/firmware.h>
27 #include <drm/drm_drv.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_psp.h"
31 #include "amdgpu_ucode.h"
32 #include "amdgpu_xgmi.h"
33 #include "soc15_common.h"
34 #include "psp_v3_1.h"
35 #include "psp_v10_0.h"
36 #include "psp_v11_0.h"
37 #include "psp_v11_0_8.h"
38 #include "psp_v12_0.h"
39 #include "psp_v13_0.h"
40 #include "psp_v13_0_4.h"
41
42 #include "amdgpu_ras.h"
43 #include "amdgpu_securedisplay.h"
44 #include "amdgpu_atomfirmware.h"
45
46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3)
47
48 static int psp_sysfs_init(struct amdgpu_device *adev);
49 static void psp_sysfs_fini(struct amdgpu_device *adev);
50
51 static int psp_load_smu_fw(struct psp_context *psp);
52 static int psp_rap_terminate(struct psp_context *psp);
53 static int psp_securedisplay_terminate(struct psp_context *psp);
54
55 /*
56 * Due to DF Cstate management centralized to PMFW, the firmware
57 * loading sequence will be updated as below:
58 * - Load KDB
59 * - Load SYS_DRV
60 * - Load tOS
61 * - Load PMFW
62 * - Setup TMR
63 * - Load other non-psp fw
64 * - Load ASD
65 * - Load XGMI/RAS/HDCP/DTM TA if any
66 *
67 * This new sequence is required for
68 * - Arcturus and onwards
69 */
psp_check_pmfw_centralized_cstate_management(struct psp_context * psp)70 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
71 {
72 struct amdgpu_device *adev = psp->adev;
73
74 if (amdgpu_sriov_vf(adev)) {
75 psp->pmfw_centralized_cstate_management = false;
76 return;
77 }
78
79 switch (adev->ip_versions[MP0_HWIP][0]) {
80 case IP_VERSION(11, 0, 0):
81 case IP_VERSION(11, 0, 4):
82 case IP_VERSION(11, 0, 5):
83 case IP_VERSION(11, 0, 7):
84 case IP_VERSION(11, 0, 9):
85 case IP_VERSION(11, 0, 11):
86 case IP_VERSION(11, 0, 12):
87 case IP_VERSION(11, 0, 13):
88 case IP_VERSION(13, 0, 0):
89 case IP_VERSION(13, 0, 2):
90 case IP_VERSION(13, 0, 7):
91 psp->pmfw_centralized_cstate_management = true;
92 break;
93 default:
94 psp->pmfw_centralized_cstate_management = false;
95 break;
96 }
97 }
98
psp_early_init(void * handle)99 static int psp_early_init(void *handle)
100 {
101 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
102 struct psp_context *psp = &adev->psp;
103
104 switch (adev->ip_versions[MP0_HWIP][0]) {
105 case IP_VERSION(9, 0, 0):
106 psp_v3_1_set_psp_funcs(psp);
107 psp->autoload_supported = false;
108 break;
109 case IP_VERSION(10, 0, 0):
110 case IP_VERSION(10, 0, 1):
111 psp_v10_0_set_psp_funcs(psp);
112 psp->autoload_supported = false;
113 break;
114 case IP_VERSION(11, 0, 2):
115 case IP_VERSION(11, 0, 4):
116 psp_v11_0_set_psp_funcs(psp);
117 psp->autoload_supported = false;
118 break;
119 case IP_VERSION(11, 0, 0):
120 case IP_VERSION(11, 0, 5):
121 case IP_VERSION(11, 0, 9):
122 case IP_VERSION(11, 0, 7):
123 case IP_VERSION(11, 0, 11):
124 case IP_VERSION(11, 5, 0):
125 case IP_VERSION(11, 0, 12):
126 case IP_VERSION(11, 0, 13):
127 psp_v11_0_set_psp_funcs(psp);
128 psp->autoload_supported = true;
129 break;
130 case IP_VERSION(11, 0, 3):
131 case IP_VERSION(12, 0, 1):
132 psp_v12_0_set_psp_funcs(psp);
133 break;
134 case IP_VERSION(13, 0, 2):
135 psp_v13_0_set_psp_funcs(psp);
136 break;
137 case IP_VERSION(13, 0, 1):
138 case IP_VERSION(13, 0, 3):
139 case IP_VERSION(13, 0, 5):
140 case IP_VERSION(13, 0, 8):
141 case IP_VERSION(13, 0, 10):
142 case IP_VERSION(13, 0, 11):
143 psp_v13_0_set_psp_funcs(psp);
144 psp->autoload_supported = true;
145 break;
146 case IP_VERSION(11, 0, 8):
147 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
148 psp_v11_0_8_set_psp_funcs(psp);
149 psp->autoload_supported = false;
150 }
151 break;
152 case IP_VERSION(13, 0, 0):
153 case IP_VERSION(13, 0, 7):
154 psp_v13_0_set_psp_funcs(psp);
155 psp->autoload_supported = true;
156 break;
157 case IP_VERSION(13, 0, 4):
158 psp_v13_0_4_set_psp_funcs(psp);
159 psp->autoload_supported = true;
160 break;
161 default:
162 return -EINVAL;
163 }
164
165 psp->adev = adev;
166
167 psp_check_pmfw_centralized_cstate_management(psp);
168
169 return 0;
170 }
171
psp_ta_free_shared_buf(struct ta_mem_context * mem_ctx)172 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
173 {
174 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
175 &mem_ctx->shared_buf);
176 mem_ctx->shared_bo = NULL;
177 }
178
psp_free_shared_bufs(struct psp_context * psp)179 static void psp_free_shared_bufs(struct psp_context *psp)
180 {
181 void *tmr_buf;
182 void **pptr;
183
184 /* free TMR memory buffer */
185 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
186 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
187 psp->tmr_bo = NULL;
188
189 /* free xgmi shared memory */
190 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
191
192 /* free ras shared memory */
193 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
194
195 /* free hdcp shared memory */
196 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
197
198 /* free dtm shared memory */
199 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
200
201 /* free rap shared memory */
202 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
203
204 /* free securedisplay shared memory */
205 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
206
207
208 }
209
psp_memory_training_fini(struct psp_context * psp)210 static void psp_memory_training_fini(struct psp_context *psp)
211 {
212 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
213
214 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
215 kfree(ctx->sys_cache);
216 ctx->sys_cache = NULL;
217 }
218
psp_memory_training_init(struct psp_context * psp)219 static int psp_memory_training_init(struct psp_context *psp)
220 {
221 int ret;
222 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
223
224 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
225 DRM_DEBUG("memory training is not supported!\n");
226 return 0;
227 }
228
229 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
230 if (ctx->sys_cache == NULL) {
231 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
232 ret = -ENOMEM;
233 goto Err_out;
234 }
235
236 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
237 ctx->train_data_size,
238 ctx->p2c_train_data_offset,
239 ctx->c2p_train_data_offset);
240 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
241 return 0;
242
243 Err_out:
244 psp_memory_training_fini(psp);
245 return ret;
246 }
247
248 /*
249 * Helper funciton to query psp runtime database entry
250 *
251 * @adev: amdgpu_device pointer
252 * @entry_type: the type of psp runtime database entry
253 * @db_entry: runtime database entry pointer
254 *
255 * Return false if runtime database doesn't exit or entry is invalid
256 * or true if the specific database entry is found, and copy to @db_entry
257 */
psp_get_runtime_db_entry(struct amdgpu_device * adev,enum psp_runtime_entry_type entry_type,void * db_entry)258 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
259 enum psp_runtime_entry_type entry_type,
260 void *db_entry)
261 {
262 uint64_t db_header_pos, db_dir_pos;
263 struct psp_runtime_data_header db_header = {0};
264 struct psp_runtime_data_directory db_dir = {0};
265 bool ret = false;
266 int i;
267
268 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
269 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
270
271 /* read runtime db header from vram */
272 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
273 sizeof(struct psp_runtime_data_header), false);
274
275 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
276 /* runtime db doesn't exist, exit */
277 dev_warn(adev->dev, "PSP runtime database doesn't exist\n");
278 return false;
279 }
280
281 /* read runtime database entry from vram */
282 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
283 sizeof(struct psp_runtime_data_directory), false);
284
285 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
286 /* invalid db entry count, exit */
287 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
288 return false;
289 }
290
291 /* look up for requested entry type */
292 for (i = 0; i < db_dir.entry_count && !ret; i++) {
293 if (db_dir.entry_list[i].entry_type == entry_type) {
294 switch (entry_type) {
295 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
296 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
297 /* invalid db entry size */
298 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
299 return false;
300 }
301 /* read runtime database entry */
302 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
303 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
304 ret = true;
305 break;
306 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
307 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
308 /* invalid db entry size */
309 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
310 return false;
311 }
312 /* read runtime database entry */
313 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
314 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
315 ret = true;
316 break;
317 default:
318 ret = false;
319 break;
320 }
321 }
322 }
323
324 return ret;
325 }
326
psp_init_sriov_microcode(struct psp_context * psp)327 static int psp_init_sriov_microcode(struct psp_context *psp)
328 {
329 struct amdgpu_device *adev = psp->adev;
330 int ret = 0;
331
332 switch (adev->ip_versions[MP0_HWIP][0]) {
333 case IP_VERSION(9, 0, 0):
334 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
335 ret = psp_init_cap_microcode(psp, "vega10");
336 break;
337 case IP_VERSION(11, 0, 9):
338 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
339 ret = psp_init_cap_microcode(psp, "navi12");
340 break;
341 case IP_VERSION(11, 0, 7):
342 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
343 ret = psp_init_cap_microcode(psp, "sienna_cichlid");
344 break;
345 case IP_VERSION(13, 0, 2):
346 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
347 ret = psp_init_cap_microcode(psp, "aldebaran");
348 ret &= psp_init_ta_microcode(psp, "aldebaran");
349 break;
350 case IP_VERSION(13, 0, 0):
351 adev->virt.autoload_ucode_id = 0;
352 break;
353 case IP_VERSION(13, 0, 10):
354 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
355 break;
356 default:
357 BUG();
358 break;
359 }
360 return ret;
361 }
362
psp_sw_init(void * handle)363 static int psp_sw_init(void *handle)
364 {
365 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
366 struct psp_context *psp = &adev->psp;
367 int ret;
368 struct psp_runtime_boot_cfg_entry boot_cfg_entry;
369 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
370 struct psp_runtime_scpm_entry scpm_entry;
371
372 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
373 if (!psp->cmd) {
374 DRM_ERROR("Failed to allocate memory to command buffer!\n");
375 ret = -ENOMEM;
376 }
377
378 if (amdgpu_sriov_vf(adev))
379 ret = psp_init_sriov_microcode(psp);
380 else
381 ret = psp_init_microcode(psp);
382 if (ret) {
383 DRM_ERROR("Failed to load psp firmware!\n");
384 return ret;
385 }
386
387 adev->psp.xgmi_context.supports_extended_data =
388 !adev->gmc.xgmi.connected_to_cpu &&
389 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
390
391 memset(&scpm_entry, 0, sizeof(scpm_entry));
392 if ((psp_get_runtime_db_entry(adev,
393 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
394 &scpm_entry)) &&
395 (SCPM_DISABLE != scpm_entry.scpm_status)) {
396 adev->scpm_enabled = true;
397 adev->scpm_status = scpm_entry.scpm_status;
398 } else {
399 adev->scpm_enabled = false;
400 adev->scpm_status = SCPM_DISABLE;
401 }
402
403 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
404
405 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
406 if (psp_get_runtime_db_entry(adev,
407 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
408 &boot_cfg_entry)) {
409 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
410 if ((psp->boot_cfg_bitmask) &
411 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
412 /* If psp runtime database exists, then
413 * only enable two stage memory training
414 * when TWO_STAGE_DRAM_TRAINING bit is set
415 * in runtime database */
416 mem_training_ctx->enable_mem_training = true;
417 }
418
419 } else {
420 /* If psp runtime database doesn't exist or
421 * is invalid, force enable two stage memory
422 * training */
423 mem_training_ctx->enable_mem_training = true;
424 }
425
426 if (mem_training_ctx->enable_mem_training) {
427 ret = psp_memory_training_init(psp);
428 if (ret) {
429 DRM_ERROR("Failed to initialize memory training!\n");
430 return ret;
431 }
432
433 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
434 if (ret) {
435 DRM_ERROR("Failed to process memory training!\n");
436 return ret;
437 }
438 }
439
440 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
441 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
442 ret= psp_sysfs_init(adev);
443 if (ret) {
444 return ret;
445 }
446 }
447
448 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
449 amdgpu_sriov_vf(adev) ?
450 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
451 &psp->fw_pri_bo,
452 &psp->fw_pri_mc_addr,
453 &psp->fw_pri_buf);
454 if (ret)
455 return ret;
456
457 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
458 AMDGPU_GEM_DOMAIN_VRAM,
459 &psp->fence_buf_bo,
460 &psp->fence_buf_mc_addr,
461 &psp->fence_buf);
462 if (ret)
463 goto failed1;
464
465 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
466 AMDGPU_GEM_DOMAIN_VRAM,
467 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
468 (void **)&psp->cmd_buf_mem);
469 if (ret)
470 goto failed2;
471
472 return 0;
473
474 failed2:
475 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
476 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
477 failed1:
478 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
479 &psp->fence_buf_mc_addr, &psp->fence_buf);
480 return ret;
481 }
482
psp_sw_fini(void * handle)483 static int psp_sw_fini(void *handle)
484 {
485 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
486 struct psp_context *psp = &adev->psp;
487 struct psp_gfx_cmd_resp *cmd = psp->cmd;
488
489 psp_memory_training_fini(psp);
490 if (psp->sos_fw) {
491 release_firmware(psp->sos_fw);
492 psp->sos_fw = NULL;
493 }
494 if (psp->asd_fw) {
495 release_firmware(psp->asd_fw);
496 psp->asd_fw = NULL;
497 }
498 if (psp->ta_fw) {
499 release_firmware(psp->ta_fw);
500 psp->ta_fw = NULL;
501 }
502 if (psp->cap_fw) {
503 release_firmware(psp->cap_fw);
504 psp->cap_fw = NULL;
505 }
506 if (psp->toc_fw) {
507 release_firmware(psp->toc_fw);
508 psp->toc_fw = NULL;
509 }
510 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
511 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
512 psp_sysfs_fini(adev);
513
514 kfree(cmd);
515 cmd = NULL;
516
517 if (psp->km_ring.ring_mem)
518 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
519 &psp->km_ring.ring_mem_mc_addr,
520 (void **)&psp->km_ring.ring_mem);
521
522 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
523 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
524 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
525 &psp->fence_buf_mc_addr, &psp->fence_buf);
526 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
527 (void **)&psp->cmd_buf_mem);
528
529 return 0;
530 }
531
psp_wait_for(struct psp_context * psp,uint32_t reg_index,uint32_t reg_val,uint32_t mask,bool check_changed)532 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
533 uint32_t reg_val, uint32_t mask, bool check_changed)
534 {
535 uint32_t val;
536 int i;
537 struct amdgpu_device *adev = psp->adev;
538
539 if (psp->adev->no_hw_access)
540 return 0;
541
542 for (i = 0; i < adev->usec_timeout; i++) {
543 val = RREG32(reg_index);
544 if (check_changed) {
545 if (val != reg_val)
546 return 0;
547 } else {
548 if ((val & mask) == reg_val)
549 return 0;
550 }
551 udelay(1);
552 }
553
554 return -ETIME;
555 }
556
psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)557 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
558 {
559 switch (cmd_id) {
560 case GFX_CMD_ID_LOAD_TA:
561 return "LOAD_TA";
562 case GFX_CMD_ID_UNLOAD_TA:
563 return "UNLOAD_TA";
564 case GFX_CMD_ID_INVOKE_CMD:
565 return "INVOKE_CMD";
566 case GFX_CMD_ID_LOAD_ASD:
567 return "LOAD_ASD";
568 case GFX_CMD_ID_SETUP_TMR:
569 return "SETUP_TMR";
570 case GFX_CMD_ID_LOAD_IP_FW:
571 return "LOAD_IP_FW";
572 case GFX_CMD_ID_DESTROY_TMR:
573 return "DESTROY_TMR";
574 case GFX_CMD_ID_SAVE_RESTORE:
575 return "SAVE_RESTORE_IP_FW";
576 case GFX_CMD_ID_SETUP_VMR:
577 return "SETUP_VMR";
578 case GFX_CMD_ID_DESTROY_VMR:
579 return "DESTROY_VMR";
580 case GFX_CMD_ID_PROG_REG:
581 return "PROG_REG";
582 case GFX_CMD_ID_GET_FW_ATTESTATION:
583 return "GET_FW_ATTESTATION";
584 case GFX_CMD_ID_LOAD_TOC:
585 return "ID_LOAD_TOC";
586 case GFX_CMD_ID_AUTOLOAD_RLC:
587 return "AUTOLOAD_RLC";
588 case GFX_CMD_ID_BOOT_CFG:
589 return "BOOT_CFG";
590 default:
591 return "UNKNOWN CMD";
592 }
593 }
594
595 static int
psp_cmd_submit_buf(struct psp_context * psp,struct amdgpu_firmware_info * ucode,struct psp_gfx_cmd_resp * cmd,uint64_t fence_mc_addr)596 psp_cmd_submit_buf(struct psp_context *psp,
597 struct amdgpu_firmware_info *ucode,
598 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
599 {
600 int ret;
601 int index, idx;
602 int timeout = 20000;
603 bool ras_intr = false;
604 bool skip_unsupport = false;
605
606 if (psp->adev->no_hw_access)
607 return 0;
608
609 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
610 return 0;
611
612 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
613
614 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
615
616 index = atomic_inc_return(&psp->fence_value);
617 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
618 if (ret) {
619 atomic_dec(&psp->fence_value);
620 goto exit;
621 }
622
623 amdgpu_device_invalidate_hdp(psp->adev, NULL);
624 while (*((unsigned int *)psp->fence_buf) != index) {
625 if (--timeout == 0)
626 break;
627 /*
628 * Shouldn't wait for timeout when err_event_athub occurs,
629 * because gpu reset thread triggered and lock resource should
630 * be released for psp resume sequence.
631 */
632 ras_intr = amdgpu_ras_intr_triggered();
633 if (ras_intr)
634 break;
635 usleep_range(10, 100);
636 amdgpu_device_invalidate_hdp(psp->adev, NULL);
637 }
638
639 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
640 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
641 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
642
643 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
644
645 /* In some cases, psp response status is not 0 even there is no
646 * problem while the command is submitted. Some version of PSP FW
647 * doesn't write 0 to that field.
648 * So here we would like to only print a warning instead of an error
649 * during psp initialization to avoid breaking hw_init and it doesn't
650 * return -EINVAL.
651 */
652 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
653 if (ucode)
654 DRM_WARN("failed to load ucode %s(0x%X) ",
655 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
656 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
657 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
658 psp->cmd_buf_mem->resp.status);
659 /* If any firmware (including CAP) load fails under SRIOV, it should
660 * return failure to stop the VF from initializing.
661 * Also return failure in case of timeout
662 */
663 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
664 ret = -EINVAL;
665 goto exit;
666 }
667 }
668
669 if (ucode) {
670 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
671 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
672 }
673
674 exit:
675 drm_dev_exit(idx);
676 return ret;
677 }
678
acquire_psp_cmd_buf(struct psp_context * psp)679 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
680 {
681 struct psp_gfx_cmd_resp *cmd = psp->cmd;
682
683 mutex_lock(&psp->mutex);
684
685 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
686
687 return cmd;
688 }
689
release_psp_cmd_buf(struct psp_context * psp)690 static void release_psp_cmd_buf(struct psp_context *psp)
691 {
692 mutex_unlock(&psp->mutex);
693 }
694
psp_prep_tmr_cmd_buf(struct psp_context * psp,struct psp_gfx_cmd_resp * cmd,uint64_t tmr_mc,struct amdgpu_bo * tmr_bo)695 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
696 struct psp_gfx_cmd_resp *cmd,
697 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
698 {
699 struct amdgpu_device *adev = psp->adev;
700 uint32_t size = amdgpu_bo_size(tmr_bo);
701 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
702
703 if (amdgpu_sriov_vf(psp->adev))
704 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
705 else
706 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
707 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
708 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
709 cmd->cmd.cmd_setup_tmr.buf_size = size;
710 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
711 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
712 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
713 }
714
psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint64_t pri_buf_mc,uint32_t size)715 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
716 uint64_t pri_buf_mc, uint32_t size)
717 {
718 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
719 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
720 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
721 cmd->cmd.cmd_load_toc.toc_size = size;
722 }
723
724 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
psp_load_toc(struct psp_context * psp,uint32_t * tmr_size)725 static int psp_load_toc(struct psp_context *psp,
726 uint32_t *tmr_size)
727 {
728 int ret;
729 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
730
731 /* Copy toc to psp firmware private buffer */
732 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
733
734 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
735
736 ret = psp_cmd_submit_buf(psp, NULL, cmd,
737 psp->fence_buf_mc_addr);
738 if (!ret)
739 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
740
741 release_psp_cmd_buf(psp);
742
743 return ret;
744 }
745
746 /* Set up Trusted Memory Region */
psp_tmr_init(struct psp_context * psp)747 static int psp_tmr_init(struct psp_context *psp)
748 {
749 int ret = 0;
750 int tmr_size;
751 void *tmr_buf;
752 void **pptr;
753
754 /*
755 * According to HW engineer, they prefer the TMR address be "naturally
756 * aligned" , e.g. the start address be an integer divide of TMR size.
757 *
758 * Note: this memory need be reserved till the driver
759 * uninitializes.
760 */
761 tmr_size = PSP_TMR_SIZE(psp->adev);
762
763 /* For ASICs support RLC autoload, psp will parse the toc
764 * and calculate the total size of TMR needed */
765 if (!amdgpu_sriov_vf(psp->adev) &&
766 psp->toc.start_addr &&
767 psp->toc.size_bytes &&
768 psp->fw_pri_buf) {
769 ret = psp_load_toc(psp, &tmr_size);
770 if (ret) {
771 DRM_ERROR("Failed to load toc\n");
772 return ret;
773 }
774 }
775
776 if (!psp->tmr_bo) {
777 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
778 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT,
779 AMDGPU_GEM_DOMAIN_VRAM,
780 &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
781 }
782
783 return ret;
784 }
785
psp_skip_tmr(struct psp_context * psp)786 static bool psp_skip_tmr(struct psp_context *psp)
787 {
788 switch (psp->adev->ip_versions[MP0_HWIP][0]) {
789 case IP_VERSION(11, 0, 9):
790 case IP_VERSION(11, 0, 7):
791 case IP_VERSION(13, 0, 2):
792 case IP_VERSION(13, 0, 10):
793 return true;
794 default:
795 return false;
796 }
797 }
798
psp_tmr_load(struct psp_context * psp)799 static int psp_tmr_load(struct psp_context *psp)
800 {
801 int ret;
802 struct psp_gfx_cmd_resp *cmd;
803
804 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
805 * Already set up by host driver.
806 */
807 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
808 return 0;
809
810 cmd = acquire_psp_cmd_buf(psp);
811
812 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
813 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
814 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
815
816 ret = psp_cmd_submit_buf(psp, NULL, cmd,
817 psp->fence_buf_mc_addr);
818
819 release_psp_cmd_buf(psp);
820
821 return ret;
822 }
823
psp_prep_tmr_unload_cmd_buf(struct psp_context * psp,struct psp_gfx_cmd_resp * cmd)824 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
825 struct psp_gfx_cmd_resp *cmd)
826 {
827 if (amdgpu_sriov_vf(psp->adev))
828 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
829 else
830 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
831 }
832
psp_tmr_unload(struct psp_context * psp)833 static int psp_tmr_unload(struct psp_context *psp)
834 {
835 int ret;
836 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
837
838 psp_prep_tmr_unload_cmd_buf(psp, cmd);
839 dev_info(psp->adev->dev, "free PSP TMR buffer\n");
840
841 ret = psp_cmd_submit_buf(psp, NULL, cmd,
842 psp->fence_buf_mc_addr);
843
844 release_psp_cmd_buf(psp);
845
846 return ret;
847 }
848
psp_tmr_terminate(struct psp_context * psp)849 static int psp_tmr_terminate(struct psp_context *psp)
850 {
851 return psp_tmr_unload(psp);
852 }
853
psp_get_fw_attestation_records_addr(struct psp_context * psp,uint64_t * output_ptr)854 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
855 uint64_t *output_ptr)
856 {
857 int ret;
858 struct psp_gfx_cmd_resp *cmd;
859
860 if (!output_ptr)
861 return -EINVAL;
862
863 if (amdgpu_sriov_vf(psp->adev))
864 return 0;
865
866 cmd = acquire_psp_cmd_buf(psp);
867
868 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
869
870 ret = psp_cmd_submit_buf(psp, NULL, cmd,
871 psp->fence_buf_mc_addr);
872
873 if (!ret) {
874 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
875 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
876 }
877
878 release_psp_cmd_buf(psp);
879
880 return ret;
881 }
882
psp_boot_config_get(struct amdgpu_device * adev,uint32_t * boot_cfg)883 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
884 {
885 struct psp_context *psp = &adev->psp;
886 struct psp_gfx_cmd_resp *cmd;
887 int ret;
888
889 if (amdgpu_sriov_vf(adev))
890 return 0;
891
892 cmd = acquire_psp_cmd_buf(psp);
893
894 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
895 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
896
897 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
898 if (!ret) {
899 *boot_cfg =
900 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
901 }
902
903 release_psp_cmd_buf(psp);
904
905 return ret;
906 }
907
psp_boot_config_set(struct amdgpu_device * adev,uint32_t boot_cfg)908 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
909 {
910 int ret;
911 struct psp_context *psp = &adev->psp;
912 struct psp_gfx_cmd_resp *cmd;
913
914 if (amdgpu_sriov_vf(adev))
915 return 0;
916
917 cmd = acquire_psp_cmd_buf(psp);
918
919 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
920 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
921 cmd->cmd.boot_cfg.boot_config = boot_cfg;
922 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
923
924 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
925
926 release_psp_cmd_buf(psp);
927
928 return ret;
929 }
930
psp_rl_load(struct amdgpu_device * adev)931 static int psp_rl_load(struct amdgpu_device *adev)
932 {
933 int ret;
934 struct psp_context *psp = &adev->psp;
935 struct psp_gfx_cmd_resp *cmd;
936
937 if (!is_psp_fw_valid(psp->rl))
938 return 0;
939
940 cmd = acquire_psp_cmd_buf(psp);
941
942 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
943 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
944
945 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
946 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
947 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
948 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
949 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
950
951 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
952
953 release_psp_cmd_buf(psp);
954
955 return ret;
956 }
957
psp_asd_initialize(struct psp_context * psp)958 static int psp_asd_initialize(struct psp_context *psp)
959 {
960 int ret;
961
962 /* If PSP version doesn't match ASD version, asd loading will be failed.
963 * add workaround to bypass it for sriov now.
964 * TODO: add version check to make it common
965 */
966 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
967 return 0;
968
969 psp->asd_context.mem_context.shared_mc_addr = 0;
970 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
971 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD;
972
973 ret = psp_ta_load(psp, &psp->asd_context);
974 if (!ret)
975 psp->asd_context.initialized = true;
976
977 return ret;
978 }
979
psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint32_t session_id)980 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
981 uint32_t session_id)
982 {
983 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
984 cmd->cmd.cmd_unload_ta.session_id = session_id;
985 }
986
psp_ta_unload(struct psp_context * psp,struct ta_context * context)987 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
988 {
989 int ret;
990 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
991
992 psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
993
994 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
995
996 release_psp_cmd_buf(psp);
997
998 return ret;
999 }
1000
psp_asd_terminate(struct psp_context * psp)1001 static int psp_asd_terminate(struct psp_context *psp)
1002 {
1003 int ret;
1004
1005 if (amdgpu_sriov_vf(psp->adev))
1006 return 0;
1007
1008 if (!psp->asd_context.initialized)
1009 return 0;
1010
1011 ret = psp_ta_unload(psp, &psp->asd_context);
1012 if (!ret)
1013 psp->asd_context.initialized = false;
1014
1015 return ret;
1016 }
1017
psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint32_t id,uint32_t value)1018 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1019 uint32_t id, uint32_t value)
1020 {
1021 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1022 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1023 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1024 }
1025
psp_reg_program(struct psp_context * psp,enum psp_reg_prog_id reg,uint32_t value)1026 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1027 uint32_t value)
1028 {
1029 struct psp_gfx_cmd_resp *cmd;
1030 int ret = 0;
1031
1032 if (reg >= PSP_REG_LAST)
1033 return -EINVAL;
1034
1035 cmd = acquire_psp_cmd_buf(psp);
1036
1037 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1038 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1039 if (ret)
1040 DRM_ERROR("PSP failed to program reg id %d", reg);
1041
1042 release_psp_cmd_buf(psp);
1043
1044 return ret;
1045 }
1046
psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint64_t ta_bin_mc,struct ta_context * context)1047 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1048 uint64_t ta_bin_mc,
1049 struct ta_context *context)
1050 {
1051 cmd->cmd_id = context->ta_load_type;
1052 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
1053 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
1054 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes;
1055
1056 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1057 lower_32_bits(context->mem_context.shared_mc_addr);
1058 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1059 upper_32_bits(context->mem_context.shared_mc_addr);
1060 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1061 }
1062
psp_ta_init_shared_buf(struct psp_context * psp,struct ta_mem_context * mem_ctx)1063 int psp_ta_init_shared_buf(struct psp_context *psp,
1064 struct ta_mem_context *mem_ctx)
1065 {
1066 /*
1067 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1068 * physical) for ta to host memory
1069 */
1070 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1071 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1072 &mem_ctx->shared_bo,
1073 &mem_ctx->shared_mc_addr,
1074 &mem_ctx->shared_buf);
1075 }
1076
psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint32_t ta_cmd_id,struct ta_context * context)1077 static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1078 uint32_t ta_cmd_id,
1079 struct ta_context *context)
1080 {
1081 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1082 cmd->cmd.cmd_invoke_cmd.session_id = context->session_id;
1083 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1084
1085 cmd->cmd.cmd_invoke_cmd.buf.num_desc = 1;
1086 cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size;
1087 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size;
1088 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo =
1089 lower_32_bits(context->mem_context.shared_mc_addr);
1090 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi =
1091 upper_32_bits(context->mem_context.shared_mc_addr);
1092 }
1093
psp_ta_invoke_indirect(struct psp_context * psp,uint32_t ta_cmd_id,struct ta_context * context)1094 int psp_ta_invoke_indirect(struct psp_context *psp,
1095 uint32_t ta_cmd_id,
1096 struct ta_context *context)
1097 {
1098 int ret;
1099 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1100
1101 psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context);
1102
1103 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1104 psp->fence_buf_mc_addr);
1105
1106 context->resp_status = cmd->resp.status;
1107
1108 release_psp_cmd_buf(psp);
1109
1110 return ret;
1111 }
1112
psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp * cmd,uint32_t ta_cmd_id,uint32_t session_id)1113 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1114 uint32_t ta_cmd_id,
1115 uint32_t session_id)
1116 {
1117 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1118 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
1119 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
1120 }
1121
psp_ta_invoke(struct psp_context * psp,uint32_t ta_cmd_id,struct ta_context * context)1122 int psp_ta_invoke(struct psp_context *psp,
1123 uint32_t ta_cmd_id,
1124 struct ta_context *context)
1125 {
1126 int ret;
1127 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1128
1129 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1130
1131 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1132 psp->fence_buf_mc_addr);
1133
1134 context->resp_status = cmd->resp.status;
1135
1136 release_psp_cmd_buf(psp);
1137
1138 return ret;
1139 }
1140
psp_ta_load(struct psp_context * psp,struct ta_context * context)1141 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1142 {
1143 int ret;
1144 struct psp_gfx_cmd_resp *cmd;
1145
1146 cmd = acquire_psp_cmd_buf(psp);
1147
1148 psp_copy_fw(psp, context->bin_desc.start_addr,
1149 context->bin_desc.size_bytes);
1150
1151 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1152
1153 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1154 psp->fence_buf_mc_addr);
1155
1156 context->resp_status = cmd->resp.status;
1157
1158 if (!ret) {
1159 context->session_id = cmd->resp.session_id;
1160 }
1161
1162 release_psp_cmd_buf(psp);
1163
1164 return ret;
1165 }
1166
psp_xgmi_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1167 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1168 {
1169 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1170 }
1171
psp_xgmi_terminate(struct psp_context * psp)1172 int psp_xgmi_terminate(struct psp_context *psp)
1173 {
1174 int ret;
1175 struct amdgpu_device *adev = psp->adev;
1176
1177 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1178 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1179 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1180 adev->gmc.xgmi.connected_to_cpu))
1181 return 0;
1182
1183 if (!psp->xgmi_context.context.initialized)
1184 return 0;
1185
1186 ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1187
1188 psp->xgmi_context.context.initialized = false;
1189
1190 return ret;
1191 }
1192
psp_xgmi_initialize(struct psp_context * psp,bool set_extended_data,bool load_ta)1193 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1194 {
1195 struct ta_xgmi_shared_memory *xgmi_cmd;
1196 int ret;
1197
1198 if (!psp->ta_fw ||
1199 !psp->xgmi_context.context.bin_desc.size_bytes ||
1200 !psp->xgmi_context.context.bin_desc.start_addr)
1201 return -ENOENT;
1202
1203 if (!load_ta)
1204 goto invoke;
1205
1206 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1207 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1208
1209 if (!psp->xgmi_context.context.mem_context.shared_buf) {
1210 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1211 if (ret)
1212 return ret;
1213 }
1214
1215 /* Load XGMI TA */
1216 ret = psp_ta_load(psp, &psp->xgmi_context.context);
1217 if (!ret)
1218 psp->xgmi_context.context.initialized = true;
1219 else
1220 return ret;
1221
1222 invoke:
1223 /* Initialize XGMI session */
1224 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1225 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1226 xgmi_cmd->flag_extend_link_record = set_extended_data;
1227 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1228
1229 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1230
1231 return ret;
1232 }
1233
psp_xgmi_get_hive_id(struct psp_context * psp,uint64_t * hive_id)1234 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1235 {
1236 struct ta_xgmi_shared_memory *xgmi_cmd;
1237 int ret;
1238
1239 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1240 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1241
1242 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1243
1244 /* Invoke xgmi ta to get hive id */
1245 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1246 if (ret)
1247 return ret;
1248
1249 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1250
1251 return 0;
1252 }
1253
psp_xgmi_get_node_id(struct psp_context * psp,uint64_t * node_id)1254 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1255 {
1256 struct ta_xgmi_shared_memory *xgmi_cmd;
1257 int ret;
1258
1259 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1260 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1261
1262 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1263
1264 /* Invoke xgmi ta to get the node id */
1265 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1266 if (ret)
1267 return ret;
1268
1269 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1270
1271 return 0;
1272 }
1273
psp_xgmi_peer_link_info_supported(struct psp_context * psp)1274 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1275 {
1276 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1277 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b;
1278 }
1279
1280 /*
1281 * Chips that support extended topology information require the driver to
1282 * reflect topology information in the opposite direction. This is
1283 * because the TA has already exceeded its link record limit and if the
1284 * TA holds bi-directional information, the driver would have to do
1285 * multiple fetches instead of just two.
1286 */
psp_xgmi_reflect_topology_info(struct psp_context * psp,struct psp_xgmi_node_info node_info)1287 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1288 struct psp_xgmi_node_info node_info)
1289 {
1290 struct amdgpu_device *mirror_adev;
1291 struct amdgpu_hive_info *hive;
1292 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1293 uint64_t dst_node_id = node_info.node_id;
1294 uint8_t dst_num_hops = node_info.num_hops;
1295 uint8_t dst_num_links = node_info.num_links;
1296
1297 hive = amdgpu_get_xgmi_hive(psp->adev);
1298 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1299 struct psp_xgmi_topology_info *mirror_top_info;
1300 int j;
1301
1302 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1303 continue;
1304
1305 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1306 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1307 if (mirror_top_info->nodes[j].node_id != src_node_id)
1308 continue;
1309
1310 mirror_top_info->nodes[j].num_hops = dst_num_hops;
1311 /*
1312 * prevent 0 num_links value re-reflection since reflection
1313 * criteria is based on num_hops (direct or indirect).
1314 *
1315 */
1316 if (dst_num_links)
1317 mirror_top_info->nodes[j].num_links = dst_num_links;
1318
1319 break;
1320 }
1321
1322 break;
1323 }
1324
1325 amdgpu_put_xgmi_hive(hive);
1326 }
1327
psp_xgmi_get_topology_info(struct psp_context * psp,int number_devices,struct psp_xgmi_topology_info * topology,bool get_extended_data)1328 int psp_xgmi_get_topology_info(struct psp_context *psp,
1329 int number_devices,
1330 struct psp_xgmi_topology_info *topology,
1331 bool get_extended_data)
1332 {
1333 struct ta_xgmi_shared_memory *xgmi_cmd;
1334 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1335 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1336 int i;
1337 int ret;
1338
1339 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1340 return -EINVAL;
1341
1342 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1343 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1344 xgmi_cmd->flag_extend_link_record = get_extended_data;
1345
1346 /* Fill in the shared memory with topology information as input */
1347 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1348 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1349 topology_info_input->num_nodes = number_devices;
1350
1351 for (i = 0; i < topology_info_input->num_nodes; i++) {
1352 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1353 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1354 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1355 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1356 }
1357
1358 /* Invoke xgmi ta to get the topology information */
1359 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1360 if (ret)
1361 return ret;
1362
1363 /* Read the output topology information from the shared memory */
1364 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1365 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1366 for (i = 0; i < topology->num_nodes; i++) {
1367 /* extended data will either be 0 or equal to non-extended data */
1368 if (topology_info_output->nodes[i].num_hops)
1369 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1370
1371 /* non-extended data gets everything here so no need to update */
1372 if (!get_extended_data) {
1373 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1374 topology->nodes[i].is_sharing_enabled =
1375 topology_info_output->nodes[i].is_sharing_enabled;
1376 topology->nodes[i].sdma_engine =
1377 topology_info_output->nodes[i].sdma_engine;
1378 }
1379
1380 }
1381
1382 /* Invoke xgmi ta again to get the link information */
1383 if (psp_xgmi_peer_link_info_supported(psp)) {
1384 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1385
1386 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1387
1388 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1389
1390 if (ret)
1391 return ret;
1392
1393 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1394 for (i = 0; i < topology->num_nodes; i++) {
1395 /* accumulate num_links on extended data */
1396 topology->nodes[i].num_links = get_extended_data ?
1397 topology->nodes[i].num_links +
1398 link_info_output->nodes[i].num_links :
1399 link_info_output->nodes[i].num_links;
1400
1401 /* reflect the topology information for bi-directionality */
1402 if (psp->xgmi_context.supports_extended_data &&
1403 get_extended_data && topology->nodes[i].num_hops)
1404 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1405 }
1406 }
1407
1408 return 0;
1409 }
1410
psp_xgmi_set_topology_info(struct psp_context * psp,int number_devices,struct psp_xgmi_topology_info * topology)1411 int psp_xgmi_set_topology_info(struct psp_context *psp,
1412 int number_devices,
1413 struct psp_xgmi_topology_info *topology)
1414 {
1415 struct ta_xgmi_shared_memory *xgmi_cmd;
1416 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1417 int i;
1418
1419 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1420 return -EINVAL;
1421
1422 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1423 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1424
1425 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1426 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1427 topology_info_input->num_nodes = number_devices;
1428
1429 for (i = 0; i < topology_info_input->num_nodes; i++) {
1430 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1431 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1432 topology_info_input->nodes[i].is_sharing_enabled = 1;
1433 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1434 }
1435
1436 /* Invoke xgmi ta to set topology information */
1437 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1438 }
1439
1440 // ras begin
psp_ras_ta_check_status(struct psp_context * psp)1441 static void psp_ras_ta_check_status(struct psp_context *psp)
1442 {
1443 struct ta_ras_shared_memory *ras_cmd =
1444 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1445
1446 switch (ras_cmd->ras_status) {
1447 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1448 dev_warn(psp->adev->dev,
1449 "RAS WARNING: cmd failed due to unsupported ip\n");
1450 break;
1451 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1452 dev_warn(psp->adev->dev,
1453 "RAS WARNING: cmd failed due to unsupported error injection\n");
1454 break;
1455 case TA_RAS_STATUS__SUCCESS:
1456 break;
1457 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1458 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1459 dev_warn(psp->adev->dev,
1460 "RAS WARNING: Inject error to critical region is not allowed\n");
1461 break;
1462 default:
1463 dev_warn(psp->adev->dev,
1464 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1465 break;
1466 }
1467 }
1468
psp_ras_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1469 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1470 {
1471 struct ta_ras_shared_memory *ras_cmd;
1472 int ret;
1473
1474 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1475
1476 /*
1477 * TODO: bypass the loading in sriov for now
1478 */
1479 if (amdgpu_sriov_vf(psp->adev))
1480 return 0;
1481
1482 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1483
1484 if (amdgpu_ras_intr_triggered())
1485 return ret;
1486
1487 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1488 {
1489 DRM_WARN("RAS: Unsupported Interface");
1490 return -EINVAL;
1491 }
1492
1493 if (!ret) {
1494 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1495 dev_warn(psp->adev->dev, "ECC switch disabled\n");
1496
1497 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1498 }
1499 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1500 dev_warn(psp->adev->dev,
1501 "RAS internal register access blocked\n");
1502
1503 psp_ras_ta_check_status(psp);
1504 }
1505
1506 return ret;
1507 }
1508
psp_ras_enable_features(struct psp_context * psp,union ta_ras_cmd_input * info,bool enable)1509 int psp_ras_enable_features(struct psp_context *psp,
1510 union ta_ras_cmd_input *info, bool enable)
1511 {
1512 struct ta_ras_shared_memory *ras_cmd;
1513 int ret;
1514
1515 if (!psp->ras_context.context.initialized)
1516 return -EINVAL;
1517
1518 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1519 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1520
1521 if (enable)
1522 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1523 else
1524 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1525
1526 ras_cmd->ras_in_message = *info;
1527
1528 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1529 if (ret)
1530 return -EINVAL;
1531
1532 return 0;
1533 }
1534
psp_ras_terminate(struct psp_context * psp)1535 int psp_ras_terminate(struct psp_context *psp)
1536 {
1537 int ret;
1538
1539 /*
1540 * TODO: bypass the terminate in sriov for now
1541 */
1542 if (amdgpu_sriov_vf(psp->adev))
1543 return 0;
1544
1545 if (!psp->ras_context.context.initialized)
1546 return 0;
1547
1548 ret = psp_ta_unload(psp, &psp->ras_context.context);
1549
1550 psp->ras_context.context.initialized = false;
1551
1552 return ret;
1553 }
1554
psp_ras_initialize(struct psp_context * psp)1555 static int psp_ras_initialize(struct psp_context *psp)
1556 {
1557 int ret;
1558 uint32_t boot_cfg = 0xFF;
1559 struct amdgpu_device *adev = psp->adev;
1560 struct ta_ras_shared_memory *ras_cmd;
1561
1562 /*
1563 * TODO: bypass the initialize in sriov for now
1564 */
1565 if (amdgpu_sriov_vf(adev))
1566 return 0;
1567
1568 if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1569 !adev->psp.ras_context.context.bin_desc.start_addr) {
1570 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1571 return 0;
1572 }
1573
1574 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1575 /* query GECC enablement status from boot config
1576 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1577 */
1578 ret = psp_boot_config_get(adev, &boot_cfg);
1579 if (ret)
1580 dev_warn(adev->dev, "PSP get boot config failed\n");
1581
1582 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1583 if (!boot_cfg) {
1584 dev_info(adev->dev, "GECC is disabled\n");
1585 } else {
1586 /* disable GECC in next boot cycle if ras is
1587 * disabled by module parameter amdgpu_ras_enable
1588 * and/or amdgpu_ras_mask, or boot_config_get call
1589 * is failed
1590 */
1591 ret = psp_boot_config_set(adev, 0);
1592 if (ret)
1593 dev_warn(adev->dev, "PSP set boot config failed\n");
1594 else
1595 dev_warn(adev->dev, "GECC will be disabled in next boot cycle "
1596 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1597 }
1598 } else {
1599 if (1 == boot_cfg) {
1600 dev_info(adev->dev, "GECC is enabled\n");
1601 } else {
1602 /* enable GECC in next boot cycle if it is disabled
1603 * in boot config, or force enable GECC if failed to
1604 * get boot configuration
1605 */
1606 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1607 if (ret)
1608 dev_warn(adev->dev, "PSP set boot config failed\n");
1609 else
1610 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1611 }
1612 }
1613 }
1614
1615 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1616 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1617
1618 if (!psp->ras_context.context.initialized) {
1619 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1620 if (ret)
1621 return ret;
1622 }
1623
1624 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1625 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1626
1627 if (amdgpu_ras_is_poison_mode_supported(adev))
1628 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1629 if (!adev->gmc.xgmi.connected_to_cpu)
1630 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1631
1632 ret = psp_ta_load(psp, &psp->ras_context.context);
1633
1634 if (!ret && !ras_cmd->ras_status)
1635 psp->ras_context.context.initialized = true;
1636 else {
1637 if (ras_cmd->ras_status)
1638 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1639 amdgpu_ras_fini(psp->adev);
1640 }
1641
1642 return ret;
1643 }
1644
psp_ras_trigger_error(struct psp_context * psp,struct ta_ras_trigger_error_input * info)1645 int psp_ras_trigger_error(struct psp_context *psp,
1646 struct ta_ras_trigger_error_input *info)
1647 {
1648 struct ta_ras_shared_memory *ras_cmd;
1649 int ret;
1650
1651 if (!psp->ras_context.context.initialized)
1652 return -EINVAL;
1653
1654 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1655 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1656
1657 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1658 ras_cmd->ras_in_message.trigger_error = *info;
1659
1660 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1661 if (ret)
1662 return -EINVAL;
1663
1664 /* If err_event_athub occurs error inject was successful, however
1665 return status from TA is no long reliable */
1666 if (amdgpu_ras_intr_triggered())
1667 return 0;
1668
1669 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1670 return -EACCES;
1671 else if (ras_cmd->ras_status)
1672 return -EINVAL;
1673
1674 return 0;
1675 }
1676 // ras end
1677
1678 // HDCP start
psp_hdcp_initialize(struct psp_context * psp)1679 static int psp_hdcp_initialize(struct psp_context *psp)
1680 {
1681 int ret;
1682
1683 /*
1684 * TODO: bypass the initialize in sriov for now
1685 */
1686 if (amdgpu_sriov_vf(psp->adev))
1687 return 0;
1688
1689 if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1690 !psp->hdcp_context.context.bin_desc.start_addr) {
1691 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1692 return 0;
1693 }
1694
1695 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1696 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1697
1698 if (!psp->hdcp_context.context.initialized) {
1699 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1700 if (ret)
1701 return ret;
1702 }
1703
1704 ret = psp_ta_load(psp, &psp->hdcp_context.context);
1705 if (!ret) {
1706 psp->hdcp_context.context.initialized = true;
1707 mutex_init(&psp->hdcp_context.mutex);
1708 }
1709
1710 return ret;
1711 }
1712
psp_hdcp_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1713 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1714 {
1715 /*
1716 * TODO: bypass the loading in sriov for now
1717 */
1718 if (amdgpu_sriov_vf(psp->adev))
1719 return 0;
1720
1721 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1722 }
1723
psp_hdcp_terminate(struct psp_context * psp)1724 static int psp_hdcp_terminate(struct psp_context *psp)
1725 {
1726 int ret;
1727
1728 /*
1729 * TODO: bypass the terminate in sriov for now
1730 */
1731 if (amdgpu_sriov_vf(psp->adev))
1732 return 0;
1733
1734 if (!psp->hdcp_context.context.initialized)
1735 return 0;
1736
1737 ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1738
1739 psp->hdcp_context.context.initialized = false;
1740
1741 return ret;
1742 }
1743 // HDCP end
1744
1745 // DTM start
psp_dtm_initialize(struct psp_context * psp)1746 static int psp_dtm_initialize(struct psp_context *psp)
1747 {
1748 int ret;
1749
1750 /*
1751 * TODO: bypass the initialize in sriov for now
1752 */
1753 if (amdgpu_sriov_vf(psp->adev))
1754 return 0;
1755
1756 if (!psp->dtm_context.context.bin_desc.size_bytes ||
1757 !psp->dtm_context.context.bin_desc.start_addr) {
1758 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1759 return 0;
1760 }
1761
1762 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1763 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1764
1765 if (!psp->dtm_context.context.initialized) {
1766 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1767 if (ret)
1768 return ret;
1769 }
1770
1771 ret = psp_ta_load(psp, &psp->dtm_context.context);
1772 if (!ret) {
1773 psp->dtm_context.context.initialized = true;
1774 mutex_init(&psp->dtm_context.mutex);
1775 }
1776
1777 return ret;
1778 }
1779
psp_dtm_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1780 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1781 {
1782 /*
1783 * TODO: bypass the loading in sriov for now
1784 */
1785 if (amdgpu_sriov_vf(psp->adev))
1786 return 0;
1787
1788 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1789 }
1790
psp_dtm_terminate(struct psp_context * psp)1791 static int psp_dtm_terminate(struct psp_context *psp)
1792 {
1793 int ret;
1794
1795 /*
1796 * TODO: bypass the terminate in sriov for now
1797 */
1798 if (amdgpu_sriov_vf(psp->adev))
1799 return 0;
1800
1801 if (!psp->dtm_context.context.initialized)
1802 return 0;
1803
1804 ret = psp_ta_unload(psp, &psp->dtm_context.context);
1805
1806 psp->dtm_context.context.initialized = false;
1807
1808 return ret;
1809 }
1810 // DTM end
1811
1812 // RAP start
psp_rap_initialize(struct psp_context * psp)1813 static int psp_rap_initialize(struct psp_context *psp)
1814 {
1815 int ret;
1816 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1817
1818 /*
1819 * TODO: bypass the initialize in sriov for now
1820 */
1821 if (amdgpu_sriov_vf(psp->adev))
1822 return 0;
1823
1824 if (!psp->rap_context.context.bin_desc.size_bytes ||
1825 !psp->rap_context.context.bin_desc.start_addr) {
1826 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1827 return 0;
1828 }
1829
1830 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1831 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1832
1833 if (!psp->rap_context.context.initialized) {
1834 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1835 if (ret)
1836 return ret;
1837 }
1838
1839 ret = psp_ta_load(psp, &psp->rap_context.context);
1840 if (!ret) {
1841 psp->rap_context.context.initialized = true;
1842 mutex_init(&psp->rap_context.mutex);
1843 } else
1844 return ret;
1845
1846 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1847 if (ret || status != TA_RAP_STATUS__SUCCESS) {
1848 psp_rap_terminate(psp);
1849 /* free rap shared memory */
1850 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1851
1852 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1853 ret, status);
1854
1855 return ret;
1856 }
1857
1858 return 0;
1859 }
1860
psp_rap_terminate(struct psp_context * psp)1861 static int psp_rap_terminate(struct psp_context *psp)
1862 {
1863 int ret;
1864
1865 if (!psp->rap_context.context.initialized)
1866 return 0;
1867
1868 ret = psp_ta_unload(psp, &psp->rap_context.context);
1869
1870 psp->rap_context.context.initialized = false;
1871
1872 return ret;
1873 }
1874
psp_rap_invoke(struct psp_context * psp,uint32_t ta_cmd_id,enum ta_rap_status * status)1875 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1876 {
1877 struct ta_rap_shared_memory *rap_cmd;
1878 int ret = 0;
1879
1880 if (!psp->rap_context.context.initialized)
1881 return 0;
1882
1883 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1884 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1885 return -EINVAL;
1886
1887 mutex_lock(&psp->rap_context.mutex);
1888
1889 rap_cmd = (struct ta_rap_shared_memory *)
1890 psp->rap_context.context.mem_context.shared_buf;
1891 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1892
1893 rap_cmd->cmd_id = ta_cmd_id;
1894 rap_cmd->validation_method_id = METHOD_A;
1895
1896 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1897 if (ret)
1898 goto out_unlock;
1899
1900 if (status)
1901 *status = rap_cmd->rap_status;
1902
1903 out_unlock:
1904 mutex_unlock(&psp->rap_context.mutex);
1905
1906 return ret;
1907 }
1908 // RAP end
1909
1910 /* securedisplay start */
psp_securedisplay_initialize(struct psp_context * psp)1911 static int psp_securedisplay_initialize(struct psp_context *psp)
1912 {
1913 int ret;
1914 struct securedisplay_cmd *securedisplay_cmd;
1915
1916 /*
1917 * TODO: bypass the initialize in sriov for now
1918 */
1919 if (amdgpu_sriov_vf(psp->adev))
1920 return 0;
1921
1922 if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1923 !psp->securedisplay_context.context.bin_desc.start_addr) {
1924 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1925 return 0;
1926 }
1927
1928 psp->securedisplay_context.context.mem_context.shared_mem_size =
1929 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1930 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1931
1932 if (!psp->securedisplay_context.context.initialized) {
1933 ret = psp_ta_init_shared_buf(psp,
1934 &psp->securedisplay_context.context.mem_context);
1935 if (ret)
1936 return ret;
1937 }
1938
1939 ret = psp_ta_load(psp, &psp->securedisplay_context.context);
1940 if (!ret) {
1941 psp->securedisplay_context.context.initialized = true;
1942 mutex_init(&psp->securedisplay_context.mutex);
1943 } else
1944 return ret;
1945
1946 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1947 TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1948
1949 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1950 if (ret) {
1951 psp_securedisplay_terminate(psp);
1952 /* free securedisplay shared memory */
1953 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
1954 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1955 return -EINVAL;
1956 }
1957
1958 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1959 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1960 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1961 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1962 }
1963
1964 return 0;
1965 }
1966
psp_securedisplay_terminate(struct psp_context * psp)1967 static int psp_securedisplay_terminate(struct psp_context *psp)
1968 {
1969 int ret;
1970
1971 /*
1972 * TODO:bypass the terminate in sriov for now
1973 */
1974 if (amdgpu_sriov_vf(psp->adev))
1975 return 0;
1976
1977 if (!psp->securedisplay_context.context.initialized)
1978 return 0;
1979
1980 ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
1981
1982 psp->securedisplay_context.context.initialized = false;
1983
1984 return ret;
1985 }
1986
psp_securedisplay_invoke(struct psp_context * psp,uint32_t ta_cmd_id)1987 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1988 {
1989 int ret;
1990
1991 if (!psp->securedisplay_context.context.initialized)
1992 return -EINVAL;
1993
1994 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1995 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
1996 return -EINVAL;
1997
1998 mutex_lock(&psp->securedisplay_context.mutex);
1999
2000 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
2001
2002 mutex_unlock(&psp->securedisplay_context.mutex);
2003
2004 return ret;
2005 }
2006 /* SECUREDISPLAY end */
2007
psp_hw_start(struct psp_context * psp)2008 static int psp_hw_start(struct psp_context *psp)
2009 {
2010 struct amdgpu_device *adev = psp->adev;
2011 int ret;
2012
2013 if (!amdgpu_sriov_vf(adev)) {
2014 if ((is_psp_fw_valid(psp->kdb)) &&
2015 (psp->funcs->bootloader_load_kdb != NULL)) {
2016 ret = psp_bootloader_load_kdb(psp);
2017 if (ret) {
2018 DRM_ERROR("PSP load kdb failed!\n");
2019 return ret;
2020 }
2021 }
2022
2023 if ((is_psp_fw_valid(psp->spl)) &&
2024 (psp->funcs->bootloader_load_spl != NULL)) {
2025 ret = psp_bootloader_load_spl(psp);
2026 if (ret) {
2027 DRM_ERROR("PSP load spl failed!\n");
2028 return ret;
2029 }
2030 }
2031
2032 if ((is_psp_fw_valid(psp->sys)) &&
2033 (psp->funcs->bootloader_load_sysdrv != NULL)) {
2034 ret = psp_bootloader_load_sysdrv(psp);
2035 if (ret) {
2036 DRM_ERROR("PSP load sys drv failed!\n");
2037 return ret;
2038 }
2039 }
2040
2041 if ((is_psp_fw_valid(psp->soc_drv)) &&
2042 (psp->funcs->bootloader_load_soc_drv != NULL)) {
2043 ret = psp_bootloader_load_soc_drv(psp);
2044 if (ret) {
2045 DRM_ERROR("PSP load soc drv failed!\n");
2046 return ret;
2047 }
2048 }
2049
2050 if ((is_psp_fw_valid(psp->intf_drv)) &&
2051 (psp->funcs->bootloader_load_intf_drv != NULL)) {
2052 ret = psp_bootloader_load_intf_drv(psp);
2053 if (ret) {
2054 DRM_ERROR("PSP load intf drv failed!\n");
2055 return ret;
2056 }
2057 }
2058
2059 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2060 (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2061 ret = psp_bootloader_load_dbg_drv(psp);
2062 if (ret) {
2063 DRM_ERROR("PSP load dbg drv failed!\n");
2064 return ret;
2065 }
2066 }
2067
2068 if ((is_psp_fw_valid(psp->ras_drv)) &&
2069 (psp->funcs->bootloader_load_ras_drv != NULL)) {
2070 ret = psp_bootloader_load_ras_drv(psp);
2071 if (ret) {
2072 DRM_ERROR("PSP load ras_drv failed!\n");
2073 return ret;
2074 }
2075 }
2076
2077 if ((is_psp_fw_valid(psp->sos)) &&
2078 (psp->funcs->bootloader_load_sos != NULL)) {
2079 ret = psp_bootloader_load_sos(psp);
2080 if (ret) {
2081 DRM_ERROR("PSP load sos failed!\n");
2082 return ret;
2083 }
2084 }
2085 }
2086
2087 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2088 if (ret) {
2089 DRM_ERROR("PSP create ring failed!\n");
2090 return ret;
2091 }
2092
2093 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2094 goto skip_pin_bo;
2095
2096 ret = psp_tmr_init(psp);
2097 if (ret) {
2098 DRM_ERROR("PSP tmr init failed!\n");
2099 return ret;
2100 }
2101
2102 skip_pin_bo:
2103 /*
2104 * For ASICs with DF Cstate management centralized
2105 * to PMFW, TMR setup should be performed after PMFW
2106 * loaded and before other non-psp firmware loaded.
2107 */
2108 if (psp->pmfw_centralized_cstate_management) {
2109 ret = psp_load_smu_fw(psp);
2110 if (ret)
2111 return ret;
2112 }
2113
2114 ret = psp_tmr_load(psp);
2115 if (ret) {
2116 DRM_ERROR("PSP load tmr failed!\n");
2117 return ret;
2118 }
2119
2120 return 0;
2121 }
2122
psp_get_fw_type(struct amdgpu_firmware_info * ucode,enum psp_gfx_fw_type * type)2123 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2124 enum psp_gfx_fw_type *type)
2125 {
2126 switch (ucode->ucode_id) {
2127 case AMDGPU_UCODE_ID_CAP:
2128 *type = GFX_FW_TYPE_CAP;
2129 break;
2130 case AMDGPU_UCODE_ID_SDMA0:
2131 *type = GFX_FW_TYPE_SDMA0;
2132 break;
2133 case AMDGPU_UCODE_ID_SDMA1:
2134 *type = GFX_FW_TYPE_SDMA1;
2135 break;
2136 case AMDGPU_UCODE_ID_SDMA2:
2137 *type = GFX_FW_TYPE_SDMA2;
2138 break;
2139 case AMDGPU_UCODE_ID_SDMA3:
2140 *type = GFX_FW_TYPE_SDMA3;
2141 break;
2142 case AMDGPU_UCODE_ID_SDMA4:
2143 *type = GFX_FW_TYPE_SDMA4;
2144 break;
2145 case AMDGPU_UCODE_ID_SDMA5:
2146 *type = GFX_FW_TYPE_SDMA5;
2147 break;
2148 case AMDGPU_UCODE_ID_SDMA6:
2149 *type = GFX_FW_TYPE_SDMA6;
2150 break;
2151 case AMDGPU_UCODE_ID_SDMA7:
2152 *type = GFX_FW_TYPE_SDMA7;
2153 break;
2154 case AMDGPU_UCODE_ID_CP_MES:
2155 *type = GFX_FW_TYPE_CP_MES;
2156 break;
2157 case AMDGPU_UCODE_ID_CP_MES_DATA:
2158 *type = GFX_FW_TYPE_MES_STACK;
2159 break;
2160 case AMDGPU_UCODE_ID_CP_MES1:
2161 *type = GFX_FW_TYPE_CP_MES_KIQ;
2162 break;
2163 case AMDGPU_UCODE_ID_CP_MES1_DATA:
2164 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2165 break;
2166 case AMDGPU_UCODE_ID_CP_CE:
2167 *type = GFX_FW_TYPE_CP_CE;
2168 break;
2169 case AMDGPU_UCODE_ID_CP_PFP:
2170 *type = GFX_FW_TYPE_CP_PFP;
2171 break;
2172 case AMDGPU_UCODE_ID_CP_ME:
2173 *type = GFX_FW_TYPE_CP_ME;
2174 break;
2175 case AMDGPU_UCODE_ID_CP_MEC1:
2176 *type = GFX_FW_TYPE_CP_MEC;
2177 break;
2178 case AMDGPU_UCODE_ID_CP_MEC1_JT:
2179 *type = GFX_FW_TYPE_CP_MEC_ME1;
2180 break;
2181 case AMDGPU_UCODE_ID_CP_MEC2:
2182 *type = GFX_FW_TYPE_CP_MEC;
2183 break;
2184 case AMDGPU_UCODE_ID_CP_MEC2_JT:
2185 *type = GFX_FW_TYPE_CP_MEC_ME2;
2186 break;
2187 case AMDGPU_UCODE_ID_RLC_P:
2188 *type = GFX_FW_TYPE_RLC_P;
2189 break;
2190 case AMDGPU_UCODE_ID_RLC_V:
2191 *type = GFX_FW_TYPE_RLC_V;
2192 break;
2193 case AMDGPU_UCODE_ID_RLC_G:
2194 *type = GFX_FW_TYPE_RLC_G;
2195 break;
2196 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2197 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2198 break;
2199 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2200 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2201 break;
2202 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2203 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2204 break;
2205 case AMDGPU_UCODE_ID_RLC_IRAM:
2206 *type = GFX_FW_TYPE_RLC_IRAM;
2207 break;
2208 case AMDGPU_UCODE_ID_RLC_DRAM:
2209 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2210 break;
2211 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2212 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2213 break;
2214 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2215 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2216 break;
2217 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2218 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2219 break;
2220 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2221 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2222 break;
2223 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2224 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2225 break;
2226 case AMDGPU_UCODE_ID_SMC:
2227 *type = GFX_FW_TYPE_SMU;
2228 break;
2229 case AMDGPU_UCODE_ID_PPTABLE:
2230 *type = GFX_FW_TYPE_PPTABLE;
2231 break;
2232 case AMDGPU_UCODE_ID_UVD:
2233 *type = GFX_FW_TYPE_UVD;
2234 break;
2235 case AMDGPU_UCODE_ID_UVD1:
2236 *type = GFX_FW_TYPE_UVD1;
2237 break;
2238 case AMDGPU_UCODE_ID_VCE:
2239 *type = GFX_FW_TYPE_VCE;
2240 break;
2241 case AMDGPU_UCODE_ID_VCN:
2242 *type = GFX_FW_TYPE_VCN;
2243 break;
2244 case AMDGPU_UCODE_ID_VCN1:
2245 *type = GFX_FW_TYPE_VCN1;
2246 break;
2247 case AMDGPU_UCODE_ID_DMCU_ERAM:
2248 *type = GFX_FW_TYPE_DMCU_ERAM;
2249 break;
2250 case AMDGPU_UCODE_ID_DMCU_INTV:
2251 *type = GFX_FW_TYPE_DMCU_ISR;
2252 break;
2253 case AMDGPU_UCODE_ID_VCN0_RAM:
2254 *type = GFX_FW_TYPE_VCN0_RAM;
2255 break;
2256 case AMDGPU_UCODE_ID_VCN1_RAM:
2257 *type = GFX_FW_TYPE_VCN1_RAM;
2258 break;
2259 case AMDGPU_UCODE_ID_DMCUB:
2260 *type = GFX_FW_TYPE_DMUB;
2261 break;
2262 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2263 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2264 break;
2265 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2266 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2267 break;
2268 case AMDGPU_UCODE_ID_IMU_I:
2269 *type = GFX_FW_TYPE_IMU_I;
2270 break;
2271 case AMDGPU_UCODE_ID_IMU_D:
2272 *type = GFX_FW_TYPE_IMU_D;
2273 break;
2274 case AMDGPU_UCODE_ID_CP_RS64_PFP:
2275 *type = GFX_FW_TYPE_RS64_PFP;
2276 break;
2277 case AMDGPU_UCODE_ID_CP_RS64_ME:
2278 *type = GFX_FW_TYPE_RS64_ME;
2279 break;
2280 case AMDGPU_UCODE_ID_CP_RS64_MEC:
2281 *type = GFX_FW_TYPE_RS64_MEC;
2282 break;
2283 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2284 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2285 break;
2286 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2287 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2288 break;
2289 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2290 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2291 break;
2292 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2293 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2294 break;
2295 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2296 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2297 break;
2298 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2299 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2300 break;
2301 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2302 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2303 break;
2304 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2305 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2306 break;
2307 case AMDGPU_UCODE_ID_MAXIMUM:
2308 default:
2309 return -EINVAL;
2310 }
2311
2312 return 0;
2313 }
2314
psp_print_fw_hdr(struct psp_context * psp,struct amdgpu_firmware_info * ucode)2315 static void psp_print_fw_hdr(struct psp_context *psp,
2316 struct amdgpu_firmware_info *ucode)
2317 {
2318 struct amdgpu_device *adev = psp->adev;
2319 struct common_firmware_header *hdr;
2320
2321 switch (ucode->ucode_id) {
2322 case AMDGPU_UCODE_ID_SDMA0:
2323 case AMDGPU_UCODE_ID_SDMA1:
2324 case AMDGPU_UCODE_ID_SDMA2:
2325 case AMDGPU_UCODE_ID_SDMA3:
2326 case AMDGPU_UCODE_ID_SDMA4:
2327 case AMDGPU_UCODE_ID_SDMA5:
2328 case AMDGPU_UCODE_ID_SDMA6:
2329 case AMDGPU_UCODE_ID_SDMA7:
2330 hdr = (struct common_firmware_header *)
2331 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2332 amdgpu_ucode_print_sdma_hdr(hdr);
2333 break;
2334 case AMDGPU_UCODE_ID_CP_CE:
2335 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2336 amdgpu_ucode_print_gfx_hdr(hdr);
2337 break;
2338 case AMDGPU_UCODE_ID_CP_PFP:
2339 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2340 amdgpu_ucode_print_gfx_hdr(hdr);
2341 break;
2342 case AMDGPU_UCODE_ID_CP_ME:
2343 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2344 amdgpu_ucode_print_gfx_hdr(hdr);
2345 break;
2346 case AMDGPU_UCODE_ID_CP_MEC1:
2347 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2348 amdgpu_ucode_print_gfx_hdr(hdr);
2349 break;
2350 case AMDGPU_UCODE_ID_RLC_G:
2351 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2352 amdgpu_ucode_print_rlc_hdr(hdr);
2353 break;
2354 case AMDGPU_UCODE_ID_SMC:
2355 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2356 amdgpu_ucode_print_smc_hdr(hdr);
2357 break;
2358 default:
2359 break;
2360 }
2361 }
2362
psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info * ucode,struct psp_gfx_cmd_resp * cmd)2363 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2364 struct psp_gfx_cmd_resp *cmd)
2365 {
2366 int ret;
2367 uint64_t fw_mem_mc_addr = ucode->mc_addr;
2368
2369 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2370 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2371 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2372 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2373
2374 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2375 if (ret)
2376 DRM_ERROR("Unknown firmware type\n");
2377
2378 return ret;
2379 }
2380
psp_execute_non_psp_fw_load(struct psp_context * psp,struct amdgpu_firmware_info * ucode)2381 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2382 struct amdgpu_firmware_info *ucode)
2383 {
2384 int ret = 0;
2385 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2386
2387 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2388 if (!ret) {
2389 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2390 psp->fence_buf_mc_addr);
2391 }
2392
2393 release_psp_cmd_buf(psp);
2394
2395 return ret;
2396 }
2397
psp_load_smu_fw(struct psp_context * psp)2398 static int psp_load_smu_fw(struct psp_context *psp)
2399 {
2400 int ret;
2401 struct amdgpu_device *adev = psp->adev;
2402 struct amdgpu_firmware_info *ucode =
2403 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2404 struct amdgpu_ras *ras = psp->ras_context.ras;
2405
2406 /*
2407 * Skip SMU FW reloading in case of using BACO for runpm only,
2408 * as SMU is always alive.
2409 */
2410 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2411 return 0;
2412
2413 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2414 return 0;
2415
2416 if ((amdgpu_in_reset(adev) &&
2417 ras && adev->ras_enabled &&
2418 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2419 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2420 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2421 if (ret) {
2422 DRM_WARN("Failed to set MP1 state prepare for reload\n");
2423 }
2424 }
2425
2426 ret = psp_execute_non_psp_fw_load(psp, ucode);
2427
2428 if (ret)
2429 DRM_ERROR("PSP load smu failed!\n");
2430
2431 return ret;
2432 }
2433
fw_load_skip_check(struct psp_context * psp,struct amdgpu_firmware_info * ucode)2434 static bool fw_load_skip_check(struct psp_context *psp,
2435 struct amdgpu_firmware_info *ucode)
2436 {
2437 if (!ucode->fw || !ucode->ucode_size)
2438 return true;
2439
2440 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2441 (psp_smu_reload_quirk(psp) ||
2442 psp->autoload_supported ||
2443 psp->pmfw_centralized_cstate_management))
2444 return true;
2445
2446 if (amdgpu_sriov_vf(psp->adev) &&
2447 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2448 return true;
2449
2450 if (psp->autoload_supported &&
2451 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2452 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2453 /* skip mec JT when autoload is enabled */
2454 return true;
2455
2456 return false;
2457 }
2458
psp_load_fw_list(struct psp_context * psp,struct amdgpu_firmware_info ** ucode_list,int ucode_count)2459 int psp_load_fw_list(struct psp_context *psp,
2460 struct amdgpu_firmware_info **ucode_list, int ucode_count)
2461 {
2462 int ret = 0, i;
2463 struct amdgpu_firmware_info *ucode;
2464
2465 for (i = 0; i < ucode_count; ++i) {
2466 ucode = ucode_list[i];
2467 psp_print_fw_hdr(psp, ucode);
2468 ret = psp_execute_non_psp_fw_load(psp, ucode);
2469 if (ret)
2470 return ret;
2471 }
2472 return ret;
2473 }
2474
psp_load_non_psp_fw(struct psp_context * psp)2475 static int psp_load_non_psp_fw(struct psp_context *psp)
2476 {
2477 int i, ret;
2478 struct amdgpu_firmware_info *ucode;
2479 struct amdgpu_device *adev = psp->adev;
2480
2481 if (psp->autoload_supported &&
2482 !psp->pmfw_centralized_cstate_management) {
2483 ret = psp_load_smu_fw(psp);
2484 if (ret)
2485 return ret;
2486 }
2487
2488 for (i = 0; i < adev->firmware.max_ucodes; i++) {
2489 ucode = &adev->firmware.ucode[i];
2490
2491 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2492 !fw_load_skip_check(psp, ucode)) {
2493 ret = psp_load_smu_fw(psp);
2494 if (ret)
2495 return ret;
2496 continue;
2497 }
2498
2499 if (fw_load_skip_check(psp, ucode))
2500 continue;
2501
2502 if (psp->autoload_supported &&
2503 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2504 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2505 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2506 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2507 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2508 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2509 /* PSP only receive one SDMA fw for sienna_cichlid,
2510 * as all four sdma fw are same */
2511 continue;
2512
2513 psp_print_fw_hdr(psp, ucode);
2514
2515 ret = psp_execute_non_psp_fw_load(psp, ucode);
2516 if (ret)
2517 return ret;
2518
2519 /* Start rlc autoload after psp recieved all the gfx firmware */
2520 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2521 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2522 ret = psp_rlc_autoload_start(psp);
2523 if (ret) {
2524 DRM_ERROR("Failed to start rlc autoload\n");
2525 return ret;
2526 }
2527 }
2528 }
2529
2530 return 0;
2531 }
2532
psp_load_fw(struct amdgpu_device * adev)2533 static int psp_load_fw(struct amdgpu_device *adev)
2534 {
2535 int ret;
2536 struct psp_context *psp = &adev->psp;
2537
2538 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2539 /* should not destroy ring, only stop */
2540 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2541 } else {
2542 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2543
2544 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2545 if (ret) {
2546 DRM_ERROR("PSP ring init failed!\n");
2547 goto failed;
2548 }
2549 }
2550
2551 ret = psp_hw_start(psp);
2552 if (ret)
2553 goto failed;
2554
2555 ret = psp_load_non_psp_fw(psp);
2556 if (ret)
2557 goto failed1;
2558
2559 ret = psp_asd_initialize(psp);
2560 if (ret) {
2561 DRM_ERROR("PSP load asd failed!\n");
2562 goto failed1;
2563 }
2564
2565 ret = psp_rl_load(adev);
2566 if (ret) {
2567 DRM_ERROR("PSP load RL failed!\n");
2568 goto failed1;
2569 }
2570
2571 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2572 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2573 ret = psp_xgmi_initialize(psp, false, true);
2574 /* Warning the XGMI seesion initialize failure
2575 * Instead of stop driver initialization
2576 */
2577 if (ret)
2578 dev_err(psp->adev->dev,
2579 "XGMI: Failed to initialize XGMI session\n");
2580 }
2581 }
2582
2583 if (psp->ta_fw) {
2584 ret = psp_ras_initialize(psp);
2585 if (ret)
2586 dev_err(psp->adev->dev,
2587 "RAS: Failed to initialize RAS\n");
2588
2589 ret = psp_hdcp_initialize(psp);
2590 if (ret)
2591 dev_err(psp->adev->dev,
2592 "HDCP: Failed to initialize HDCP\n");
2593
2594 ret = psp_dtm_initialize(psp);
2595 if (ret)
2596 dev_err(psp->adev->dev,
2597 "DTM: Failed to initialize DTM\n");
2598
2599 ret = psp_rap_initialize(psp);
2600 if (ret)
2601 dev_err(psp->adev->dev,
2602 "RAP: Failed to initialize RAP\n");
2603
2604 ret = psp_securedisplay_initialize(psp);
2605 if (ret)
2606 dev_err(psp->adev->dev,
2607 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2608 }
2609
2610 return 0;
2611
2612 failed1:
2613 psp_free_shared_bufs(psp);
2614 failed:
2615 /*
2616 * all cleanup jobs (xgmi terminate, ras terminate,
2617 * ring destroy, cmd/fence/fw buffers destory,
2618 * psp->cmd destory) are delayed to psp_hw_fini
2619 */
2620 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2621 return ret;
2622 }
2623
psp_hw_init(void * handle)2624 static int psp_hw_init(void *handle)
2625 {
2626 int ret;
2627 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2628
2629 mutex_lock(&adev->firmware.mutex);
2630 /*
2631 * This sequence is just used on hw_init only once, no need on
2632 * resume.
2633 */
2634 ret = amdgpu_ucode_init_bo(adev);
2635 if (ret)
2636 goto failed;
2637
2638 ret = psp_load_fw(adev);
2639 if (ret) {
2640 DRM_ERROR("PSP firmware loading failed\n");
2641 goto failed;
2642 }
2643
2644 mutex_unlock(&adev->firmware.mutex);
2645 return 0;
2646
2647 failed:
2648 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2649 mutex_unlock(&adev->firmware.mutex);
2650 return -EINVAL;
2651 }
2652
psp_hw_fini(void * handle)2653 static int psp_hw_fini(void *handle)
2654 {
2655 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2656 struct psp_context *psp = &adev->psp;
2657
2658 if (psp->ta_fw) {
2659 psp_ras_terminate(psp);
2660 psp_securedisplay_terminate(psp);
2661 psp_rap_terminate(psp);
2662 psp_dtm_terminate(psp);
2663 psp_hdcp_terminate(psp);
2664
2665 if (adev->gmc.xgmi.num_physical_nodes > 1)
2666 psp_xgmi_terminate(psp);
2667 }
2668
2669 psp_asd_terminate(psp);
2670 psp_tmr_terminate(psp);
2671
2672 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2673
2674 psp_free_shared_bufs(psp);
2675
2676 return 0;
2677 }
2678
psp_suspend(void * handle)2679 static int psp_suspend(void *handle)
2680 {
2681 int ret = 0;
2682 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2683 struct psp_context *psp = &adev->psp;
2684
2685 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2686 psp->xgmi_context.context.initialized) {
2687 ret = psp_xgmi_terminate(psp);
2688 if (ret) {
2689 DRM_ERROR("Failed to terminate xgmi ta\n");
2690 goto out;
2691 }
2692 }
2693
2694 if (psp->ta_fw) {
2695 ret = psp_ras_terminate(psp);
2696 if (ret) {
2697 DRM_ERROR("Failed to terminate ras ta\n");
2698 goto out;
2699 }
2700 ret = psp_hdcp_terminate(psp);
2701 if (ret) {
2702 DRM_ERROR("Failed to terminate hdcp ta\n");
2703 goto out;
2704 }
2705 ret = psp_dtm_terminate(psp);
2706 if (ret) {
2707 DRM_ERROR("Failed to terminate dtm ta\n");
2708 goto out;
2709 }
2710 ret = psp_rap_terminate(psp);
2711 if (ret) {
2712 DRM_ERROR("Failed to terminate rap ta\n");
2713 goto out;
2714 }
2715 ret = psp_securedisplay_terminate(psp);
2716 if (ret) {
2717 DRM_ERROR("Failed to terminate securedisplay ta\n");
2718 goto out;
2719 }
2720 }
2721
2722 ret = psp_asd_terminate(psp);
2723 if (ret) {
2724 DRM_ERROR("Failed to terminate asd\n");
2725 goto out;
2726 }
2727
2728 ret = psp_tmr_terminate(psp);
2729 if (ret) {
2730 DRM_ERROR("Failed to terminate tmr\n");
2731 goto out;
2732 }
2733
2734 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2735 if (ret) {
2736 DRM_ERROR("PSP ring stop failed\n");
2737 }
2738
2739 out:
2740 return ret;
2741 }
2742
psp_resume(void * handle)2743 static int psp_resume(void *handle)
2744 {
2745 int ret;
2746 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2747 struct psp_context *psp = &adev->psp;
2748
2749 DRM_INFO("PSP is resuming...\n");
2750
2751 if (psp->mem_train_ctx.enable_mem_training) {
2752 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2753 if (ret) {
2754 DRM_ERROR("Failed to process memory training!\n");
2755 return ret;
2756 }
2757 }
2758
2759 mutex_lock(&adev->firmware.mutex);
2760
2761 ret = psp_hw_start(psp);
2762 if (ret)
2763 goto failed;
2764
2765 ret = psp_load_non_psp_fw(psp);
2766 if (ret)
2767 goto failed;
2768
2769 ret = psp_asd_initialize(psp);
2770 if (ret) {
2771 DRM_ERROR("PSP load asd failed!\n");
2772 goto failed;
2773 }
2774
2775 ret = psp_rl_load(adev);
2776 if (ret) {
2777 dev_err(adev->dev, "PSP load RL failed!\n");
2778 goto failed;
2779 }
2780
2781 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2782 ret = psp_xgmi_initialize(psp, false, true);
2783 /* Warning the XGMI seesion initialize failure
2784 * Instead of stop driver initialization
2785 */
2786 if (ret)
2787 dev_err(psp->adev->dev,
2788 "XGMI: Failed to initialize XGMI session\n");
2789 }
2790
2791 if (psp->ta_fw) {
2792 ret = psp_ras_initialize(psp);
2793 if (ret)
2794 dev_err(psp->adev->dev,
2795 "RAS: Failed to initialize RAS\n");
2796
2797 ret = psp_hdcp_initialize(psp);
2798 if (ret)
2799 dev_err(psp->adev->dev,
2800 "HDCP: Failed to initialize HDCP\n");
2801
2802 ret = psp_dtm_initialize(psp);
2803 if (ret)
2804 dev_err(psp->adev->dev,
2805 "DTM: Failed to initialize DTM\n");
2806
2807 ret = psp_rap_initialize(psp);
2808 if (ret)
2809 dev_err(psp->adev->dev,
2810 "RAP: Failed to initialize RAP\n");
2811
2812 ret = psp_securedisplay_initialize(psp);
2813 if (ret)
2814 dev_err(psp->adev->dev,
2815 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2816 }
2817
2818 mutex_unlock(&adev->firmware.mutex);
2819
2820 return 0;
2821
2822 failed:
2823 DRM_ERROR("PSP resume failed\n");
2824 mutex_unlock(&adev->firmware.mutex);
2825 return ret;
2826 }
2827
psp_gpu_reset(struct amdgpu_device * adev)2828 int psp_gpu_reset(struct amdgpu_device *adev)
2829 {
2830 int ret;
2831
2832 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2833 return 0;
2834
2835 mutex_lock(&adev->psp.mutex);
2836 ret = psp_mode1_reset(&adev->psp);
2837 mutex_unlock(&adev->psp.mutex);
2838
2839 return ret;
2840 }
2841
psp_rlc_autoload_start(struct psp_context * psp)2842 int psp_rlc_autoload_start(struct psp_context *psp)
2843 {
2844 int ret;
2845 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2846
2847 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2848
2849 ret = psp_cmd_submit_buf(psp, NULL, cmd,
2850 psp->fence_buf_mc_addr);
2851
2852 release_psp_cmd_buf(psp);
2853
2854 return ret;
2855 }
2856
psp_update_vcn_sram(struct amdgpu_device * adev,int inst_idx,uint64_t cmd_gpu_addr,int cmd_size)2857 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2858 uint64_t cmd_gpu_addr, int cmd_size)
2859 {
2860 struct amdgpu_firmware_info ucode = {0};
2861
2862 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2863 AMDGPU_UCODE_ID_VCN0_RAM;
2864 ucode.mc_addr = cmd_gpu_addr;
2865 ucode.ucode_size = cmd_size;
2866
2867 return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2868 }
2869
psp_ring_cmd_submit(struct psp_context * psp,uint64_t cmd_buf_mc_addr,uint64_t fence_mc_addr,int index)2870 int psp_ring_cmd_submit(struct psp_context *psp,
2871 uint64_t cmd_buf_mc_addr,
2872 uint64_t fence_mc_addr,
2873 int index)
2874 {
2875 unsigned int psp_write_ptr_reg = 0;
2876 struct psp_gfx_rb_frame *write_frame;
2877 struct psp_ring *ring = &psp->km_ring;
2878 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2879 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2880 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2881 struct amdgpu_device *adev = psp->adev;
2882 uint32_t ring_size_dw = ring->ring_size / 4;
2883 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2884
2885 /* KM (GPCOM) prepare write pointer */
2886 psp_write_ptr_reg = psp_ring_get_wptr(psp);
2887
2888 /* Update KM RB frame pointer to new frame */
2889 /* write_frame ptr increments by size of rb_frame in bytes */
2890 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2891 if ((psp_write_ptr_reg % ring_size_dw) == 0)
2892 write_frame = ring_buffer_start;
2893 else
2894 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2895 /* Check invalid write_frame ptr address */
2896 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2897 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2898 ring_buffer_start, ring_buffer_end, write_frame);
2899 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2900 return -EINVAL;
2901 }
2902
2903 /* Initialize KM RB frame */
2904 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2905
2906 /* Update KM RB frame */
2907 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2908 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2909 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2910 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2911 write_frame->fence_value = index;
2912 amdgpu_device_flush_hdp(adev, NULL);
2913
2914 /* Update the write Pointer in DWORDs */
2915 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2916 psp_ring_set_wptr(psp, psp_write_ptr_reg);
2917 return 0;
2918 }
2919
psp_init_asd_microcode(struct psp_context * psp,const char * chip_name)2920 int psp_init_asd_microcode(struct psp_context *psp,
2921 const char *chip_name)
2922 {
2923 struct amdgpu_device *adev = psp->adev;
2924 char fw_name[PSP_FW_NAME_LEN];
2925 const struct psp_firmware_header_v1_0 *asd_hdr;
2926 int err = 0;
2927
2928 if (!chip_name) {
2929 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2930 return -EINVAL;
2931 }
2932
2933 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2934 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2935 if (err)
2936 goto out;
2937
2938 err = amdgpu_ucode_validate(adev->psp.asd_fw);
2939 if (err)
2940 goto out;
2941
2942 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2943 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2944 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2945 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2946 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2947 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2948 return 0;
2949 out:
2950 dev_err(adev->dev, "fail to initialize asd microcode\n");
2951 release_firmware(adev->psp.asd_fw);
2952 adev->psp.asd_fw = NULL;
2953 return err;
2954 }
2955
psp_init_toc_microcode(struct psp_context * psp,const char * chip_name)2956 int psp_init_toc_microcode(struct psp_context *psp,
2957 const char *chip_name)
2958 {
2959 struct amdgpu_device *adev = psp->adev;
2960 char fw_name[PSP_FW_NAME_LEN];
2961 const struct psp_firmware_header_v1_0 *toc_hdr;
2962 int err = 0;
2963
2964 if (!chip_name) {
2965 dev_err(adev->dev, "invalid chip name for toc microcode\n");
2966 return -EINVAL;
2967 }
2968
2969 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2970 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
2971 if (err)
2972 goto out;
2973
2974 err = amdgpu_ucode_validate(adev->psp.toc_fw);
2975 if (err)
2976 goto out;
2977
2978 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2979 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2980 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
2981 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2982 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
2983 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2984 return 0;
2985 out:
2986 dev_err(adev->dev, "fail to request/validate toc microcode\n");
2987 release_firmware(adev->psp.toc_fw);
2988 adev->psp.toc_fw = NULL;
2989 return err;
2990 }
2991
parse_sos_bin_descriptor(struct psp_context * psp,const struct psp_fw_bin_desc * desc,const struct psp_firmware_header_v2_0 * sos_hdr)2992 static int parse_sos_bin_descriptor(struct psp_context *psp,
2993 const struct psp_fw_bin_desc *desc,
2994 const struct psp_firmware_header_v2_0 *sos_hdr)
2995 {
2996 uint8_t *ucode_start_addr = NULL;
2997
2998 if (!psp || !desc || !sos_hdr)
2999 return -EINVAL;
3000
3001 ucode_start_addr = (uint8_t *)sos_hdr +
3002 le32_to_cpu(desc->offset_bytes) +
3003 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3004
3005 switch (desc->fw_type) {
3006 case PSP_FW_TYPE_PSP_SOS:
3007 psp->sos.fw_version = le32_to_cpu(desc->fw_version);
3008 psp->sos.feature_version = le32_to_cpu(desc->fw_version);
3009 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes);
3010 psp->sos.start_addr = ucode_start_addr;
3011 break;
3012 case PSP_FW_TYPE_PSP_SYS_DRV:
3013 psp->sys.fw_version = le32_to_cpu(desc->fw_version);
3014 psp->sys.feature_version = le32_to_cpu(desc->fw_version);
3015 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes);
3016 psp->sys.start_addr = ucode_start_addr;
3017 break;
3018 case PSP_FW_TYPE_PSP_KDB:
3019 psp->kdb.fw_version = le32_to_cpu(desc->fw_version);
3020 psp->kdb.feature_version = le32_to_cpu(desc->fw_version);
3021 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes);
3022 psp->kdb.start_addr = ucode_start_addr;
3023 break;
3024 case PSP_FW_TYPE_PSP_TOC:
3025 psp->toc.fw_version = le32_to_cpu(desc->fw_version);
3026 psp->toc.feature_version = le32_to_cpu(desc->fw_version);
3027 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes);
3028 psp->toc.start_addr = ucode_start_addr;
3029 break;
3030 case PSP_FW_TYPE_PSP_SPL:
3031 psp->spl.fw_version = le32_to_cpu(desc->fw_version);
3032 psp->spl.feature_version = le32_to_cpu(desc->fw_version);
3033 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes);
3034 psp->spl.start_addr = ucode_start_addr;
3035 break;
3036 case PSP_FW_TYPE_PSP_RL:
3037 psp->rl.fw_version = le32_to_cpu(desc->fw_version);
3038 psp->rl.feature_version = le32_to_cpu(desc->fw_version);
3039 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes);
3040 psp->rl.start_addr = ucode_start_addr;
3041 break;
3042 case PSP_FW_TYPE_PSP_SOC_DRV:
3043 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version);
3044 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version);
3045 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3046 psp->soc_drv.start_addr = ucode_start_addr;
3047 break;
3048 case PSP_FW_TYPE_PSP_INTF_DRV:
3049 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version);
3050 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version);
3051 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3052 psp->intf_drv.start_addr = ucode_start_addr;
3053 break;
3054 case PSP_FW_TYPE_PSP_DBG_DRV:
3055 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version);
3056 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version);
3057 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3058 psp->dbg_drv.start_addr = ucode_start_addr;
3059 break;
3060 case PSP_FW_TYPE_PSP_RAS_DRV:
3061 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version);
3062 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version);
3063 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3064 psp->ras_drv.start_addr = ucode_start_addr;
3065 break;
3066 default:
3067 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3068 break;
3069 }
3070
3071 return 0;
3072 }
3073
psp_init_sos_base_fw(struct amdgpu_device * adev)3074 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3075 {
3076 const struct psp_firmware_header_v1_0 *sos_hdr;
3077 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3078 uint8_t *ucode_array_start_addr;
3079
3080 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3081 ucode_array_start_addr = (uint8_t *)sos_hdr +
3082 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3083
3084 if (adev->gmc.xgmi.connected_to_cpu ||
3085 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3086 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3087 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3088
3089 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3090 adev->psp.sys.start_addr = ucode_array_start_addr;
3091
3092 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3093 adev->psp.sos.start_addr = ucode_array_start_addr +
3094 le32_to_cpu(sos_hdr->sos.offset_bytes);
3095 } else {
3096 /* Load alternate PSP SOS FW */
3097 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3098
3099 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3100 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3101
3102 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3103 adev->psp.sys.start_addr = ucode_array_start_addr +
3104 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3105
3106 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3107 adev->psp.sos.start_addr = ucode_array_start_addr +
3108 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3109 }
3110
3111 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3112 dev_warn(adev->dev, "PSP SOS FW not available");
3113 return -EINVAL;
3114 }
3115
3116 return 0;
3117 }
3118
psp_init_sos_microcode(struct psp_context * psp,const char * chip_name)3119 int psp_init_sos_microcode(struct psp_context *psp,
3120 const char *chip_name)
3121 {
3122 struct amdgpu_device *adev = psp->adev;
3123 char fw_name[PSP_FW_NAME_LEN];
3124 const struct psp_firmware_header_v1_0 *sos_hdr;
3125 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3126 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3127 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3128 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3129 int err = 0;
3130 uint8_t *ucode_array_start_addr;
3131 int fw_index = 0;
3132
3133 if (!chip_name) {
3134 dev_err(adev->dev, "invalid chip name for sos microcode\n");
3135 return -EINVAL;
3136 }
3137
3138 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3139 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
3140 if (err)
3141 goto out;
3142
3143 err = amdgpu_ucode_validate(adev->psp.sos_fw);
3144 if (err)
3145 goto out;
3146
3147 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3148 ucode_array_start_addr = (uint8_t *)sos_hdr +
3149 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3150 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3151
3152 switch (sos_hdr->header.header_version_major) {
3153 case 1:
3154 err = psp_init_sos_base_fw(adev);
3155 if (err)
3156 goto out;
3157
3158 if (sos_hdr->header.header_version_minor == 1) {
3159 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3160 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3161 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3162 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3163 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3164 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3165 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3166 }
3167 if (sos_hdr->header.header_version_minor == 2) {
3168 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3169 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3170 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3171 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3172 }
3173 if (sos_hdr->header.header_version_minor == 3) {
3174 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3175 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3176 adev->psp.toc.start_addr = ucode_array_start_addr +
3177 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3178 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3179 adev->psp.kdb.start_addr = ucode_array_start_addr +
3180 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3181 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3182 adev->psp.spl.start_addr = ucode_array_start_addr +
3183 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3184 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3185 adev->psp.rl.start_addr = ucode_array_start_addr +
3186 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3187 }
3188 break;
3189 case 2:
3190 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3191
3192 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3193 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3194 err = -EINVAL;
3195 goto out;
3196 }
3197
3198 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3199 err = parse_sos_bin_descriptor(psp,
3200 &sos_hdr_v2_0->psp_fw_bin[fw_index],
3201 sos_hdr_v2_0);
3202 if (err)
3203 goto out;
3204 }
3205 break;
3206 default:
3207 dev_err(adev->dev,
3208 "unsupported psp sos firmware\n");
3209 err = -EINVAL;
3210 goto out;
3211 }
3212
3213 return 0;
3214 out:
3215 dev_err(adev->dev,
3216 "failed to init sos firmware\n");
3217 release_firmware(adev->psp.sos_fw);
3218 adev->psp.sos_fw = NULL;
3219
3220 return err;
3221 }
3222
parse_ta_bin_descriptor(struct psp_context * psp,const struct psp_fw_bin_desc * desc,const struct ta_firmware_header_v2_0 * ta_hdr)3223 static int parse_ta_bin_descriptor(struct psp_context *psp,
3224 const struct psp_fw_bin_desc *desc,
3225 const struct ta_firmware_header_v2_0 *ta_hdr)
3226 {
3227 uint8_t *ucode_start_addr = NULL;
3228
3229 if (!psp || !desc || !ta_hdr)
3230 return -EINVAL;
3231
3232 ucode_start_addr = (uint8_t *)ta_hdr +
3233 le32_to_cpu(desc->offset_bytes) +
3234 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3235
3236 switch (desc->fw_type) {
3237 case TA_FW_TYPE_PSP_ASD:
3238 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3239 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version);
3240 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3241 psp->asd_context.bin_desc.start_addr = ucode_start_addr;
3242 break;
3243 case TA_FW_TYPE_PSP_XGMI:
3244 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3245 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3246 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr;
3247 break;
3248 case TA_FW_TYPE_PSP_RAS:
3249 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3250 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3251 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr;
3252 break;
3253 case TA_FW_TYPE_PSP_HDCP:
3254 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3255 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3256 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr;
3257 break;
3258 case TA_FW_TYPE_PSP_DTM:
3259 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3260 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3261 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr;
3262 break;
3263 case TA_FW_TYPE_PSP_RAP:
3264 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3265 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3266 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr;
3267 break;
3268 case TA_FW_TYPE_PSP_SECUREDISPLAY:
3269 psp->securedisplay_context.context.bin_desc.fw_version =
3270 le32_to_cpu(desc->fw_version);
3271 psp->securedisplay_context.context.bin_desc.size_bytes =
3272 le32_to_cpu(desc->size_bytes);
3273 psp->securedisplay_context.context.bin_desc.start_addr =
3274 ucode_start_addr;
3275 break;
3276 default:
3277 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3278 break;
3279 }
3280
3281 return 0;
3282 }
3283
psp_init_ta_microcode(struct psp_context * psp,const char * chip_name)3284 int psp_init_ta_microcode(struct psp_context *psp,
3285 const char *chip_name)
3286 {
3287 struct amdgpu_device *adev = psp->adev;
3288 char fw_name[PSP_FW_NAME_LEN];
3289 const struct ta_firmware_header_v2_0 *ta_hdr;
3290 int err = 0;
3291 int ta_index = 0;
3292
3293 if (!chip_name) {
3294 dev_err(adev->dev, "invalid chip name for ta microcode\n");
3295 return -EINVAL;
3296 }
3297
3298 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3299 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
3300 if (err)
3301 goto out;
3302
3303 err = amdgpu_ucode_validate(adev->psp.ta_fw);
3304 if (err)
3305 goto out;
3306
3307 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3308
3309 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
3310 dev_err(adev->dev, "unsupported TA header version\n");
3311 err = -EINVAL;
3312 goto out;
3313 }
3314
3315 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3316 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3317 err = -EINVAL;
3318 goto out;
3319 }
3320
3321 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3322 err = parse_ta_bin_descriptor(psp,
3323 &ta_hdr->ta_fw_bin[ta_index],
3324 ta_hdr);
3325 if (err)
3326 goto out;
3327 }
3328
3329 return 0;
3330 out:
3331 dev_err(adev->dev, "fail to initialize ta microcode\n");
3332 release_firmware(adev->psp.ta_fw);
3333 adev->psp.ta_fw = NULL;
3334 return err;
3335 }
3336
psp_init_cap_microcode(struct psp_context * psp,const char * chip_name)3337 int psp_init_cap_microcode(struct psp_context *psp,
3338 const char *chip_name)
3339 {
3340 struct amdgpu_device *adev = psp->adev;
3341 char fw_name[PSP_FW_NAME_LEN];
3342 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3343 struct amdgpu_firmware_info *info = NULL;
3344 int err = 0;
3345
3346 if (!chip_name) {
3347 dev_err(adev->dev, "invalid chip name for cap microcode\n");
3348 return -EINVAL;
3349 }
3350
3351 if (!amdgpu_sriov_vf(adev)) {
3352 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3353 return -EINVAL;
3354 }
3355
3356 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3357 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev);
3358 if (err) {
3359 dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3360 err = 0;
3361 goto out;
3362 }
3363
3364 err = amdgpu_ucode_validate(adev->psp.cap_fw);
3365 if (err) {
3366 dev_err(adev->dev, "fail to initialize cap microcode\n");
3367 goto out;
3368 }
3369
3370 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3371 info->ucode_id = AMDGPU_UCODE_ID_CAP;
3372 info->fw = adev->psp.cap_fw;
3373 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3374 adev->psp.cap_fw->data;
3375 adev->firmware.fw_size += ALIGN(
3376 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3377 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3378 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3379 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3380
3381 return 0;
3382
3383 out:
3384 release_firmware(adev->psp.cap_fw);
3385 adev->psp.cap_fw = NULL;
3386 return err;
3387 }
3388
psp_set_clockgating_state(void * handle,enum amd_clockgating_state state)3389 static int psp_set_clockgating_state(void *handle,
3390 enum amd_clockgating_state state)
3391 {
3392 return 0;
3393 }
3394
psp_set_powergating_state(void * handle,enum amd_powergating_state state)3395 static int psp_set_powergating_state(void *handle,
3396 enum amd_powergating_state state)
3397 {
3398 return 0;
3399 }
3400
psp_usbc_pd_fw_sysfs_read(struct device * dev,struct device_attribute * attr,char * buf)3401 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3402 struct device_attribute *attr,
3403 char *buf)
3404 {
3405 struct drm_device *ddev = dev_get_drvdata(dev);
3406 struct amdgpu_device *adev = drm_to_adev(ddev);
3407 uint32_t fw_ver;
3408 int ret;
3409
3410 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3411 DRM_INFO("PSP block is not ready yet.");
3412 return -EBUSY;
3413 }
3414
3415 mutex_lock(&adev->psp.mutex);
3416 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3417 mutex_unlock(&adev->psp.mutex);
3418
3419 if (ret) {
3420 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3421 return ret;
3422 }
3423
3424 return sysfs_emit(buf, "%x\n", fw_ver);
3425 }
3426
psp_usbc_pd_fw_sysfs_write(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3427 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3428 struct device_attribute *attr,
3429 const char *buf,
3430 size_t count)
3431 {
3432 struct drm_device *ddev = dev_get_drvdata(dev);
3433 struct amdgpu_device *adev = drm_to_adev(ddev);
3434 int ret, idx;
3435 char fw_name[100];
3436 const struct firmware *usbc_pd_fw;
3437 struct amdgpu_bo *fw_buf_bo = NULL;
3438 uint64_t fw_pri_mc_addr;
3439 void *fw_pri_cpu_addr;
3440
3441 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3442 DRM_INFO("PSP block is not ready yet.");
3443 return -EBUSY;
3444 }
3445
3446 if (!drm_dev_enter(ddev, &idx))
3447 return -ENODEV;
3448
3449 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3450 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3451 if (ret)
3452 goto fail;
3453
3454 /* LFB address which is aligned to 1MB boundary per PSP request */
3455 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3456 AMDGPU_GEM_DOMAIN_VRAM,
3457 &fw_buf_bo,
3458 &fw_pri_mc_addr,
3459 &fw_pri_cpu_addr);
3460 if (ret)
3461 goto rel_buf;
3462
3463 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3464
3465 mutex_lock(&adev->psp.mutex);
3466 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3467 mutex_unlock(&adev->psp.mutex);
3468
3469 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3470
3471 rel_buf:
3472 release_firmware(usbc_pd_fw);
3473 fail:
3474 if (ret) {
3475 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3476 count = ret;
3477 }
3478
3479 drm_dev_exit(idx);
3480 return count;
3481 }
3482
psp_copy_fw(struct psp_context * psp,uint8_t * start_addr,uint32_t bin_size)3483 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3484 {
3485 int idx;
3486
3487 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3488 return;
3489
3490 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3491 memcpy(psp->fw_pri_buf, start_addr, bin_size);
3492
3493 drm_dev_exit(idx);
3494 }
3495
3496 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3497 psp_usbc_pd_fw_sysfs_read,
3498 psp_usbc_pd_fw_sysfs_write);
3499
is_psp_fw_valid(struct psp_bin_desc bin)3500 int is_psp_fw_valid(struct psp_bin_desc bin)
3501 {
3502 return bin.size_bytes;
3503 }
3504
amdgpu_psp_vbflash_write(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buffer,loff_t pos,size_t count)3505 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3506 struct bin_attribute *bin_attr,
3507 char *buffer, loff_t pos, size_t count)
3508 {
3509 struct device *dev = kobj_to_dev(kobj);
3510 struct drm_device *ddev = dev_get_drvdata(dev);
3511 struct amdgpu_device *adev = drm_to_adev(ddev);
3512
3513 adev->psp.vbflash_done = false;
3514
3515 /* Safeguard against memory drain */
3516 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3517 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3518 kvfree(adev->psp.vbflash_tmp_buf);
3519 adev->psp.vbflash_tmp_buf = NULL;
3520 adev->psp.vbflash_image_size = 0;
3521 return -ENOMEM;
3522 }
3523
3524 /* TODO Just allocate max for now and optimize to realloc later if needed */
3525 if (!adev->psp.vbflash_tmp_buf) {
3526 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3527 if (!adev->psp.vbflash_tmp_buf)
3528 return -ENOMEM;
3529 }
3530
3531 mutex_lock(&adev->psp.mutex);
3532 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3533 adev->psp.vbflash_image_size += count;
3534 mutex_unlock(&adev->psp.mutex);
3535
3536 dev_info(adev->dev, "VBIOS flash write PSP done");
3537
3538 return count;
3539 }
3540
amdgpu_psp_vbflash_read(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buffer,loff_t pos,size_t count)3541 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3542 struct bin_attribute *bin_attr, char *buffer,
3543 loff_t pos, size_t count)
3544 {
3545 struct device *dev = kobj_to_dev(kobj);
3546 struct drm_device *ddev = dev_get_drvdata(dev);
3547 struct amdgpu_device *adev = drm_to_adev(ddev);
3548 struct amdgpu_bo *fw_buf_bo = NULL;
3549 uint64_t fw_pri_mc_addr;
3550 void *fw_pri_cpu_addr;
3551 int ret;
3552
3553 dev_info(adev->dev, "VBIOS flash to PSP started");
3554
3555 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3556 AMDGPU_GPU_PAGE_SIZE,
3557 AMDGPU_GEM_DOMAIN_VRAM,
3558 &fw_buf_bo,
3559 &fw_pri_mc_addr,
3560 &fw_pri_cpu_addr);
3561 if (ret)
3562 goto rel_buf;
3563
3564 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3565
3566 mutex_lock(&adev->psp.mutex);
3567 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3568 mutex_unlock(&adev->psp.mutex);
3569
3570 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3571
3572 rel_buf:
3573 kvfree(adev->psp.vbflash_tmp_buf);
3574 adev->psp.vbflash_tmp_buf = NULL;
3575 adev->psp.vbflash_image_size = 0;
3576
3577 if (ret) {
3578 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret);
3579 return ret;
3580 }
3581
3582 dev_info(adev->dev, "VBIOS flash to PSP done");
3583 return 0;
3584 }
3585
amdgpu_psp_vbflash_status(struct device * dev,struct device_attribute * attr,char * buf)3586 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3587 struct device_attribute *attr,
3588 char *buf)
3589 {
3590 struct drm_device *ddev = dev_get_drvdata(dev);
3591 struct amdgpu_device *adev = drm_to_adev(ddev);
3592 uint32_t vbflash_status;
3593
3594 vbflash_status = psp_vbflash_status(&adev->psp);
3595 if (!adev->psp.vbflash_done)
3596 vbflash_status = 0;
3597 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3598 vbflash_status = 1;
3599
3600 return sysfs_emit(buf, "0x%x\n", vbflash_status);
3601 }
3602
3603 static const struct bin_attribute psp_vbflash_bin_attr = {
3604 .attr = {.name = "psp_vbflash", .mode = 0664},
3605 .size = 0,
3606 .write = amdgpu_psp_vbflash_write,
3607 .read = amdgpu_psp_vbflash_read,
3608 };
3609
3610 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL);
3611
amdgpu_psp_sysfs_init(struct amdgpu_device * adev)3612 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
3613 {
3614 int ret = 0;
3615 struct psp_context *psp = &adev->psp;
3616
3617 if (amdgpu_sriov_vf(adev))
3618 return -EINVAL;
3619
3620 switch (adev->ip_versions[MP0_HWIP][0]) {
3621 case IP_VERSION(13, 0, 0):
3622 case IP_VERSION(13, 0, 7):
3623 if (!psp->adev) {
3624 psp->adev = adev;
3625 psp_v13_0_set_psp_funcs(psp);
3626 }
3627 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3628 if (ret)
3629 dev_err(adev->dev, "Failed to create device file psp_vbflash");
3630 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status);
3631 if (ret)
3632 dev_err(adev->dev, "Failed to create device file psp_vbflash_status");
3633 return ret;
3634 default:
3635 return 0;
3636 }
3637 }
3638
3639 const struct amd_ip_funcs psp_ip_funcs = {
3640 .name = "psp",
3641 .early_init = psp_early_init,
3642 .late_init = NULL,
3643 .sw_init = psp_sw_init,
3644 .sw_fini = psp_sw_fini,
3645 .hw_init = psp_hw_init,
3646 .hw_fini = psp_hw_fini,
3647 .suspend = psp_suspend,
3648 .resume = psp_resume,
3649 .is_idle = NULL,
3650 .check_soft_reset = NULL,
3651 .wait_for_idle = NULL,
3652 .soft_reset = NULL,
3653 .set_clockgating_state = psp_set_clockgating_state,
3654 .set_powergating_state = psp_set_powergating_state,
3655 };
3656
psp_sysfs_init(struct amdgpu_device * adev)3657 static int psp_sysfs_init(struct amdgpu_device *adev)
3658 {
3659 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3660
3661 if (ret)
3662 DRM_ERROR("Failed to create USBC PD FW control file!");
3663
3664 return ret;
3665 }
3666
amdgpu_psp_sysfs_fini(struct amdgpu_device * adev)3667 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
3668 {
3669 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3670 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status);
3671 }
3672
psp_sysfs_fini(struct amdgpu_device * adev)3673 static void psp_sysfs_fini(struct amdgpu_device *adev)
3674 {
3675 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3676 }
3677
3678 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3679 {
3680 .type = AMD_IP_BLOCK_TYPE_PSP,
3681 .major = 3,
3682 .minor = 1,
3683 .rev = 0,
3684 .funcs = &psp_ip_funcs,
3685 };
3686
3687 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3688 {
3689 .type = AMD_IP_BLOCK_TYPE_PSP,
3690 .major = 10,
3691 .minor = 0,
3692 .rev = 0,
3693 .funcs = &psp_ip_funcs,
3694 };
3695
3696 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3697 {
3698 .type = AMD_IP_BLOCK_TYPE_PSP,
3699 .major = 11,
3700 .minor = 0,
3701 .rev = 0,
3702 .funcs = &psp_ip_funcs,
3703 };
3704
3705 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3706 .type = AMD_IP_BLOCK_TYPE_PSP,
3707 .major = 11,
3708 .minor = 0,
3709 .rev = 8,
3710 .funcs = &psp_ip_funcs,
3711 };
3712
3713 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3714 {
3715 .type = AMD_IP_BLOCK_TYPE_PSP,
3716 .major = 12,
3717 .minor = 0,
3718 .rev = 0,
3719 .funcs = &psp_ip_funcs,
3720 };
3721
3722 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3723 .type = AMD_IP_BLOCK_TYPE_PSP,
3724 .major = 13,
3725 .minor = 0,
3726 .rev = 0,
3727 .funcs = &psp_ip_funcs,
3728 };
3729
3730 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3731 .type = AMD_IP_BLOCK_TYPE_PSP,
3732 .major = 13,
3733 .minor = 0,
3734 .rev = 4,
3735 .funcs = &psp_ip_funcs,
3736 };
3737