1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright © 2006-2011 Intel Corporation
4 *
5 * Authors:
6 * Eric Anholt <eric@anholt.net>
7 */
8
9 #include <linux/delay.h>
10 #include <linux/i2c.h>
11
12 #include <drm/drm_modeset_helper.h>
13 #include <drm/drm_modeset_helper_vtables.h>
14
15 #include "framebuffer.h"
16 #include "gem.h"
17 #include "gma_display.h"
18 #include "power.h"
19 #include "psb_drv.h"
20 #include "psb_intel_drv.h"
21 #include "psb_intel_reg.h"
22
23 #define INTEL_LIMIT_I9XX_SDVO_DAC 0
24 #define INTEL_LIMIT_I9XX_LVDS 1
25
26 static const struct gma_limit_t psb_intel_limits[] = {
27 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
28 .dot = {.min = 20000, .max = 400000},
29 .vco = {.min = 1400000, .max = 2800000},
30 .n = {.min = 1, .max = 6},
31 .m = {.min = 70, .max = 120},
32 .m1 = {.min = 8, .max = 18},
33 .m2 = {.min = 3, .max = 7},
34 .p = {.min = 5, .max = 80},
35 .p1 = {.min = 1, .max = 8},
36 .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5},
37 .find_pll = gma_find_best_pll,
38 },
39 { /* INTEL_LIMIT_I9XX_LVDS */
40 .dot = {.min = 20000, .max = 400000},
41 .vco = {.min = 1400000, .max = 2800000},
42 .n = {.min = 1, .max = 6},
43 .m = {.min = 70, .max = 120},
44 .m1 = {.min = 8, .max = 18},
45 .m2 = {.min = 3, .max = 7},
46 .p = {.min = 7, .max = 98},
47 .p1 = {.min = 1, .max = 8},
48 /* The single-channel range is 25-112Mhz, and dual-channel
49 * is 80-224Mhz. Prefer single channel as much as possible.
50 */
51 .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7},
52 .find_pll = gma_find_best_pll,
53 },
54 };
55
psb_intel_limit(struct drm_crtc * crtc,int refclk)56 static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc,
57 int refclk)
58 {
59 const struct gma_limit_t *limit;
60
61 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
62 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
63 else
64 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
65 return limit;
66 }
67
psb_intel_clock(int refclk,struct gma_clock_t * clock)68 static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
69 {
70 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
71 clock->p = clock->p1 * clock->p2;
72 clock->vco = refclk * clock->m / (clock->n + 2);
73 clock->dot = clock->vco / clock->p;
74 }
75
76 /*
77 * Return the pipe currently connected to the panel fitter,
78 * or -1 if the panel fitter is not present or not in use
79 */
psb_intel_panel_fitter_pipe(struct drm_device * dev)80 static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
81 {
82 u32 pfit_control;
83
84 pfit_control = REG_READ(PFIT_CONTROL);
85
86 /* See if the panel fitter is in use */
87 if ((pfit_control & PFIT_ENABLE) == 0)
88 return -1;
89 /* Must be on PIPE 1 for PSB */
90 return 1;
91 }
92
psb_intel_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * old_fb)93 static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
94 struct drm_display_mode *mode,
95 struct drm_display_mode *adjusted_mode,
96 int x, int y,
97 struct drm_framebuffer *old_fb)
98 {
99 struct drm_device *dev = crtc->dev;
100 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
101 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
102 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
103 int pipe = gma_crtc->pipe;
104 const struct psb_offset *map = &dev_priv->regmap[pipe];
105 int refclk;
106 struct gma_clock_t clock;
107 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
108 bool ok, is_sdvo = false;
109 bool is_lvds = false, is_tv = false;
110 struct drm_connector_list_iter conn_iter;
111 struct drm_connector *connector;
112 const struct gma_limit_t *limit;
113
114 /* No scan out no play */
115 if (crtc->primary->fb == NULL) {
116 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
117 return 0;
118 }
119
120 drm_connector_list_iter_begin(dev, &conn_iter);
121 drm_for_each_connector_iter(connector, &conn_iter) {
122 struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
123
124 if (!connector->encoder
125 || connector->encoder->crtc != crtc)
126 continue;
127
128 switch (gma_encoder->type) {
129 case INTEL_OUTPUT_LVDS:
130 is_lvds = true;
131 break;
132 case INTEL_OUTPUT_SDVO:
133 is_sdvo = true;
134 break;
135 case INTEL_OUTPUT_TVOUT:
136 is_tv = true;
137 break;
138 }
139
140 break;
141 }
142 drm_connector_list_iter_end(&conn_iter);
143
144 refclk = 96000;
145
146 limit = gma_crtc->clock_funcs->limit(crtc, refclk);
147
148 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
149 &clock);
150 if (!ok) {
151 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
152 adjusted_mode->clock, clock.dot);
153 return 0;
154 }
155
156 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
157
158 dpll = DPLL_VGA_MODE_DIS;
159 if (is_lvds) {
160 dpll |= DPLLB_MODE_LVDS;
161 dpll |= DPLL_DVO_HIGH_SPEED;
162 } else
163 dpll |= DPLLB_MODE_DAC_SERIAL;
164 if (is_sdvo) {
165 int sdvo_pixel_multiply =
166 adjusted_mode->clock / mode->clock;
167 dpll |= DPLL_DVO_HIGH_SPEED;
168 dpll |=
169 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
170 }
171
172 /* compute bitmask from p1 value */
173 dpll |= (1 << (clock.p1 - 1)) << 16;
174 switch (clock.p2) {
175 case 5:
176 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
177 break;
178 case 7:
179 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
180 break;
181 case 10:
182 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
183 break;
184 case 14:
185 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
186 break;
187 }
188
189 if (is_tv) {
190 /* XXX: just matching BIOS for now */
191 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
192 dpll |= 3;
193 }
194 dpll |= PLL_REF_INPUT_DREFCLK;
195
196 /* setup pipeconf */
197 pipeconf = REG_READ(map->conf);
198
199 /* Set up the display plane register */
200 dspcntr = DISPPLANE_GAMMA_ENABLE;
201
202 if (pipe == 0)
203 dspcntr |= DISPPLANE_SEL_PIPE_A;
204 else
205 dspcntr |= DISPPLANE_SEL_PIPE_B;
206
207 dspcntr |= DISPLAY_PLANE_ENABLE;
208 pipeconf |= PIPEACONF_ENABLE;
209 dpll |= DPLL_VCO_ENABLE;
210
211
212 /* Disable the panel fitter if it was on our pipe */
213 if (psb_intel_panel_fitter_pipe(dev) == pipe)
214 REG_WRITE(PFIT_CONTROL, 0);
215
216 drm_mode_debug_printmodeline(mode);
217
218 if (dpll & DPLL_VCO_ENABLE) {
219 REG_WRITE(map->fp0, fp);
220 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
221 REG_READ(map->dpll);
222 udelay(150);
223 }
224
225 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
226 * This is an exception to the general rule that mode_set doesn't turn
227 * things on.
228 */
229 if (is_lvds) {
230 u32 lvds = REG_READ(LVDS);
231
232 lvds &= ~LVDS_PIPEB_SELECT;
233 if (pipe == 1)
234 lvds |= LVDS_PIPEB_SELECT;
235
236 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
237 /* Set the B0-B3 data pairs corresponding to
238 * whether we're going to
239 * set the DPLLs for dual-channel mode or not.
240 */
241 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
242 if (clock.p2 == 7)
243 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
244
245 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
246 * appropriately here, but we need to look more
247 * thoroughly into how panels behave in the two modes.
248 */
249
250 REG_WRITE(LVDS, lvds);
251 REG_READ(LVDS);
252 }
253
254 REG_WRITE(map->fp0, fp);
255 REG_WRITE(map->dpll, dpll);
256 REG_READ(map->dpll);
257 /* Wait for the clocks to stabilize. */
258 udelay(150);
259
260 /* write it again -- the BIOS does, after all */
261 REG_WRITE(map->dpll, dpll);
262
263 REG_READ(map->dpll);
264 /* Wait for the clocks to stabilize. */
265 udelay(150);
266
267 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
268 ((adjusted_mode->crtc_htotal - 1) << 16));
269 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
270 ((adjusted_mode->crtc_hblank_end - 1) << 16));
271 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
272 ((adjusted_mode->crtc_hsync_end - 1) << 16));
273 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
274 ((adjusted_mode->crtc_vtotal - 1) << 16));
275 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
276 ((adjusted_mode->crtc_vblank_end - 1) << 16));
277 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
278 ((adjusted_mode->crtc_vsync_end - 1) << 16));
279 /* pipesrc and dspsize control the size that is scaled from,
280 * which should always be the user's requested size.
281 */
282 REG_WRITE(map->size,
283 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
284 REG_WRITE(map->pos, 0);
285 REG_WRITE(map->src,
286 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
287 REG_WRITE(map->conf, pipeconf);
288 REG_READ(map->conf);
289
290 gma_wait_for_vblank(dev);
291
292 REG_WRITE(map->cntr, dspcntr);
293
294 /* Flush the plane changes */
295 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
296
297 gma_wait_for_vblank(dev);
298
299 return 0;
300 }
301
302 /* Returns the clock of the currently programmed mode of the given pipe. */
psb_intel_crtc_clock_get(struct drm_device * dev,struct drm_crtc * crtc)303 static int psb_intel_crtc_clock_get(struct drm_device *dev,
304 struct drm_crtc *crtc)
305 {
306 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
307 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
308 int pipe = gma_crtc->pipe;
309 const struct psb_offset *map = &dev_priv->regmap[pipe];
310 u32 dpll;
311 u32 fp;
312 struct gma_clock_t clock;
313 bool is_lvds;
314 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
315
316 if (gma_power_begin(dev, false)) {
317 dpll = REG_READ(map->dpll);
318 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
319 fp = REG_READ(map->fp0);
320 else
321 fp = REG_READ(map->fp1);
322 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
323 gma_power_end(dev);
324 } else {
325 dpll = p->dpll;
326
327 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
328 fp = p->fp0;
329 else
330 fp = p->fp1;
331
332 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
333 LVDS_PORT_EN);
334 }
335
336 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
337 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
338 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
339
340 if (is_lvds) {
341 clock.p1 =
342 ffs((dpll &
343 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
344 DPLL_FPA01_P1_POST_DIV_SHIFT);
345 clock.p2 = 14;
346
347 if ((dpll & PLL_REF_INPUT_MASK) ==
348 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
349 /* XXX: might not be 66MHz */
350 psb_intel_clock(66000, &clock);
351 } else
352 psb_intel_clock(48000, &clock);
353 } else {
354 if (dpll & PLL_P1_DIVIDE_BY_TWO)
355 clock.p1 = 2;
356 else {
357 clock.p1 =
358 ((dpll &
359 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
360 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
361 }
362 if (dpll & PLL_P2_DIVIDE_BY_4)
363 clock.p2 = 4;
364 else
365 clock.p2 = 2;
366
367 psb_intel_clock(48000, &clock);
368 }
369
370 /* XXX: It would be nice to validate the clocks, but we can't reuse
371 * i830PllIsValid() because it relies on the xf86_config connector
372 * configuration being accurate, which it isn't necessarily.
373 */
374
375 return clock.dot;
376 }
377
378 /** Returns the currently programmed mode of the given pipe. */
psb_intel_crtc_mode_get(struct drm_device * dev,struct drm_crtc * crtc)379 struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
380 struct drm_crtc *crtc)
381 {
382 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
383 int pipe = gma_crtc->pipe;
384 struct drm_display_mode *mode;
385 int htot;
386 int hsync;
387 int vtot;
388 int vsync;
389 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
390 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
391 const struct psb_offset *map = &dev_priv->regmap[pipe];
392
393 if (gma_power_begin(dev, false)) {
394 htot = REG_READ(map->htotal);
395 hsync = REG_READ(map->hsync);
396 vtot = REG_READ(map->vtotal);
397 vsync = REG_READ(map->vsync);
398 gma_power_end(dev);
399 } else {
400 htot = p->htotal;
401 hsync = p->hsync;
402 vtot = p->vtotal;
403 vsync = p->vsync;
404 }
405
406 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
407 if (!mode)
408 return NULL;
409
410 mode->clock = psb_intel_crtc_clock_get(dev, crtc);
411 mode->hdisplay = (htot & 0xffff) + 1;
412 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
413 mode->hsync_start = (hsync & 0xffff) + 1;
414 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
415 mode->vdisplay = (vtot & 0xffff) + 1;
416 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
417 mode->vsync_start = (vsync & 0xffff) + 1;
418 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
419
420 drm_mode_set_name(mode);
421 drm_mode_set_crtcinfo(mode, 0);
422
423 return mode;
424 }
425
426 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
427 .dpms = gma_crtc_dpms,
428 .mode_set = psb_intel_crtc_mode_set,
429 .mode_set_base = gma_pipe_set_base,
430 .prepare = gma_crtc_prepare,
431 .commit = gma_crtc_commit,
432 .disable = gma_crtc_disable,
433 };
434
435 const struct gma_clock_funcs psb_clock_funcs = {
436 .clock = psb_intel_clock,
437 .limit = psb_intel_limit,
438 .pll_is_valid = gma_pll_is_valid,
439 };
440
441 /*
442 * Set the default value of cursor control and base register
443 * to zero. This is a workaround for h/w defect on Oaktrail
444 */
psb_intel_cursor_init(struct drm_device * dev,struct gma_crtc * gma_crtc)445 static void psb_intel_cursor_init(struct drm_device *dev,
446 struct gma_crtc *gma_crtc)
447 {
448 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
449 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
450 u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
451 struct psb_gem_object *cursor_pobj;
452
453 if (dev_priv->ops->cursor_needs_phys) {
454 /* Allocate 4 pages of stolen mem for a hardware cursor. That
455 * is enough for the 64 x 64 ARGB cursors we support.
456 */
457 cursor_pobj = psb_gem_create(dev, 4 * PAGE_SIZE, "cursor", true, PAGE_SIZE);
458 if (IS_ERR(cursor_pobj)) {
459 gma_crtc->cursor_pobj = NULL;
460 goto out;
461 }
462 gma_crtc->cursor_pobj = cursor_pobj;
463 gma_crtc->cursor_addr = dev_priv->stolen_base + cursor_pobj->offset;
464 } else {
465 gma_crtc->cursor_pobj = NULL;
466 }
467
468 out:
469 REG_WRITE(control[gma_crtc->pipe], 0);
470 REG_WRITE(base[gma_crtc->pipe], 0);
471 }
472
psb_intel_crtc_init(struct drm_device * dev,int pipe,struct psb_intel_mode_device * mode_dev)473 void psb_intel_crtc_init(struct drm_device *dev, int pipe,
474 struct psb_intel_mode_device *mode_dev)
475 {
476 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
477 struct gma_crtc *gma_crtc;
478 int i;
479
480 /* We allocate a extra array of drm_connector pointers
481 * for fbdev after the crtc */
482 gma_crtc = kzalloc(sizeof(struct gma_crtc) +
483 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
484 GFP_KERNEL);
485 if (gma_crtc == NULL)
486 return;
487
488 gma_crtc->crtc_state =
489 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
490 if (!gma_crtc->crtc_state) {
491 dev_err(dev->dev, "Crtc state error: No memory\n");
492 kfree(gma_crtc);
493 return;
494 }
495
496 drm_crtc_init(dev, &gma_crtc->base, &gma_crtc_funcs);
497
498 /* Set the CRTC clock functions from chip specific data */
499 gma_crtc->clock_funcs = dev_priv->ops->clock_funcs;
500
501 drm_mode_crtc_set_gamma_size(&gma_crtc->base, 256);
502 gma_crtc->pipe = pipe;
503 gma_crtc->plane = pipe;
504
505 for (i = 0; i < 256; i++)
506 gma_crtc->lut_adj[i] = 0;
507
508 gma_crtc->mode_dev = mode_dev;
509 gma_crtc->cursor_addr = 0;
510
511 drm_crtc_helper_add(&gma_crtc->base,
512 dev_priv->ops->crtc_helper);
513
514 /* Setup the array of drm_connector pointer array */
515 gma_crtc->mode_set.crtc = &gma_crtc->base;
516 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
517 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != NULL);
518 dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = &gma_crtc->base;
519 dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = &gma_crtc->base;
520 gma_crtc->mode_set.connectors = (struct drm_connector **)(gma_crtc + 1);
521 gma_crtc->mode_set.num_connectors = 0;
522 psb_intel_cursor_init(dev, gma_crtc);
523
524 /* Set to true so that the pipe is forced off on initial config. */
525 gma_crtc->active = true;
526 }
527
psb_intel_get_crtc_from_pipe(struct drm_device * dev,int pipe)528 struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
529 {
530 struct drm_crtc *crtc;
531
532 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
533 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
534
535 if (gma_crtc->pipe == pipe)
536 return crtc;
537 }
538 return NULL;
539 }
540
gma_connector_clones(struct drm_device * dev,int type_mask)541 int gma_connector_clones(struct drm_device *dev, int type_mask)
542 {
543 struct drm_connector_list_iter conn_iter;
544 struct drm_connector *connector;
545 int index_mask = 0;
546 int entry = 0;
547
548 drm_connector_list_iter_begin(dev, &conn_iter);
549 drm_for_each_connector_iter(connector, &conn_iter) {
550 struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
551 if (type_mask & (1 << gma_encoder->type))
552 index_mask |= (1 << entry);
553 entry++;
554 }
555 drm_connector_list_iter_end(&conn_iter);
556
557 return index_mask;
558 }
559