1 /**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
19 * develop this driver.
20 *
21 **************************************************************************/
22 /*
23 */
24
25 #include <drm/drmP.h>
26 #include "psb_drv.h"
27 #include "psb_reg.h"
28 #include "psb_intel_reg.h"
29 #include "power.h"
30 #include "psb_irq.h"
31 #include "mdfld_output.h"
32
33 /*
34 * inline functions
35 */
36
37 static inline u32
psb_pipestat(int pipe)38 psb_pipestat(int pipe)
39 {
40 if (pipe == 0)
41 return PIPEASTAT;
42 if (pipe == 1)
43 return PIPEBSTAT;
44 if (pipe == 2)
45 return PIPECSTAT;
46 BUG();
47 }
48
49 static inline u32
mid_pipe_event(int pipe)50 mid_pipe_event(int pipe)
51 {
52 if (pipe == 0)
53 return _PSB_PIPEA_EVENT_FLAG;
54 if (pipe == 1)
55 return _MDFLD_PIPEB_EVENT_FLAG;
56 if (pipe == 2)
57 return _MDFLD_PIPEC_EVENT_FLAG;
58 BUG();
59 }
60
61 static inline u32
mid_pipe_vsync(int pipe)62 mid_pipe_vsync(int pipe)
63 {
64 if (pipe == 0)
65 return _PSB_VSYNC_PIPEA_FLAG;
66 if (pipe == 1)
67 return _PSB_VSYNC_PIPEB_FLAG;
68 if (pipe == 2)
69 return _MDFLD_PIPEC_VBLANK_FLAG;
70 BUG();
71 }
72
73 static inline u32
mid_pipeconf(int pipe)74 mid_pipeconf(int pipe)
75 {
76 if (pipe == 0)
77 return PIPEACONF;
78 if (pipe == 1)
79 return PIPEBCONF;
80 if (pipe == 2)
81 return PIPECCONF;
82 BUG();
83 }
84
85 void
psb_enable_pipestat(struct drm_psb_private * dev_priv,int pipe,u32 mask)86 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
87 {
88 if ((dev_priv->pipestat[pipe] & mask) != mask) {
89 u32 reg = psb_pipestat(pipe);
90 dev_priv->pipestat[pipe] |= mask;
91 /* Enable the interrupt, clear any pending status */
92 if (gma_power_begin(dev_priv->dev, false)) {
93 u32 writeVal = PSB_RVDC32(reg);
94 writeVal |= (mask | (mask >> 16));
95 PSB_WVDC32(writeVal, reg);
96 (void) PSB_RVDC32(reg);
97 gma_power_end(dev_priv->dev);
98 }
99 }
100 }
101
102 void
psb_disable_pipestat(struct drm_psb_private * dev_priv,int pipe,u32 mask)103 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
104 {
105 if ((dev_priv->pipestat[pipe] & mask) != 0) {
106 u32 reg = psb_pipestat(pipe);
107 dev_priv->pipestat[pipe] &= ~mask;
108 if (gma_power_begin(dev_priv->dev, false)) {
109 u32 writeVal = PSB_RVDC32(reg);
110 writeVal &= ~mask;
111 PSB_WVDC32(writeVal, reg);
112 (void) PSB_RVDC32(reg);
113 gma_power_end(dev_priv->dev);
114 }
115 }
116 }
117
mid_enable_pipe_event(struct drm_psb_private * dev_priv,int pipe)118 static void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
119 {
120 if (gma_power_begin(dev_priv->dev, false)) {
121 u32 pipe_event = mid_pipe_event(pipe);
122 dev_priv->vdc_irq_mask |= pipe_event;
123 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
124 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
125 gma_power_end(dev_priv->dev);
126 }
127 }
128
mid_disable_pipe_event(struct drm_psb_private * dev_priv,int pipe)129 static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
130 {
131 if (dev_priv->pipestat[pipe] == 0) {
132 if (gma_power_begin(dev_priv->dev, false)) {
133 u32 pipe_event = mid_pipe_event(pipe);
134 dev_priv->vdc_irq_mask &= ~pipe_event;
135 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
136 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
137 gma_power_end(dev_priv->dev);
138 }
139 }
140 }
141
142 /**
143 * Display controller interrupt handler for pipe event.
144 *
145 */
mid_pipe_event_handler(struct drm_device * dev,int pipe)146 static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
147 {
148 struct drm_psb_private *dev_priv =
149 (struct drm_psb_private *) dev->dev_private;
150
151 uint32_t pipe_stat_val = 0;
152 uint32_t pipe_stat_reg = psb_pipestat(pipe);
153 uint32_t pipe_enable = dev_priv->pipestat[pipe];
154 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
155 uint32_t pipe_clear;
156 uint32_t i = 0;
157
158 spin_lock(&dev_priv->irqmask_lock);
159
160 pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
161 pipe_stat_val &= pipe_enable | pipe_status;
162 pipe_stat_val &= pipe_stat_val >> 16;
163
164 spin_unlock(&dev_priv->irqmask_lock);
165
166 /* Clear the 2nd level interrupt status bits
167 * Sometimes the bits are very sticky so we repeat until they unstick */
168 for (i = 0; i < 0xffff; i++) {
169 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
170 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
171
172 if (pipe_clear == 0)
173 break;
174 }
175
176 if (pipe_clear)
177 dev_err(dev->dev,
178 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
179 __func__, pipe, PSB_RVDC32(pipe_stat_reg));
180
181 if (pipe_stat_val & PIPE_VBLANK_STATUS)
182 drm_handle_vblank(dev, pipe);
183
184 if (pipe_stat_val & PIPE_TE_STATUS)
185 drm_handle_vblank(dev, pipe);
186 }
187
188 /*
189 * Display controller interrupt handler.
190 */
psb_vdc_interrupt(struct drm_device * dev,uint32_t vdc_stat)191 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
192 {
193 if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
194 mid_pipe_event_handler(dev, 0);
195
196 if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
197 mid_pipe_event_handler(dev, 1);
198 }
199
psb_irq_handler(DRM_IRQ_ARGS)200 irqreturn_t psb_irq_handler(DRM_IRQ_ARGS)
201 {
202 struct drm_device *dev = (struct drm_device *) arg;
203 struct drm_psb_private *dev_priv =
204 (struct drm_psb_private *) dev->dev_private;
205
206 uint32_t vdc_stat, dsp_int = 0, sgx_int = 0;
207 int handled = 0;
208
209 spin_lock(&dev_priv->irqmask_lock);
210
211 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
212
213 if (vdc_stat & _PSB_PIPE_EVENT_FLAG)
214 dsp_int = 1;
215
216 /* FIXME: Handle Medfield
217 if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
218 dsp_int = 1;
219 */
220
221 if (vdc_stat & _PSB_IRQ_SGX_FLAG)
222 sgx_int = 1;
223
224 vdc_stat &= dev_priv->vdc_irq_mask;
225 spin_unlock(&dev_priv->irqmask_lock);
226
227 if (dsp_int && gma_power_is_on(dev)) {
228 psb_vdc_interrupt(dev, vdc_stat);
229 handled = 1;
230 }
231
232 if (sgx_int) {
233 /* Not expected - we have it masked, shut it up */
234 u32 s, s2;
235 s = PSB_RSGX32(PSB_CR_EVENT_STATUS);
236 s2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
237 PSB_WSGX32(s, PSB_CR_EVENT_HOST_CLEAR);
238 PSB_WSGX32(s2, PSB_CR_EVENT_HOST_CLEAR2);
239 /* if s & _PSB_CE_TWOD_COMPLETE we have 2D done but
240 we may as well poll even if we add that ! */
241 handled = 1;
242 }
243
244 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
245 (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
246 DRM_READMEMORYBARRIER();
247
248 if (!handled)
249 return IRQ_NONE;
250
251 return IRQ_HANDLED;
252 }
253
psb_irq_preinstall(struct drm_device * dev)254 void psb_irq_preinstall(struct drm_device *dev)
255 {
256 struct drm_psb_private *dev_priv =
257 (struct drm_psb_private *) dev->dev_private;
258 unsigned long irqflags;
259
260 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
261
262 if (gma_power_is_on(dev))
263 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
264 if (dev->vblank_enabled[0])
265 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
266 if (dev->vblank_enabled[1])
267 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
268
269 /* FIXME: Handle Medfield irq mask
270 if (dev->vblank_enabled[1])
271 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
272 if (dev->vblank_enabled[2])
273 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
274 */
275
276 /* This register is safe even if display island is off */
277 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
278 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
279 }
280
psb_irq_postinstall(struct drm_device * dev)281 int psb_irq_postinstall(struct drm_device *dev)
282 {
283 struct drm_psb_private *dev_priv =
284 (struct drm_psb_private *) dev->dev_private;
285 unsigned long irqflags;
286
287 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
288
289 /* This register is safe even if display island is off */
290 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
291 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
292
293 if (dev->vblank_enabled[0])
294 psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
295 else
296 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
297
298 if (dev->vblank_enabled[1])
299 psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
300 else
301 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
302
303 if (dev->vblank_enabled[2])
304 psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
305 else
306 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
307
308 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
309 return 0;
310 }
311
psb_irq_uninstall(struct drm_device * dev)312 void psb_irq_uninstall(struct drm_device *dev)
313 {
314 struct drm_psb_private *dev_priv =
315 (struct drm_psb_private *) dev->dev_private;
316 unsigned long irqflags;
317
318 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
319
320 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
321
322 if (dev->vblank_enabled[0])
323 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
324
325 if (dev->vblank_enabled[1])
326 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
327
328 if (dev->vblank_enabled[2])
329 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
330
331 dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
332 _PSB_IRQ_MSVDX_FLAG |
333 _LNC_IRQ_TOPAZ_FLAG;
334
335 /* These two registers are safe even if display island is off */
336 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
337 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
338
339 wmb();
340
341 /* This register is safe even if display island is off */
342 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
343 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
344 }
345
psb_irq_turn_on_dpst(struct drm_device * dev)346 void psb_irq_turn_on_dpst(struct drm_device *dev)
347 {
348 struct drm_psb_private *dev_priv =
349 (struct drm_psb_private *) dev->dev_private;
350 u32 hist_reg;
351 u32 pwm_reg;
352
353 if (gma_power_begin(dev, false)) {
354 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
355 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
356 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
357 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
358
359 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
360 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
361 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
362 | PWM_PHASEIN_INT_ENABLE,
363 PWM_CONTROL_LOGIC);
364 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
365
366 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
367
368 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
369 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
370 HISTOGRAM_INT_CONTROL);
371 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
372 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
373 PWM_CONTROL_LOGIC);
374
375 gma_power_end(dev);
376 }
377 }
378
psb_irq_enable_dpst(struct drm_device * dev)379 int psb_irq_enable_dpst(struct drm_device *dev)
380 {
381 struct drm_psb_private *dev_priv =
382 (struct drm_psb_private *) dev->dev_private;
383 unsigned long irqflags;
384
385 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
386
387 /* enable DPST */
388 mid_enable_pipe_event(dev_priv, 0);
389 psb_irq_turn_on_dpst(dev);
390
391 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
392 return 0;
393 }
394
psb_irq_turn_off_dpst(struct drm_device * dev)395 void psb_irq_turn_off_dpst(struct drm_device *dev)
396 {
397 struct drm_psb_private *dev_priv =
398 (struct drm_psb_private *) dev->dev_private;
399 u32 hist_reg;
400 u32 pwm_reg;
401
402 if (gma_power_begin(dev, false)) {
403 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
404 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
405
406 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
407
408 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
409 PSB_WVDC32(pwm_reg & !(PWM_PHASEIN_INT_ENABLE),
410 PWM_CONTROL_LOGIC);
411 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
412
413 gma_power_end(dev);
414 }
415 }
416
psb_irq_disable_dpst(struct drm_device * dev)417 int psb_irq_disable_dpst(struct drm_device *dev)
418 {
419 struct drm_psb_private *dev_priv =
420 (struct drm_psb_private *) dev->dev_private;
421 unsigned long irqflags;
422
423 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
424
425 mid_disable_pipe_event(dev_priv, 0);
426 psb_irq_turn_off_dpst(dev);
427
428 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
429
430 return 0;
431 }
432
433 #ifdef PSB_FIXME
psb_vblank_do_wait(struct drm_device * dev,unsigned int * sequence,atomic_t * counter)434 static int psb_vblank_do_wait(struct drm_device *dev,
435 unsigned int *sequence, atomic_t *counter)
436 {
437 unsigned int cur_vblank;
438 int ret = 0;
439 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
440 (((cur_vblank = atomic_read(counter))
441 - *sequence) <= (1 << 23)));
442 *sequence = cur_vblank;
443
444 return ret;
445 }
446 #endif
447
448 /*
449 * It is used to enable VBLANK interrupt
450 */
psb_enable_vblank(struct drm_device * dev,int pipe)451 int psb_enable_vblank(struct drm_device *dev, int pipe)
452 {
453 struct drm_psb_private *dev_priv = dev->dev_private;
454 unsigned long irqflags;
455 uint32_t reg_val = 0;
456 uint32_t pipeconf_reg = mid_pipeconf(pipe);
457
458 /* Medfield is different - we should perhaps extract out vblank
459 and blacklight etc ops */
460 if (IS_MFLD(dev))
461 return mdfld_enable_te(dev, pipe);
462
463 if (gma_power_begin(dev, false)) {
464 reg_val = REG_READ(pipeconf_reg);
465 gma_power_end(dev);
466 }
467
468 if (!(reg_val & PIPEACONF_ENABLE))
469 return -EINVAL;
470
471 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
472
473 if (pipe == 0)
474 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
475 else if (pipe == 1)
476 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
477
478 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
479 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
480 psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
481
482 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
483
484 return 0;
485 }
486
487 /*
488 * It is used to disable VBLANK interrupt
489 */
psb_disable_vblank(struct drm_device * dev,int pipe)490 void psb_disable_vblank(struct drm_device *dev, int pipe)
491 {
492 struct drm_psb_private *dev_priv = dev->dev_private;
493 unsigned long irqflags;
494
495 if (IS_MFLD(dev))
496 mdfld_disable_te(dev, pipe);
497 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
498
499 if (pipe == 0)
500 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
501 else if (pipe == 1)
502 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
503
504 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
505 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
506 psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
507
508 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
509 }
510
511 /*
512 * It is used to enable TE interrupt
513 */
mdfld_enable_te(struct drm_device * dev,int pipe)514 int mdfld_enable_te(struct drm_device *dev, int pipe)
515 {
516 struct drm_psb_private *dev_priv =
517 (struct drm_psb_private *) dev->dev_private;
518 unsigned long irqflags;
519 uint32_t reg_val = 0;
520 uint32_t pipeconf_reg = mid_pipeconf(pipe);
521
522 if (gma_power_begin(dev, false)) {
523 reg_val = REG_READ(pipeconf_reg);
524 gma_power_end(dev);
525 }
526
527 if (!(reg_val & PIPEACONF_ENABLE))
528 return -EINVAL;
529
530 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
531
532 mid_enable_pipe_event(dev_priv, pipe);
533 psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
534
535 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
536
537 return 0;
538 }
539
540 /*
541 * It is used to disable TE interrupt
542 */
mdfld_disable_te(struct drm_device * dev,int pipe)543 void mdfld_disable_te(struct drm_device *dev, int pipe)
544 {
545 struct drm_psb_private *dev_priv =
546 (struct drm_psb_private *) dev->dev_private;
547 unsigned long irqflags;
548
549 if (!dev_priv->dsr_enable)
550 return;
551
552 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
553
554 mid_disable_pipe_event(dev_priv, pipe);
555 psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
556
557 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
558 }
559
560 /* Called from drm generic code, passed a 'crtc', which
561 * we use as a pipe index
562 */
psb_get_vblank_counter(struct drm_device * dev,int pipe)563 u32 psb_get_vblank_counter(struct drm_device *dev, int pipe)
564 {
565 uint32_t high_frame = PIPEAFRAMEHIGH;
566 uint32_t low_frame = PIPEAFRAMEPIXEL;
567 uint32_t pipeconf_reg = PIPEACONF;
568 uint32_t reg_val = 0;
569 uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
570
571 switch (pipe) {
572 case 0:
573 break;
574 case 1:
575 high_frame = PIPEBFRAMEHIGH;
576 low_frame = PIPEBFRAMEPIXEL;
577 pipeconf_reg = PIPEBCONF;
578 break;
579 case 2:
580 high_frame = PIPECFRAMEHIGH;
581 low_frame = PIPECFRAMEPIXEL;
582 pipeconf_reg = PIPECCONF;
583 break;
584 default:
585 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
586 return 0;
587 }
588
589 if (!gma_power_begin(dev, false))
590 return 0;
591
592 reg_val = REG_READ(pipeconf_reg);
593
594 if (!(reg_val & PIPEACONF_ENABLE)) {
595 dev_err(dev->dev, "trying to get vblank count for disabled pipe %d\n",
596 pipe);
597 goto psb_get_vblank_counter_exit;
598 }
599
600 /*
601 * High & low register fields aren't synchronized, so make sure
602 * we get a low value that's stable across two reads of the high
603 * register.
604 */
605 do {
606 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
607 PIPE_FRAME_HIGH_SHIFT);
608 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
609 PIPE_FRAME_LOW_SHIFT);
610 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
611 PIPE_FRAME_HIGH_SHIFT);
612 } while (high1 != high2);
613
614 count = (high1 << 8) | low;
615
616 psb_get_vblank_counter_exit:
617
618 gma_power_end(dev);
619
620 return count;
621 }
622
623