1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright © 2006-2015, Intel Corporation.
4 *
5 * Authors: Ashok Raj <ashok.raj@intel.com>
6 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
7 * David Woodhouse <David.Woodhouse@intel.com>
8 */
9
10 #ifndef _INTEL_IOMMU_H_
11 #define _INTEL_IOMMU_H_
12
13 #include <linux/types.h>
14 #include <linux/iova.h>
15 #include <linux/io.h>
16 #include <linux/idr.h>
17 #include <linux/mmu_notifier.h>
18 #include <linux/list.h>
19 #include <linux/iommu.h>
20 #include <linux/io-64-nonatomic-lo-hi.h>
21 #include <linux/dmar.h>
22 #include <linux/bitfield.h>
23 #include <linux/xarray.h>
24 #include <linux/perf_event.h>
25
26 #include <asm/cacheflush.h>
27 #include <asm/iommu.h>
28
29 /*
30 * VT-d hardware uses 4KiB page size regardless of host page size.
31 */
32 #define VTD_PAGE_SHIFT (12)
33 #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT)
34 #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT)
35 #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
36
37 #define VTD_STRIDE_SHIFT (9)
38 #define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT)
39
40 #define DMA_PTE_READ BIT_ULL(0)
41 #define DMA_PTE_WRITE BIT_ULL(1)
42 #define DMA_PTE_LARGE_PAGE BIT_ULL(7)
43 #define DMA_PTE_SNP BIT_ULL(11)
44
45 #define DMA_FL_PTE_PRESENT BIT_ULL(0)
46 #define DMA_FL_PTE_US BIT_ULL(2)
47 #define DMA_FL_PTE_ACCESS BIT_ULL(5)
48 #define DMA_FL_PTE_DIRTY BIT_ULL(6)
49 #define DMA_FL_PTE_XD BIT_ULL(63)
50
51 #define ADDR_WIDTH_5LEVEL (57)
52 #define ADDR_WIDTH_4LEVEL (48)
53
54 #define CONTEXT_TT_MULTI_LEVEL 0
55 #define CONTEXT_TT_DEV_IOTLB 1
56 #define CONTEXT_TT_PASS_THROUGH 2
57 #define CONTEXT_PASIDE BIT_ULL(3)
58
59 /*
60 * Intel IOMMU register specification per version 1.0 public spec.
61 */
62 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
63 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
64 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
65 #define DMAR_GCMD_REG 0x18 /* Global command register */
66 #define DMAR_GSTS_REG 0x1c /* Global status register */
67 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
68 #define DMAR_CCMD_REG 0x28 /* Context command reg */
69 #define DMAR_FSTS_REG 0x34 /* Fault Status register */
70 #define DMAR_FECTL_REG 0x38 /* Fault control register */
71 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
72 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
73 #define DMAR_FEUADDR_REG 0x44 /* Upper address register */
74 #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
75 #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
76 #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
77 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
78 #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
79 #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
80 #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
81 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
82 #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
83 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
84 #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
85 #define DMAR_IQER_REG 0xb0 /* Invalidation queue error record register */
86 #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
87 #define DMAR_PQH_REG 0xc0 /* Page request queue head register */
88 #define DMAR_PQT_REG 0xc8 /* Page request queue tail register */
89 #define DMAR_PQA_REG 0xd0 /* Page request queue address register */
90 #define DMAR_PRS_REG 0xdc /* Page request status register */
91 #define DMAR_PECTL_REG 0xe0 /* Page request event control register */
92 #define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */
93 #define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
94 #define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */
95 #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability register */
96 #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type register */
97 #define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */
98 #define DMAR_MTRR_FIX16K_80000_REG 0x128
99 #define DMAR_MTRR_FIX16K_A0000_REG 0x130
100 #define DMAR_MTRR_FIX4K_C0000_REG 0x138
101 #define DMAR_MTRR_FIX4K_C8000_REG 0x140
102 #define DMAR_MTRR_FIX4K_D0000_REG 0x148
103 #define DMAR_MTRR_FIX4K_D8000_REG 0x150
104 #define DMAR_MTRR_FIX4K_E0000_REG 0x158
105 #define DMAR_MTRR_FIX4K_E8000_REG 0x160
106 #define DMAR_MTRR_FIX4K_F0000_REG 0x168
107 #define DMAR_MTRR_FIX4K_F8000_REG 0x170
108 #define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */
109 #define DMAR_MTRR_PHYSMASK0_REG 0x188
110 #define DMAR_MTRR_PHYSBASE1_REG 0x190
111 #define DMAR_MTRR_PHYSMASK1_REG 0x198
112 #define DMAR_MTRR_PHYSBASE2_REG 0x1a0
113 #define DMAR_MTRR_PHYSMASK2_REG 0x1a8
114 #define DMAR_MTRR_PHYSBASE3_REG 0x1b0
115 #define DMAR_MTRR_PHYSMASK3_REG 0x1b8
116 #define DMAR_MTRR_PHYSBASE4_REG 0x1c0
117 #define DMAR_MTRR_PHYSMASK4_REG 0x1c8
118 #define DMAR_MTRR_PHYSBASE5_REG 0x1d0
119 #define DMAR_MTRR_PHYSMASK5_REG 0x1d8
120 #define DMAR_MTRR_PHYSBASE6_REG 0x1e0
121 #define DMAR_MTRR_PHYSMASK6_REG 0x1e8
122 #define DMAR_MTRR_PHYSBASE7_REG 0x1f0
123 #define DMAR_MTRR_PHYSMASK7_REG 0x1f8
124 #define DMAR_MTRR_PHYSBASE8_REG 0x200
125 #define DMAR_MTRR_PHYSMASK8_REG 0x208
126 #define DMAR_MTRR_PHYSBASE9_REG 0x210
127 #define DMAR_MTRR_PHYSMASK9_REG 0x218
128 #define DMAR_PERFCAP_REG 0x300
129 #define DMAR_PERFCFGOFF_REG 0x310
130 #define DMAR_PERFOVFOFF_REG 0x318
131 #define DMAR_PERFCNTROFF_REG 0x31c
132 #define DMAR_PERFINTRSTS_REG 0x324
133 #define DMAR_PERFINTRCTL_REG 0x328
134 #define DMAR_PERFEVNTCAP_REG 0x380
135 #define DMAR_ECMD_REG 0x400
136 #define DMAR_ECEO_REG 0x408
137 #define DMAR_ECRSP_REG 0x410
138 #define DMAR_ECCAP_REG 0x430
139 #define DMAR_VCCAP_REG 0xe30 /* Virtual command capability register */
140 #define DMAR_VCMD_REG 0xe00 /* Virtual command register */
141 #define DMAR_VCRSP_REG 0xe10 /* Virtual command response register */
142
143 #define DMAR_IQER_REG_IQEI(reg) FIELD_GET(GENMASK_ULL(3, 0), reg)
144 #define DMAR_IQER_REG_ITESID(reg) FIELD_GET(GENMASK_ULL(47, 32), reg)
145 #define DMAR_IQER_REG_ICESID(reg) FIELD_GET(GENMASK_ULL(63, 48), reg)
146
147 #define OFFSET_STRIDE (9)
148
149 #define dmar_readq(a) readq(a)
150 #define dmar_writeq(a,v) writeq(v,a)
151 #define dmar_readl(a) readl(a)
152 #define dmar_writel(a, v) writel(v, a)
153
154 #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
155 #define DMAR_VER_MINOR(v) ((v) & 0x0f)
156
157 /*
158 * Decoding Capability Register
159 */
160 #define cap_esrtps(c) (((c) >> 63) & 1)
161 #define cap_esirtps(c) (((c) >> 62) & 1)
162 #define cap_ecmds(c) (((c) >> 61) & 1)
163 #define cap_fl5lp_support(c) (((c) >> 60) & 1)
164 #define cap_pi_support(c) (((c) >> 59) & 1)
165 #define cap_fl1gp_support(c) (((c) >> 56) & 1)
166 #define cap_read_drain(c) (((c) >> 55) & 1)
167 #define cap_write_drain(c) (((c) >> 54) & 1)
168 #define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
169 #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
170 #define cap_pgsel_inv(c) (((c) >> 39) & 1)
171
172 #define cap_super_page_val(c) (((c) >> 34) & 0xf)
173 #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
174 * OFFSET_STRIDE) + 21)
175
176 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
177 #define cap_max_fault_reg_offset(c) \
178 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
179
180 #define cap_zlr(c) (((c) >> 22) & 1)
181 #define cap_isoch(c) (((c) >> 23) & 1)
182 #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
183 #define cap_sagaw(c) (((c) >> 8) & 0x1f)
184 #define cap_caching_mode(c) (((c) >> 7) & 1)
185 #define cap_phmr(c) (((c) >> 6) & 1)
186 #define cap_plmr(c) (((c) >> 5) & 1)
187 #define cap_rwbf(c) (((c) >> 4) & 1)
188 #define cap_afl(c) (((c) >> 3) & 1)
189 #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
190 /*
191 * Extended Capability Register
192 */
193
194 #define ecap_pms(e) (((e) >> 51) & 0x1)
195 #define ecap_rps(e) (((e) >> 49) & 0x1)
196 #define ecap_smpwc(e) (((e) >> 48) & 0x1)
197 #define ecap_flts(e) (((e) >> 47) & 0x1)
198 #define ecap_slts(e) (((e) >> 46) & 0x1)
199 #define ecap_slads(e) (((e) >> 45) & 0x1)
200 #define ecap_smts(e) (((e) >> 43) & 0x1)
201 #define ecap_dit(e) (((e) >> 41) & 0x1)
202 #define ecap_pds(e) (((e) >> 42) & 0x1)
203 #define ecap_pasid(e) (((e) >> 40) & 0x1)
204 #define ecap_pss(e) (((e) >> 35) & 0x1f)
205 #define ecap_eafs(e) (((e) >> 34) & 0x1)
206 #define ecap_nwfs(e) (((e) >> 33) & 0x1)
207 #define ecap_srs(e) (((e) >> 31) & 0x1)
208 #define ecap_ers(e) (((e) >> 30) & 0x1)
209 #define ecap_prs(e) (((e) >> 29) & 0x1)
210 #define ecap_broken_pasid(e) (((e) >> 28) & 0x1)
211 #define ecap_dis(e) (((e) >> 27) & 0x1)
212 #define ecap_nest(e) (((e) >> 26) & 0x1)
213 #define ecap_mts(e) (((e) >> 25) & 0x1)
214 #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
215 #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
216 #define ecap_coherent(e) ((e) & 0x1)
217 #define ecap_qis(e) ((e) & 0x2)
218 #define ecap_pass_through(e) (((e) >> 6) & 0x1)
219 #define ecap_eim_support(e) (((e) >> 4) & 0x1)
220 #define ecap_ir_support(e) (((e) >> 3) & 0x1)
221 #define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)
222 #define ecap_max_handle_mask(e) (((e) >> 20) & 0xf)
223 #define ecap_sc_support(e) (((e) >> 7) & 0x1) /* Snooping Control */
224
225 /*
226 * Decoding Perf Capability Register
227 */
228 #define pcap_num_cntr(p) ((p) & 0xffff)
229 #define pcap_cntr_width(p) (((p) >> 16) & 0x7f)
230 #define pcap_num_event_group(p) (((p) >> 24) & 0x1f)
231 #define pcap_filters_mask(p) (((p) >> 32) & 0x1f)
232 #define pcap_interrupt(p) (((p) >> 50) & 0x1)
233 /* The counter stride is calculated as 2 ^ (x+10) bytes */
234 #define pcap_cntr_stride(p) (1ULL << ((((p) >> 52) & 0x7) + 10))
235
236 /*
237 * Decoding Perf Event Capability Register
238 */
239 #define pecap_es(p) ((p) & 0xfffffff)
240
241 /* Virtual command interface capability */
242 #define vccap_pasid(v) (((v) & DMA_VCS_PAS)) /* PASID allocation */
243
244 /* IOTLB_REG */
245 #define DMA_TLB_FLUSH_GRANU_OFFSET 60
246 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
247 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
248 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
249 #define DMA_TLB_IIRG(type) ((type >> 60) & 3)
250 #define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
251 #define DMA_TLB_READ_DRAIN (((u64)1) << 49)
252 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
253 #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
254 #define DMA_TLB_IVT (((u64)1) << 63)
255 #define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
256 #define DMA_TLB_MAX_SIZE (0x3f)
257
258 /* INVALID_DESC */
259 #define DMA_CCMD_INVL_GRANU_OFFSET 61
260 #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
261 #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4)
262 #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)
263 #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
264 #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
265 #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
266 #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
267 #define DMA_ID_TLB_ADDR(addr) (addr)
268 #define DMA_ID_TLB_ADDR_MASK(mask) (mask)
269
270 /* PMEN_REG */
271 #define DMA_PMEN_EPM (((u32)1)<<31)
272 #define DMA_PMEN_PRS (((u32)1)<<0)
273
274 /* GCMD_REG */
275 #define DMA_GCMD_TE (((u32)1) << 31)
276 #define DMA_GCMD_SRTP (((u32)1) << 30)
277 #define DMA_GCMD_SFL (((u32)1) << 29)
278 #define DMA_GCMD_EAFL (((u32)1) << 28)
279 #define DMA_GCMD_WBF (((u32)1) << 27)
280 #define DMA_GCMD_QIE (((u32)1) << 26)
281 #define DMA_GCMD_SIRTP (((u32)1) << 24)
282 #define DMA_GCMD_IRE (((u32) 1) << 25)
283 #define DMA_GCMD_CFI (((u32) 1) << 23)
284
285 /* GSTS_REG */
286 #define DMA_GSTS_TES (((u32)1) << 31)
287 #define DMA_GSTS_RTPS (((u32)1) << 30)
288 #define DMA_GSTS_FLS (((u32)1) << 29)
289 #define DMA_GSTS_AFLS (((u32)1) << 28)
290 #define DMA_GSTS_WBFS (((u32)1) << 27)
291 #define DMA_GSTS_QIES (((u32)1) << 26)
292 #define DMA_GSTS_IRTPS (((u32)1) << 24)
293 #define DMA_GSTS_IRES (((u32)1) << 25)
294 #define DMA_GSTS_CFIS (((u32)1) << 23)
295
296 /* DMA_RTADDR_REG */
297 #define DMA_RTADDR_SMT (((u64)1) << 10)
298
299 /* CCMD_REG */
300 #define DMA_CCMD_ICC (((u64)1) << 63)
301 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
302 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
303 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
304 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
305 #define DMA_CCMD_MASK_NOBIT 0
306 #define DMA_CCMD_MASK_1BIT 1
307 #define DMA_CCMD_MASK_2BIT 2
308 #define DMA_CCMD_MASK_3BIT 3
309 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
310 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
311
312 /* ECMD_REG */
313 #define DMA_MAX_NUM_ECMD 256
314 #define DMA_MAX_NUM_ECMDCAP (DMA_MAX_NUM_ECMD / 64)
315 #define DMA_ECMD_REG_STEP 8
316 #define DMA_ECMD_ENABLE 0xf0
317 #define DMA_ECMD_DISABLE 0xf1
318 #define DMA_ECMD_FREEZE 0xf4
319 #define DMA_ECMD_UNFREEZE 0xf5
320 #define DMA_ECMD_OA_SHIFT 16
321 #define DMA_ECMD_ECRSP_IP 0x1
322 #define DMA_ECMD_ECCAP3 3
323 #define DMA_ECMD_ECCAP3_ECNTS BIT_ULL(48)
324 #define DMA_ECMD_ECCAP3_DCNTS BIT_ULL(49)
325 #define DMA_ECMD_ECCAP3_FCNTS BIT_ULL(52)
326 #define DMA_ECMD_ECCAP3_UFCNTS BIT_ULL(53)
327 #define DMA_ECMD_ECCAP3_ESSENTIAL (DMA_ECMD_ECCAP3_ECNTS | \
328 DMA_ECMD_ECCAP3_DCNTS | \
329 DMA_ECMD_ECCAP3_FCNTS | \
330 DMA_ECMD_ECCAP3_UFCNTS)
331
332 /* FECTL_REG */
333 #define DMA_FECTL_IM (((u32)1) << 31)
334
335 /* FSTS_REG */
336 #define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */
337 #define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */
338 #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */
339 #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */
340 #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */
341 #define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */
342 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
343
344 /* FRCD_REG, 32 bits access */
345 #define DMA_FRCD_F (((u32)1) << 31)
346 #define dma_frcd_type(d) ((d >> 30) & 1)
347 #define dma_frcd_fault_reason(c) (c & 0xff)
348 #define dma_frcd_source_id(c) (c & 0xffff)
349 #define dma_frcd_pasid_value(c) (((c) >> 8) & 0xfffff)
350 #define dma_frcd_pasid_present(c) (((c) >> 31) & 1)
351 /* low 64 bit */
352 #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
353
354 /* PRS_REG */
355 #define DMA_PRS_PPR ((u32)1)
356 #define DMA_PRS_PRO ((u32)2)
357
358 #define DMA_VCS_PAS ((u64)1)
359
360 /* PERFINTRSTS_REG */
361 #define DMA_PERFINTRSTS_PIS ((u32)1)
362
363 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
364 do { \
365 cycles_t start_time = get_cycles(); \
366 while (1) { \
367 sts = op(iommu->reg + offset); \
368 if (cond) \
369 break; \
370 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
371 panic("DMAR hardware is malfunctioning\n"); \
372 cpu_relax(); \
373 } \
374 } while (0)
375
376 #define QI_LENGTH 256 /* queue length */
377
378 enum {
379 QI_FREE,
380 QI_IN_USE,
381 QI_DONE,
382 QI_ABORT
383 };
384
385 #define QI_CC_TYPE 0x1
386 #define QI_IOTLB_TYPE 0x2
387 #define QI_DIOTLB_TYPE 0x3
388 #define QI_IEC_TYPE 0x4
389 #define QI_IWD_TYPE 0x5
390 #define QI_EIOTLB_TYPE 0x6
391 #define QI_PC_TYPE 0x7
392 #define QI_DEIOTLB_TYPE 0x8
393 #define QI_PGRP_RESP_TYPE 0x9
394 #define QI_PSTRM_RESP_TYPE 0xa
395
396 #define QI_IEC_SELECTIVE (((u64)1) << 4)
397 #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
398 #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
399
400 #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
401 #define QI_IWD_STATUS_WRITE (((u64)1) << 5)
402 #define QI_IWD_FENCE (((u64)1) << 6)
403 #define QI_IWD_PRQ_DRAIN (((u64)1) << 7)
404
405 #define QI_IOTLB_DID(did) (((u64)did) << 16)
406 #define QI_IOTLB_DR(dr) (((u64)dr) << 7)
407 #define QI_IOTLB_DW(dw) (((u64)dw) << 6)
408 #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
409 #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
410 #define QI_IOTLB_IH(ih) (((u64)ih) << 6)
411 #define QI_IOTLB_AM(am) (((u8)am) & 0x3f)
412
413 #define QI_CC_FM(fm) (((u64)fm) << 48)
414 #define QI_CC_SID(sid) (((u64)sid) << 32)
415 #define QI_CC_DID(did) (((u64)did) << 16)
416 #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
417
418 #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
419 #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
420 #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
421 #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
422 ((u64)((pfsid >> 4) & 0xfff) << 52))
423 #define QI_DEV_IOTLB_SIZE 1
424 #define QI_DEV_IOTLB_MAX_INVS 32
425
426 #define QI_PC_PASID(pasid) (((u64)pasid) << 32)
427 #define QI_PC_DID(did) (((u64)did) << 16)
428 #define QI_PC_GRAN(gran) (((u64)gran) << 4)
429
430 /* PASID cache invalidation granu */
431 #define QI_PC_ALL_PASIDS 0
432 #define QI_PC_PASID_SEL 1
433 #define QI_PC_GLOBAL 3
434
435 #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
436 #define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
437 #define QI_EIOTLB_AM(am) (((u64)am) & 0x3f)
438 #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
439 #define QI_EIOTLB_DID(did) (((u64)did) << 16)
440 #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
441
442 /* QI Dev-IOTLB inv granu */
443 #define QI_DEV_IOTLB_GRAN_ALL 1
444 #define QI_DEV_IOTLB_GRAN_PASID_SEL 0
445
446 #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
447 #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
448 #define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32)
449 #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
450 #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
451 #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
452 ((u64)((pfsid >> 4) & 0xfff) << 52))
453 #define QI_DEV_EIOTLB_MAX_INVS 32
454
455 /* Page group response descriptor QW0 */
456 #define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
457 #define QI_PGRP_PDP(p) (((u64)(p)) << 5)
458 #define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12)
459 #define QI_PGRP_DID(rid) (((u64)(rid)) << 16)
460 #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
461
462 /* Page group response descriptor QW1 */
463 #define QI_PGRP_LPIG(x) (((u64)(x)) << 2)
464 #define QI_PGRP_IDX(idx) (((u64)(idx)) << 3)
465
466
467 #define QI_RESP_SUCCESS 0x0
468 #define QI_RESP_INVALID 0x1
469 #define QI_RESP_FAILURE 0xf
470
471 #define QI_GRAN_NONG_PASID 2
472 #define QI_GRAN_PSI_PASID 3
473
474 #define qi_shift(iommu) (DMAR_IQ_SHIFT + !!ecap_smts((iommu)->ecap))
475
476 struct qi_desc {
477 u64 qw0;
478 u64 qw1;
479 u64 qw2;
480 u64 qw3;
481 };
482
483 struct q_inval {
484 raw_spinlock_t q_lock;
485 void *desc; /* invalidation queue */
486 int *desc_status; /* desc status */
487 int free_head; /* first free entry */
488 int free_tail; /* last free entry */
489 int free_cnt;
490 };
491
492 /* Page Request Queue depth */
493 #define PRQ_ORDER 4
494 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x20)
495 #define PRQ_DEPTH ((0x1000 << PRQ_ORDER) >> 5)
496
497 struct dmar_pci_notify_info;
498
499 #ifdef CONFIG_IRQ_REMAP
500 /* 1MB - maximum possible interrupt remapping table size */
501 #define INTR_REMAP_PAGE_ORDER 8
502 #define INTR_REMAP_TABLE_REG_SIZE 0xf
503 #define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf
504
505 #define INTR_REMAP_TABLE_ENTRIES 65536
506
507 struct irq_domain;
508
509 struct ir_table {
510 struct irte *base;
511 unsigned long *bitmap;
512 };
513
514 void intel_irq_remap_add_device(struct dmar_pci_notify_info *info);
515 #else
516 static inline void
intel_irq_remap_add_device(struct dmar_pci_notify_info * info)517 intel_irq_remap_add_device(struct dmar_pci_notify_info *info) { }
518 #endif
519
520 struct iommu_flush {
521 void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
522 u8 fm, u64 type);
523 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
524 unsigned int size_order, u64 type);
525 };
526
527 enum {
528 SR_DMAR_FECTL_REG,
529 SR_DMAR_FEDATA_REG,
530 SR_DMAR_FEADDR_REG,
531 SR_DMAR_FEUADDR_REG,
532 MAX_SR_DMAR_REGS
533 };
534
535 #define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
536 #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
537 #define VTD_FLAG_SVM_CAPABLE (1 << 2)
538
539 #define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap))
540 #define pasid_supported(iommu) (sm_supported(iommu) && \
541 ecap_pasid((iommu)->ecap))
542
543 struct pasid_entry;
544 struct pasid_state_entry;
545 struct page_req_dsc;
546
547 /*
548 * 0: Present
549 * 1-11: Reserved
550 * 12-63: Context Ptr (12 - (haw-1))
551 * 64-127: Reserved
552 */
553 struct root_entry {
554 u64 lo;
555 u64 hi;
556 };
557
558 /*
559 * low 64 bits:
560 * 0: present
561 * 1: fault processing disable
562 * 2-3: translation type
563 * 12-63: address space root
564 * high 64 bits:
565 * 0-2: address width
566 * 3-6: aval
567 * 8-23: domain id
568 */
569 struct context_entry {
570 u64 lo;
571 u64 hi;
572 };
573
574 struct iommu_domain_info {
575 struct intel_iommu *iommu;
576 unsigned int refcnt; /* Refcount of devices per iommu */
577 u16 did; /* Domain ids per IOMMU. Use u16 since
578 * domain ids are 16 bit wide according
579 * to VT-d spec, section 9.3 */
580 };
581
582 struct dmar_domain {
583 int nid; /* node id */
584 struct xarray iommu_array; /* Attached IOMMU array */
585
586 u8 has_iotlb_device: 1;
587 u8 iommu_coherency: 1; /* indicate coherency of iommu access */
588 u8 force_snooping : 1; /* Create IOPTEs with snoop control */
589 u8 set_pte_snp:1;
590 u8 use_first_level:1; /* DMA translation for the domain goes
591 * through the first level page table,
592 * otherwise, goes through the second
593 * level.
594 */
595 u8 has_mappings:1; /* Has mappings configured through
596 * iommu_map() interface.
597 */
598
599 spinlock_t lock; /* Protect device tracking lists */
600 struct list_head devices; /* all devices' list */
601 struct list_head dev_pasids; /* all attached pasids */
602
603 struct dma_pte *pgd; /* virtual address */
604 int gaw; /* max guest address width */
605
606 /* adjusted guest address width, 0 is level 2 30-bit */
607 int agaw;
608 int iommu_superpage;/* Level of superpages supported:
609 0 == 4KiB (no superpages), 1 == 2MiB,
610 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
611 u64 max_addr; /* maximum mapped address */
612
613 struct iommu_domain domain; /* generic domain data structure for
614 iommu core */
615 };
616
617 /*
618 * In theory, the VT-d 4.0 spec can support up to 2 ^ 16 counters.
619 * But in practice, there are only 14 counters for the existing
620 * platform. Setting the max number of counters to 64 should be good
621 * enough for a long time. Also, supporting more than 64 counters
622 * requires more extras, e.g., extra freeze and overflow registers,
623 * which is not necessary for now.
624 */
625 #define IOMMU_PMU_IDX_MAX 64
626
627 struct iommu_pmu {
628 struct intel_iommu *iommu;
629 u32 num_cntr; /* Number of counters */
630 u32 num_eg; /* Number of event group */
631 u32 cntr_width; /* Counter width */
632 u32 cntr_stride; /* Counter Stride */
633 u32 filter; /* Bitmask of filter support */
634 void __iomem *base; /* the PerfMon base address */
635 void __iomem *cfg_reg; /* counter configuration base address */
636 void __iomem *cntr_reg; /* counter 0 address*/
637 void __iomem *overflow; /* overflow status register */
638
639 u64 *evcap; /* Indicates all supported events */
640 u32 **cntr_evcap; /* Supported events of each counter. */
641
642 struct pmu pmu;
643 DECLARE_BITMAP(used_mask, IOMMU_PMU_IDX_MAX);
644 struct perf_event *event_list[IOMMU_PMU_IDX_MAX];
645 unsigned char irq_name[16];
646 struct hlist_node cpuhp_node;
647 int cpu;
648 };
649
650 #define IOMMU_IRQ_ID_OFFSET_PRQ (DMAR_UNITS_SUPPORTED)
651 #define IOMMU_IRQ_ID_OFFSET_PERF (2 * DMAR_UNITS_SUPPORTED)
652
653 struct intel_iommu {
654 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
655 u64 reg_phys; /* physical address of hw register set */
656 u64 reg_size; /* size of hw register set */
657 u64 cap;
658 u64 ecap;
659 u64 vccap;
660 u64 ecmdcap[DMA_MAX_NUM_ECMDCAP];
661 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
662 raw_spinlock_t register_lock; /* protect register handling */
663 int seq_id; /* sequence id of the iommu */
664 int agaw; /* agaw of this iommu */
665 int msagaw; /* max sagaw of this iommu */
666 unsigned int irq, pr_irq, perf_irq;
667 u16 segment; /* PCI segment# */
668 unsigned char name[13]; /* Device Name */
669
670 #ifdef CONFIG_INTEL_IOMMU
671 unsigned long *domain_ids; /* bitmap of domains */
672 unsigned long *copied_tables; /* bitmap of copied tables */
673 spinlock_t lock; /* protect context, domain ids */
674 struct root_entry *root_entry; /* virtual address */
675
676 struct iommu_flush flush;
677 #endif
678 #ifdef CONFIG_INTEL_IOMMU_SVM
679 struct page_req_dsc *prq;
680 unsigned char prq_name[16]; /* Name for PRQ interrupt */
681 unsigned long prq_seq_number;
682 struct completion prq_complete;
683 #endif
684 struct iopf_queue *iopf_queue;
685 unsigned char iopfq_name[16];
686 struct q_inval *qi; /* Queued invalidation info */
687 u32 iommu_state[MAX_SR_DMAR_REGS]; /* Store iommu states between suspend and resume.*/
688
689 #ifdef CONFIG_IRQ_REMAP
690 struct ir_table *ir_table; /* Interrupt remapping info */
691 struct irq_domain *ir_domain;
692 #endif
693 struct iommu_device iommu; /* IOMMU core code handle */
694 int node;
695 u32 flags; /* Software defined flags */
696
697 struct dmar_drhd_unit *drhd;
698 void *perf_statistic;
699
700 struct iommu_pmu *pmu;
701 };
702
703 /* PCI domain-device relationship */
704 struct device_domain_info {
705 struct list_head link; /* link to domain siblings */
706 u32 segment; /* PCI segment number */
707 u8 bus; /* PCI bus number */
708 u8 devfn; /* PCI devfn number */
709 u16 pfsid; /* SRIOV physical function source ID */
710 u8 pasid_supported:3;
711 u8 pasid_enabled:1;
712 u8 pri_supported:1;
713 u8 pri_enabled:1;
714 u8 ats_supported:1;
715 u8 ats_enabled:1;
716 u8 dtlb_extra_inval:1; /* Quirk for devices need extra flush */
717 u8 ats_qdep;
718 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
719 struct intel_iommu *iommu; /* IOMMU used by this device */
720 struct dmar_domain *domain; /* pointer to domain */
721 struct pasid_table *pasid_table; /* pasid table */
722 };
723
724 struct dev_pasid_info {
725 struct list_head link_domain; /* link to domain siblings */
726 struct device *dev;
727 ioasid_t pasid;
728 };
729
__iommu_flush_cache(struct intel_iommu * iommu,void * addr,int size)730 static inline void __iommu_flush_cache(
731 struct intel_iommu *iommu, void *addr, int size)
732 {
733 if (!ecap_coherent(iommu->ecap))
734 clflush_cache_range(addr, size);
735 }
736
737 /* Convert generic struct iommu_domain to private struct dmar_domain */
to_dmar_domain(struct iommu_domain * dom)738 static inline struct dmar_domain *to_dmar_domain(struct iommu_domain *dom)
739 {
740 return container_of(dom, struct dmar_domain, domain);
741 }
742
743 /* Retrieve the domain ID which has allocated to the domain */
744 static inline u16
domain_id_iommu(struct dmar_domain * domain,struct intel_iommu * iommu)745 domain_id_iommu(struct dmar_domain *domain, struct intel_iommu *iommu)
746 {
747 struct iommu_domain_info *info =
748 xa_load(&domain->iommu_array, iommu->seq_id);
749
750 return info->did;
751 }
752
753 /*
754 * 0: readable
755 * 1: writable
756 * 2-6: reserved
757 * 7: super page
758 * 8-10: available
759 * 11: snoop behavior
760 * 12-63: Host physical address
761 */
762 struct dma_pte {
763 u64 val;
764 };
765
dma_clear_pte(struct dma_pte * pte)766 static inline void dma_clear_pte(struct dma_pte *pte)
767 {
768 pte->val = 0;
769 }
770
dma_pte_addr(struct dma_pte * pte)771 static inline u64 dma_pte_addr(struct dma_pte *pte)
772 {
773 #ifdef CONFIG_64BIT
774 return pte->val & VTD_PAGE_MASK & (~DMA_FL_PTE_XD);
775 #else
776 /* Must have a full atomic 64-bit read */
777 return __cmpxchg64(&pte->val, 0ULL, 0ULL) &
778 VTD_PAGE_MASK & (~DMA_FL_PTE_XD);
779 #endif
780 }
781
dma_pte_present(struct dma_pte * pte)782 static inline bool dma_pte_present(struct dma_pte *pte)
783 {
784 return (pte->val & 3) != 0;
785 }
786
dma_pte_superpage(struct dma_pte * pte)787 static inline bool dma_pte_superpage(struct dma_pte *pte)
788 {
789 return (pte->val & DMA_PTE_LARGE_PAGE);
790 }
791
first_pte_in_page(struct dma_pte * pte)792 static inline bool first_pte_in_page(struct dma_pte *pte)
793 {
794 return IS_ALIGNED((unsigned long)pte, VTD_PAGE_SIZE);
795 }
796
nr_pte_to_next_page(struct dma_pte * pte)797 static inline int nr_pte_to_next_page(struct dma_pte *pte)
798 {
799 return first_pte_in_page(pte) ? BIT_ULL(VTD_STRIDE_SHIFT) :
800 (struct dma_pte *)ALIGN((unsigned long)pte, VTD_PAGE_SIZE) - pte;
801 }
802
context_present(struct context_entry * context)803 static inline bool context_present(struct context_entry *context)
804 {
805 return (context->lo & 1);
806 }
807
808 struct dmar_drhd_unit *dmar_find_matched_drhd_unit(struct pci_dev *dev);
809
810 int dmar_enable_qi(struct intel_iommu *iommu);
811 void dmar_disable_qi(struct intel_iommu *iommu);
812 int dmar_reenable_qi(struct intel_iommu *iommu);
813 void qi_global_iec(struct intel_iommu *iommu);
814
815 void qi_flush_context(struct intel_iommu *iommu, u16 did,
816 u16 sid, u8 fm, u64 type);
817 void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
818 unsigned int size_order, u64 type);
819 void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
820 u16 qdep, u64 addr, unsigned mask);
821
822 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
823 unsigned long npages, bool ih);
824
825 void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
826 u32 pasid, u16 qdep, u64 addr,
827 unsigned int size_order);
828 void quirk_extra_dev_tlb_flush(struct device_domain_info *info,
829 unsigned long address, unsigned long pages,
830 u32 pasid, u16 qdep);
831 void qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu,
832 u32 pasid);
833
834 int qi_submit_sync(struct intel_iommu *iommu, struct qi_desc *desc,
835 unsigned int count, unsigned long options);
836 /*
837 * Options used in qi_submit_sync:
838 * QI_OPT_WAIT_DRAIN - Wait for PRQ drain completion, spec 6.5.2.8.
839 */
840 #define QI_OPT_WAIT_DRAIN BIT(0)
841
842 int dmar_ir_support(void);
843
844 void *alloc_pgtable_page(int node, gfp_t gfp);
845 void free_pgtable_page(void *vaddr);
846 void iommu_flush_write_buffer(struct intel_iommu *iommu);
847 struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn);
848
849 #ifdef CONFIG_INTEL_IOMMU_SVM
850 void intel_svm_check(struct intel_iommu *iommu);
851 int intel_svm_enable_prq(struct intel_iommu *iommu);
852 int intel_svm_finish_prq(struct intel_iommu *iommu);
853 int intel_svm_page_response(struct device *dev, struct iommu_fault_event *evt,
854 struct iommu_page_response *msg);
855 struct iommu_domain *intel_svm_domain_alloc(void);
856 void intel_svm_remove_dev_pasid(struct device *dev, ioasid_t pasid);
857 void intel_drain_pasid_prq(struct device *dev, u32 pasid);
858
859 struct intel_svm_dev {
860 struct list_head list;
861 struct rcu_head rcu;
862 struct device *dev;
863 struct intel_iommu *iommu;
864 u16 did;
865 u16 sid, qdep;
866 };
867
868 struct intel_svm {
869 struct mmu_notifier notifier;
870 struct mm_struct *mm;
871 u32 pasid;
872 struct list_head devs;
873 };
874 #else
intel_svm_check(struct intel_iommu * iommu)875 static inline void intel_svm_check(struct intel_iommu *iommu) {}
intel_drain_pasid_prq(struct device * dev,u32 pasid)876 static inline void intel_drain_pasid_prq(struct device *dev, u32 pasid) {}
intel_svm_domain_alloc(void)877 static inline struct iommu_domain *intel_svm_domain_alloc(void)
878 {
879 return NULL;
880 }
881
intel_svm_remove_dev_pasid(struct device * dev,ioasid_t pasid)882 static inline void intel_svm_remove_dev_pasid(struct device *dev, ioasid_t pasid)
883 {
884 }
885 #endif
886
887 #ifdef CONFIG_INTEL_IOMMU_DEBUGFS
888 void intel_iommu_debugfs_init(void);
889 #else
intel_iommu_debugfs_init(void)890 static inline void intel_iommu_debugfs_init(void) {}
891 #endif /* CONFIG_INTEL_IOMMU_DEBUGFS */
892
893 extern const struct attribute_group *intel_iommu_groups[];
894 struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus,
895 u8 devfn, int alloc);
896
897 extern const struct iommu_ops intel_iommu_ops;
898
899 #ifdef CONFIG_INTEL_IOMMU
900 extern int intel_iommu_sm;
901 int iommu_calculate_agaw(struct intel_iommu *iommu);
902 int iommu_calculate_max_sagaw(struct intel_iommu *iommu);
903 int ecmd_submit_sync(struct intel_iommu *iommu, u8 ecmd, u64 oa, u64 ob);
904
ecmd_has_pmu_essential(struct intel_iommu * iommu)905 static inline bool ecmd_has_pmu_essential(struct intel_iommu *iommu)
906 {
907 return (iommu->ecmdcap[DMA_ECMD_ECCAP3] & DMA_ECMD_ECCAP3_ESSENTIAL) ==
908 DMA_ECMD_ECCAP3_ESSENTIAL;
909 }
910
911 extern int dmar_disabled;
912 extern int intel_iommu_enabled;
913 #else
iommu_calculate_agaw(struct intel_iommu * iommu)914 static inline int iommu_calculate_agaw(struct intel_iommu *iommu)
915 {
916 return 0;
917 }
iommu_calculate_max_sagaw(struct intel_iommu * iommu)918 static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
919 {
920 return 0;
921 }
922 #define dmar_disabled (1)
923 #define intel_iommu_enabled (0)
924 #define intel_iommu_sm (0)
925 #endif
926
decode_prq_descriptor(char * str,size_t size,u64 dw0,u64 dw1,u64 dw2,u64 dw3)927 static inline const char *decode_prq_descriptor(char *str, size_t size,
928 u64 dw0, u64 dw1, u64 dw2, u64 dw3)
929 {
930 char *buf = str;
931 int bytes;
932
933 bytes = snprintf(buf, size,
934 "rid=0x%llx addr=0x%llx %c%c%c%c%c pasid=0x%llx index=0x%llx",
935 FIELD_GET(GENMASK_ULL(31, 16), dw0),
936 FIELD_GET(GENMASK_ULL(63, 12), dw1),
937 dw1 & BIT_ULL(0) ? 'r' : '-',
938 dw1 & BIT_ULL(1) ? 'w' : '-',
939 dw0 & BIT_ULL(52) ? 'x' : '-',
940 dw0 & BIT_ULL(53) ? 'p' : '-',
941 dw1 & BIT_ULL(2) ? 'l' : '-',
942 FIELD_GET(GENMASK_ULL(51, 32), dw0),
943 FIELD_GET(GENMASK_ULL(11, 3), dw1));
944
945 /* Private Data */
946 if (dw0 & BIT_ULL(9)) {
947 size -= bytes;
948 buf += bytes;
949 snprintf(buf, size, " private=0x%llx/0x%llx\n", dw2, dw3);
950 }
951
952 return str;
953 }
954
955 #endif
956