1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *
4  * Common boot and setup code.
5  *
6  * Copyright (C) 2001 PPC64 Team, IBM Corp
7  */
8 
9 #include <linux/export.h>
10 #include <linux/string.h>
11 #include <linux/sched.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/reboot.h>
15 #include <linux/delay.h>
16 #include <linux/initrd.h>
17 #include <linux/seq_file.h>
18 #include <linux/ioport.h>
19 #include <linux/console.h>
20 #include <linux/utsname.h>
21 #include <linux/tty.h>
22 #include <linux/root_dev.h>
23 #include <linux/notifier.h>
24 #include <linux/cpu.h>
25 #include <linux/unistd.h>
26 #include <linux/serial.h>
27 #include <linux/serial_8250.h>
28 #include <linux/memblock.h>
29 #include <linux/pci.h>
30 #include <linux/lockdep.h>
31 #include <linux/memory.h>
32 #include <linux/nmi.h>
33 #include <linux/pgtable.h>
34 #include <linux/of.h>
35 #include <linux/of_fdt.h>
36 
37 #include <asm/kvm_guest.h>
38 #include <asm/io.h>
39 #include <asm/kdump.h>
40 #include <asm/processor.h>
41 #include <asm/smp.h>
42 #include <asm/elf.h>
43 #include <asm/machdep.h>
44 #include <asm/paca.h>
45 #include <asm/time.h>
46 #include <asm/cputable.h>
47 #include <asm/dt_cpu_ftrs.h>
48 #include <asm/sections.h>
49 #include <asm/btext.h>
50 #include <asm/nvram.h>
51 #include <asm/setup.h>
52 #include <asm/rtas.h>
53 #include <asm/iommu.h>
54 #include <asm/serial.h>
55 #include <asm/cache.h>
56 #include <asm/page.h>
57 #include <asm/mmu.h>
58 #include <asm/firmware.h>
59 #include <asm/xmon.h>
60 #include <asm/udbg.h>
61 #include <asm/kexec.h>
62 #include <asm/code-patching.h>
63 #include <asm/ftrace.h>
64 #include <asm/opal.h>
65 #include <asm/cputhreads.h>
66 #include <asm/hw_irq.h>
67 #include <asm/feature-fixups.h>
68 #include <asm/kup.h>
69 #include <asm/early_ioremap.h>
70 #include <asm/pgalloc.h>
71 
72 #include "setup.h"
73 
74 int spinning_secondaries;
75 u64 ppc64_pft_size;
76 
77 struct ppc64_caches ppc64_caches = {
78 	.l1d = {
79 		.block_size = 0x40,
80 		.log_block_size = 6,
81 	},
82 	.l1i = {
83 		.block_size = 0x40,
84 		.log_block_size = 6
85 	},
86 };
87 EXPORT_SYMBOL_GPL(ppc64_caches);
88 
89 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
setup_tlb_core_data(void)90 void __init setup_tlb_core_data(void)
91 {
92 	int cpu;
93 
94 	BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
95 
96 	for_each_possible_cpu(cpu) {
97 		int first = cpu_first_thread_sibling(cpu);
98 
99 		/*
100 		 * If we boot via kdump on a non-primary thread,
101 		 * make sure we point at the thread that actually
102 		 * set up this TLB.
103 		 */
104 		if (cpu_first_thread_sibling(boot_cpuid) == first)
105 			first = boot_cpuid;
106 
107 		paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd;
108 
109 		/*
110 		 * If we have threads, we need either tlbsrx.
111 		 * or e6500 tablewalk mode, or else TLB handlers
112 		 * will be racy and could produce duplicate entries.
113 		 * Should we panic instead?
114 		 */
115 		WARN_ONCE(smt_enabled_at_boot >= 2 &&
116 			  !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
117 			  book3e_htw_mode != PPC_HTW_E6500,
118 			  "%s: unsupported MMU configuration\n", __func__);
119 	}
120 }
121 #endif
122 
123 #ifdef CONFIG_SMP
124 
125 static char *smt_enabled_cmdline;
126 
127 /* Look for ibm,smt-enabled OF option */
check_smt_enabled(void)128 void __init check_smt_enabled(void)
129 {
130 	struct device_node *dn;
131 	const char *smt_option;
132 
133 	/* Default to enabling all threads */
134 	smt_enabled_at_boot = threads_per_core;
135 
136 	/* Allow the command line to overrule the OF option */
137 	if (smt_enabled_cmdline) {
138 		if (!strcmp(smt_enabled_cmdline, "on"))
139 			smt_enabled_at_boot = threads_per_core;
140 		else if (!strcmp(smt_enabled_cmdline, "off"))
141 			smt_enabled_at_boot = 0;
142 		else {
143 			int smt;
144 			int rc;
145 
146 			rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
147 			if (!rc)
148 				smt_enabled_at_boot =
149 					min(threads_per_core, smt);
150 		}
151 	} else {
152 		dn = of_find_node_by_path("/options");
153 		if (dn) {
154 			smt_option = of_get_property(dn, "ibm,smt-enabled",
155 						     NULL);
156 
157 			if (smt_option) {
158 				if (!strcmp(smt_option, "on"))
159 					smt_enabled_at_boot = threads_per_core;
160 				else if (!strcmp(smt_option, "off"))
161 					smt_enabled_at_boot = 0;
162 			}
163 
164 			of_node_put(dn);
165 		}
166 	}
167 }
168 
169 /* Look for smt-enabled= cmdline option */
early_smt_enabled(char * p)170 static int __init early_smt_enabled(char *p)
171 {
172 	smt_enabled_cmdline = p;
173 	return 0;
174 }
175 early_param("smt-enabled", early_smt_enabled);
176 
177 #endif /* CONFIG_SMP */
178 
179 /** Fix up paca fields required for the boot cpu */
fixup_boot_paca(void)180 static void __init fixup_boot_paca(void)
181 {
182 	/* The boot cpu is started */
183 	get_paca()->cpu_start = 1;
184 	/* Allow percpu accesses to work until we setup percpu data */
185 	get_paca()->data_offset = 0;
186 	/* Mark interrupts disabled in PACA */
187 	irq_soft_mask_set(IRQS_DISABLED);
188 }
189 
configure_exceptions(void)190 static void __init configure_exceptions(void)
191 {
192 	/*
193 	 * Setup the trampolines from the lowmem exception vectors
194 	 * to the kdump kernel when not using a relocatable kernel.
195 	 */
196 	setup_kdump_trampoline();
197 
198 	/* Under a PAPR hypervisor, we need hypercalls */
199 	if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
200 		/*
201 		 * - PR KVM does not support AIL mode interrupts in the host
202 		 *   while a PR guest is running.
203 		 *
204 		 * - SCV system call interrupt vectors are only implemented for
205 		 *   AIL mode interrupts.
206 		 *
207 		 * - On pseries, AIL mode can only be enabled and disabled
208 		 *   system-wide so when a PR VM is created on a pseries host,
209 		 *   all CPUs of the host are set to AIL=0 mode.
210 		 *
211 		 * - Therefore host CPUs must not execute scv while a PR VM
212 		 *   exists.
213 		 *
214 		 * - SCV support can not be disabled dynamically because the
215 		 *   feature is advertised to host userspace. Disabling the
216 		 *   facility and emulating it would be possible but is not
217 		 *   implemented.
218 		 *
219 		 * - So SCV support is blanket disabled if PR KVM could possibly
220 		 *   run. That is, PR support compiled in, booting on pseries
221 		 *   with hash MMU.
222 		 */
223 		if (IS_ENABLED(CONFIG_KVM_BOOK3S_PR_POSSIBLE) && !radix_enabled()) {
224 			init_task.thread.fscr &= ~FSCR_SCV;
225 			cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_SCV;
226 		}
227 
228 		/* Enable AIL if possible */
229 		if (!pseries_enable_reloc_on_exc()) {
230 			init_task.thread.fscr &= ~FSCR_SCV;
231 			cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_SCV;
232 		}
233 
234 		/*
235 		 * Tell the hypervisor that we want our exceptions to
236 		 * be taken in little endian mode.
237 		 *
238 		 * We don't call this for big endian as our calling convention
239 		 * makes us always enter in BE, and the call may fail under
240 		 * some circumstances with kdump.
241 		 */
242 #ifdef __LITTLE_ENDIAN__
243 		pseries_little_endian_exceptions();
244 #endif
245 	} else {
246 		/* Set endian mode using OPAL */
247 		if (firmware_has_feature(FW_FEATURE_OPAL))
248 			opal_configure_cores();
249 
250 		/* AIL on native is done in cpu_ready_for_interrupts() */
251 	}
252 }
253 
cpu_ready_for_interrupts(void)254 static void cpu_ready_for_interrupts(void)
255 {
256 	/*
257 	 * Enable AIL if supported, and we are in hypervisor mode. This
258 	 * is called once for every processor.
259 	 *
260 	 * If we are not in hypervisor mode the job is done once for
261 	 * the whole partition in configure_exceptions().
262 	 */
263 	if (cpu_has_feature(CPU_FTR_HVMODE)) {
264 		unsigned long lpcr = mfspr(SPRN_LPCR);
265 		unsigned long new_lpcr = lpcr;
266 
267 		if (cpu_has_feature(CPU_FTR_ARCH_31)) {
268 			/* P10 DD1 does not have HAIL */
269 			if (pvr_version_is(PVR_POWER10) &&
270 					(mfspr(SPRN_PVR) & 0xf00) == 0x100)
271 				new_lpcr |= LPCR_AIL_3;
272 			else
273 				new_lpcr |= LPCR_HAIL;
274 		} else if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
275 			new_lpcr |= LPCR_AIL_3;
276 		}
277 
278 		if (new_lpcr != lpcr)
279 			mtspr(SPRN_LPCR, new_lpcr);
280 	}
281 
282 	/*
283 	 * Set HFSCR:TM based on CPU features:
284 	 * In the special case of TM no suspend (P9N DD2.1), Linux is
285 	 * told TM is off via the dt-ftrs but told to (partially) use
286 	 * it via OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED. So HFSCR[TM]
287 	 * will be off from dt-ftrs but we need to turn it on for the
288 	 * no suspend case.
289 	 */
290 	if (cpu_has_feature(CPU_FTR_HVMODE)) {
291 		if (cpu_has_feature(CPU_FTR_TM_COMP))
292 			mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) | HFSCR_TM);
293 		else
294 			mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
295 	}
296 
297 	/* Set IR and DR in PACA MSR */
298 	get_paca()->kernel_msr = MSR_KERNEL;
299 }
300 
301 unsigned long spr_default_dscr = 0;
302 
record_spr_defaults(void)303 static void __init record_spr_defaults(void)
304 {
305 	if (early_cpu_has_feature(CPU_FTR_DSCR))
306 		spr_default_dscr = mfspr(SPRN_DSCR);
307 }
308 
309 /*
310  * Early initialization entry point. This is called by head.S
311  * with MMU translation disabled. We rely on the "feature" of
312  * the CPU that ignores the top 2 bits of the address in real
313  * mode so we can access kernel globals normally provided we
314  * only toy with things in the RMO region. From here, we do
315  * some early parsing of the device-tree to setup out MEMBLOCK
316  * data structures, and allocate & initialize the hash table
317  * and segment tables so we can start running with translation
318  * enabled.
319  *
320  * It is this function which will call the probe() callback of
321  * the various platform types and copy the matching one to the
322  * global ppc_md structure. Your platform can eventually do
323  * some very early initializations from the probe() routine, but
324  * this is not recommended, be very careful as, for example, the
325  * device-tree is not accessible via normal means at this point.
326  */
327 
early_setup(unsigned long dt_ptr)328 void __init early_setup(unsigned long dt_ptr)
329 {
330 	static __initdata struct paca_struct boot_paca;
331 
332 	/* -------- printk is _NOT_ safe to use here ! ------- */
333 
334 	/*
335 	 * Assume we're on cpu 0 for now.
336 	 *
337 	 * We need to load a PACA very early for a few reasons.
338 	 *
339 	 * The stack protector canary is stored in the paca, so as soon as we
340 	 * call any stack protected code we need r13 pointing somewhere valid.
341 	 *
342 	 * If we are using kcov it will call in_task() in its instrumentation,
343 	 * which relies on the current task from the PACA.
344 	 *
345 	 * dt_cpu_ftrs_init() calls into generic OF/fdt code, as well as
346 	 * printk(), which can trigger both stack protector and kcov.
347 	 *
348 	 * percpu variables and spin locks also use the paca.
349 	 *
350 	 * So set up a temporary paca. It will be replaced below once we know
351 	 * what CPU we are on.
352 	 */
353 	initialise_paca(&boot_paca, 0);
354 	setup_paca(&boot_paca);
355 	fixup_boot_paca();
356 
357 	/* -------- printk is now safe to use ------- */
358 
359 	/* Try new device tree based feature discovery ... */
360 	if (!dt_cpu_ftrs_init(__va(dt_ptr)))
361 		/* Otherwise use the old style CPU table */
362 		identify_cpu(0, mfspr(SPRN_PVR));
363 
364 	/* Enable early debugging if any specified (see udbg.h) */
365 	udbg_early_init();
366 
367 	udbg_printf(" -> %s(), dt_ptr: 0x%lx\n", __func__, dt_ptr);
368 
369 	/*
370 	 * Do early initialization using the flattened device
371 	 * tree, such as retrieving the physical memory map or
372 	 * calculating/retrieving the hash table size.
373 	 */
374 	early_init_devtree(__va(dt_ptr));
375 
376 	/* Now we know the logical id of our boot cpu, setup the paca. */
377 	if (boot_cpuid != 0) {
378 		/* Poison paca_ptrs[0] again if it's not the boot cpu */
379 		memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0]));
380 	}
381 	setup_paca(paca_ptrs[boot_cpuid]);
382 	fixup_boot_paca();
383 
384 	/*
385 	 * Configure exception handlers. This include setting up trampolines
386 	 * if needed, setting exception endian mode, etc...
387 	 */
388 	configure_exceptions();
389 
390 	/*
391 	 * Configure Kernel Userspace Protection. This needs to happen before
392 	 * feature fixups for platforms that implement this using features.
393 	 */
394 	setup_kup();
395 
396 	/* Apply all the dynamic patching */
397 	apply_feature_fixups();
398 	setup_feature_keys();
399 
400 	/* Initialize the hash table or TLB handling */
401 	early_init_mmu();
402 
403 	early_ioremap_setup();
404 
405 	/*
406 	 * After firmware and early platform setup code has set things up,
407 	 * we note the SPR values for configurable control/performance
408 	 * registers, and use those as initial defaults.
409 	 */
410 	record_spr_defaults();
411 
412 	/*
413 	 * At this point, we can let interrupts switch to virtual mode
414 	 * (the MMU has been setup), so adjust the MSR in the PACA to
415 	 * have IR and DR set and enable AIL if it exists
416 	 */
417 	cpu_ready_for_interrupts();
418 
419 	/*
420 	 * We enable ftrace here, but since we only support DYNAMIC_FTRACE, it
421 	 * will only actually get enabled on the boot cpu much later once
422 	 * ftrace itself has been initialized.
423 	 */
424 	this_cpu_enable_ftrace();
425 
426 	udbg_printf(" <- %s()\n", __func__);
427 
428 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
429 	/*
430 	 * This needs to be done *last* (after the above udbg_printf() even)
431 	 *
432 	 * Right after we return from this function, we turn on the MMU
433 	 * which means the real-mode access trick that btext does will
434 	 * no longer work, it needs to switch to using a real MMU
435 	 * mapping. This call will ensure that it does
436 	 */
437 	btext_map();
438 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
439 }
440 
441 #ifdef CONFIG_SMP
early_setup_secondary(void)442 void early_setup_secondary(void)
443 {
444 	/* Mark interrupts disabled in PACA */
445 	irq_soft_mask_set(IRQS_DISABLED);
446 
447 	/* Initialize the hash table or TLB handling */
448 	early_init_mmu_secondary();
449 
450 	/* Perform any KUP setup that is per-cpu */
451 	setup_kup();
452 
453 	/*
454 	 * At this point, we can let interrupts switch to virtual mode
455 	 * (the MMU has been setup), so adjust the MSR in the PACA to
456 	 * have IR and DR set.
457 	 */
458 	cpu_ready_for_interrupts();
459 }
460 
461 #endif /* CONFIG_SMP */
462 
panic_smp_self_stop(void)463 void panic_smp_self_stop(void)
464 {
465 	hard_irq_disable();
466 	spin_begin();
467 	while (1)
468 		spin_cpu_relax();
469 }
470 
471 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
use_spinloop(void)472 static bool use_spinloop(void)
473 {
474 	if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
475 		/*
476 		 * See comments in head_64.S -- not all platforms insert
477 		 * secondaries at __secondary_hold and wait at the spin
478 		 * loop.
479 		 */
480 		if (firmware_has_feature(FW_FEATURE_OPAL))
481 			return false;
482 		return true;
483 	}
484 
485 	/*
486 	 * When book3e boots from kexec, the ePAPR spin table does
487 	 * not get used.
488 	 */
489 	return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
490 }
491 
smp_release_cpus(void)492 void smp_release_cpus(void)
493 {
494 	unsigned long *ptr;
495 	int i;
496 
497 	if (!use_spinloop())
498 		return;
499 
500 	/* All secondary cpus are spinning on a common spinloop, release them
501 	 * all now so they can start to spin on their individual paca
502 	 * spinloops. For non SMP kernels, the secondary cpus never get out
503 	 * of the common spinloop.
504 	 */
505 
506 	ptr  = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
507 			- PHYSICAL_START);
508 	*ptr = ppc_function_entry(generic_secondary_smp_init);
509 
510 	/* And wait a bit for them to catch up */
511 	for (i = 0; i < 100000; i++) {
512 		mb();
513 		HMT_low();
514 		if (spinning_secondaries == 0)
515 			break;
516 		udelay(1);
517 	}
518 	pr_debug("spinning_secondaries = %d\n", spinning_secondaries);
519 }
520 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
521 
522 /*
523  * Initialize some remaining members of the ppc64_caches and systemcfg
524  * structures
525  * (at least until we get rid of them completely). This is mostly some
526  * cache informations about the CPU that will be used by cache flush
527  * routines and/or provided to userland
528  */
529 
init_cache_info(struct ppc_cache_info * info,u32 size,u32 lsize,u32 bsize,u32 sets)530 static void __init init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
531 			    u32 bsize, u32 sets)
532 {
533 	info->size = size;
534 	info->sets = sets;
535 	info->line_size = lsize;
536 	info->block_size = bsize;
537 	info->log_block_size = __ilog2(bsize);
538 	if (bsize)
539 		info->blocks_per_page = PAGE_SIZE / bsize;
540 	else
541 		info->blocks_per_page = 0;
542 
543 	if (sets == 0)
544 		info->assoc = 0xffff;
545 	else
546 		info->assoc = size / (sets * lsize);
547 }
548 
parse_cache_info(struct device_node * np,bool icache,struct ppc_cache_info * info)549 static bool __init parse_cache_info(struct device_node *np,
550 				    bool icache,
551 				    struct ppc_cache_info *info)
552 {
553 	static const char *ipropnames[] __initdata = {
554 		"i-cache-size",
555 		"i-cache-sets",
556 		"i-cache-block-size",
557 		"i-cache-line-size",
558 	};
559 	static const char *dpropnames[] __initdata = {
560 		"d-cache-size",
561 		"d-cache-sets",
562 		"d-cache-block-size",
563 		"d-cache-line-size",
564 	};
565 	const char **propnames = icache ? ipropnames : dpropnames;
566 	const __be32 *sizep, *lsizep, *bsizep, *setsp;
567 	u32 size, lsize, bsize, sets;
568 	bool success = true;
569 
570 	size = 0;
571 	sets = -1u;
572 	lsize = bsize = cur_cpu_spec->dcache_bsize;
573 	sizep = of_get_property(np, propnames[0], NULL);
574 	if (sizep != NULL)
575 		size = be32_to_cpu(*sizep);
576 	setsp = of_get_property(np, propnames[1], NULL);
577 	if (setsp != NULL)
578 		sets = be32_to_cpu(*setsp);
579 	bsizep = of_get_property(np, propnames[2], NULL);
580 	lsizep = of_get_property(np, propnames[3], NULL);
581 	if (bsizep == NULL)
582 		bsizep = lsizep;
583 	if (lsizep == NULL)
584 		lsizep = bsizep;
585 	if (lsizep != NULL)
586 		lsize = be32_to_cpu(*lsizep);
587 	if (bsizep != NULL)
588 		bsize = be32_to_cpu(*bsizep);
589 	if (sizep == NULL || bsizep == NULL || lsizep == NULL)
590 		success = false;
591 
592 	/*
593 	 * OF is weird .. it represents fully associative caches
594 	 * as "1 way" which doesn't make much sense and doesn't
595 	 * leave room for direct mapped. We'll assume that 0
596 	 * in OF means direct mapped for that reason.
597 	 */
598 	if (sets == 1)
599 		sets = 0;
600 	else if (sets == 0)
601 		sets = 1;
602 
603 	init_cache_info(info, size, lsize, bsize, sets);
604 
605 	return success;
606 }
607 
initialize_cache_info(void)608 void __init initialize_cache_info(void)
609 {
610 	struct device_node *cpu = NULL, *l2, *l3 = NULL;
611 	u32 pvr;
612 
613 	/*
614 	 * All shipping POWER8 machines have a firmware bug that
615 	 * puts incorrect information in the device-tree. This will
616 	 * be (hopefully) fixed for future chips but for now hard
617 	 * code the values if we are running on one of these
618 	 */
619 	pvr = PVR_VER(mfspr(SPRN_PVR));
620 	if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
621 	    pvr == PVR_POWER8NVL) {
622 						/* size    lsize   blk  sets */
623 		init_cache_info(&ppc64_caches.l1i, 0x8000,   128,  128, 32);
624 		init_cache_info(&ppc64_caches.l1d, 0x10000,  128,  128, 64);
625 		init_cache_info(&ppc64_caches.l2,  0x80000,  128,  0,   512);
626 		init_cache_info(&ppc64_caches.l3,  0x800000, 128,  0,   8192);
627 	} else
628 		cpu = of_find_node_by_type(NULL, "cpu");
629 
630 	/*
631 	 * We're assuming *all* of the CPUs have the same
632 	 * d-cache and i-cache sizes... -Peter
633 	 */
634 	if (cpu) {
635 		if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
636 			pr_warn("Argh, can't find dcache properties !\n");
637 
638 		if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
639 			pr_warn("Argh, can't find icache properties !\n");
640 
641 		/*
642 		 * Try to find the L2 and L3 if any. Assume they are
643 		 * unified and use the D-side properties.
644 		 */
645 		l2 = of_find_next_cache_node(cpu);
646 		of_node_put(cpu);
647 		if (l2) {
648 			parse_cache_info(l2, false, &ppc64_caches.l2);
649 			l3 = of_find_next_cache_node(l2);
650 			of_node_put(l2);
651 		}
652 		if (l3) {
653 			parse_cache_info(l3, false, &ppc64_caches.l3);
654 			of_node_put(l3);
655 		}
656 	}
657 
658 	/* For use by binfmt_elf */
659 	dcache_bsize = ppc64_caches.l1d.block_size;
660 	icache_bsize = ppc64_caches.l1i.block_size;
661 
662 	cur_cpu_spec->dcache_bsize = dcache_bsize;
663 	cur_cpu_spec->icache_bsize = icache_bsize;
664 }
665 
666 /*
667  * This returns the limit below which memory accesses to the linear
668  * mapping are guarnateed not to cause an architectural exception (e.g.,
669  * TLB or SLB miss fault).
670  *
671  * This is used to allocate PACAs and various interrupt stacks that
672  * that are accessed early in interrupt handlers that must not cause
673  * re-entrant interrupts.
674  */
ppc64_bolted_size(void)675 __init u64 ppc64_bolted_size(void)
676 {
677 #ifdef CONFIG_PPC_BOOK3E
678 	/* Freescale BookE bolts the entire linear mapping */
679 	/* XXX: BookE ppc64_rma_limit setup seems to disagree? */
680 	if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E))
681 		return linear_map_top;
682 	/* Other BookE, we assume the first GB is bolted */
683 	return 1ul << 30;
684 #else
685 	/* BookS radix, does not take faults on linear mapping */
686 	if (early_radix_enabled())
687 		return ULONG_MAX;
688 
689 	/* BookS hash, the first segment is bolted */
690 	if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT))
691 		return 1UL << SID_SHIFT_1T;
692 	return 1UL << SID_SHIFT;
693 #endif
694 }
695 
alloc_stack(unsigned long limit,int cpu)696 static void *__init alloc_stack(unsigned long limit, int cpu)
697 {
698 	void *ptr;
699 
700 	BUILD_BUG_ON(STACK_INT_FRAME_SIZE % 16);
701 
702 	ptr = memblock_alloc_try_nid(THREAD_SIZE, THREAD_ALIGN,
703 				     MEMBLOCK_LOW_LIMIT, limit,
704 				     early_cpu_to_node(cpu));
705 	if (!ptr)
706 		panic("cannot allocate stacks");
707 
708 	return ptr;
709 }
710 
irqstack_early_init(void)711 void __init irqstack_early_init(void)
712 {
713 	u64 limit = ppc64_bolted_size();
714 	unsigned int i;
715 
716 	/*
717 	 * Interrupt stacks must be in the first segment since we
718 	 * cannot afford to take SLB misses on them. They are not
719 	 * accessed in realmode.
720 	 */
721 	for_each_possible_cpu(i) {
722 		softirq_ctx[i] = alloc_stack(limit, i);
723 		hardirq_ctx[i] = alloc_stack(limit, i);
724 	}
725 }
726 
727 #ifdef CONFIG_PPC_BOOK3E
exc_lvl_early_init(void)728 void __init exc_lvl_early_init(void)
729 {
730 	unsigned int i;
731 
732 	for_each_possible_cpu(i) {
733 		void *sp;
734 
735 		sp = alloc_stack(ULONG_MAX, i);
736 		critirq_ctx[i] = sp;
737 		paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE;
738 
739 		sp = alloc_stack(ULONG_MAX, i);
740 		dbgirq_ctx[i] = sp;
741 		paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE;
742 
743 		sp = alloc_stack(ULONG_MAX, i);
744 		mcheckirq_ctx[i] = sp;
745 		paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE;
746 	}
747 
748 	if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
749 		patch_exception(0x040, exc_debug_debug_book3e);
750 }
751 #endif
752 
753 /*
754  * Stack space used when we detect a bad kernel stack pointer, and
755  * early in SMP boots before relocation is enabled. Exclusive emergency
756  * stack for machine checks.
757  */
emergency_stack_init(void)758 void __init emergency_stack_init(void)
759 {
760 	u64 limit, mce_limit;
761 	unsigned int i;
762 
763 	/*
764 	 * Emergency stacks must be under 256MB, we cannot afford to take
765 	 * SLB misses on them. The ABI also requires them to be 128-byte
766 	 * aligned.
767 	 *
768 	 * Since we use these as temporary stacks during secondary CPU
769 	 * bringup, machine check, system reset, and HMI, we need to get
770 	 * at them in real mode. This means they must also be within the RMO
771 	 * region.
772 	 *
773 	 * The IRQ stacks allocated elsewhere in this file are zeroed and
774 	 * initialized in kernel/irq.c. These are initialized here in order
775 	 * to have emergency stacks available as early as possible.
776 	 */
777 	limit = mce_limit = min(ppc64_bolted_size(), ppc64_rma_size);
778 
779 	/*
780 	 * Machine check on pseries calls rtas, but can't use the static
781 	 * rtas_args due to a machine check hitting while the lock is held.
782 	 * rtas args have to be under 4GB, so the machine check stack is
783 	 * limited to 4GB so args can be put on stack.
784 	 */
785 	if (firmware_has_feature(FW_FEATURE_LPAR) && mce_limit > SZ_4G)
786 		mce_limit = SZ_4G;
787 
788 	for_each_possible_cpu(i) {
789 		paca_ptrs[i]->emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
790 
791 #ifdef CONFIG_PPC_BOOK3S_64
792 		/* emergency stack for NMI exception handling. */
793 		paca_ptrs[i]->nmi_emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
794 
795 		/* emergency stack for machine check exception handling. */
796 		paca_ptrs[i]->mc_emergency_sp = alloc_stack(mce_limit, i) + THREAD_SIZE;
797 #endif
798 	}
799 }
800 
801 #ifdef CONFIG_SMP
pcpu_cpu_distance(unsigned int from,unsigned int to)802 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
803 {
804 	if (early_cpu_to_node(from) == early_cpu_to_node(to))
805 		return LOCAL_DISTANCE;
806 	else
807 		return REMOTE_DISTANCE;
808 }
809 
pcpu_cpu_to_node(int cpu)810 static __init int pcpu_cpu_to_node(int cpu)
811 {
812 	return early_cpu_to_node(cpu);
813 }
814 
815 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
816 EXPORT_SYMBOL(__per_cpu_offset);
817 
setup_per_cpu_areas(void)818 void __init setup_per_cpu_areas(void)
819 {
820 	const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
821 	size_t atom_size;
822 	unsigned long delta;
823 	unsigned int cpu;
824 	int rc = -EINVAL;
825 
826 	/*
827 	 * BookE and BookS radix are historical values and should be revisited.
828 	 */
829 	if (IS_ENABLED(CONFIG_PPC_BOOK3E)) {
830 		atom_size = SZ_1M;
831 	} else if (radix_enabled()) {
832 		atom_size = PAGE_SIZE;
833 	} else if (IS_ENABLED(CONFIG_PPC_64S_HASH_MMU)) {
834 		/*
835 		 * Linear mapping is one of 4K, 1M and 16M.  For 4K, no need
836 		 * to group units.  For larger mappings, use 1M atom which
837 		 * should be large enough to contain a number of units.
838 		 */
839 		if (mmu_linear_psize == MMU_PAGE_4K)
840 			atom_size = PAGE_SIZE;
841 		else
842 			atom_size = SZ_1M;
843 	}
844 
845 	if (pcpu_chosen_fc != PCPU_FC_PAGE) {
846 		rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
847 					    pcpu_cpu_to_node);
848 		if (rc)
849 			pr_warn("PERCPU: %s allocator failed (%d), "
850 				"falling back to page size\n",
851 				pcpu_fc_names[pcpu_chosen_fc], rc);
852 	}
853 
854 	if (rc < 0)
855 		rc = pcpu_page_first_chunk(0, pcpu_cpu_to_node);
856 	if (rc < 0)
857 		panic("cannot initialize percpu area (err=%d)", rc);
858 
859 	delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
860 	for_each_possible_cpu(cpu) {
861                 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
862 		paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu];
863 	}
864 }
865 #endif
866 
867 #ifdef CONFIG_MEMORY_HOTPLUG
memory_block_size_bytes(void)868 unsigned long memory_block_size_bytes(void)
869 {
870 	if (ppc_md.memory_block_size)
871 		return ppc_md.memory_block_size();
872 
873 	return MIN_MEMORY_BLOCK_SIZE;
874 }
875 #endif
876 
877 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
878 struct ppc_pci_io ppc_pci_io;
879 EXPORT_SYMBOL(ppc_pci_io);
880 #endif
881 
882 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
hw_nmi_get_sample_period(int watchdog_thresh)883 u64 hw_nmi_get_sample_period(int watchdog_thresh)
884 {
885 	return ppc_proc_freq * watchdog_thresh;
886 }
887 #endif
888 
889 /*
890  * The perf based hardlockup detector breaks PMU event based branches, so
891  * disable it by default. Book3S has a soft-nmi hardlockup detector based
892  * on the decrementer interrupt, so it does not suffer from this problem.
893  *
894  * It is likely to get false positives in KVM guests, so disable it there
895  * by default too. PowerVM will not stop or arbitrarily oversubscribe
896  * CPUs, but give a minimum regular allotment even with SPLPAR, so enable
897  * the detector for non-KVM guests, assume PowerVM.
898  */
disable_hardlockup_detector(void)899 static int __init disable_hardlockup_detector(void)
900 {
901 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
902 	hardlockup_detector_disable();
903 #else
904 	if (firmware_has_feature(FW_FEATURE_LPAR)) {
905 		if (is_kvm_guest())
906 			hardlockup_detector_disable();
907 	}
908 #endif
909 
910 	return 0;
911 }
912 early_initcall(disable_hardlockup_detector);
913