1 #ifndef __MV64340_ETH_H__ 2 #define __MV64340_ETH_H__ 3 4 #include <linux/config.h> 5 #include <linux/version.h> 6 #include <linux/module.h> 7 #include <linux/kernel.h> 8 #include <linux/config.h> 9 #include <linux/spinlock.h> 10 11 #include <asm/mv64340.h> 12 13 #define BIT0 0x00000001 14 #define BIT1 0x00000002 15 #define BIT2 0x00000004 16 #define BIT3 0x00000008 17 #define BIT4 0x00000010 18 #define BIT5 0x00000020 19 #define BIT6 0x00000040 20 #define BIT7 0x00000080 21 #define BIT8 0x00000100 22 #define BIT9 0x00000200 23 #define BIT10 0x00000400 24 #define BIT11 0x00000800 25 #define BIT12 0x00001000 26 #define BIT13 0x00002000 27 #define BIT14 0x00004000 28 #define BIT15 0x00008000 29 #define BIT16 0x00010000 30 #define BIT17 0x00020000 31 #define BIT18 0x00040000 32 #define BIT19 0x00080000 33 #define BIT20 0x00100000 34 #define BIT21 0x00200000 35 #define BIT22 0x00400000 36 #define BIT23 0x00800000 37 #define BIT24 0x01000000 38 #define BIT25 0x02000000 39 #define BIT26 0x04000000 40 #define BIT27 0x08000000 41 #define BIT28 0x10000000 42 #define BIT29 0x20000000 43 #define BIT30 0x40000000 44 #define BIT31 0x80000000 45 46 /************************************************************************* 47 ************************************************************************** 48 ************************************************************************** 49 * The first part is the high level driver of the gigE ethernet ports. * 50 ************************************************************************** 51 ************************************************************************** 52 *************************************************************************/ 53 54 #define ETH_PORT0_IRQ_NUM 48 /* main high register, bit0 */ 55 #define ETH_PORT1_IRQ_NUM ETH_PORT0_IRQ_NUM+1 /* main high register, bit1 */ 56 #define ETH_PORT2_IRQ_NUM ETH_PORT0_IRQ_NUM+2 /* main high register, bit1 */ 57 58 /* Checksum offload for Tx works */ 59 #define MV64340_CHECKSUM_OFFLOAD_TX 1 60 #define MV64340_NAPI 1 61 #define MV64340_TX_FAST_REFILL 1 62 #undef MV64340_COAL 63 64 /* 65 * Number of RX / TX descriptors on RX / TX rings. 66 * Note that allocating RX descriptors is done by allocating the RX 67 * ring AND a preallocated RX buffers (skb's) for each descriptor. 68 * The TX descriptors only allocates the TX descriptors ring, 69 * with no pre allocated TX buffers (skb's are allocated by higher layers. 70 */ 71 72 /* Default TX ring size is 1000 descriptors */ 73 #define MV64340_TX_QUEUE_SIZE 1000 74 75 /* Default RX ring size is 400 descriptors */ 76 #define MV64340_RX_QUEUE_SIZE 400 77 78 #define MV64340_TX_COAL 100 79 #ifdef MV64340_COAL 80 #define MV64340_RX_COAL 100 81 #endif 82 83 /* Private data structure used for ethernet device */ 84 struct mv64340_eth_priv { 85 unsigned int port_num; 86 struct net_device_stats stats; 87 spinlock_t lock; 88 /* Size of Tx Ring per queue */ 89 unsigned int tx_ring_size; 90 /* Ammont of SKBs outstanding on Tx queue */ 91 unsigned int tx_ring_skbs; 92 /* Size of Rx Ring per queue */ 93 unsigned int rx_ring_size; 94 /* Ammount of SKBs allocated to Rx Ring per queue */ 95 unsigned int rx_ring_skbs; 96 97 /* 98 * rx_task used to fill RX ring out of bottom half context 99 */ 100 struct tq_struct rx_task; 101 102 /* 103 * Used in case RX Ring is empty, which can be caused when 104 * system does not have resources (skb's) 105 */ 106 struct timer_list timeout; 107 long rx_task_busy __attribute__ ((aligned(SMP_CACHE_BYTES))); 108 unsigned rx_timer_flag; 109 110 u32 rx_int_coal; 111 u32 tx_int_coal; 112 }; 113 114 115 /************************************************************************* 116 ************************************************************************** 117 ************************************************************************** 118 * The second part is the low level driver of the gigE ethernet ports. * 119 ************************************************************************** 120 ************************************************************************** 121 *************************************************************************/ 122 123 124 /******************************************************************************** 125 * Header File for : MV-643xx network interface header 126 * 127 * DESCRIPTION: 128 * This header file contains macros typedefs and function declaration for 129 * the Marvell Gig Bit Ethernet Controller. 130 * 131 * DEPENDENCIES: 132 * None. 133 * 134 *******************************************************************************/ 135 136 typedef enum _bool { false, true } bool; 137 138 /* defines */ 139 140 /* Default port configuration value */ 141 #define PORT_CONFIG_VALUE \ 142 ETH_UNICAST_NORMAL_MODE | \ 143 ETH_DEFAULT_RX_QUEUE_0 | \ 144 ETH_DEFAULT_RX_ARP_QUEUE_0 | \ 145 ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ 146 ETH_RECEIVE_BC_IF_IP | \ 147 ETH_RECEIVE_BC_IF_ARP | \ 148 ETH_CAPTURE_TCP_FRAMES_DIS | \ 149 ETH_CAPTURE_UDP_FRAMES_DIS | \ 150 ETH_DEFAULT_RX_TCP_QUEUE_0 | \ 151 ETH_DEFAULT_RX_UDP_QUEUE_0 | \ 152 ETH_DEFAULT_RX_BPDU_QUEUE_0 153 154 /* Default port extend configuration value */ 155 #define PORT_CONFIG_EXTEND_VALUE \ 156 ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ 157 ETH_PARTITION_DISABLE 158 159 160 /* Default sdma control value */ 161 #define PORT_SDMA_CONFIG_VALUE \ 162 ETH_RX_BURST_SIZE_16_64BIT | \ 163 GT_ETH_IPG_INT_RX(0) | \ 164 ETH_TX_BURST_SIZE_16_64BIT; 165 166 #define GT_ETH_IPG_INT_RX(value) \ 167 ((value & 0x3fff) << 8) 168 169 /* Default port serial control value */ 170 #define PORT_SERIAL_CONTROL_VALUE \ 171 ETH_FORCE_LINK_PASS | \ 172 ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ 173 ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ 174 ETH_ADV_SYMMETRIC_FLOW_CTRL | \ 175 ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 176 ETH_FORCE_BP_MODE_NO_JAM | \ 177 BIT9 | \ 178 ETH_DO_NOT_FORCE_LINK_FAIL | \ 179 ETH_RETRANSMIT_16_ATTEMPTS | \ 180 ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ 181 ETH_DTE_ADV_0 | \ 182 ETH_DISABLE_AUTO_NEG_BYPASS | \ 183 ETH_AUTO_NEG_NO_CHANGE | \ 184 ETH_MAX_RX_PACKET_9700BYTE | \ 185 ETH_CLR_EXT_LOOPBACK | \ 186 ETH_SET_FULL_DUPLEX_MODE | \ 187 ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 188 189 #define RX_BUFFER_MAX_SIZE 0x4000000 190 #define TX_BUFFER_MAX_SIZE 0x4000000 191 192 /* MAC accepet/reject macros */ 193 #define ACCEPT_MAC_ADDR 0 194 #define REJECT_MAC_ADDR 1 195 196 /* Buffer offset from buffer pointer */ 197 #define RX_BUF_OFFSET 0x2 198 199 /* Gigabit Ethernet Unit Global Registers */ 200 201 /* MIB Counters register definitions */ 202 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 203 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 204 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 205 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc 206 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 207 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 208 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 209 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c 210 #define ETH_MIB_FRAMES_64_OCTETS 0x20 211 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 212 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 213 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c 214 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 215 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 216 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 217 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c 218 #define ETH_MIB_GOOD_FRAMES_SENT 0x40 219 #define ETH_MIB_EXCESSIVE_COLLISION 0x44 220 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 221 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c 222 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 223 #define ETH_MIB_FC_SENT 0x54 224 #define ETH_MIB_GOOD_FC_RECEIVED 0x58 225 #define ETH_MIB_BAD_FC_RECEIVED 0x5c 226 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60 227 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64 228 #define ETH_MIB_OVERSIZE_RECEIVED 0x68 229 #define ETH_MIB_JABBER_RECEIVED 0x6c 230 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70 231 #define ETH_MIB_BAD_CRC_EVENT 0x74 232 #define ETH_MIB_COLLISION 0x78 233 #define ETH_MIB_LATE_COLLISION 0x7c 234 235 /* Port serial status reg (PSR) */ 236 #define ETH_INTERFACE_GMII_MII 0 237 #define ETH_INTERFACE_PCM BIT0 238 #define ETH_LINK_IS_DOWN 0 239 #define ETH_LINK_IS_UP BIT1 240 #define ETH_PORT_AT_HALF_DUPLEX 0 241 #define ETH_PORT_AT_FULL_DUPLEX BIT2 242 #define ETH_RX_FLOW_CTRL_DISABLED 0 243 #define ETH_RX_FLOW_CTRL_ENBALED BIT3 244 #define ETH_GMII_SPEED_100_10 0 245 #define ETH_GMII_SPEED_1000 BIT4 246 #define ETH_MII_SPEED_10 0 247 #define ETH_MII_SPEED_100 BIT5 248 #define ETH_NO_TX 0 249 #define ETH_TX_IN_PROGRESS BIT7 250 #define ETH_BYPASS_NO_ACTIVE 0 251 #define ETH_BYPASS_ACTIVE BIT8 252 #define ETH_PORT_NOT_AT_PARTITION_STATE 0 253 #define ETH_PORT_AT_PARTITION_STATE BIT9 254 #define ETH_PORT_TX_FIFO_NOT_EMPTY 0 255 #define ETH_PORT_TX_FIFO_EMPTY BIT10 256 257 258 /* These macros describes the Port configuration reg (Px_cR) bits */ 259 #define ETH_UNICAST_NORMAL_MODE 0 260 #define ETH_UNICAST_PROMISCUOUS_MODE BIT0 261 #define ETH_DEFAULT_RX_QUEUE_0 0 262 #define ETH_DEFAULT_RX_QUEUE_1 BIT1 263 #define ETH_DEFAULT_RX_QUEUE_2 BIT2 264 #define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1) 265 #define ETH_DEFAULT_RX_QUEUE_4 BIT3 266 #define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1) 267 #define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2) 268 #define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1) 269 #define ETH_DEFAULT_RX_ARP_QUEUE_0 0 270 #define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4 271 #define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5 272 #define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4) 273 #define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6 274 #define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4) 275 #define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5) 276 #define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4) 277 #define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 278 #define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7 279 #define ETH_RECEIVE_BC_IF_IP 0 280 #define ETH_REJECT_BC_IF_IP BIT8 281 #define ETH_RECEIVE_BC_IF_ARP 0 282 #define ETH_REJECT_BC_IF_ARP BIT9 283 #define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12 284 #define ETH_CAPTURE_TCP_FRAMES_DIS 0 285 #define ETH_CAPTURE_TCP_FRAMES_EN BIT14 286 #define ETH_CAPTURE_UDP_FRAMES_DIS 0 287 #define ETH_CAPTURE_UDP_FRAMES_EN BIT15 288 #define ETH_DEFAULT_RX_TCP_QUEUE_0 0 289 #define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16 290 #define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17 291 #define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16) 292 #define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18 293 #define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16) 294 #define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17) 295 #define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16) 296 #define ETH_DEFAULT_RX_UDP_QUEUE_0 0 297 #define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19 298 #define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20 299 #define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19) 300 #define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21 301 #define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19) 302 #define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20) 303 #define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19) 304 #define ETH_DEFAULT_RX_BPDU_QUEUE_0 0 305 #define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22 306 #define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23 307 #define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22) 308 #define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24 309 #define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22) 310 #define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23) 311 #define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22) 312 313 314 /* These macros describes the Port configuration extend reg (Px_cXR) bits*/ 315 #define ETH_CLASSIFY_EN BIT0 316 #define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 317 #define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1 318 #define ETH_PARTITION_DISABLE 0 319 #define ETH_PARTITION_ENABLE BIT2 320 321 322 /* Tx/Rx queue command reg (RQCR/TQCR)*/ 323 #define ETH_QUEUE_0_ENABLE BIT0 324 #define ETH_QUEUE_1_ENABLE BIT1 325 #define ETH_QUEUE_2_ENABLE BIT2 326 #define ETH_QUEUE_3_ENABLE BIT3 327 #define ETH_QUEUE_4_ENABLE BIT4 328 #define ETH_QUEUE_5_ENABLE BIT5 329 #define ETH_QUEUE_6_ENABLE BIT6 330 #define ETH_QUEUE_7_ENABLE BIT7 331 #define ETH_QUEUE_0_DISABLE BIT8 332 #define ETH_QUEUE_1_DISABLE BIT9 333 #define ETH_QUEUE_2_DISABLE BIT10 334 #define ETH_QUEUE_3_DISABLE BIT11 335 #define ETH_QUEUE_4_DISABLE BIT12 336 #define ETH_QUEUE_5_DISABLE BIT13 337 #define ETH_QUEUE_6_DISABLE BIT14 338 #define ETH_QUEUE_7_DISABLE BIT15 339 340 341 /* These macros describes the Port Sdma configuration reg (SDCR) bits */ 342 #define ETH_RIFB BIT0 343 #define ETH_RX_BURST_SIZE_1_64BIT 0 344 #define ETH_RX_BURST_SIZE_2_64BIT BIT1 345 #define ETH_RX_BURST_SIZE_4_64BIT BIT2 346 #define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1) 347 #define ETH_RX_BURST_SIZE_16_64BIT BIT3 348 #define ETH_BLM_RX_NO_SWAP BIT4 349 #define ETH_BLM_RX_BYTE_SWAP 0 350 #define ETH_BLM_TX_NO_SWAP BIT5 351 #define ETH_BLM_TX_BYTE_SWAP 0 352 #define ETH_DESCRIPTORS_BYTE_SWAP BIT6 353 #define ETH_DESCRIPTORS_NO_SWAP 0 354 #define ETH_TX_BURST_SIZE_1_64BIT 0 355 #define ETH_TX_BURST_SIZE_2_64BIT BIT22 356 #define ETH_TX_BURST_SIZE_4_64BIT BIT23 357 #define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22) 358 #define ETH_TX_BURST_SIZE_16_64BIT BIT24 359 360 361 362 /* These macros describes the Port serial control reg (PSCR) bits */ 363 #define ETH_SERIAL_PORT_DISABLE 0 364 #define ETH_SERIAL_PORT_ENABLE BIT0 365 #define ETH_FORCE_LINK_PASS BIT1 366 #define ETH_DO_NOT_FORCE_LINK_PASS 0 367 #define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 368 #define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2 369 #define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 370 #define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3 371 #define ETH_ADV_NO_FLOW_CTRL 0 372 #define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4 373 #define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 374 #define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5 375 #define ETH_FORCE_BP_MODE_NO_JAM 0 376 #define ETH_FORCE_BP_MODE_JAM_TX BIT7 377 #define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8 378 #define ETH_FORCE_LINK_FAIL 0 379 #define ETH_DO_NOT_FORCE_LINK_FAIL BIT10 380 #define ETH_RETRANSMIT_16_ATTEMPTS 0 381 #define ETH_RETRANSMIT_FOREVER BIT11 382 #define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13 383 #define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 384 #define ETH_DTE_ADV_0 0 385 #define ETH_DTE_ADV_1 BIT14 386 #define ETH_DISABLE_AUTO_NEG_BYPASS 0 387 #define ETH_ENABLE_AUTO_NEG_BYPASS BIT15 388 #define ETH_AUTO_NEG_NO_CHANGE 0 389 #define ETH_RESTART_AUTO_NEG BIT16 390 #define ETH_MAX_RX_PACKET_1518BYTE 0 391 #define ETH_MAX_RX_PACKET_1522BYTE BIT17 392 #define ETH_MAX_RX_PACKET_1552BYTE BIT18 393 #define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17) 394 #define ETH_MAX_RX_PACKET_9192BYTE BIT19 395 #define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17) 396 #define ETH_SET_EXT_LOOPBACK BIT20 397 #define ETH_CLR_EXT_LOOPBACK 0 398 #define ETH_SET_FULL_DUPLEX_MODE BIT21 399 #define ETH_SET_HALF_DUPLEX_MODE 0 400 #define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22 401 #define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 402 #define ETH_SET_GMII_SPEED_TO_10_100 0 403 #define ETH_SET_GMII_SPEED_TO_1000 BIT23 404 #define ETH_SET_MII_SPEED_TO_10 0 405 #define ETH_SET_MII_SPEED_TO_100 BIT24 406 407 408 /* SMI reg */ 409 #define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */ 410 #define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */ 411 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */ 412 #define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */ 413 414 /* SDMA command status fields macros */ 415 416 /* Tx & Rx descriptors status */ 417 #define ETH_ERROR_SUMMARY (BIT0) 418 419 /* Tx & Rx descriptors command */ 420 #define ETH_BUFFER_OWNED_BY_DMA (BIT31) 421 422 /* Tx descriptors status */ 423 #define ETH_LC_ERROR (0 ) 424 #define ETH_UR_ERROR (BIT1 ) 425 #define ETH_RL_ERROR (BIT2 ) 426 #define ETH_LLC_SNAP_FORMAT (BIT9 ) 427 428 /* Rx descriptors status */ 429 #define ETH_CRC_ERROR (0 ) 430 #define ETH_OVERRUN_ERROR (BIT1 ) 431 #define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 ) 432 #define ETH_RESOURCE_ERROR ((BIT2 | BIT1)) 433 #define ETH_VLAN_TAGGED (BIT19) 434 #define ETH_BPDU_FRAME (BIT20) 435 #define ETH_TCP_FRAME_OVER_IP_V_4 (0 ) 436 #define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21) 437 #define ETH_OTHER_FRAME_TYPE (BIT22) 438 #define ETH_LAYER_2_IS_ETH_V_2 (BIT23) 439 #define ETH_FRAME_TYPE_IP_V_4 (BIT24) 440 #define ETH_FRAME_HEADER_OK (BIT25) 441 #define ETH_RX_LAST_DESC (BIT26) 442 #define ETH_RX_FIRST_DESC (BIT27) 443 #define ETH_UNKNOWN_DESTINATION_ADDR (BIT28) 444 #define ETH_RX_ENABLE_INTERRUPT (BIT29) 445 #define ETH_LAYER_4_CHECKSUM_OK (BIT30) 446 447 /* Rx descriptors byte count */ 448 #define ETH_FRAME_FRAGMENTED (BIT2) 449 450 /* Tx descriptors command */ 451 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10) 452 #define ETH_FRAME_SET_TO_VLAN (BIT15) 453 #define ETH_TCP_FRAME (0 ) 454 #define ETH_UDP_FRAME (BIT16) 455 #define ETH_GEN_TCP_UDP_CHECKSUM (BIT17) 456 #define ETH_GEN_IP_V_4_CHECKSUM (BIT18) 457 #define ETH_ZERO_PADDING (BIT19) 458 #define ETH_TX_LAST_DESC (BIT20) 459 #define ETH_TX_FIRST_DESC (BIT21) 460 #define ETH_GEN_CRC (BIT22) 461 #define ETH_TX_ENABLE_INTERRUPT (BIT23) 462 #define ETH_AUTO_MODE (BIT30) 463 464 /* typedefs */ 465 466 typedef enum _eth_port { 467 ETH_0 = 0, 468 ETH_1 = 1, 469 ETH_2 = 2 470 } ETH_PORT; 471 472 typedef enum _eth_func_ret_status { 473 ETH_OK, /* Returned as expected. */ 474 ETH_ERROR, /* Fundamental error. */ 475 ETH_RETRY, /* Could not process request. Try later. */ 476 ETH_END_OF_JOB, /* Ring has nothing to process. */ 477 ETH_QUEUE_FULL, /* Ring resource error. */ 478 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ 479 } ETH_FUNC_RET_STATUS; 480 481 typedef enum _eth_target { 482 ETH_TARGET_DRAM, 483 ETH_TARGET_DEVICE, 484 ETH_TARGET_CBS, 485 ETH_TARGET_PCI0, 486 ETH_TARGET_PCI1 487 } ETH_TARGET; 488 489 /* These are for big-endian machines. Little endian needs different 490 * definitions. 491 */ 492 #if defined(__BIG_ENDIAN) 493 typedef struct _eth_rx_desc { 494 u16 byte_cnt; /* Descriptor buffer byte count */ 495 u16 buf_size; /* Buffer size */ 496 u32 cmd_sts; /* Descriptor command status */ 497 u32 next_desc_ptr; /* Next descriptor pointer */ 498 u32 buf_ptr; /* Descriptor buffer pointer */ 499 } ETH_RX_DESC; 500 501 typedef struct _eth_tx_desc { 502 u16 byte_cnt; /* buffer byte count */ 503 u16 l4i_chk; /* CPU provided TCP checksum */ 504 u32 cmd_sts; /* Command/status field */ 505 u32 next_desc_ptr; /* Pointer to next descriptor */ 506 u32 buf_ptr; /* pointer to buffer for this descriptor */ 507 } ETH_TX_DESC; 508 509 #elif defined(__LITTLE_ENDIAN) 510 typedef struct _eth_rx_desc { 511 u32 cmd_sts; /* Descriptor command status */ 512 u16 buf_size; /* Buffer size */ 513 u16 byte_cnt; /* Descriptor buffer byte count */ 514 u32 buf_ptr; /* Descriptor buffer pointer */ 515 u32 next_desc_ptr; /* Next descriptor pointer */ 516 } ETH_RX_DESC; 517 518 typedef struct _eth_tx_desc { 519 u32 cmd_sts; /* Command/status field */ 520 u16 l4i_chk; /* CPU provided TCP checksum */ 521 u16 byte_cnt; /* buffer byte count */ 522 u32 buf_ptr; /* pointer to buffer for this descriptor */ 523 u32 next_desc_ptr; /* Pointer to next descriptor */ 524 } ETH_TX_DESC; 525 #else 526 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined 527 #endif 528 529 /* Unified struct for Rx and Tx operations. The user is not required to */ 530 /* be familier with neither Tx nor Rx descriptors. */ 531 typedef struct _pkt_info { 532 unsigned short byte_cnt; /* Descriptor buffer byte count */ 533 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */ 534 unsigned int cmd_sts; /* Descriptor command status */ 535 unsigned int buf_ptr; /* Descriptor buffer pointer */ 536 struct sk_buff* return_info; /* User resource return information */ 537 } PKT_INFO; 538 539 540 /* Ethernet port specific infomation */ 541 542 typedef struct _eth_port_ctrl { 543 ETH_PORT port_num; /* User Ethernet port number */ 544 u8 port_mac_addr[6]; /* User defined port MAC address. */ 545 u32 port_config; /* User port configuration value */ 546 u32 port_config_extend; /* User port config extend value */ 547 u32 port_sdma_config; /* User port SDMA config value */ 548 u32 port_serial_control; /* User port serial control value */ 549 u32 port_tx_queue_command; /* Port active Tx queues summary */ 550 u32 port_rx_queue_command; /* Port active Rx queues summary */ 551 552 /* User scratch pad for user specific data structures */ 553 void* port_private; 554 555 bool rx_resource_err; /* Rx ring resource error flag */ 556 bool tx_resource_err; /* Tx ring resource error flag */ 557 558 /* Tx/Rx rings managment indexes fields. For driver use */ 559 560 /* Next available and first returning Rx resource */ 561 int rx_curr_desc_q, rx_used_desc_q; 562 563 /* Next available and first returning Tx resource */ 564 int tx_curr_desc_q, tx_used_desc_q; 565 #ifdef MV64340_CHECKSUM_OFFLOAD_TX 566 int tx_first_desc_q; 567 #endif 568 569 #ifdef MV64340_TX_FAST_REFILL 570 u32 tx_clean_threshold; 571 #endif 572 573 /* Tx/Rx rings size and base variables fields. For driver use */ 574 volatile ETH_RX_DESC *p_rx_desc_area; 575 unsigned int rx_desc_area_size; 576 struct sk_buff* rx_skb[MV64340_RX_QUEUE_SIZE]; 577 578 volatile ETH_TX_DESC *p_tx_desc_area; 579 unsigned int tx_desc_area_size; 580 struct sk_buff* tx_skb[MV64340_TX_QUEUE_SIZE]; 581 struct tq_struct tx_timeout_task; 582 } ETH_PORT_INFO; 583 584 585 /* ethernet.h API list */ 586 587 /* Port operation control routines */ 588 static void eth_port_init(ETH_PORT_INFO * p_eth_port_ctrl); 589 static void eth_port_reset(ETH_PORT eth_port_num); 590 static bool eth_port_start(ETH_PORT_INFO * p_eth_port_ctrl); 591 592 static void ethernet_set_config_reg(ETH_PORT eth_port_num, 593 unsigned int value); 594 static unsigned int ethernet_get_config_reg(ETH_PORT eth_port_num); 595 596 /* Interrupt Coalesting functions */ 597 static unsigned int eth_port_set_rx_coal(ETH_PORT, unsigned int, 598 unsigned int); 599 static unsigned int eth_port_set_tx_coal(ETH_PORT, unsigned int, 600 unsigned int); 601 602 /* Port MAC address routines */ 603 static void eth_port_uc_addr_set(ETH_PORT eth_port_num, 604 unsigned char *p_addr); 605 606 /* PHY and MIB routines */ 607 static bool ethernet_phy_reset(ETH_PORT eth_port_num); 608 609 static bool eth_port_write_smi_reg(ETH_PORT eth_port_num, 610 unsigned int phy_reg, 611 unsigned int value); 612 613 static bool eth_port_read_smi_reg(ETH_PORT eth_port_num, 614 unsigned int phy_reg, 615 unsigned int *value); 616 617 static void eth_clear_mib_counters(ETH_PORT eth_port_num); 618 619 /* Port data flow control routines */ 620 static ETH_FUNC_RET_STATUS eth_port_send(ETH_PORT_INFO * p_eth_port_ctrl, 621 PKT_INFO * p_pkt_info); 622 static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO * 623 p_eth_port_ctrl, 624 PKT_INFO * p_pkt_info); 625 static ETH_FUNC_RET_STATUS eth_port_receive(ETH_PORT_INFO * 626 p_eth_port_ctrl, 627 PKT_INFO * p_pkt_info); 628 static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO * 629 p_eth_port_ctrl, 630 PKT_INFO * p_pkt_info); 631 632 633 static bool ether_init_tx_desc_ring(ETH_PORT_INFO * p_eth_port_ctrl, 634 int tx_desc_num, 635 unsigned long tx_desc_base_addr); 636 637 static bool ether_init_rx_desc_ring(ETH_PORT_INFO * p_eth_port_ctrl, 638 int rx_desc_num, 639 int rx_buff_size, 640 unsigned long rx_desc_base_addr, 641 unsigned long rx_buff_base_addr); 642 643 #endif /* MV64340_ETH_ */ 644