1 #include <linux/config.h>
2 #include <linux/stddef.h>
3 #include <linux/init.h>
4 #include <linux/sched.h>
5 #include <linux/signal.h>
6 #include <linux/pci.h>
7
8 #include <asm/sections.h>
9 #include <asm/io.h>
10 #include <asm/smp.h>
11 #include <asm/prom.h>
12 #include <asm/pci-bridge.h>
13 #include <asm/time.h>
14 #include <asm/open_pic.h>
15
16 #include "pmac_pic.h"
17
18 struct pmac_irq_hw {
19 unsigned int event;
20 unsigned int enable;
21 unsigned int ack;
22 unsigned int level;
23 };
24
25 /* Default addresses */
26 static volatile struct pmac_irq_hw *pmac_irq_hw[4] __pmacdata = {
27 (struct pmac_irq_hw *) 0xf3000020,
28 (struct pmac_irq_hw *) 0xf3000010,
29 (struct pmac_irq_hw *) 0xf4000020,
30 (struct pmac_irq_hw *) 0xf4000010,
31 };
32
33 #define GC_LEVEL_MASK 0x3ff00000
34 #define OHARE_LEVEL_MASK 0x1ff00000
35 #define HEATHROW_LEVEL_MASK 0x1ff00000
36
37 static int max_irqs __pmacdata;
38 static int max_real_irqs __pmacdata;
39 static u32 level_mask[4] __pmacdata;
40
41 static spinlock_t pmac_pic_lock __pmacdata = SPIN_LOCK_UNLOCKED;
42
43
44 #define GATWICK_IRQ_POOL_SIZE 10
45 static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE] __pmacdata;
46
47 /*
48 * Mark an irq as "lost". This is only used on the pmac
49 * since it can lose interrupts (see pmac_set_irq_mask).
50 * -- Cort
51 */
52 void __pmac
__set_lost(unsigned long irq_nr,int nokick)53 __set_lost(unsigned long irq_nr, int nokick)
54 {
55 if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
56 atomic_inc(&ppc_n_lost_interrupts);
57 if (!nokick)
58 set_dec(1);
59 }
60 }
61
62 static void __pmac
pmac_mask_and_ack_irq(unsigned int irq_nr)63 pmac_mask_and_ack_irq(unsigned int irq_nr)
64 {
65 unsigned long bit = 1UL << (irq_nr & 0x1f);
66 int i = irq_nr >> 5;
67 unsigned long flags;
68
69 if ((unsigned)irq_nr >= max_irqs)
70 return;
71
72 clear_bit(irq_nr, ppc_cached_irq_mask);
73 if (test_and_clear_bit(irq_nr, ppc_lost_interrupts))
74 atomic_dec(&ppc_n_lost_interrupts);
75 spin_lock_irqsave(&pmac_pic_lock, flags);
76 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
77 out_le32(&pmac_irq_hw[i]->ack, bit);
78 do {
79 /* make sure ack gets to controller before we enable
80 interrupts */
81 mb();
82 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
83 != (ppc_cached_irq_mask[i] & bit));
84 spin_unlock_irqrestore(&pmac_pic_lock, flags);
85 }
86
pmac_set_irq_mask(unsigned int irq_nr,int nokicklost)87 static void __pmac pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
88 {
89 unsigned long bit = 1UL << (irq_nr & 0x1f);
90 int i = irq_nr >> 5;
91 unsigned long flags;
92
93 if ((unsigned)irq_nr >= max_irqs)
94 return;
95
96 spin_lock_irqsave(&pmac_pic_lock, flags);
97 /* enable unmasked interrupts */
98 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
99
100 do {
101 /* make sure mask gets to controller before we
102 return to user */
103 mb();
104 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
105 != (ppc_cached_irq_mask[i] & bit));
106
107 /*
108 * Unfortunately, setting the bit in the enable register
109 * when the device interrupt is already on *doesn't* set
110 * the bit in the flag register or request another interrupt.
111 */
112 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
113 __set_lost((ulong)irq_nr, nokicklost);
114 spin_unlock_irqrestore(&pmac_pic_lock, flags);
115 }
116
pmac_mask_irq(unsigned int irq_nr)117 static void __pmac pmac_mask_irq(unsigned int irq_nr)
118 {
119 clear_bit(irq_nr, ppc_cached_irq_mask);
120 pmac_set_irq_mask(irq_nr, 0);
121 mb();
122 }
123
pmac_unmask_irq(unsigned int irq_nr)124 static void __pmac pmac_unmask_irq(unsigned int irq_nr)
125 {
126 set_bit(irq_nr, ppc_cached_irq_mask);
127 pmac_set_irq_mask(irq_nr, 0);
128 }
129
pmac_end_irq(unsigned int irq_nr)130 static void __pmac pmac_end_irq(unsigned int irq_nr)
131 {
132 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
133 set_bit(irq_nr, ppc_cached_irq_mask);
134 pmac_set_irq_mask(irq_nr, 1);
135 }
136 }
137
138
139 struct hw_interrupt_type pmac_pic = {
140 " PMAC-PIC ",
141 NULL,
142 NULL,
143 pmac_unmask_irq,
144 pmac_mask_irq,
145 pmac_mask_and_ack_irq,
146 pmac_end_irq,
147 NULL
148 };
149
150 struct hw_interrupt_type gatwick_pic = {
151 " GATWICK ",
152 NULL,
153 NULL,
154 pmac_unmask_irq,
155 pmac_mask_irq,
156 pmac_mask_and_ack_irq,
157 pmac_end_irq,
158 NULL
159 };
160
gatwick_action(int cpl,void * dev_id,struct pt_regs * regs)161 static void gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
162 {
163 int irq, bits;
164
165 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
166 int i = irq >> 5;
167 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
168 /* We must read level interrupts from the level register */
169 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
170 bits &= ppc_cached_irq_mask[i];
171 if (bits == 0)
172 continue;
173 irq += __ilog2(bits);
174 break;
175 }
176 /* The previous version of this code allowed for this case, we
177 * don't. Put this here to check for it.
178 * -- Cort
179 */
180 if ( irq_desc[irq].handler != &gatwick_pic )
181 printk("gatwick irq not from gatwick pic\n");
182 else
183 ppc_irq_dispatch_handler( regs, irq );
184 }
185
186 int
pmac_get_irq(struct pt_regs * regs)187 pmac_get_irq(struct pt_regs *regs)
188 {
189 int irq;
190 unsigned long bits = 0;
191
192 #ifdef CONFIG_SMP
193 void psurge_smp_message_recv(struct pt_regs *);
194
195 /* IPI's are a hack on the powersurge -- Cort */
196 if ( smp_processor_id() != 0 ) {
197 psurge_smp_message_recv(regs);
198 return -2; /* ignore, already handled */
199 }
200 #endif /* CONFIG_SMP */
201 for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
202 int i = irq >> 5;
203 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
204 /* We must read level interrupts from the level register */
205 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
206 bits &= ppc_cached_irq_mask[i];
207 if (bits == 0)
208 continue;
209 irq += __ilog2(bits);
210 break;
211 }
212
213 return irq;
214 }
215
216 /* This routine will fix some missing interrupt values in the device tree
217 * on the gatwick mac-io controller used by some PowerBooks
218 */
219 static void __init
pmac_fix_gatwick_interrupts(struct device_node * gw,int irq_base)220 pmac_fix_gatwick_interrupts(struct device_node *gw, int irq_base)
221 {
222 struct device_node *node;
223 int count;
224
225 memset(gatwick_int_pool, 0, sizeof(gatwick_int_pool));
226 node = gw->child;
227 count = 0;
228 while(node)
229 {
230 /* Fix SCC */
231 if (strcasecmp(node->name, "escc") == 0)
232 if (node->child) {
233 if (node->child->n_intrs < 3) {
234 node->child->intrs = &gatwick_int_pool[count];
235 count += 3;
236 }
237 node->child->n_intrs = 3;
238 node->child->intrs[0].line = 15+irq_base;
239 node->child->intrs[1].line = 4+irq_base;
240 node->child->intrs[2].line = 5+irq_base;
241 printk(KERN_INFO "irq: fixed SCC on second controller (%d,%d,%d)\n",
242 node->child->intrs[0].line,
243 node->child->intrs[1].line,
244 node->child->intrs[2].line);
245 }
246 /* Fix media-bay & left SWIM */
247 if (strcasecmp(node->name, "media-bay") == 0) {
248 struct device_node* ya_node;
249
250 if (node->n_intrs == 0)
251 node->intrs = &gatwick_int_pool[count++];
252 node->n_intrs = 1;
253 node->intrs[0].line = 29+irq_base;
254 printk(KERN_INFO "irq: fixed media-bay on second controller (%d)\n",
255 node->intrs[0].line);
256
257 ya_node = node->child;
258 while(ya_node)
259 {
260 if (strcasecmp(ya_node->name, "floppy") == 0) {
261 if (ya_node->n_intrs < 2) {
262 ya_node->intrs = &gatwick_int_pool[count];
263 count += 2;
264 }
265 ya_node->n_intrs = 2;
266 ya_node->intrs[0].line = 19+irq_base;
267 ya_node->intrs[1].line = 1+irq_base;
268 printk(KERN_INFO "irq: fixed floppy on second controller (%d,%d)\n",
269 ya_node->intrs[0].line, ya_node->intrs[1].line);
270 }
271 if (strcasecmp(ya_node->name, "ata4") == 0) {
272 if (ya_node->n_intrs < 2) {
273 ya_node->intrs = &gatwick_int_pool[count];
274 count += 2;
275 }
276 ya_node->n_intrs = 2;
277 ya_node->intrs[0].line = 14+irq_base;
278 ya_node->intrs[1].line = 3+irq_base;
279 printk(KERN_INFO "irq: fixed ide on second controller (%d,%d)\n",
280 ya_node->intrs[0].line, ya_node->intrs[1].line);
281 }
282 ya_node = ya_node->sibling;
283 }
284 }
285 node = node->sibling;
286 }
287 if (count > 10) {
288 printk("WARNING !! Gatwick interrupt pool overflow\n");
289 printk(" GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE);
290 printk(" requested = %d\n", count);
291 }
292 }
293
294 /*
295 * The PowerBook 3400/2400/3500 can have a combo ethernet/modem
296 * card which includes an ohare chip that acts as a second interrupt
297 * controller. If we find this second ohare, set it up and fix the
298 * interrupt value in the device tree for the ethernet chip.
299 */
enable_second_ohare(void)300 static int __init enable_second_ohare(void)
301 {
302 unsigned char bus, devfn;
303 unsigned short cmd;
304 unsigned long addr;
305 struct device_node *irqctrler = find_devices("pci106b,7");
306 struct device_node *ether;
307
308 if (irqctrler == NULL || irqctrler->n_addrs <= 0)
309 return -1;
310 addr = (unsigned long) ioremap(irqctrler->addrs[0].address, 0x40);
311 pmac_irq_hw[1] = (volatile struct pmac_irq_hw *)(addr + 0x20);
312 max_irqs = 64;
313 if (pci_device_from_OF_node(irqctrler, &bus, &devfn) == 0) {
314 struct pci_controller* hose = pci_find_hose_for_OF_device(irqctrler);
315 if (!hose)
316 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
317 else {
318 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
319 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
320 cmd &= ~PCI_COMMAND_IO;
321 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
322 }
323 }
324
325 /* Fix interrupt for the modem/ethernet combo controller. The number
326 in the device tree (27) is bogus (correct for the ethernet-only
327 board but not the combo ethernet/modem board).
328 The real interrupt is 28 on the second controller -> 28+32 = 60.
329 */
330 ether = find_devices("pci1011,14");
331 if (ether && ether->n_intrs > 0) {
332 ether->intrs[0].line = 60;
333 printk(KERN_INFO "irq: Fixed ethernet IRQ to %d\n",
334 ether->intrs[0].line);
335 }
336
337 /* Return the interrupt number of the cascade */
338 return irqctrler->intrs[0].line;
339 }
340
341 void __init
pmac_pic_init(void)342 pmac_pic_init(void)
343 {
344 int i;
345 struct device_node *irqctrler;
346 unsigned long addr;
347 int irq_cascade = -1;
348
349 /* We first try to detect Apple's new Core99 chipset, since mac-io
350 * is quite different on those machines and contains an IBM MPIC2.
351 */
352 irqctrler = find_type_devices("open-pic");
353 if (irqctrler != NULL)
354 {
355 printk("PowerMac using OpenPIC irq controller\n");
356 if (irqctrler->n_addrs > 0)
357 {
358 unsigned char senses[NR_IRQS];
359
360 prom_get_irq_senses(senses, 0, NR_IRQS);
361 OpenPIC_InitSenses = senses;
362 OpenPIC_NumInitSenses = NR_IRQS;
363 ppc_md.get_irq = openpic_get_irq;
364 OpenPIC_Addr = ioremap(irqctrler->addrs[0].address,
365 irqctrler->addrs[0].size);
366 openpic_init(0);
367 #ifdef CONFIG_XMON
368 {
369 struct device_node* pswitch;
370 int nmi_irq;
371
372 pswitch = find_devices("programmer-switch");
373 if (pswitch && pswitch->n_intrs) {
374 nmi_irq = pswitch->intrs[0].line;
375 openpic_init_nmi_irq(nmi_irq);
376 request_irq(nmi_irq, xmon_irq, 0,
377 "NMI - XMON", 0);
378 }
379 }
380 #endif /* CONFIG_XMON */
381 return;
382 }
383 irqctrler = NULL;
384 }
385
386 /* Get the level/edge settings, assume if it's not
387 * a Grand Central nor an OHare, then it's an Heathrow
388 * (or Paddington).
389 */
390 if (find_devices("gc"))
391 level_mask[0] = GC_LEVEL_MASK;
392 else if (find_devices("ohare")) {
393 level_mask[0] = OHARE_LEVEL_MASK;
394 /* We might have a second cascaded ohare */
395 level_mask[1] = OHARE_LEVEL_MASK;
396 } else {
397 level_mask[0] = HEATHROW_LEVEL_MASK;
398 level_mask[1] = 0;
399 /* We might have a second cascaded heathrow */
400 level_mask[2] = HEATHROW_LEVEL_MASK;
401 level_mask[3] = 0;
402 }
403
404 /*
405 * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
406 * 1998 G3 Series PowerBooks have 128,
407 * other powermacs have 32.
408 * The combo ethernet/modem card for the Powerstar powerbooks
409 * (2400/3400/3500, ohare based) has a second ohare chip
410 * effectively making a total of 64.
411 */
412 max_irqs = max_real_irqs = 32;
413 irqctrler = find_devices("mac-io");
414 if (irqctrler)
415 {
416 max_real_irqs = 64;
417 if (irqctrler->next)
418 max_irqs = 128;
419 else
420 max_irqs = 64;
421 }
422 for ( i = 0; i < max_real_irqs ; i++ )
423 irq_desc[i].handler = &pmac_pic;
424
425 /* get addresses of first controller */
426 if (irqctrler) {
427 if (irqctrler->n_addrs > 0) {
428 addr = (unsigned long)
429 ioremap(irqctrler->addrs[0].address, 0x40);
430 for (i = 0; i < 2; ++i)
431 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
432 (addr + (2 - i) * 0x10);
433 }
434
435 /* get addresses of second controller */
436 irqctrler = irqctrler->next;
437 if (irqctrler && irqctrler->n_addrs > 0) {
438 addr = (unsigned long)
439 ioremap(irqctrler->addrs[0].address, 0x40);
440 for (i = 2; i < 4; ++i)
441 pmac_irq_hw[i] = (volatile struct pmac_irq_hw*)
442 (addr + (4 - i) * 0x10);
443 irq_cascade = irqctrler->intrs[0].line;
444 if (device_is_compatible(irqctrler, "gatwick"))
445 pmac_fix_gatwick_interrupts(irqctrler, max_real_irqs);
446 }
447 } else {
448 /* older powermacs have a GC (grand central) or ohare at
449 f3000000, with interrupt control registers at f3000020. */
450 addr = (unsigned long) ioremap(0xf3000000, 0x40);
451 pmac_irq_hw[0] = (volatile struct pmac_irq_hw *) (addr + 0x20);
452 }
453
454 /* PowerBooks 3400 and 3500 can have a second controller in a second
455 ohare chip, on the combo ethernet/modem card */
456 if (machine_is_compatible("AAPL,3400/2400")
457 || machine_is_compatible("AAPL,3500"))
458 irq_cascade = enable_second_ohare();
459
460 /* disable all interrupts in all controllers */
461 for (i = 0; i * 32 < max_irqs; ++i)
462 out_le32(&pmac_irq_hw[i]->enable, 0);
463 /* mark level interrupts */
464 for (i = 0; i < max_irqs; i++)
465 if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
466 irq_desc[i].status = IRQ_LEVEL;
467
468 /* get interrupt line of secondary interrupt controller */
469 if (irq_cascade >= 0) {
470 printk(KERN_INFO "irq: secondary controller on irq %d\n",
471 (int)irq_cascade);
472 for ( i = max_real_irqs ; i < max_irqs ; i++ )
473 irq_desc[i].handler = &gatwick_pic;
474 request_irq( irq_cascade, gatwick_action, SA_INTERRUPT,
475 "cascade", 0 );
476 }
477 printk("System has %d possible interrupts\n", max_irqs);
478 if (max_irqs != max_real_irqs)
479 printk(KERN_DEBUG "%d interrupts on main controller\n",
480 max_real_irqs);
481
482 #ifdef CONFIG_XMON
483 request_irq(20, xmon_irq, 0, "NMI - XMON", 0);
484 #endif /* CONFIG_XMON */
485 }
486
487 #ifdef CONFIG_PMAC_PBOOK
488 /*
489 * These procedures are used in implementing sleep on the powerbooks.
490 * sleep_save_intrs() saves the states of all interrupt enables
491 * and disables all interrupts except for the nominated one.
492 * sleep_restore_intrs() restores the states of all interrupt enables.
493 */
494 unsigned int sleep_save_mask[2];
495
496 void __pmac
pmac_sleep_save_intrs(int viaint)497 pmac_sleep_save_intrs(int viaint)
498 {
499 sleep_save_mask[0] = ppc_cached_irq_mask[0];
500 sleep_save_mask[1] = ppc_cached_irq_mask[1];
501 ppc_cached_irq_mask[0] = 0;
502 ppc_cached_irq_mask[1] = 0;
503 if (viaint > 0)
504 set_bit(viaint, ppc_cached_irq_mask);
505 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
506 if (max_real_irqs > 32)
507 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
508 (void)in_le32(&pmac_irq_hw[0]->event);
509 /* make sure mask gets to controller before we return to caller */
510 mb();
511 (void)in_le32(&pmac_irq_hw[0]->enable);
512 }
513
514 void __pmac
pmac_sleep_restore_intrs(void)515 pmac_sleep_restore_intrs(void)
516 {
517 int i;
518
519 out_le32(&pmac_irq_hw[0]->enable, 0);
520 if (max_real_irqs > 32)
521 out_le32(&pmac_irq_hw[1]->enable, 0);
522 mb();
523 for (i = 0; i < max_real_irqs; ++i)
524 if (test_bit(i, sleep_save_mask))
525 pmac_unmask_irq(i);
526 }
527 #endif /* CONFIG_PMAC_PBOOK */
528