1 /* 2 * ti_hdmi.h 3 * 4 * HDMI driver definition for TI OMAP4, DM81xx, DM38xx Processor. 5 * 6 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef _TI_HDMI_H 22 #define _TI_HDMI_H 23 24 struct hdmi_ip_data; 25 26 enum hdmi_pll_pwr { 27 HDMI_PLLPWRCMD_ALLOFF = 0, 28 HDMI_PLLPWRCMD_PLLONLY = 1, 29 HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, 30 HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 31 }; 32 33 enum hdmi_core_hdmi_dvi { 34 HDMI_DVI = 0, 35 HDMI_HDMI = 1 36 }; 37 38 enum hdmi_clk_refsel { 39 HDMI_REFSEL_PCLK = 0, 40 HDMI_REFSEL_REF1 = 1, 41 HDMI_REFSEL_REF2 = 2, 42 HDMI_REFSEL_SYSCLK = 3 43 }; 44 45 /* HDMI timing structure */ 46 struct hdmi_video_timings { 47 u16 x_res; 48 u16 y_res; 49 /* Unit: KHz */ 50 u32 pixel_clock; 51 u16 hsw; 52 u16 hfp; 53 u16 hbp; 54 u16 vsw; 55 u16 vfp; 56 u16 vbp; 57 bool vsync_pol; 58 bool hsync_pol; 59 bool interlace; 60 }; 61 62 struct hdmi_cm { 63 int code; 64 int mode; 65 }; 66 67 struct hdmi_config { 68 struct hdmi_video_timings timings; 69 struct hdmi_cm cm; 70 }; 71 72 /* HDMI PLL structure */ 73 struct hdmi_pll_info { 74 u16 regn; 75 u16 regm; 76 u32 regmf; 77 u16 regm2; 78 u16 regsd; 79 u16 dcofreq; 80 enum hdmi_clk_refsel refsel; 81 }; 82 83 struct ti_hdmi_ip_ops { 84 85 void (*video_configure)(struct hdmi_ip_data *ip_data); 86 87 int (*phy_enable)(struct hdmi_ip_data *ip_data); 88 89 void (*phy_disable)(struct hdmi_ip_data *ip_data); 90 91 int (*read_edid)(struct hdmi_ip_data *ip_data, u8 *edid, int len); 92 93 bool (*detect)(struct hdmi_ip_data *ip_data); 94 95 int (*pll_enable)(struct hdmi_ip_data *ip_data); 96 97 void (*pll_disable)(struct hdmi_ip_data *ip_data); 98 99 void (*video_enable)(struct hdmi_ip_data *ip_data, bool start); 100 101 void (*dump_wrapper)(struct hdmi_ip_data *ip_data, struct seq_file *s); 102 103 void (*dump_core)(struct hdmi_ip_data *ip_data, struct seq_file *s); 104 105 void (*dump_pll)(struct hdmi_ip_data *ip_data, struct seq_file *s); 106 107 void (*dump_phy)(struct hdmi_ip_data *ip_data, struct seq_file *s); 108 109 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ 110 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) 111 void (*audio_enable)(struct hdmi_ip_data *ip_data, bool start); 112 #endif 113 114 }; 115 116 /* 117 * Refer to section 8.2 in HDMI 1.3 specification for 118 * details about infoframe databytes 119 */ 120 struct hdmi_core_infoframe_avi { 121 /* Y0, Y1 rgb,yCbCr */ 122 u8 db1_format; 123 /* A0 Active information Present */ 124 u8 db1_active_info; 125 /* B0, B1 Bar info data valid */ 126 u8 db1_bar_info_dv; 127 /* S0, S1 scan information */ 128 u8 db1_scan_info; 129 /* C0, C1 colorimetry */ 130 u8 db2_colorimetry; 131 /* M0, M1 Aspect ratio (4:3, 16:9) */ 132 u8 db2_aspect_ratio; 133 /* R0...R3 Active format aspect ratio */ 134 u8 db2_active_fmt_ar; 135 /* ITC IT content. */ 136 u8 db3_itc; 137 /* EC0, EC1, EC2 Extended colorimetry */ 138 u8 db3_ec; 139 /* Q1, Q0 Quantization range */ 140 u8 db3_q_range; 141 /* SC1, SC0 Non-uniform picture scaling */ 142 u8 db3_nup_scaling; 143 /* VIC0..6 Video format identification */ 144 u8 db4_videocode; 145 /* PR0..PR3 Pixel repetition factor */ 146 u8 db5_pixel_repeat; 147 /* Line number end of top bar */ 148 u16 db6_7_line_eoftop; 149 /* Line number start of bottom bar */ 150 u16 db8_9_line_sofbottom; 151 /* Pixel number end of left bar */ 152 u16 db10_11_pixel_eofleft; 153 /* Pixel number start of right bar */ 154 u16 db12_13_pixel_sofright; 155 }; 156 157 struct hdmi_ip_data { 158 void __iomem *base_wp; /* HDMI wrapper */ 159 unsigned long core_sys_offset; 160 unsigned long core_av_offset; 161 unsigned long pll_offset; 162 unsigned long phy_offset; 163 const struct ti_hdmi_ip_ops *ops; 164 struct hdmi_config cfg; 165 struct hdmi_pll_info pll_data; 166 struct hdmi_core_infoframe_avi avi_cfg; 167 168 /* ti_hdmi_4xxx_ip private data. These should be in a separate struct */ 169 int hpd_gpio; 170 bool phy_tx_enabled; 171 }; 172 int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data); 173 void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data); 174 int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, u8 *edid, int len); 175 bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data); 176 void ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start); 177 int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data); 178 void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data); 179 void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data); 180 void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s); 181 void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s); 182 void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s); 183 void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s); 184 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \ 185 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE) 186 void ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data, bool enable); 187 #endif 188 #endif 189