1 /*
2 * isp.h
3 *
4 * TI OMAP3 ISP - Core
5 *
6 * Copyright (C) 2009-2010 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments, Inc.
8 *
9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10 * Sakari Ailus <sakari.ailus@iki.fi>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 */
26
27 #ifndef OMAP3_ISP_CORE_H
28 #define OMAP3_ISP_CORE_H
29
30 #include <media/omap3isp.h>
31 #include <media/v4l2-device.h>
32 #include <linux/device.h>
33 #include <linux/io.h>
34 #include <linux/platform_device.h>
35 #include <linux/wait.h>
36 #include <linux/iommu.h>
37 #include <plat/iommu.h>
38 #include <plat/iovmm.h>
39
40 #include "ispstat.h"
41 #include "ispccdc.h"
42 #include "ispreg.h"
43 #include "ispresizer.h"
44 #include "isppreview.h"
45 #include "ispcsiphy.h"
46 #include "ispcsi2.h"
47 #include "ispccp2.h"
48
49 #define IOMMU_FLAG (IOVMF_ENDIAN_LITTLE | IOVMF_ELSZ_8)
50
51 #define ISP_TOK_TERM 0xFFFFFFFF /*
52 * terminating token for ISP
53 * modules reg list
54 */
55 #define to_isp_device(ptr_module) \
56 container_of(ptr_module, struct isp_device, isp_##ptr_module)
57 #define to_device(ptr_module) \
58 (to_isp_device(ptr_module)->dev)
59
60 enum isp_mem_resources {
61 OMAP3_ISP_IOMEM_MAIN,
62 OMAP3_ISP_IOMEM_CCP2,
63 OMAP3_ISP_IOMEM_CCDC,
64 OMAP3_ISP_IOMEM_HIST,
65 OMAP3_ISP_IOMEM_H3A,
66 OMAP3_ISP_IOMEM_PREV,
67 OMAP3_ISP_IOMEM_RESZ,
68 OMAP3_ISP_IOMEM_SBL,
69 OMAP3_ISP_IOMEM_CSI2A_REGS1,
70 OMAP3_ISP_IOMEM_CSIPHY2,
71 OMAP3_ISP_IOMEM_CSI2A_REGS2,
72 OMAP3_ISP_IOMEM_CSI2C_REGS1,
73 OMAP3_ISP_IOMEM_CSIPHY1,
74 OMAP3_ISP_IOMEM_CSI2C_REGS2,
75 OMAP3_ISP_IOMEM_LAST
76 };
77
78 enum isp_sbl_resource {
79 OMAP3_ISP_SBL_CSI1_READ = 0x1,
80 OMAP3_ISP_SBL_CSI1_WRITE = 0x2,
81 OMAP3_ISP_SBL_CSI2A_WRITE = 0x4,
82 OMAP3_ISP_SBL_CSI2C_WRITE = 0x8,
83 OMAP3_ISP_SBL_CCDC_LSC_READ = 0x10,
84 OMAP3_ISP_SBL_CCDC_WRITE = 0x20,
85 OMAP3_ISP_SBL_PREVIEW_READ = 0x40,
86 OMAP3_ISP_SBL_PREVIEW_WRITE = 0x80,
87 OMAP3_ISP_SBL_RESIZER_READ = 0x100,
88 OMAP3_ISP_SBL_RESIZER_WRITE = 0x200,
89 };
90
91 enum isp_subclk_resource {
92 OMAP3_ISP_SUBCLK_CCDC = (1 << 0),
93 OMAP3_ISP_SUBCLK_H3A = (1 << 1),
94 OMAP3_ISP_SUBCLK_HIST = (1 << 2),
95 OMAP3_ISP_SUBCLK_PREVIEW = (1 << 3),
96 OMAP3_ISP_SUBCLK_RESIZER = (1 << 4),
97 };
98
99 /* ISP: OMAP 34xx ES 1.0 */
100 #define ISP_REVISION_1_0 0x10
101 /* ISP2: OMAP 34xx ES 2.0, 2.1 and 3.0 */
102 #define ISP_REVISION_2_0 0x20
103 /* ISP2P: OMAP 36xx */
104 #define ISP_REVISION_15_0 0xF0
105
106 /*
107 * struct isp_res_mapping - Map ISP io resources to ISP revision.
108 * @isp_rev: ISP_REVISION_x_x
109 * @map: bitmap for enum isp_mem_resources
110 */
111 struct isp_res_mapping {
112 u32 isp_rev;
113 u32 map;
114 };
115
116 /*
117 * struct isp_reg - Structure for ISP register values.
118 * @reg: 32-bit Register address.
119 * @val: 32-bit Register value.
120 */
121 struct isp_reg {
122 enum isp_mem_resources mmio_range;
123 u32 reg;
124 u32 val;
125 };
126
127 struct isp_platform_callback {
128 u32 (*set_xclk)(struct isp_device *isp, u32 xclk, u8 xclksel);
129 int (*csiphy_config)(struct isp_csiphy *phy,
130 struct isp_csiphy_dphy_cfg *dphy,
131 struct isp_csiphy_lanes_cfg *lanes);
132 void (*set_pixel_clock)(struct isp_device *isp, unsigned int pixelclk);
133 };
134
135 /*
136 * struct isp_device - ISP device structure.
137 * @dev: Device pointer specific to the OMAP3 ISP.
138 * @revision: Stores current ISP module revision.
139 * @irq_num: Currently used IRQ number.
140 * @mmio_base: Array with kernel base addresses for ioremapped ISP register
141 * regions.
142 * @mmio_base_phys: Array with physical L4 bus addresses for ISP register
143 * regions.
144 * @mmio_size: Array with ISP register regions size in bytes.
145 * @raw_dmamask: Raw DMA mask
146 * @stat_lock: Spinlock for handling statistics
147 * @isp_mutex: Mutex for serializing requests to ISP.
148 * @has_context: Context has been saved at least once and can be restored.
149 * @ref_count: Reference count for handling multiple ISP requests.
150 * @cam_ick: Pointer to camera interface clock structure.
151 * @cam_mclk: Pointer to camera functional clock structure.
152 * @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure.
153 * @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
154 * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
155 * @irq: Currently attached ISP ISR callbacks information structure.
156 * @isp_af: Pointer to current settings for ISP AutoFocus SCM.
157 * @isp_hist: Pointer to current settings for ISP Histogram SCM.
158 * @isp_h3a: Pointer to current settings for ISP Auto Exposure and
159 * White Balance SCM.
160 * @isp_res: Pointer to current settings for ISP Resizer.
161 * @isp_prev: Pointer to current settings for ISP Preview.
162 * @isp_ccdc: Pointer to current settings for ISP CCDC.
163 * @iommu: Pointer to requested IOMMU instance for ISP.
164 * @platform_cb: ISP driver callback function pointers for platform code
165 *
166 * This structure is used to store the OMAP ISP Information.
167 */
168 struct isp_device {
169 struct v4l2_device v4l2_dev;
170 struct media_device media_dev;
171 struct device *dev;
172 u32 revision;
173
174 /* platform HW resources */
175 struct isp_platform_data *pdata;
176 unsigned int irq_num;
177
178 void __iomem *mmio_base[OMAP3_ISP_IOMEM_LAST];
179 unsigned long mmio_base_phys[OMAP3_ISP_IOMEM_LAST];
180 resource_size_t mmio_size[OMAP3_ISP_IOMEM_LAST];
181
182 u64 raw_dmamask;
183
184 /* ISP Obj */
185 spinlock_t stat_lock; /* common lock for statistic drivers */
186 struct mutex isp_mutex; /* For handling ref_count field */
187 bool needs_reset;
188 int has_context;
189 int ref_count;
190 unsigned int autoidle;
191 u32 xclk_divisor[2]; /* Two clocks, a and b. */
192 #define ISP_CLK_CAM_ICK 0
193 #define ISP_CLK_CAM_MCLK 1
194 #define ISP_CLK_DPLL4_M5_CK 2
195 #define ISP_CLK_CSI2_FCK 3
196 #define ISP_CLK_L3_ICK 4
197 struct clk *clock[5];
198
199 /* ISP modules */
200 struct ispstat isp_af;
201 struct ispstat isp_aewb;
202 struct ispstat isp_hist;
203 struct isp_res_device isp_res;
204 struct isp_prev_device isp_prev;
205 struct isp_ccdc_device isp_ccdc;
206 struct isp_csi2_device isp_csi2a;
207 struct isp_csi2_device isp_csi2c;
208 struct isp_ccp2_device isp_ccp2;
209 struct isp_csiphy isp_csiphy1;
210 struct isp_csiphy isp_csiphy2;
211
212 unsigned int sbl_resources;
213 unsigned int subclk_resources;
214
215 struct iommu_domain *domain;
216
217 struct isp_platform_callback platform_cb;
218 };
219
220 #define v4l2_dev_to_isp_device(dev) \
221 container_of(dev, struct isp_device, v4l2_dev)
222
223 void omap3isp_hist_dma_done(struct isp_device *isp);
224
225 void omap3isp_flush(struct isp_device *isp);
226
227 int omap3isp_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
228 atomic_t *stopping);
229
230 int omap3isp_module_sync_is_stopping(wait_queue_head_t *wait,
231 atomic_t *stopping);
232
233 int omap3isp_pipeline_set_stream(struct isp_pipeline *pipe,
234 enum isp_pipeline_stream_state state);
235 void omap3isp_configure_bridge(struct isp_device *isp,
236 enum ccdc_input_entity input,
237 const struct isp_parallel_platform_data *pdata,
238 unsigned int shift);
239
240 #define ISP_XCLK_NONE 0
241 #define ISP_XCLK_A 1
242 #define ISP_XCLK_B 2
243
244 struct isp_device *omap3isp_get(struct isp_device *isp);
245 void omap3isp_put(struct isp_device *isp);
246
247 void omap3isp_print_status(struct isp_device *isp);
248
249 void omap3isp_sbl_enable(struct isp_device *isp, enum isp_sbl_resource res);
250 void omap3isp_sbl_disable(struct isp_device *isp, enum isp_sbl_resource res);
251
252 void omap3isp_subclk_enable(struct isp_device *isp,
253 enum isp_subclk_resource res);
254 void omap3isp_subclk_disable(struct isp_device *isp,
255 enum isp_subclk_resource res);
256
257 int omap3isp_pipeline_pm_use(struct media_entity *entity, int use);
258
259 int omap3isp_register_entities(struct platform_device *pdev,
260 struct v4l2_device *v4l2_dev);
261 void omap3isp_unregister_entities(struct platform_device *pdev);
262
263 /*
264 * isp_reg_readl - Read value of an OMAP3 ISP register
265 * @dev: Device pointer specific to the OMAP3 ISP.
266 * @isp_mmio_range: Range to which the register offset refers to.
267 * @reg_offset: Register offset to read from.
268 *
269 * Returns an unsigned 32 bit value with the required register contents.
270 */
271 static inline
isp_reg_readl(struct isp_device * isp,enum isp_mem_resources isp_mmio_range,u32 reg_offset)272 u32 isp_reg_readl(struct isp_device *isp, enum isp_mem_resources isp_mmio_range,
273 u32 reg_offset)
274 {
275 return __raw_readl(isp->mmio_base[isp_mmio_range] + reg_offset);
276 }
277
278 /*
279 * isp_reg_writel - Write value to an OMAP3 ISP register
280 * @dev: Device pointer specific to the OMAP3 ISP.
281 * @reg_value: 32 bit value to write to the register.
282 * @isp_mmio_range: Range to which the register offset refers to.
283 * @reg_offset: Register offset to write into.
284 */
285 static inline
isp_reg_writel(struct isp_device * isp,u32 reg_value,enum isp_mem_resources isp_mmio_range,u32 reg_offset)286 void isp_reg_writel(struct isp_device *isp, u32 reg_value,
287 enum isp_mem_resources isp_mmio_range, u32 reg_offset)
288 {
289 __raw_writel(reg_value, isp->mmio_base[isp_mmio_range] + reg_offset);
290 }
291
292 /*
293 * isp_reg_and - Clear individual bits in an OMAP3 ISP register
294 * @dev: Device pointer specific to the OMAP3 ISP.
295 * @mmio_range: Range to which the register offset refers to.
296 * @reg: Register offset to work on.
297 * @clr_bits: 32 bit value which would be cleared in the register.
298 */
299 static inline
isp_reg_clr(struct isp_device * isp,enum isp_mem_resources mmio_range,u32 reg,u32 clr_bits)300 void isp_reg_clr(struct isp_device *isp, enum isp_mem_resources mmio_range,
301 u32 reg, u32 clr_bits)
302 {
303 u32 v = isp_reg_readl(isp, mmio_range, reg);
304
305 isp_reg_writel(isp, v & ~clr_bits, mmio_range, reg);
306 }
307
308 /*
309 * isp_reg_set - Set individual bits in an OMAP3 ISP register
310 * @dev: Device pointer specific to the OMAP3 ISP.
311 * @mmio_range: Range to which the register offset refers to.
312 * @reg: Register offset to work on.
313 * @set_bits: 32 bit value which would be set in the register.
314 */
315 static inline
isp_reg_set(struct isp_device * isp,enum isp_mem_resources mmio_range,u32 reg,u32 set_bits)316 void isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
317 u32 reg, u32 set_bits)
318 {
319 u32 v = isp_reg_readl(isp, mmio_range, reg);
320
321 isp_reg_writel(isp, v | set_bits, mmio_range, reg);
322 }
323
324 /*
325 * isp_reg_clr_set - Clear and set invidial bits in an OMAP3 ISP register
326 * @dev: Device pointer specific to the OMAP3 ISP.
327 * @mmio_range: Range to which the register offset refers to.
328 * @reg: Register offset to work on.
329 * @clr_bits: 32 bit value which would be cleared in the register.
330 * @set_bits: 32 bit value which would be set in the register.
331 *
332 * The clear operation is done first, and then the set operation.
333 */
334 static inline
isp_reg_clr_set(struct isp_device * isp,enum isp_mem_resources mmio_range,u32 reg,u32 clr_bits,u32 set_bits)335 void isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range,
336 u32 reg, u32 clr_bits, u32 set_bits)
337 {
338 u32 v = isp_reg_readl(isp, mmio_range, reg);
339
340 isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
341 }
342
343 static inline enum v4l2_buf_type
isp_pad_buffer_type(const struct v4l2_subdev * subdev,int pad)344 isp_pad_buffer_type(const struct v4l2_subdev *subdev, int pad)
345 {
346 if (pad >= subdev->entity.num_pads)
347 return 0;
348
349 if (subdev->entity.pads[pad].flags & MEDIA_PAD_FL_SINK)
350 return V4L2_BUF_TYPE_VIDEO_OUTPUT;
351 else
352 return V4L2_BUF_TYPE_VIDEO_CAPTURE;
353 }
354
355 #endif /* OMAP3_ISP_CORE_H */
356