1 /* $Id$ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved. 8 */ 9 #ifndef _ASM_SN_PCI_PCIIO_PRIVATE_H 10 #define _ASM_SN_PCI_PCIIO_PRIVATE_H 11 12 #include <asm/sn/pci/pciio.h> 13 #include <asm/sn/pci/pci_defs.h> 14 15 /* 16 * pciio_private.h -- private definitions for pciio 17 * PCI drivers should NOT include this file. 18 */ 19 20 #ident "sys/PCI/pciio_private: $Revision: 1.13 $" 21 22 /* 23 * All PCI providers set up PIO using this information. 24 */ 25 struct pciio_piomap_s { 26 unsigned pp_flags; /* PCIIO_PIOMAP flags */ 27 vertex_hdl_t pp_dev; /* associated pci card */ 28 pciio_slot_t pp_slot; /* which slot the card is in */ 29 pciio_space_t pp_space; /* which address space */ 30 iopaddr_t pp_pciaddr; /* starting offset of mapping */ 31 size_t pp_mapsz; /* size of this mapping */ 32 caddr_t pp_kvaddr; /* kernel virtual address to use */ 33 }; 34 35 /* 36 * All PCI providers set up DMA using this information. 37 */ 38 struct pciio_dmamap_s { 39 unsigned pd_flags; /* PCIIO_DMAMAP flags */ 40 vertex_hdl_t pd_dev; /* associated pci card */ 41 pciio_slot_t pd_slot; /* which slot the card is in */ 42 }; 43 44 /* 45 * All PCI providers set up interrupts using this information. 46 */ 47 48 struct pciio_intr_s { 49 unsigned pi_flags; /* PCIIO_INTR flags */ 50 vertex_hdl_t pi_dev; /* associated pci card */ 51 device_desc_t pi_dev_desc; /* override device descriptor */ 52 pciio_intr_line_t pi_lines; /* which interrupt line(s) */ 53 intr_func_t pi_func; /* handler function (when connected) */ 54 intr_arg_t pi_arg; /* handler parameter (when connected) */ 55 cpuid_t pi_mustruncpu; /* Where we must run. */ 56 int pi_irq; /* IRQ assigned */ 57 int pi_cpu; /* cpu assigned */ 58 }; 59 60 /* PCIIO_INTR (pi_flags) flags */ 61 #define PCIIO_INTR_CONNECTED 1 /* interrupt handler/thread has been connected */ 62 #define PCIIO_INTR_NOTHREAD 2 /* interrupt handler wants to be called at interrupt level */ 63 64 /* 65 * Some PCI provider implementations keep track of PCI window Base Address 66 * Register (BAR) address range assignment via the rmalloc()/rmfree() arena 67 * management routines. These implementations use the following data 68 * structure for each allocation address space (e.g. memory, I/O, small 69 * window, etc.). 70 * 71 * The ``page size'' encodes the minimum allocation unit and must be a power 72 * of 2. The main use of this allocation ``page size'' is to control the 73 * number of free address ranges that the mapping allocation software will 74 * need to track. Smaller values will allow more efficient use of the address 75 * ranges but will result in much larger allocation map structures ... For 76 * instance, if we want to manage allocations for a 256MB address range, 77 * choosing a 1MB allocation page size will result in up to 1MB being wasted 78 * for allocation requests smaller than 1MB. The worst case allocation 79 * pattern for the allocation software to track would be a pattern of 1MB 80 * allocated, 1MB free. This results in the need to track up to 128 free 81 * ranges. 82 */ 83 struct pciio_win_map_s { 84 struct map *wm_map; /* window address map */ 85 int wm_page_size; /* allocation ``page size'' */ 86 }; 87 88 /* 89 * Opaque structure used to keep track of window allocation information. 90 */ 91 struct pciio_win_alloc_s { 92 struct resource *wa_resource; /* window map allocation resource */ 93 unsigned long wa_base; /* allocation starting page number */ 94 size_t wa_pages; /* number of pages in allocation */ 95 }; 96 97 /* 98 * Each PCI Card has one of these. 99 */ 100 101 struct pciio_info_s { 102 char *c_fingerprint; 103 vertex_hdl_t c_vertex; /* back pointer to vertex */ 104 pciio_bus_t c_bus; /* which bus the card is in */ 105 pciio_slot_t c_slot; /* which slot the card is in */ 106 pciio_function_t c_func; /* which func (on multi-func cards) */ 107 pciio_vendor_id_t c_vendor; /* PCI card "vendor" code */ 108 pciio_device_id_t c_device; /* PCI card "device" code */ 109 vertex_hdl_t c_master; /* PCI bus provider */ 110 arbitrary_info_t c_mfast; /* cached fastinfo from c_master */ 111 pciio_provider_t *c_pops; /* cached provider from c_master */ 112 error_handler_f *c_efunc; /* error handling function */ 113 error_handler_arg_t c_einfo; /* first parameter for efunc */ 114 115 struct pciio_win_info_s { /* state of BASE regs */ 116 pciio_space_t w_space; 117 iopaddr_t w_base; 118 size_t w_size; 119 int w_devio_index; /* DevIO[] register used to 120 access this window */ 121 struct pciio_win_alloc_s w_win_alloc; /* window allocation cookie */ 122 } c_window[PCI_CFG_BASE_ADDRS + 1]; 123 #define c_rwindow c_window[PCI_CFG_BASE_ADDRS] /* EXPANSION ROM window */ 124 #define c_rbase c_rwindow.w_base /* EXPANSION ROM base addr */ 125 #define c_rsize c_rwindow.w_size /* EXPANSION ROM size (bytes) */ 126 pciio_piospace_t c_piospace; /* additional I/O spaces allocated */ 127 }; 128 129 extern char pciio_info_fingerprint[]; 130 #endif /* _ASM_SN_PCI_PCIIO_PRIVATE_H */ 131