1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020-2021 Intel Corporation. */
3 #ifndef __CXL_MEM_H__
4 #define __CXL_MEM_H__
5 #include <uapi/linux/cxl_mem.h>
6 #include <linux/cdev.h>
7 #include "cxl.h"
8
9 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
10 #define CXLMDEV_STATUS_OFFSET 0x0
11 #define CXLMDEV_DEV_FATAL BIT(0)
12 #define CXLMDEV_FW_HALT BIT(1)
13 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
14 #define CXLMDEV_MS_NOT_READY 0
15 #define CXLMDEV_MS_READY 1
16 #define CXLMDEV_MS_ERROR 2
17 #define CXLMDEV_MS_DISABLED 3
18 #define CXLMDEV_READY(status) \
19 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \
20 CXLMDEV_MS_READY)
21 #define CXLMDEV_MBOX_IF_READY BIT(4)
22 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
23 #define CXLMDEV_RESET_NEEDED_NOT 0
24 #define CXLMDEV_RESET_NEEDED_COLD 1
25 #define CXLMDEV_RESET_NEEDED_WARM 2
26 #define CXLMDEV_RESET_NEEDED_HOT 3
27 #define CXLMDEV_RESET_NEEDED_CXL 4
28 #define CXLMDEV_RESET_NEEDED(status) \
29 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \
30 CXLMDEV_RESET_NEEDED_NOT)
31
32 /**
33 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
34 * @dev: driver core device object
35 * @cdev: char dev core object for ioctl operations
36 * @cxlds: The device state backing this device
37 * @detach_work: active memdev lost a port in its ancestry
38 * @id: id number of this memdev instance.
39 */
40 struct cxl_memdev {
41 struct device dev;
42 struct cdev cdev;
43 struct cxl_dev_state *cxlds;
44 struct work_struct detach_work;
45 int id;
46 };
47
to_cxl_memdev(struct device * dev)48 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
49 {
50 return container_of(dev, struct cxl_memdev, dev);
51 }
52
53 bool is_cxl_memdev(struct device *dev);
is_cxl_endpoint(struct cxl_port * port)54 static inline bool is_cxl_endpoint(struct cxl_port *port)
55 {
56 return is_cxl_memdev(port->uport);
57 }
58
59 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds);
60
61 /**
62 * struct cxl_mbox_cmd - A command to be submitted to hardware.
63 * @opcode: (input) The command set and command submitted to hardware.
64 * @payload_in: (input) Pointer to the input payload.
65 * @payload_out: (output) Pointer to the output payload. Must be allocated by
66 * the caller.
67 * @size_in: (input) Number of bytes to load from @payload_in.
68 * @size_out: (input) Max number of bytes loaded into @payload_out.
69 * (output) Number of bytes generated by the device. For fixed size
70 * outputs commands this is always expected to be deterministic. For
71 * variable sized output commands, it tells the exact number of bytes
72 * written.
73 * @return_code: (output) Error code returned from hardware.
74 *
75 * This is the primary mechanism used to send commands to the hardware.
76 * All the fields except @payload_* correspond exactly to the fields described in
77 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and
78 * @payload_out are written to, and read from the Command Payload Registers
79 * defined in CXL 2.0 8.2.8.4.8.
80 */
81 struct cxl_mbox_cmd {
82 u16 opcode;
83 void *payload_in;
84 void *payload_out;
85 size_t size_in;
86 size_t size_out;
87 u16 return_code;
88 };
89
90 /*
91 * Per CXL 2.0 Section 8.2.8.4.5.1
92 */
93 #define CMD_CMD_RC_TABLE \
94 C(SUCCESS, 0, NULL), \
95 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \
96 C(INPUT, -ENXIO, "cmd input was invalid"), \
97 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \
98 C(INTERNAL, -ENXIO, "internal device error"), \
99 C(RETRY, -ENXIO, "temporary error, retry once"), \
100 C(BUSY, -ENXIO, "ongoing background operation"), \
101 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \
102 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \
103 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \
104 C(FWAUTH, -ENXIO, "FW package authentication failed"), \
105 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \
106 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \
107 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \
108 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \
109 C(PADDR, -ENXIO, "physical address specified is invalid"), \
110 C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \
111 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \
112 C(ABORT, -ENXIO, "background cmd was aborted by device"), \
113 C(SECURITY, -ENXIO, "not valid in the current security state"), \
114 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \
115 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\
116 C(PAYLOADLEN, -ENXIO, "invalid payload length")
117
118 #undef C
119 #define C(a, b, c) CXL_MBOX_CMD_RC_##a
120 enum { CMD_CMD_RC_TABLE };
121 #undef C
122 #define C(a, b, c) { b, c }
123 struct cxl_mbox_cmd_rc {
124 int err;
125 const char *desc;
126 };
127
128 static const
129 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };
130 #undef C
131
cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd * mbox_cmd)132 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd)
133 {
134 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;
135 }
136
cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd * mbox_cmd)137 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
138 {
139 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;
140 }
141
142 /*
143 * CXL 2.0 - Memory capacity multiplier
144 * See Section 8.2.9.5
145 *
146 * Volatile, Persistent, and Partition capacities are specified to be in
147 * multiples of 256MB - define a multiplier to convert to/from bytes.
148 */
149 #define CXL_CAPACITY_MULTIPLIER SZ_256M
150
151 /**
152 * struct cxl_endpoint_dvsec_info - Cached DVSEC info
153 * @mem_enabled: cached value of mem_enabled in the DVSEC, PCIE_DEVICE
154 * @ranges: Number of active HDM ranges this device uses.
155 * @dvsec_range: cached attributes of the ranges in the DVSEC, PCIE_DEVICE
156 */
157 struct cxl_endpoint_dvsec_info {
158 bool mem_enabled;
159 int ranges;
160 struct range dvsec_range[2];
161 };
162
163 /**
164 * struct cxl_dev_state - The driver device state
165 *
166 * cxl_dev_state represents the CXL driver/device state. It provides an
167 * interface to mailbox commands as well as some cached data about the device.
168 * Currently only memory devices are represented.
169 *
170 * @dev: The device associated with this CXL state
171 * @regs: Parsed register blocks
172 * @cxl_dvsec: Offset to the PCIe device DVSEC
173 * @payload_size: Size of space for payload
174 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
175 * @lsa_size: Size of Label Storage Area
176 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
177 * @mbox_mutex: Mutex to synchronize mailbox access.
178 * @firmware_version: Firmware version for the memory device.
179 * @enabled_cmds: Hardware commands found enabled in CEL.
180 * @exclusive_cmds: Commands that are kernel-internal only
181 * @pmem_range: Active Persistent memory capacity configuration
182 * @ram_range: Active Volatile memory capacity configuration
183 * @total_bytes: sum of all possible capacities
184 * @volatile_only_bytes: hard volatile capacity
185 * @persistent_only_bytes: hard persistent capacity
186 * @partition_align_bytes: alignment size for partition-able capacity
187 * @active_volatile_bytes: sum of hard + soft volatile
188 * @active_persistent_bytes: sum of hard + soft persistent
189 * @next_volatile_bytes: volatile capacity change pending device reset
190 * @next_persistent_bytes: persistent capacity change pending device reset
191 * @component_reg_phys: register base of component registers
192 * @info: Cached DVSEC information about the device.
193 * @serial: PCIe Device Serial Number
194 * @mbox_send: @dev specific transport for transmitting mailbox commands
195 *
196 * See section 8.2.9.5.2 Capacity Configuration and Label Storage for
197 * details on capacity parameters.
198 */
199 struct cxl_dev_state {
200 struct device *dev;
201
202 struct cxl_regs regs;
203 int cxl_dvsec;
204
205 size_t payload_size;
206 size_t lsa_size;
207 struct mutex mbox_mutex; /* Protects device mailbox and firmware */
208 char firmware_version[0x10];
209 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX);
210 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX);
211
212 struct range pmem_range;
213 struct range ram_range;
214 u64 total_bytes;
215 u64 volatile_only_bytes;
216 u64 persistent_only_bytes;
217 u64 partition_align_bytes;
218
219 u64 active_volatile_bytes;
220 u64 active_persistent_bytes;
221 u64 next_volatile_bytes;
222 u64 next_persistent_bytes;
223
224 resource_size_t component_reg_phys;
225 u64 serial;
226
227 int (*mbox_send)(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *cmd);
228 };
229
230 enum cxl_opcode {
231 CXL_MBOX_OP_INVALID = 0x0000,
232 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID,
233 CXL_MBOX_OP_GET_FW_INFO = 0x0200,
234 CXL_MBOX_OP_ACTIVATE_FW = 0x0202,
235 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400,
236 CXL_MBOX_OP_GET_LOG = 0x0401,
237 CXL_MBOX_OP_IDENTIFY = 0x4000,
238 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
239 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
240 CXL_MBOX_OP_GET_LSA = 0x4102,
241 CXL_MBOX_OP_SET_LSA = 0x4103,
242 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200,
243 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201,
244 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202,
245 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203,
246 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204,
247 CXL_MBOX_OP_GET_POISON = 0x4300,
248 CXL_MBOX_OP_INJECT_POISON = 0x4301,
249 CXL_MBOX_OP_CLEAR_POISON = 0x4302,
250 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303,
251 CXL_MBOX_OP_SCAN_MEDIA = 0x4304,
252 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305,
253 CXL_MBOX_OP_MAX = 0x10000
254 };
255
256 #define DEFINE_CXL_CEL_UUID \
257 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \
258 0x3b, 0x3f, 0x17)
259
260 #define DEFINE_CXL_VENDOR_DEBUG_UUID \
261 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \
262 0x40, 0x3d, 0x86)
263
264 struct cxl_mbox_get_supported_logs {
265 __le16 entries;
266 u8 rsvd[6];
267 struct cxl_gsl_entry {
268 uuid_t uuid;
269 __le32 size;
270 } __packed entry[];
271 } __packed;
272
273 struct cxl_cel_entry {
274 __le16 opcode;
275 __le16 effect;
276 } __packed;
277
278 struct cxl_mbox_get_log {
279 uuid_t uuid;
280 __le32 offset;
281 __le32 length;
282 } __packed;
283
284 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
285 struct cxl_mbox_identify {
286 char fw_revision[0x10];
287 __le64 total_capacity;
288 __le64 volatile_capacity;
289 __le64 persistent_capacity;
290 __le64 partition_align;
291 __le16 info_event_log_size;
292 __le16 warning_event_log_size;
293 __le16 failure_event_log_size;
294 __le16 fatal_event_log_size;
295 __le32 lsa_size;
296 u8 poison_list_max_mer[3];
297 __le16 inject_poison_limit;
298 u8 poison_caps;
299 u8 qos_telemetry_caps;
300 } __packed;
301
302 struct cxl_mbox_get_lsa {
303 __le32 offset;
304 __le32 length;
305 } __packed;
306
307 struct cxl_mbox_set_lsa {
308 __le32 offset;
309 __le32 reserved;
310 u8 data[];
311 } __packed;
312
313 struct cxl_mbox_set_partition_info {
314 __le64 volatile_capacity;
315 u8 flags;
316 } __packed;
317
318 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0)
319
320 /**
321 * struct cxl_mem_command - Driver representation of a memory device command
322 * @info: Command information as it exists for the UAPI
323 * @opcode: The actual bits used for the mailbox protocol
324 * @flags: Set of flags effecting driver behavior.
325 *
326 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
327 * will be enabled by the driver regardless of what hardware may have
328 * advertised.
329 *
330 * The cxl_mem_command is the driver's internal representation of commands that
331 * are supported by the driver. Some of these commands may not be supported by
332 * the hardware. The driver will use @info to validate the fields passed in by
333 * the user then submit the @opcode to the hardware.
334 *
335 * See struct cxl_command_info.
336 */
337 struct cxl_mem_command {
338 struct cxl_command_info info;
339 enum cxl_opcode opcode;
340 u32 flags;
341 #define CXL_CMD_FLAG_NONE 0
342 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
343 };
344
345 int cxl_mbox_send_cmd(struct cxl_dev_state *cxlds, u16 opcode, void *in,
346 size_t in_size, void *out, size_t out_size);
347 int cxl_dev_state_identify(struct cxl_dev_state *cxlds);
348 int cxl_await_media_ready(struct cxl_dev_state *cxlds);
349 int cxl_enumerate_cmds(struct cxl_dev_state *cxlds);
350 int cxl_mem_create_range_info(struct cxl_dev_state *cxlds);
351 struct cxl_dev_state *cxl_dev_state_create(struct device *dev);
352 void set_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds);
353 void clear_exclusive_cxl_commands(struct cxl_dev_state *cxlds, unsigned long *cmds);
354 #ifdef CONFIG_CXL_SUSPEND
355 void cxl_mem_active_inc(void);
356 void cxl_mem_active_dec(void);
357 #else
cxl_mem_active_inc(void)358 static inline void cxl_mem_active_inc(void)
359 {
360 }
cxl_mem_active_dec(void)361 static inline void cxl_mem_active_dec(void)
362 {
363 }
364 #endif
365
366 struct cxl_hdm {
367 struct cxl_component_regs regs;
368 unsigned int decoder_count;
369 unsigned int target_count;
370 unsigned int interleave_mask;
371 struct cxl_port *port;
372 };
373 #endif /* __CXL_MEM_H__ */
374