1 #ifndef _ASM_X86_PERCPU_H 2 #define _ASM_X86_PERCPU_H 3 4 #ifdef CONFIG_X86_64 5 #define __percpu_seg gs 6 #define __percpu_mov_op movq 7 #else 8 #define __percpu_seg fs 9 #define __percpu_mov_op movl 10 #endif 11 12 #ifdef __ASSEMBLY__ 13 14 /* 15 * PER_CPU finds an address of a per-cpu variable. 16 * 17 * Args: 18 * var - variable name 19 * reg - 32bit register 20 * 21 * The resulting address is stored in the "reg" argument. 22 * 23 * Example: 24 * PER_CPU(cpu_gdt_descr, %ebx) 25 */ 26 #ifdef CONFIG_SMP 27 #define PER_CPU(var, reg) \ 28 __percpu_mov_op %__percpu_seg:this_cpu_off, reg; \ 29 lea var(reg), reg 30 #define PER_CPU_VAR(var) %__percpu_seg:var 31 #else /* ! SMP */ 32 #define PER_CPU(var, reg) __percpu_mov_op $var, reg 33 #define PER_CPU_VAR(var) var 34 #endif /* SMP */ 35 36 #ifdef CONFIG_X86_64_SMP 37 #define INIT_PER_CPU_VAR(var) init_per_cpu__##var 38 #else 39 #define INIT_PER_CPU_VAR(var) var 40 #endif 41 42 #else /* ...!ASSEMBLY */ 43 44 #include <linux/kernel.h> 45 #include <linux/stringify.h> 46 47 #ifdef CONFIG_SMP 48 #define __percpu_prefix "%%"__stringify(__percpu_seg)":" 49 #define __my_cpu_offset percpu_read(this_cpu_off) 50 51 /* 52 * Compared to the generic __my_cpu_offset version, the following 53 * saves one instruction and avoids clobbering a temp register. 54 */ 55 #define __this_cpu_ptr(ptr) \ 56 ({ \ 57 unsigned long tcp_ptr__; \ 58 __verify_pcpu_ptr(ptr); \ 59 asm volatile("add " __percpu_arg(1) ", %0" \ 60 : "=r" (tcp_ptr__) \ 61 : "m" (this_cpu_off), "0" (ptr)); \ 62 (typeof(*(ptr)) __kernel __force *)tcp_ptr__; \ 63 }) 64 #else 65 #define __percpu_prefix "" 66 #endif 67 68 #define __percpu_arg(x) __percpu_prefix "%P" #x 69 70 /* 71 * Initialized pointers to per-cpu variables needed for the boot 72 * processor need to use these macros to get the proper address 73 * offset from __per_cpu_load on SMP. 74 * 75 * There also must be an entry in vmlinux_64.lds.S 76 */ 77 #define DECLARE_INIT_PER_CPU(var) \ 78 extern typeof(var) init_per_cpu_var(var) 79 80 #ifdef CONFIG_X86_64_SMP 81 #define init_per_cpu_var(var) init_per_cpu__##var 82 #else 83 #define init_per_cpu_var(var) var 84 #endif 85 86 /* For arch-specific code, we can use direct single-insn ops (they 87 * don't give an lvalue though). */ 88 extern void __bad_percpu_size(void); 89 90 #define percpu_to_op(op, var, val) \ 91 do { \ 92 typedef typeof(var) pto_T__; \ 93 if (0) { \ 94 pto_T__ pto_tmp__; \ 95 pto_tmp__ = (val); \ 96 (void)pto_tmp__; \ 97 } \ 98 switch (sizeof(var)) { \ 99 case 1: \ 100 asm(op "b %1,"__percpu_arg(0) \ 101 : "+m" (var) \ 102 : "qi" ((pto_T__)(val))); \ 103 break; \ 104 case 2: \ 105 asm(op "w %1,"__percpu_arg(0) \ 106 : "+m" (var) \ 107 : "ri" ((pto_T__)(val))); \ 108 break; \ 109 case 4: \ 110 asm(op "l %1,"__percpu_arg(0) \ 111 : "+m" (var) \ 112 : "ri" ((pto_T__)(val))); \ 113 break; \ 114 case 8: \ 115 asm(op "q %1,"__percpu_arg(0) \ 116 : "+m" (var) \ 117 : "re" ((pto_T__)(val))); \ 118 break; \ 119 default: __bad_percpu_size(); \ 120 } \ 121 } while (0) 122 123 /* 124 * Generate a percpu add to memory instruction and optimize code 125 * if one is added or subtracted. 126 */ 127 #define percpu_add_op(var, val) \ 128 do { \ 129 typedef typeof(var) pao_T__; \ 130 const int pao_ID__ = (__builtin_constant_p(val) && \ 131 ((val) == 1 || (val) == -1)) ? (val) : 0; \ 132 if (0) { \ 133 pao_T__ pao_tmp__; \ 134 pao_tmp__ = (val); \ 135 (void)pao_tmp__; \ 136 } \ 137 switch (sizeof(var)) { \ 138 case 1: \ 139 if (pao_ID__ == 1) \ 140 asm("incb "__percpu_arg(0) : "+m" (var)); \ 141 else if (pao_ID__ == -1) \ 142 asm("decb "__percpu_arg(0) : "+m" (var)); \ 143 else \ 144 asm("addb %1, "__percpu_arg(0) \ 145 : "+m" (var) \ 146 : "qi" ((pao_T__)(val))); \ 147 break; \ 148 case 2: \ 149 if (pao_ID__ == 1) \ 150 asm("incw "__percpu_arg(0) : "+m" (var)); \ 151 else if (pao_ID__ == -1) \ 152 asm("decw "__percpu_arg(0) : "+m" (var)); \ 153 else \ 154 asm("addw %1, "__percpu_arg(0) \ 155 : "+m" (var) \ 156 : "ri" ((pao_T__)(val))); \ 157 break; \ 158 case 4: \ 159 if (pao_ID__ == 1) \ 160 asm("incl "__percpu_arg(0) : "+m" (var)); \ 161 else if (pao_ID__ == -1) \ 162 asm("decl "__percpu_arg(0) : "+m" (var)); \ 163 else \ 164 asm("addl %1, "__percpu_arg(0) \ 165 : "+m" (var) \ 166 : "ri" ((pao_T__)(val))); \ 167 break; \ 168 case 8: \ 169 if (pao_ID__ == 1) \ 170 asm("incq "__percpu_arg(0) : "+m" (var)); \ 171 else if (pao_ID__ == -1) \ 172 asm("decq "__percpu_arg(0) : "+m" (var)); \ 173 else \ 174 asm("addq %1, "__percpu_arg(0) \ 175 : "+m" (var) \ 176 : "re" ((pao_T__)(val))); \ 177 break; \ 178 default: __bad_percpu_size(); \ 179 } \ 180 } while (0) 181 182 #define percpu_from_op(op, var, constraint) \ 183 ({ \ 184 typeof(var) pfo_ret__; \ 185 switch (sizeof(var)) { \ 186 case 1: \ 187 asm(op "b "__percpu_arg(1)",%0" \ 188 : "=q" (pfo_ret__) \ 189 : constraint); \ 190 break; \ 191 case 2: \ 192 asm(op "w "__percpu_arg(1)",%0" \ 193 : "=r" (pfo_ret__) \ 194 : constraint); \ 195 break; \ 196 case 4: \ 197 asm(op "l "__percpu_arg(1)",%0" \ 198 : "=r" (pfo_ret__) \ 199 : constraint); \ 200 break; \ 201 case 8: \ 202 asm(op "q "__percpu_arg(1)",%0" \ 203 : "=r" (pfo_ret__) \ 204 : constraint); \ 205 break; \ 206 default: __bad_percpu_size(); \ 207 } \ 208 pfo_ret__; \ 209 }) 210 211 #define percpu_unary_op(op, var) \ 212 ({ \ 213 switch (sizeof(var)) { \ 214 case 1: \ 215 asm(op "b "__percpu_arg(0) \ 216 : "+m" (var)); \ 217 break; \ 218 case 2: \ 219 asm(op "w "__percpu_arg(0) \ 220 : "+m" (var)); \ 221 break; \ 222 case 4: \ 223 asm(op "l "__percpu_arg(0) \ 224 : "+m" (var)); \ 225 break; \ 226 case 8: \ 227 asm(op "q "__percpu_arg(0) \ 228 : "+m" (var)); \ 229 break; \ 230 default: __bad_percpu_size(); \ 231 } \ 232 }) 233 234 /* 235 * Add return operation 236 */ 237 #define percpu_add_return_op(var, val) \ 238 ({ \ 239 typeof(var) paro_ret__ = val; \ 240 switch (sizeof(var)) { \ 241 case 1: \ 242 asm("xaddb %0, "__percpu_arg(1) \ 243 : "+q" (paro_ret__), "+m" (var) \ 244 : : "memory"); \ 245 break; \ 246 case 2: \ 247 asm("xaddw %0, "__percpu_arg(1) \ 248 : "+r" (paro_ret__), "+m" (var) \ 249 : : "memory"); \ 250 break; \ 251 case 4: \ 252 asm("xaddl %0, "__percpu_arg(1) \ 253 : "+r" (paro_ret__), "+m" (var) \ 254 : : "memory"); \ 255 break; \ 256 case 8: \ 257 asm("xaddq %0, "__percpu_arg(1) \ 258 : "+re" (paro_ret__), "+m" (var) \ 259 : : "memory"); \ 260 break; \ 261 default: __bad_percpu_size(); \ 262 } \ 263 paro_ret__ += val; \ 264 paro_ret__; \ 265 }) 266 267 /* 268 * xchg is implemented using cmpxchg without a lock prefix. xchg is 269 * expensive due to the implied lock prefix. The processor cannot prefetch 270 * cachelines if xchg is used. 271 */ 272 #define percpu_xchg_op(var, nval) \ 273 ({ \ 274 typeof(var) pxo_ret__; \ 275 typeof(var) pxo_new__ = (nval); \ 276 switch (sizeof(var)) { \ 277 case 1: \ 278 asm("\n\tmov "__percpu_arg(1)",%%al" \ 279 "\n1:\tcmpxchgb %2, "__percpu_arg(1) \ 280 "\n\tjnz 1b" \ 281 : "=&a" (pxo_ret__), "+m" (var) \ 282 : "q" (pxo_new__) \ 283 : "memory"); \ 284 break; \ 285 case 2: \ 286 asm("\n\tmov "__percpu_arg(1)",%%ax" \ 287 "\n1:\tcmpxchgw %2, "__percpu_arg(1) \ 288 "\n\tjnz 1b" \ 289 : "=&a" (pxo_ret__), "+m" (var) \ 290 : "r" (pxo_new__) \ 291 : "memory"); \ 292 break; \ 293 case 4: \ 294 asm("\n\tmov "__percpu_arg(1)",%%eax" \ 295 "\n1:\tcmpxchgl %2, "__percpu_arg(1) \ 296 "\n\tjnz 1b" \ 297 : "=&a" (pxo_ret__), "+m" (var) \ 298 : "r" (pxo_new__) \ 299 : "memory"); \ 300 break; \ 301 case 8: \ 302 asm("\n\tmov "__percpu_arg(1)",%%rax" \ 303 "\n1:\tcmpxchgq %2, "__percpu_arg(1) \ 304 "\n\tjnz 1b" \ 305 : "=&a" (pxo_ret__), "+m" (var) \ 306 : "r" (pxo_new__) \ 307 : "memory"); \ 308 break; \ 309 default: __bad_percpu_size(); \ 310 } \ 311 pxo_ret__; \ 312 }) 313 314 /* 315 * cmpxchg has no such implied lock semantics as a result it is much 316 * more efficient for cpu local operations. 317 */ 318 #define percpu_cmpxchg_op(var, oval, nval) \ 319 ({ \ 320 typeof(var) pco_ret__; \ 321 typeof(var) pco_old__ = (oval); \ 322 typeof(var) pco_new__ = (nval); \ 323 switch (sizeof(var)) { \ 324 case 1: \ 325 asm("cmpxchgb %2, "__percpu_arg(1) \ 326 : "=a" (pco_ret__), "+m" (var) \ 327 : "q" (pco_new__), "0" (pco_old__) \ 328 : "memory"); \ 329 break; \ 330 case 2: \ 331 asm("cmpxchgw %2, "__percpu_arg(1) \ 332 : "=a" (pco_ret__), "+m" (var) \ 333 : "r" (pco_new__), "0" (pco_old__) \ 334 : "memory"); \ 335 break; \ 336 case 4: \ 337 asm("cmpxchgl %2, "__percpu_arg(1) \ 338 : "=a" (pco_ret__), "+m" (var) \ 339 : "r" (pco_new__), "0" (pco_old__) \ 340 : "memory"); \ 341 break; \ 342 case 8: \ 343 asm("cmpxchgq %2, "__percpu_arg(1) \ 344 : "=a" (pco_ret__), "+m" (var) \ 345 : "r" (pco_new__), "0" (pco_old__) \ 346 : "memory"); \ 347 break; \ 348 default: __bad_percpu_size(); \ 349 } \ 350 pco_ret__; \ 351 }) 352 353 /* 354 * percpu_read() makes gcc load the percpu variable every time it is 355 * accessed while percpu_read_stable() allows the value to be cached. 356 * percpu_read_stable() is more efficient and can be used if its value 357 * is guaranteed to be valid across cpus. The current users include 358 * get_current() and get_thread_info() both of which are actually 359 * per-thread variables implemented as per-cpu variables and thus 360 * stable for the duration of the respective task. 361 */ 362 #define percpu_read(var) percpu_from_op("mov", var, "m" (var)) 363 #define percpu_read_stable(var) percpu_from_op("mov", var, "p" (&(var))) 364 #define percpu_write(var, val) percpu_to_op("mov", var, val) 365 #define percpu_add(var, val) percpu_add_op(var, val) 366 #define percpu_sub(var, val) percpu_add_op(var, -(val)) 367 #define percpu_and(var, val) percpu_to_op("and", var, val) 368 #define percpu_or(var, val) percpu_to_op("or", var, val) 369 #define percpu_xor(var, val) percpu_to_op("xor", var, val) 370 #define percpu_inc(var) percpu_unary_op("inc", var) 371 372 #define __this_cpu_read_1(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 373 #define __this_cpu_read_2(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 374 #define __this_cpu_read_4(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 375 376 #define __this_cpu_write_1(pcp, val) percpu_to_op("mov", (pcp), val) 377 #define __this_cpu_write_2(pcp, val) percpu_to_op("mov", (pcp), val) 378 #define __this_cpu_write_4(pcp, val) percpu_to_op("mov", (pcp), val) 379 #define __this_cpu_add_1(pcp, val) percpu_add_op((pcp), val) 380 #define __this_cpu_add_2(pcp, val) percpu_add_op((pcp), val) 381 #define __this_cpu_add_4(pcp, val) percpu_add_op((pcp), val) 382 #define __this_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val) 383 #define __this_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val) 384 #define __this_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val) 385 #define __this_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val) 386 #define __this_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val) 387 #define __this_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val) 388 #define __this_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val) 389 #define __this_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val) 390 #define __this_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val) 391 /* 392 * Generic fallback operations for __this_cpu_xchg_[1-4] are okay and much 393 * faster than an xchg with forced lock semantics. 394 */ 395 #define __this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) 396 #define __this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 397 398 #define this_cpu_read_1(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 399 #define this_cpu_read_2(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 400 #define this_cpu_read_4(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 401 #define this_cpu_write_1(pcp, val) percpu_to_op("mov", (pcp), val) 402 #define this_cpu_write_2(pcp, val) percpu_to_op("mov", (pcp), val) 403 #define this_cpu_write_4(pcp, val) percpu_to_op("mov", (pcp), val) 404 #define this_cpu_add_1(pcp, val) percpu_add_op((pcp), val) 405 #define this_cpu_add_2(pcp, val) percpu_add_op((pcp), val) 406 #define this_cpu_add_4(pcp, val) percpu_add_op((pcp), val) 407 #define this_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val) 408 #define this_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val) 409 #define this_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val) 410 #define this_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val) 411 #define this_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val) 412 #define this_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val) 413 #define this_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val) 414 #define this_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val) 415 #define this_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val) 416 #define this_cpu_xchg_1(pcp, nval) percpu_xchg_op(pcp, nval) 417 #define this_cpu_xchg_2(pcp, nval) percpu_xchg_op(pcp, nval) 418 #define this_cpu_xchg_4(pcp, nval) percpu_xchg_op(pcp, nval) 419 420 #define irqsafe_cpu_add_1(pcp, val) percpu_add_op((pcp), val) 421 #define irqsafe_cpu_add_2(pcp, val) percpu_add_op((pcp), val) 422 #define irqsafe_cpu_add_4(pcp, val) percpu_add_op((pcp), val) 423 #define irqsafe_cpu_and_1(pcp, val) percpu_to_op("and", (pcp), val) 424 #define irqsafe_cpu_and_2(pcp, val) percpu_to_op("and", (pcp), val) 425 #define irqsafe_cpu_and_4(pcp, val) percpu_to_op("and", (pcp), val) 426 #define irqsafe_cpu_or_1(pcp, val) percpu_to_op("or", (pcp), val) 427 #define irqsafe_cpu_or_2(pcp, val) percpu_to_op("or", (pcp), val) 428 #define irqsafe_cpu_or_4(pcp, val) percpu_to_op("or", (pcp), val) 429 #define irqsafe_cpu_xor_1(pcp, val) percpu_to_op("xor", (pcp), val) 430 #define irqsafe_cpu_xor_2(pcp, val) percpu_to_op("xor", (pcp), val) 431 #define irqsafe_cpu_xor_4(pcp, val) percpu_to_op("xor", (pcp), val) 432 #define irqsafe_cpu_xchg_1(pcp, nval) percpu_xchg_op(pcp, nval) 433 #define irqsafe_cpu_xchg_2(pcp, nval) percpu_xchg_op(pcp, nval) 434 #define irqsafe_cpu_xchg_4(pcp, nval) percpu_xchg_op(pcp, nval) 435 436 #ifndef CONFIG_M386 437 #define __this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val) 438 #define __this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val) 439 #define __this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val) 440 #define __this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 441 #define __this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 442 #define __this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 443 444 #define this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val) 445 #define this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val) 446 #define this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val) 447 #define this_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 448 #define this_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 449 #define this_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 450 451 #define irqsafe_cpu_cmpxchg_1(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 452 #define irqsafe_cpu_cmpxchg_2(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 453 #define irqsafe_cpu_cmpxchg_4(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 454 #endif /* !CONFIG_M386 */ 455 456 #ifdef CONFIG_X86_CMPXCHG64 457 #define percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2) \ 458 ({ \ 459 char __ret; \ 460 typeof(o1) __o1 = o1; \ 461 typeof(o1) __n1 = n1; \ 462 typeof(o2) __o2 = o2; \ 463 typeof(o2) __n2 = n2; \ 464 typeof(o2) __dummy = n2; \ 465 asm volatile("cmpxchg8b "__percpu_arg(1)"\n\tsetz %0\n\t" \ 466 : "=a"(__ret), "=m" (pcp1), "=d"(__dummy) \ 467 : "b"(__n1), "c"(__n2), "a"(__o1), "d"(__o2)); \ 468 __ret; \ 469 }) 470 471 #define __this_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2) 472 #define this_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2) 473 #define irqsafe_cpu_cmpxchg_double_4(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg8b_double(pcp1, o1, o2, n1, n2) 474 #endif /* CONFIG_X86_CMPXCHG64 */ 475 476 /* 477 * Per cpu atomic 64 bit operations are only available under 64 bit. 478 * 32 bit must fall back to generic operations. 479 */ 480 #ifdef CONFIG_X86_64 481 #define __this_cpu_read_8(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 482 #define __this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val) 483 #define __this_cpu_add_8(pcp, val) percpu_add_op((pcp), val) 484 #define __this_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val) 485 #define __this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) 486 #define __this_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val) 487 #define __this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val) 488 489 #define this_cpu_read_8(pcp) percpu_from_op("mov", (pcp), "m"(pcp)) 490 #define this_cpu_write_8(pcp, val) percpu_to_op("mov", (pcp), val) 491 #define this_cpu_add_8(pcp, val) percpu_add_op((pcp), val) 492 #define this_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val) 493 #define this_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) 494 #define this_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val) 495 #define this_cpu_add_return_8(pcp, val) percpu_add_return_op(pcp, val) 496 #define this_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) 497 #define this_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 498 499 #define irqsafe_cpu_add_8(pcp, val) percpu_add_op((pcp), val) 500 #define irqsafe_cpu_and_8(pcp, val) percpu_to_op("and", (pcp), val) 501 #define irqsafe_cpu_or_8(pcp, val) percpu_to_op("or", (pcp), val) 502 #define irqsafe_cpu_xor_8(pcp, val) percpu_to_op("xor", (pcp), val) 503 #define irqsafe_cpu_xchg_8(pcp, nval) percpu_xchg_op(pcp, nval) 504 #define irqsafe_cpu_cmpxchg_8(pcp, oval, nval) percpu_cmpxchg_op(pcp, oval, nval) 505 506 /* 507 * Pretty complex macro to generate cmpxchg16 instruction. The instruction 508 * is not supported on early AMD64 processors so we must be able to emulate 509 * it in software. The address used in the cmpxchg16 instruction must be 510 * aligned to a 16 byte boundary. 511 */ 512 #define percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) \ 513 ({ \ 514 char __ret; \ 515 typeof(o1) __o1 = o1; \ 516 typeof(o1) __n1 = n1; \ 517 typeof(o2) __o2 = o2; \ 518 typeof(o2) __n2 = n2; \ 519 typeof(o2) __dummy; \ 520 alternative_io("call this_cpu_cmpxchg16b_emu\n\t" P6_NOP4, \ 521 "cmpxchg16b " __percpu_prefix "(%%rsi)\n\tsetz %0\n\t", \ 522 X86_FEATURE_CX16, \ 523 ASM_OUTPUT2("=a"(__ret), "=d"(__dummy)), \ 524 "S" (&pcp1), "b"(__n1), "c"(__n2), \ 525 "a"(__o1), "d"(__o2) : "memory"); \ 526 __ret; \ 527 }) 528 529 #define __this_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) 530 #define this_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) 531 #define irqsafe_cpu_cmpxchg_double_8(pcp1, pcp2, o1, o2, n1, n2) percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) 532 533 #endif 534 535 /* This is not atomic against other CPUs -- CPU preemption needs to be off */ 536 #define x86_test_and_clear_bit_percpu(bit, var) \ 537 ({ \ 538 int old__; \ 539 asm volatile("btr %2,"__percpu_arg(1)"\n\tsbbl %0,%0" \ 540 : "=r" (old__), "+m" (var) \ 541 : "dIr" (bit)); \ 542 old__; \ 543 }) 544 545 #include <asm-generic/percpu.h> 546 547 /* We can use this directly for local CPU (faster). */ 548 DECLARE_PER_CPU(unsigned long, this_cpu_off); 549 550 #endif /* !__ASSEMBLY__ */ 551 552 #ifdef CONFIG_SMP 553 554 /* 555 * Define the "EARLY_PER_CPU" macros. These are used for some per_cpu 556 * variables that are initialized and accessed before there are per_cpu 557 * areas allocated. 558 */ 559 560 #define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \ 561 DEFINE_PER_CPU(_type, _name) = _initvalue; \ 562 __typeof__(_type) _name##_early_map[NR_CPUS] __initdata = \ 563 { [0 ... NR_CPUS-1] = _initvalue }; \ 564 __typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map 565 566 #define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \ 567 EXPORT_PER_CPU_SYMBOL(_name) 568 569 #define DECLARE_EARLY_PER_CPU(_type, _name) \ 570 DECLARE_PER_CPU(_type, _name); \ 571 extern __typeof__(_type) *_name##_early_ptr; \ 572 extern __typeof__(_type) _name##_early_map[] 573 574 #define early_per_cpu_ptr(_name) (_name##_early_ptr) 575 #define early_per_cpu_map(_name, _idx) (_name##_early_map[_idx]) 576 #define early_per_cpu(_name, _cpu) \ 577 *(early_per_cpu_ptr(_name) ? \ 578 &early_per_cpu_ptr(_name)[_cpu] : \ 579 &per_cpu(_name, _cpu)) 580 581 #else /* !CONFIG_SMP */ 582 #define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \ 583 DEFINE_PER_CPU(_type, _name) = _initvalue 584 585 #define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \ 586 EXPORT_PER_CPU_SYMBOL(_name) 587 588 #define DECLARE_EARLY_PER_CPU(_type, _name) \ 589 DECLARE_PER_CPU(_type, _name) 590 591 #define early_per_cpu(_name, _cpu) per_cpu(_name, _cpu) 592 #define early_per_cpu_ptr(_name) NULL 593 /* no early_per_cpu_map() */ 594 595 #endif /* !CONFIG_SMP */ 596 597 #endif /* _ASM_X86_PERCPU_H */ 598