1 /* $Id$
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
8 */
9 #ifndef _ASM_SN_PCI_PCIIO_H
10 #define _ASM_SN_PCI_PCIIO_H
11
12 /*
13 * pciio.h -- platform-independent PCI interface
14 */
15
16 #ifdef __KERNEL__
17 #include <linux/config.h>
18 #include <linux/ioport.h>
19 #include <asm/sn/ioerror.h>
20 #include <asm/sn/driver.h>
21 #include <asm/sn/invent.h>
22 #include <asm/sn/hcl.h>
23 #else
24 #include <linux/config.h>
25 #include <linux/ioport.h>
26 #include <ioerror.h>
27 #include <driver.h>
28 #include <hcl.h>
29 #endif
30
31 #ifndef __ASSEMBLY__
32
33 #ifdef __KERNEL__
34 #include <asm/sn/dmamap.h>
35 #include <asm/sn/alenlist.h>
36 #else
37 #include <dmamap.h>
38 #include <alenlist.h>
39 #endif
40
41 typedef int pciio_vendor_id_t;
42
43 #define PCIIO_VENDOR_ID_NONE (-1)
44
45 typedef int pciio_device_id_t;
46
47 #define PCIIO_DEVICE_ID_NONE (-1)
48
49 typedef uint8_t pciio_bus_t; /* PCI bus number (0..255) */
50 typedef uint8_t pciio_slot_t; /* PCI slot number (0..31, 255) */
51 typedef uint8_t pciio_function_t; /* PCI func number (0..7, 255) */
52
53 #define PCIIO_SLOTS ((pciio_slot_t)32)
54 #define PCIIO_FUNCS ((pciio_function_t)8)
55
56 #define PCIIO_SLOT_NONE ((pciio_slot_t)255)
57 #define PCIIO_FUNC_NONE ((pciio_function_t)255)
58
59 typedef int pciio_intr_line_t; /* PCI interrupt line(s) */
60
61 #define PCIIO_INTR_LINE(n) (0x1 << (n))
62 #define PCIIO_INTR_LINE_A (0x1)
63 #define PCIIO_INTR_LINE_B (0x2)
64 #define PCIIO_INTR_LINE_C (0x4)
65 #define PCIIO_INTR_LINE_D (0x8)
66
67 typedef int pciio_space_t; /* PCI address space designation */
68
69 #define PCIIO_SPACE_NONE (0)
70 #define PCIIO_SPACE_ROM (1)
71 #define PCIIO_SPACE_IO (2)
72 /* PCIIO_SPACE_ (3) */
73 #define PCIIO_SPACE_MEM (4)
74 #define PCIIO_SPACE_MEM32 (5)
75 #define PCIIO_SPACE_MEM64 (6)
76 #define PCIIO_SPACE_CFG (7)
77 #define PCIIO_SPACE_WIN0 (8)
78 #define PCIIO_SPACE_WIN(n) (PCIIO_SPACE_WIN0+(n)) /* 8..13 */
79 /* PCIIO_SPACE_ (14) */
80 #define PCIIO_SPACE_BAD (15)
81
82 #if 1 /* does anyone really use these? */
83 #define PCIIO_SPACE_USER0 (20)
84 #define PCIIO_SPACE_USER(n) (PCIIO_SPACE_USER0+(n)) /* 20 .. ? */
85 #endif
86
87 /*
88 * PCI_NOWHERE is the error value returned in
89 * place of a PCI address when there is no
90 * corresponding address.
91 */
92 #define PCI_NOWHERE (0)
93
94 /*
95 * Acceptable flag bits for pciio service calls
96 *
97 * PCIIO_FIXED: require that mappings be established
98 * using fixed sharable resources; address
99 * translation results will be permanently
100 * available. (PIOMAP_FIXED and DMAMAP_FIXED are
101 * the same numeric value and are acceptable).
102 * PCIIO_NOSLEEP: if any part of the operation would
103 * sleep waiting for resoruces, return an error
104 * instead. (PIOMAP_NOSLEEP and DMAMAP_NOSLEEP are
105 * the same numeric value and are acceptable).
106 * PCIIO_INPLACE: when operating on alenlist structures,
107 * reuse the source alenlist rather than creating a
108 * new one. (PIOMAP_INPLACE and DMAMAP_INPLACE are
109 * the same numeric value and are acceptable).
110 *
111 * PCIIO_DMA_CMD: configure this stream as a
112 * generic "command" stream. Generally this
113 * means turn off prefetchers and write
114 * gatherers, and whatever else might be
115 * necessary to make command ring DMAs
116 * work as expected.
117 * PCIIO_DMA_DATA: configure this stream as a
118 * generic "data" stream. Generally, this
119 * means turning on prefetchers and write
120 * gatherers, and anything else that might
121 * increase the DMA throughput (short of
122 * using "high priority" or "real time"
123 * resources that may lower overall system
124 * performance).
125 * PCIIO_DMA_A64: this device is capable of
126 * using 64-bit DMA addresses. Unless this
127 * flag is specified, it is assumed that
128 * the DMA address must be in the low 4G
129 * of PCI space.
130 * PCIIO_PREFETCH: if there are prefetchers
131 * available, they can be turned on.
132 * PCIIO_NOPREFETCH: any prefetchers along
133 * the dma path should be turned off.
134 * PCIIO_WRITE_GATHER: if there are write gatherers
135 * available, they can be turned on.
136 * PCIIO_NOWRITE_GATHER: any write gatherers along
137 * the dma path should be turned off.
138 *
139 * PCIIO_BYTE_STREAM: the DMA stream represents a group
140 * of ordered bytes. Arrange all byte swapping
141 * hardware so that the bytes land in the correct
142 * order. This is a common setting for data
143 * channels, but is NOT implied by PCIIO_DMA_DATA.
144 * PCIIO_WORD_VALUES: the DMA stream is used to
145 * communicate quantities stored in multiple bytes,
146 * and the device doing the DMA is little-endian;
147 * arrange any swapping hardware so that
148 * 32-bit-wide values are maintained. This is a
149 * common setting for command rings that contain
150 * DMA addresses and counts, but is NOT implied by
151 * PCIIO_DMA_CMD. CPU Accesses to 16-bit fields
152 * must have their address xor-ed with 2, and
153 * accesses to individual bytes must have their
154 * addresses xor-ed with 3 relative to what the
155 * device expects.
156 *
157 * NOTE: any "provider specific" flags that
158 * conflict with the generic flags will
159 * override the generic flags, locally
160 * at that provider.
161 *
162 * Also, note that PCI-generic flags (PCIIO_) are
163 * in bits 0-14. The upper bits, 15-31, are reserved
164 * for PCI implementation-specific flags.
165 */
166
167 #define PCIIO_FIXED DMAMAP_FIXED
168 #define PCIIO_NOSLEEP DMAMAP_NOSLEEP
169 #define PCIIO_INPLACE DMAMAP_INPLACE
170
171 #define PCIIO_DMA_CMD 0x0010
172 #define PCIIO_DMA_DATA 0x0020
173 #define PCIIO_DMA_A64 0x0040
174
175 #define PCIIO_WRITE_GATHER 0x0100
176 #define PCIIO_NOWRITE_GATHER 0x0200
177 #define PCIIO_PREFETCH 0x0400
178 #define PCIIO_NOPREFETCH 0x0800
179
180 /* Requesting an endianness setting that the
181 * underlieing hardware can not support
182 * WILL result in a failure to allocate
183 * dmamaps or complete a dmatrans.
184 */
185 #define PCIIO_BYTE_STREAM 0x1000 /* set BYTE SWAP for "byte stream" */
186 #define PCIIO_WORD_VALUES 0x2000 /* set BYTE SWAP for "word values" */
187
188 /*
189 * Interface to deal with PCI endianness.
190 * The driver calls pciio_endian_set once, supplying the actual endianness of
191 * the device and the desired endianness. On SGI systems, only use LITTLE if
192 * dealing with a driver that does software swizzling. Most of the time,
193 * it's preferable to request BIG. The return value indicates the endianness
194 * that is actually achieved. On systems that support hardware swizzling,
195 * the achieved endianness will be the desired endianness. On systems without
196 * swizzle hardware, the achieved endianness will be the device's endianness.
197 */
198 typedef enum pciio_endian_e {
199 PCIDMA_ENDIAN_BIG,
200 PCIDMA_ENDIAN_LITTLE
201 } pciio_endian_t;
202
203 /*
204 * handles of various sorts
205 */
206 typedef struct pciio_piomap_s *pciio_piomap_t;
207 typedef struct pciio_dmamap_s *pciio_dmamap_t;
208 typedef struct pciio_intr_s *pciio_intr_t;
209 typedef struct pciio_info_s *pciio_info_t;
210 typedef struct pciio_piospace_s *pciio_piospace_t;
211 typedef struct pciio_win_info_s *pciio_win_info_t;
212 typedef struct pciio_win_map_s *pciio_win_map_t;
213 typedef struct pciio_win_alloc_s *pciio_win_alloc_t;
214
215 /* PIO MANAGEMENT */
216
217 /*
218 * A NOTE ON PCI PIO ADDRESSES
219 *
220 * PCI supports three different address spaces: CFG
221 * space, MEM space and I/O space. Further, each
222 * card always accepts CFG accesses at an address
223 * based on which slot it is attached to, but can
224 * decode up to six address ranges.
225 *
226 * Assignment of the base address registers for all
227 * PCI devices is handled centrally; most commonly,
228 * device drivers will want to talk to offsets
229 * within one or another of the address ranges. In
230 * order to do this, which of these "address
231 * spaces" the PIO is directed into must be encoded
232 * in the flag word.
233 *
234 * We reserve the right to defer allocation of PCI
235 * address space for a device window until the
236 * driver makes a piomap_alloc or piotrans_addr
237 * request.
238 *
239 * If a device driver mucks with its device's base
240 * registers through a PIO mapping to CFG space,
241 * results of further PIO through the corresponding
242 * window are UNDEFINED.
243 *
244 * Windows are named by the index in the base
245 * address register set for the device of the
246 * desired register; IN THE CASE OF 64 BIT base
247 * registers, the index should be to the word of
248 * the register that contains the mapping type
249 * bits; since the PCI CFG space is natively
250 * organized little-endian fashion, this is the
251 * first of the two words.
252 *
253 * AT THE MOMENT, any required corrections for
254 * endianness are the responsibility of the device
255 * driver; not all platforms support control in
256 * hardware of byteswapping hardware. We anticipate
257 * providing flag bits to the PIO and DMA
258 * management interfaces to request different
259 * configurations of byteswapping hardware.
260 *
261 * PIO Accesses to CFG space via the "Bridge" ASIC
262 * used in IP30 platforms preserve the native byte
263 * significance within the 32-bit word; byte
264 * addresses for single byte accesses need to be
265 * XORed with 3, and addresses for 16-bit accesses
266 * need to be XORed with 2.
267 *
268 * The IOC3 used on IP30, and other SGI PCI devices
269 * as well, require use of 32-bit accesses to their
270 * configuration space registers. Any potential PCI
271 * bus providers need to be aware of this requirement.
272 */
273
274 #define PCIIO_PIOMAP_CFG (0x1)
275 #define PCIIO_PIOMAP_MEM (0x2)
276 #define PCIIO_PIOMAP_IO (0x4)
277 #define PCIIO_PIOMAP_WIN(n) (0x8+(n))
278
279 typedef pciio_piomap_t
280 pciio_piomap_alloc_f (vertex_hdl_t dev, /* set up mapping for this device */
281 device_desc_t dev_desc, /* device descriptor */
282 pciio_space_t space, /* which address space */
283 iopaddr_t pcipio_addr, /* starting address */
284 size_t byte_count,
285 size_t byte_count_max, /* maximum size of a mapping */
286 unsigned flags); /* defined in sys/pio.h */
287
288 typedef void
289 pciio_piomap_free_f (pciio_piomap_t pciio_piomap);
290
291 typedef caddr_t
292 pciio_piomap_addr_f (pciio_piomap_t pciio_piomap, /* mapping resources */
293 iopaddr_t pciio_addr, /* map for this pcipio address */
294 size_t byte_count); /* map this many bytes */
295
296 typedef void
297 pciio_piomap_done_f (pciio_piomap_t pciio_piomap);
298
299 typedef caddr_t
300 pciio_piotrans_addr_f (vertex_hdl_t dev, /* translate for this device */
301 device_desc_t dev_desc, /* device descriptor */
302 pciio_space_t space, /* which address space */
303 iopaddr_t pciio_addr, /* starting address */
304 size_t byte_count, /* map this many bytes */
305 unsigned flags);
306
307 typedef caddr_t
308 pciio_pio_addr_f (vertex_hdl_t dev, /* translate for this device */
309 device_desc_t dev_desc, /* device descriptor */
310 pciio_space_t space, /* which address space */
311 iopaddr_t pciio_addr, /* starting address */
312 size_t byte_count, /* map this many bytes */
313 pciio_piomap_t *mapp, /* in case a piomap was needed */
314 unsigned flags);
315
316 typedef iopaddr_t
317 pciio_piospace_alloc_f (vertex_hdl_t dev, /* PIO space for this device */
318 device_desc_t dev_desc, /* Device descriptor */
319 pciio_space_t space, /* which address space */
320 size_t byte_count, /* Number of bytes of space */
321 size_t alignment); /* Alignment of allocation */
322
323 typedef void
324 pciio_piospace_free_f (vertex_hdl_t dev, /* Device freeing space */
325 pciio_space_t space, /* Which space is freed */
326 iopaddr_t pci_addr, /* Address being freed */
327 size_t size); /* Size freed */
328
329 /* DMA MANAGEMENT */
330
331 typedef pciio_dmamap_t
332 pciio_dmamap_alloc_f (vertex_hdl_t dev, /* set up mappings for this device */
333 device_desc_t dev_desc, /* device descriptor */
334 size_t byte_count_max, /* max size of a mapping */
335 unsigned flags); /* defined in dma.h */
336
337 typedef void
338 pciio_dmamap_free_f (pciio_dmamap_t dmamap);
339
340 typedef iopaddr_t
341 pciio_dmamap_addr_f (pciio_dmamap_t dmamap, /* use these mapping resources */
342 paddr_t paddr, /* map for this address */
343 size_t byte_count); /* map this many bytes */
344
345 typedef void
346 pciio_dmamap_done_f (pciio_dmamap_t dmamap);
347
348 typedef iopaddr_t
349 pciio_dmatrans_addr_f (vertex_hdl_t dev, /* translate for this device */
350 device_desc_t dev_desc, /* device descriptor */
351 paddr_t paddr, /* system physical address */
352 size_t byte_count, /* length */
353 unsigned flags); /* defined in dma.h */
354
355 typedef void
356 pciio_dmamap_drain_f (pciio_dmamap_t map);
357
358 typedef void
359 pciio_dmaaddr_drain_f (vertex_hdl_t vhdl,
360 paddr_t addr,
361 size_t bytes);
362
363 typedef void
364 pciio_dmalist_drain_f (vertex_hdl_t vhdl,
365 alenlist_t list);
366
367 /* INTERRUPT MANAGEMENT */
368
369 typedef pciio_intr_t
370 pciio_intr_alloc_f (vertex_hdl_t dev, /* which PCI device */
371 device_desc_t dev_desc, /* device descriptor */
372 pciio_intr_line_t lines, /* which line(s) will be used */
373 vertex_hdl_t owner_dev); /* owner of this intr */
374
375 typedef void
376 pciio_intr_free_f (pciio_intr_t intr_hdl);
377
378 typedef int
379 pciio_intr_connect_f (pciio_intr_t intr_hdl, intr_func_t intr_func, intr_arg_t intr_arg); /* pciio intr resource handle */
380
381 typedef void
382 pciio_intr_disconnect_f (pciio_intr_t intr_hdl);
383
384 typedef vertex_hdl_t
385 pciio_intr_cpu_get_f (pciio_intr_t intr_hdl); /* pciio intr resource handle */
386
387 /* CONFIGURATION MANAGEMENT */
388
389 typedef void
390 pciio_provider_startup_f (vertex_hdl_t pciio_provider);
391
392 typedef void
393 pciio_provider_shutdown_f (vertex_hdl_t pciio_provider);
394
395 typedef int
396 pciio_reset_f (vertex_hdl_t conn); /* pci connection point */
397
398 typedef pciio_endian_t /* actual endianness */
399 pciio_endian_set_f (vertex_hdl_t dev, /* specify endianness for this device */
400 pciio_endian_t device_end, /* endianness of device */
401 pciio_endian_t desired_end); /* desired endianness */
402
403 typedef uint64_t
404 pciio_config_get_f (vertex_hdl_t conn, /* pci connection point */
405 unsigned reg, /* register byte offset */
406 unsigned size); /* width in bytes (1..4) */
407
408 typedef void
409 pciio_config_set_f (vertex_hdl_t conn, /* pci connection point */
410 unsigned reg, /* register byte offset */
411 unsigned size, /* width in bytes (1..4) */
412 uint64_t value); /* value to store */
413
414 typedef int
415 pciio_error_devenable_f (vertex_hdl_t pconn_vhdl, int error_code);
416
417 typedef pciio_slot_t
418 pciio_error_extract_f (vertex_hdl_t vhdl,
419 pciio_space_t *spacep,
420 iopaddr_t *addrp);
421
422 typedef void
423 pciio_driver_reg_callback_f (vertex_hdl_t conn,
424 int key1,
425 int key2,
426 int error);
427
428 typedef void
429 pciio_driver_unreg_callback_f (vertex_hdl_t conn, /* pci connection point */
430 int key1,
431 int key2,
432 int error);
433
434 typedef int
435 pciio_device_unregister_f (vertex_hdl_t conn);
436
437 typedef int
438 pciio_dma_enabled_f (vertex_hdl_t conn);
439
440 /*
441 * Adapters that provide a PCI interface adhere to this software interface.
442 */
443 typedef struct pciio_provider_s {
444 /* PIO MANAGEMENT */
445 pciio_piomap_alloc_f *piomap_alloc;
446 pciio_piomap_free_f *piomap_free;
447 pciio_piomap_addr_f *piomap_addr;
448 pciio_piomap_done_f *piomap_done;
449 pciio_piotrans_addr_f *piotrans_addr;
450 pciio_piospace_alloc_f *piospace_alloc;
451 pciio_piospace_free_f *piospace_free;
452
453 /* DMA MANAGEMENT */
454 pciio_dmamap_alloc_f *dmamap_alloc;
455 pciio_dmamap_free_f *dmamap_free;
456 pciio_dmamap_addr_f *dmamap_addr;
457 pciio_dmamap_done_f *dmamap_done;
458 pciio_dmatrans_addr_f *dmatrans_addr;
459 pciio_dmamap_drain_f *dmamap_drain;
460 pciio_dmaaddr_drain_f *dmaaddr_drain;
461 pciio_dmalist_drain_f *dmalist_drain;
462
463 /* INTERRUPT MANAGEMENT */
464 pciio_intr_alloc_f *intr_alloc;
465 pciio_intr_free_f *intr_free;
466 pciio_intr_connect_f *intr_connect;
467 pciio_intr_disconnect_f *intr_disconnect;
468 pciio_intr_cpu_get_f *intr_cpu_get;
469
470 /* CONFIGURATION MANAGEMENT */
471 pciio_provider_startup_f *provider_startup;
472 pciio_provider_shutdown_f *provider_shutdown;
473 pciio_reset_f *reset;
474 pciio_endian_set_f *endian_set;
475 pciio_config_get_f *config_get;
476 pciio_config_set_f *config_set;
477
478 /* Error handling interface */
479 pciio_error_devenable_f *error_devenable;
480 pciio_error_extract_f *error_extract;
481
482 /* Callback support */
483 pciio_driver_reg_callback_f *driver_reg_callback;
484 pciio_driver_unreg_callback_f *driver_unreg_callback;
485 pciio_device_unregister_f *device_unregister;
486 pciio_dma_enabled_f *dma_enabled;
487 } pciio_provider_t;
488
489 /* PCI devices use these standard PCI provider interfaces */
490 extern pciio_piomap_alloc_f pciio_piomap_alloc;
491 extern pciio_piomap_free_f pciio_piomap_free;
492 extern pciio_piomap_addr_f pciio_piomap_addr;
493 extern pciio_piomap_done_f pciio_piomap_done;
494 extern pciio_piotrans_addr_f pciio_piotrans_addr;
495 extern pciio_pio_addr_f pciio_pio_addr;
496 extern pciio_piospace_alloc_f pciio_piospace_alloc;
497 extern pciio_piospace_free_f pciio_piospace_free;
498 extern pciio_dmamap_alloc_f pciio_dmamap_alloc;
499 extern pciio_dmamap_free_f pciio_dmamap_free;
500 extern pciio_dmamap_addr_f pciio_dmamap_addr;
501 extern pciio_dmamap_done_f pciio_dmamap_done;
502 extern pciio_dmatrans_addr_f pciio_dmatrans_addr;
503 extern pciio_dmamap_drain_f pciio_dmamap_drain;
504 extern pciio_dmaaddr_drain_f pciio_dmaaddr_drain;
505 extern pciio_dmalist_drain_f pciio_dmalist_drain;
506 extern pciio_intr_alloc_f pciio_intr_alloc;
507 extern pciio_intr_free_f pciio_intr_free;
508 extern pciio_intr_connect_f pciio_intr_connect;
509 extern pciio_intr_disconnect_f pciio_intr_disconnect;
510 extern pciio_intr_cpu_get_f pciio_intr_cpu_get;
511 extern pciio_provider_startup_f pciio_provider_startup;
512 extern pciio_provider_shutdown_f pciio_provider_shutdown;
513 extern pciio_reset_f pciio_reset;
514 extern pciio_endian_set_f pciio_endian_set;
515 extern pciio_config_get_f pciio_config_get;
516 extern pciio_config_set_f pciio_config_set;
517
518 /* Widgetdev in the IOERROR structure is encoded as follows.
519 * +---------------------------+
520 * | slot (7:3) | function(2:0)|
521 * +---------------------------+
522 * Following are the convenience interfaces to get at form
523 * a widgetdev or to break it into its constituents.
524 */
525
526 #define PCIIO_WIDGETDEV_SLOT_SHFT 3
527 #define PCIIO_WIDGETDEV_SLOT_MASK 0x1f
528 #define PCIIO_WIDGETDEV_FUNC_MASK 0x7
529
530 #define pciio_widgetdev_create(slot,func) \
531 (((slot) << PCIIO_WIDGETDEV_SLOT_SHFT) + (func))
532
533 #define pciio_widgetdev_slot_get(wdev) \
534 (((wdev) >> PCIIO_WIDGETDEV_SLOT_SHFT) & PCIIO_WIDGETDEV_SLOT_MASK)
535
536 #define pciio_widgetdev_func_get(wdev) \
537 ((wdev) & PCIIO_WIDGETDEV_FUNC_MASK)
538
539
540 /* Generic PCI card initialization interface
541 */
542
543 extern int
544 pciio_driver_register (pciio_vendor_id_t vendor_id, /* card's vendor number */
545 pciio_device_id_t device_id, /* card's device number */
546 char *driver_prefix, /* driver prefix */
547 unsigned flags);
548
549 extern void
550 pciio_error_register (vertex_hdl_t pconn, /* which slot */
551 error_handler_f *efunc, /* function to call */
552 error_handler_arg_t einfo); /* first parameter */
553
554 extern void pciio_driver_unregister(char *driver_prefix);
555
556 typedef void pciio_iter_f(vertex_hdl_t pconn); /* a connect point */
557
558 /* Interfaces used by PCI Bus Providers to talk to
559 * the Generic PCI layer.
560 */
561 extern vertex_hdl_t
562 pciio_device_register (vertex_hdl_t connectpt, /* vertex at center of bus */
563 vertex_hdl_t master, /* card's master ASIC (pci provider) */
564 pciio_slot_t slot, /* card's slot (0..?) */
565 pciio_function_t func, /* card's func (0..?) */
566 pciio_vendor_id_t vendor, /* card's vendor number */
567 pciio_device_id_t device); /* card's device number */
568
569 extern void
570 pciio_device_unregister(vertex_hdl_t connectpt);
571
572 extern pciio_info_t
573 pciio_device_info_new (pciio_info_t pciio_info, /* preallocated info struct */
574 vertex_hdl_t master, /* card's master ASIC (pci provider) */
575 pciio_slot_t slot, /* card's slot (0..?) */
576 pciio_function_t func, /* card's func (0..?) */
577 pciio_vendor_id_t vendor, /* card's vendor number */
578 pciio_device_id_t device); /* card's device number */
579
580 extern void
581 pciio_device_info_free(pciio_info_t pciio_info);
582
583 extern vertex_hdl_t
584 pciio_device_info_register(
585 vertex_hdl_t connectpt, /* vertex at center of bus */
586 pciio_info_t pciio_info); /* details about conn point */
587
588 extern void
589 pciio_device_info_unregister(
590 vertex_hdl_t connectpt, /* vertex at center of bus */
591 pciio_info_t pciio_info); /* details about conn point */
592
593
594 extern int
595 pciio_device_attach(
596 vertex_hdl_t pcicard, /* vertex created by pciio_device_register */
597 int drv_flags);
598 extern int
599 pciio_device_detach(
600 vertex_hdl_t pcicard, /* vertex created by pciio_device_register */
601 int drv_flags);
602
603
604 /* create and initialize empty window mapping resource */
605 extern pciio_win_map_t
606 pciio_device_win_map_new(pciio_win_map_t win_map, /* preallocated win map structure */
607 size_t region_size, /* size of region to be tracked */
608 size_t page_size); /* allocation page size */
609
610 /* destroy window mapping resource freeing up ancillary resources */
611 extern void
612 pciio_device_win_map_free(pciio_win_map_t win_map); /* preallocated win map structure */
613
614 /* populate window mapping with free range of addresses */
615 extern void
616 pciio_device_win_populate(pciio_win_map_t win_map, /* win map */
617 iopaddr_t ioaddr, /* base address of free range */
618 size_t size); /* size of free range */
619
620 /* allocate window from mapping resource */
621 extern iopaddr_t
622 pciio_device_win_alloc(struct resource * res,
623 pciio_win_alloc_t win_alloc, /* opaque allocation cookie */
624 size_t start, /* start unit, or 0 */
625 size_t size, /* size of allocation */
626 size_t align); /* alignment of allocation */
627
628 /* free previously allocated window */
629 extern void
630 pciio_device_win_free(pciio_win_alloc_t win_alloc); /* opaque allocation cookie */
631
632
633 /*
634 * Generic PCI interface, for use with all PCI providers
635 * and all PCI devices.
636 */
637
638 /* Generic PCI interrupt interfaces */
639 extern vertex_hdl_t pciio_intr_dev_get(pciio_intr_t pciio_intr);
640 extern vertex_hdl_t pciio_intr_cpu_get(pciio_intr_t pciio_intr);
641
642 /* Generic PCI pio interfaces */
643 extern vertex_hdl_t pciio_pio_dev_get(pciio_piomap_t pciio_piomap);
644 extern pciio_slot_t pciio_pio_slot_get(pciio_piomap_t pciio_piomap);
645 extern pciio_space_t pciio_pio_space_get(pciio_piomap_t pciio_piomap);
646 extern iopaddr_t pciio_pio_pciaddr_get(pciio_piomap_t pciio_piomap);
647 extern ulong pciio_pio_mapsz_get(pciio_piomap_t pciio_piomap);
648 extern caddr_t pciio_pio_kvaddr_get(pciio_piomap_t pciio_piomap);
649
650 /* Generic PCI dma interfaces */
651 extern vertex_hdl_t pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap);
652
653 /* Register/unregister PCI providers and get implementation handle */
654 extern void pciio_provider_register(vertex_hdl_t provider, pciio_provider_t *pciio_fns);
655 extern void pciio_provider_unregister(vertex_hdl_t provider);
656 extern pciio_provider_t *pciio_provider_fns_get(vertex_hdl_t provider);
657
658 /* Generic pci slot information access interface */
659 extern pciio_info_t pciio_info_chk(vertex_hdl_t vhdl);
660 extern pciio_info_t pciio_info_get(vertex_hdl_t vhdl);
661 extern pciio_info_t pciio_hostinfo_get(vertex_hdl_t vhdl);
662 extern void pciio_info_set(vertex_hdl_t vhdl, pciio_info_t widget_info);
663 extern vertex_hdl_t pciio_info_dev_get(pciio_info_t pciio_info);
664 extern vertex_hdl_t pciio_info_hostdev_get(pciio_info_t pciio_info);
665 extern pciio_bus_t pciio_info_bus_get(pciio_info_t pciio_info);
666 extern pciio_slot_t pciio_info_slot_get(pciio_info_t pciio_info);
667 extern pciio_function_t pciio_info_function_get(pciio_info_t pciio_info);
668 extern pciio_vendor_id_t pciio_info_vendor_id_get(pciio_info_t pciio_info);
669 extern pciio_device_id_t pciio_info_device_id_get(pciio_info_t pciio_info);
670 extern vertex_hdl_t pciio_info_master_get(pciio_info_t pciio_info);
671 extern arbitrary_info_t pciio_info_mfast_get(pciio_info_t pciio_info);
672 extern pciio_provider_t *pciio_info_pops_get(pciio_info_t pciio_info);
673 extern error_handler_f *pciio_info_efunc_get(pciio_info_t);
674 extern error_handler_arg_t *pciio_info_einfo_get(pciio_info_t);
675 extern pciio_space_t pciio_info_bar_space_get(pciio_info_t, int);
676 extern iopaddr_t pciio_info_bar_base_get(pciio_info_t, int);
677 extern size_t pciio_info_bar_size_get(pciio_info_t, int);
678 extern iopaddr_t pciio_info_rom_base_get(pciio_info_t);
679 extern size_t pciio_info_rom_size_get(pciio_info_t);
680 extern int pciio_info_type1_get(pciio_info_t);
681 extern int pciio_error_handler(vertex_hdl_t, int, ioerror_mode_t, ioerror_t *);
682 extern int pciio_dma_enabled(vertex_hdl_t);
683
684 /**
685 * sn_pci_set_vchan - Set the requested Virtual Channel bits into the mapped DMA
686 * address.
687 * @pci_dev: pci device pointer
688 * @addr: mapped dma address
689 * @vchan: Virtual Channel to use 0 or 1.
690 *
691 * Set the Virtual Channel bit in the mapped dma address.
692 */
693 static inline int
sn_pci_set_vchan(struct pci_dev * pci_dev,dma_addr_t * addr,int vchan)694 sn_pci_set_vchan(struct pci_dev *pci_dev,
695 dma_addr_t *addr,
696 int vchan)
697 {
698
699 if (vchan > 1) {
700 return -1;
701 }
702
703 if (!(*addr >> 32)) /* Using a mask here would be cleaner */
704 return 0; /* but this generates better code */
705
706 if (vchan == 1) {
707 /* Set Bit 57 */
708 *addr |= (1UL << 57);
709 } else {
710 /* Clear Bit 57 */
711 *addr &= ~(1UL << 57);
712 }
713
714 return 0;
715 }
716
717 #endif /* C or C++ */
718
719
720 /*
721 * Prototypes
722 */
723
724 int snia_badaddr_val(volatile void *addr, int len, volatile void *ptr);
725 nasid_t snia_get_console_nasid(void);
726 nasid_t snia_get_master_baseio_nasid(void);
727 void snia_ioerror_dump(char *name, int error_code, int error_mode, ioerror_t *ioerror);
728 int snia_pcibr_rrb_alloc(struct pci_dev *pci_dev, int *count_vchan0, int *count_vchan1);
729 pciio_endian_t snia_pciio_endian_set(struct pci_dev *pci_dev,
730 pciio_endian_t device_end, pciio_endian_t desired_end);
731 iopaddr_t snia_pciio_dmatrans_addr(struct pci_dev *pci_dev, device_desc_t dev_desc,
732 paddr_t paddr, size_t byte_count, unsigned flags);
733 pciio_dmamap_t snia_pciio_dmamap_alloc(struct pci_dev *pci_dev,
734 device_desc_t dev_desc, size_t byte_count_max, unsigned flags);
735 void snia_pciio_dmamap_free(pciio_dmamap_t pciio_dmamap);
736 iopaddr_t snia_pciio_dmamap_addr(pciio_dmamap_t pciio_dmamap, paddr_t paddr,
737 size_t byte_count);
738 void snia_pciio_dmamap_done(pciio_dmamap_t pciio_dmamap);
739 void *snia_kmem_zalloc(size_t size);
740 void snia_kmem_free(void *ptr, size_t size);
741 void *snia_kmem_alloc_node(register size_t size, cnodeid_t node);
742
743 #endif /* _ASM_SN_PCI_PCIIO_H */
744