1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * PCI Express PCI Hot Plug Driver
4  *
5  * Copyright (C) 1995,2001 Compaq Computer Corporation
6  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7  * Copyright (C) 2001 IBM Corp.
8  * Copyright (C) 2003-2004 Intel Corporation
9  *
10  * All rights reserved.
11  *
12  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
13  */
14 
15 #define dev_fmt(fmt) "pciehp: " fmt
16 
17 #include <linux/dmi.h>
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/jiffies.h>
21 #include <linux/kthread.h>
22 #include <linux/pci.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 
27 #include "../pci.h"
28 #include "pciehp.h"
29 
30 static const struct dmi_system_id inband_presence_disabled_dmi_table[] = {
31 	/*
32 	 * Match all Dell systems, as some Dell systems have inband
33 	 * presence disabled on NVMe slots (but don't support the bit to
34 	 * report it). Setting inband presence disabled should have no
35 	 * negative effect, except on broken hotplug slots that never
36 	 * assert presence detect--and those will still work, they will
37 	 * just have a bit of extra delay before being probed.
38 	 */
39 	{
40 		.ident = "Dell System",
41 		.matches = {
42 			DMI_MATCH(DMI_OEM_STRING, "Dell System"),
43 		},
44 	},
45 	{}
46 };
47 
ctrl_dev(struct controller * ctrl)48 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
49 {
50 	return ctrl->pcie->port;
51 }
52 
53 static irqreturn_t pciehp_isr(int irq, void *dev_id);
54 static irqreturn_t pciehp_ist(int irq, void *dev_id);
55 static int pciehp_poll(void *data);
56 
pciehp_request_irq(struct controller * ctrl)57 static inline int pciehp_request_irq(struct controller *ctrl)
58 {
59 	int retval, irq = ctrl->pcie->irq;
60 
61 	if (pciehp_poll_mode) {
62 		ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
63 						"pciehp_poll-%s",
64 						slot_name(ctrl));
65 		return PTR_ERR_OR_ZERO(ctrl->poll_thread);
66 	}
67 
68 	/* Installs the interrupt handler */
69 	retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
70 				      IRQF_SHARED, "pciehp", ctrl);
71 	if (retval)
72 		ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
73 			 irq);
74 	return retval;
75 }
76 
pciehp_free_irq(struct controller * ctrl)77 static inline void pciehp_free_irq(struct controller *ctrl)
78 {
79 	if (pciehp_poll_mode)
80 		kthread_stop(ctrl->poll_thread);
81 	else
82 		free_irq(ctrl->pcie->irq, ctrl);
83 }
84 
pcie_poll_cmd(struct controller * ctrl,int timeout)85 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
86 {
87 	struct pci_dev *pdev = ctrl_dev(ctrl);
88 	u16 slot_status;
89 
90 	do {
91 		pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
92 		if (PCI_POSSIBLE_ERROR(slot_status)) {
93 			ctrl_info(ctrl, "%s: no response from device\n",
94 				  __func__);
95 			return 0;
96 		}
97 
98 		if (slot_status & PCI_EXP_SLTSTA_CC) {
99 			pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
100 						   PCI_EXP_SLTSTA_CC);
101 			ctrl->cmd_busy = 0;
102 			smp_mb();
103 			return 1;
104 		}
105 		msleep(10);
106 		timeout -= 10;
107 	} while (timeout >= 0);
108 	return 0;	/* timeout */
109 }
110 
pcie_wait_cmd(struct controller * ctrl)111 static void pcie_wait_cmd(struct controller *ctrl)
112 {
113 	unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
114 	unsigned long duration = msecs_to_jiffies(msecs);
115 	unsigned long cmd_timeout = ctrl->cmd_started + duration;
116 	unsigned long now, timeout;
117 	int rc;
118 
119 	/*
120 	 * If the controller does not generate notifications for command
121 	 * completions, we never need to wait between writes.
122 	 */
123 	if (NO_CMD_CMPL(ctrl))
124 		return;
125 
126 	if (!ctrl->cmd_busy)
127 		return;
128 
129 	/*
130 	 * Even if the command has already timed out, we want to call
131 	 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
132 	 */
133 	now = jiffies;
134 	if (time_before_eq(cmd_timeout, now))
135 		timeout = 1;
136 	else
137 		timeout = cmd_timeout - now;
138 
139 	if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
140 	    ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
141 		rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
142 	else
143 		rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
144 
145 	if (!rc)
146 		ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
147 			  ctrl->slot_ctrl,
148 			  jiffies_to_msecs(jiffies - ctrl->cmd_started));
149 }
150 
151 #define CC_ERRATUM_MASK		(PCI_EXP_SLTCTL_PCC |	\
152 				 PCI_EXP_SLTCTL_PIC |	\
153 				 PCI_EXP_SLTCTL_AIC |	\
154 				 PCI_EXP_SLTCTL_EIC)
155 
pcie_do_write_cmd(struct controller * ctrl,u16 cmd,u16 mask,bool wait)156 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
157 			      u16 mask, bool wait)
158 {
159 	struct pci_dev *pdev = ctrl_dev(ctrl);
160 	u16 slot_ctrl_orig, slot_ctrl;
161 
162 	mutex_lock(&ctrl->ctrl_lock);
163 
164 	/*
165 	 * Always wait for any previous command that might still be in progress
166 	 */
167 	pcie_wait_cmd(ctrl);
168 
169 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
170 	if (PCI_POSSIBLE_ERROR(slot_ctrl)) {
171 		ctrl_info(ctrl, "%s: no response from device\n", __func__);
172 		goto out;
173 	}
174 
175 	slot_ctrl_orig = slot_ctrl;
176 	slot_ctrl &= ~mask;
177 	slot_ctrl |= (cmd & mask);
178 	ctrl->cmd_busy = 1;
179 	smp_mb();
180 	ctrl->slot_ctrl = slot_ctrl;
181 	pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
182 	ctrl->cmd_started = jiffies;
183 
184 	/*
185 	 * Controllers with the Intel CF118 and similar errata advertise
186 	 * Command Completed support, but they only set Command Completed
187 	 * if we change the "Control" bits for power, power indicator,
188 	 * attention indicator, or interlock.  If we only change the
189 	 * "Enable" bits, they never set the Command Completed bit.
190 	 */
191 	if (pdev->broken_cmd_compl &&
192 	    (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
193 		ctrl->cmd_busy = 0;
194 
195 	/*
196 	 * Optionally wait for the hardware to be ready for a new command,
197 	 * indicating completion of the above issued command.
198 	 */
199 	if (wait)
200 		pcie_wait_cmd(ctrl);
201 
202 out:
203 	mutex_unlock(&ctrl->ctrl_lock);
204 }
205 
206 /**
207  * pcie_write_cmd - Issue controller command
208  * @ctrl: controller to which the command is issued
209  * @cmd:  command value written to slot control register
210  * @mask: bitmask of slot control register to be modified
211  */
pcie_write_cmd(struct controller * ctrl,u16 cmd,u16 mask)212 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
213 {
214 	pcie_do_write_cmd(ctrl, cmd, mask, true);
215 }
216 
217 /* Same as above without waiting for the hardware to latch */
pcie_write_cmd_nowait(struct controller * ctrl,u16 cmd,u16 mask)218 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
219 {
220 	pcie_do_write_cmd(ctrl, cmd, mask, false);
221 }
222 
223 /**
224  * pciehp_check_link_active() - Is the link active
225  * @ctrl: PCIe hotplug controller
226  *
227  * Check whether the downstream link is currently active. Note it is
228  * possible that the card is removed immediately after this so the
229  * caller may need to take it into account.
230  *
231  * If the hotplug controller itself is not available anymore returns
232  * %-ENODEV.
233  */
pciehp_check_link_active(struct controller * ctrl)234 int pciehp_check_link_active(struct controller *ctrl)
235 {
236 	struct pci_dev *pdev = ctrl_dev(ctrl);
237 	u16 lnk_status;
238 	int ret;
239 
240 	ret = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
241 	if (ret == PCIBIOS_DEVICE_NOT_FOUND || PCI_POSSIBLE_ERROR(lnk_status))
242 		return -ENODEV;
243 
244 	ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
245 	ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
246 
247 	return ret;
248 }
249 
pci_bus_check_dev(struct pci_bus * bus,int devfn)250 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
251 {
252 	u32 l;
253 	int count = 0;
254 	int delay = 1000, step = 20;
255 	bool found = false;
256 
257 	do {
258 		found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
259 		count++;
260 
261 		if (found)
262 			break;
263 
264 		msleep(step);
265 		delay -= step;
266 	} while (delay > 0);
267 
268 	if (count > 1)
269 		pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
270 			pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
271 			PCI_FUNC(devfn), count, step, l);
272 
273 	return found;
274 }
275 
pcie_wait_for_presence(struct pci_dev * pdev)276 static void pcie_wait_for_presence(struct pci_dev *pdev)
277 {
278 	int timeout = 1250;
279 	u16 slot_status;
280 
281 	do {
282 		pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
283 		if (slot_status & PCI_EXP_SLTSTA_PDS)
284 			return;
285 		msleep(10);
286 		timeout -= 10;
287 	} while (timeout > 0);
288 }
289 
pciehp_check_link_status(struct controller * ctrl)290 int pciehp_check_link_status(struct controller *ctrl)
291 {
292 	struct pci_dev *pdev = ctrl_dev(ctrl);
293 	bool found;
294 	u16 lnk_status;
295 
296 	if (!pcie_wait_for_link(pdev, true)) {
297 		ctrl_info(ctrl, "Slot(%s): No link\n", slot_name(ctrl));
298 		return -1;
299 	}
300 
301 	if (ctrl->inband_presence_disabled)
302 		pcie_wait_for_presence(pdev);
303 
304 	found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
305 					PCI_DEVFN(0, 0));
306 
307 	/* ignore link or presence changes up to this point */
308 	if (found)
309 		atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC),
310 			   &ctrl->pending_events);
311 
312 	pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
313 	ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
314 	if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
315 	    !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
316 		ctrl_info(ctrl, "Slot(%s): Cannot train link: status %#06x\n",
317 			  slot_name(ctrl), lnk_status);
318 		return -1;
319 	}
320 
321 	pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
322 
323 	if (!found) {
324 		ctrl_info(ctrl, "Slot(%s): No device found\n",
325 			  slot_name(ctrl));
326 		return -1;
327 	}
328 
329 	return 0;
330 }
331 
__pciehp_link_set(struct controller * ctrl,bool enable)332 static int __pciehp_link_set(struct controller *ctrl, bool enable)
333 {
334 	struct pci_dev *pdev = ctrl_dev(ctrl);
335 	u16 lnk_ctrl;
336 
337 	pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
338 
339 	if (enable)
340 		lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
341 	else
342 		lnk_ctrl |= PCI_EXP_LNKCTL_LD;
343 
344 	pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
345 	ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
346 	return 0;
347 }
348 
pciehp_link_enable(struct controller * ctrl)349 static int pciehp_link_enable(struct controller *ctrl)
350 {
351 	return __pciehp_link_set(ctrl, true);
352 }
353 
pciehp_get_raw_indicator_status(struct hotplug_slot * hotplug_slot,u8 * status)354 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
355 				    u8 *status)
356 {
357 	struct controller *ctrl = to_ctrl(hotplug_slot);
358 	struct pci_dev *pdev = ctrl_dev(ctrl);
359 	u16 slot_ctrl;
360 
361 	pci_config_pm_runtime_get(pdev);
362 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
363 	pci_config_pm_runtime_put(pdev);
364 	*status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
365 	return 0;
366 }
367 
pciehp_get_attention_status(struct hotplug_slot * hotplug_slot,u8 * status)368 int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status)
369 {
370 	struct controller *ctrl = to_ctrl(hotplug_slot);
371 	struct pci_dev *pdev = ctrl_dev(ctrl);
372 	u16 slot_ctrl;
373 
374 	pci_config_pm_runtime_get(pdev);
375 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
376 	pci_config_pm_runtime_put(pdev);
377 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
378 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
379 
380 	switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
381 	case PCI_EXP_SLTCTL_ATTN_IND_ON:
382 		*status = 1;	/* On */
383 		break;
384 	case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
385 		*status = 2;	/* Blink */
386 		break;
387 	case PCI_EXP_SLTCTL_ATTN_IND_OFF:
388 		*status = 0;	/* Off */
389 		break;
390 	default:
391 		*status = 0xFF;
392 		break;
393 	}
394 
395 	return 0;
396 }
397 
pciehp_get_power_status(struct controller * ctrl,u8 * status)398 void pciehp_get_power_status(struct controller *ctrl, u8 *status)
399 {
400 	struct pci_dev *pdev = ctrl_dev(ctrl);
401 	u16 slot_ctrl;
402 
403 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
404 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
405 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
406 
407 	switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
408 	case PCI_EXP_SLTCTL_PWR_ON:
409 		*status = 1;	/* On */
410 		break;
411 	case PCI_EXP_SLTCTL_PWR_OFF:
412 		*status = 0;	/* Off */
413 		break;
414 	default:
415 		*status = 0xFF;
416 		break;
417 	}
418 }
419 
pciehp_get_latch_status(struct controller * ctrl,u8 * status)420 void pciehp_get_latch_status(struct controller *ctrl, u8 *status)
421 {
422 	struct pci_dev *pdev = ctrl_dev(ctrl);
423 	u16 slot_status;
424 
425 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
426 	*status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
427 }
428 
429 /**
430  * pciehp_card_present() - Is the card present
431  * @ctrl: PCIe hotplug controller
432  *
433  * Function checks whether the card is currently present in the slot and
434  * in that case returns true. Note it is possible that the card is
435  * removed immediately after the check so the caller may need to take
436  * this into account.
437  *
438  * It the hotplug controller itself is not available anymore returns
439  * %-ENODEV.
440  */
pciehp_card_present(struct controller * ctrl)441 int pciehp_card_present(struct controller *ctrl)
442 {
443 	struct pci_dev *pdev = ctrl_dev(ctrl);
444 	u16 slot_status;
445 	int ret;
446 
447 	ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
448 	if (ret == PCIBIOS_DEVICE_NOT_FOUND || PCI_POSSIBLE_ERROR(slot_status))
449 		return -ENODEV;
450 
451 	return !!(slot_status & PCI_EXP_SLTSTA_PDS);
452 }
453 
454 /**
455  * pciehp_card_present_or_link_active() - whether given slot is occupied
456  * @ctrl: PCIe hotplug controller
457  *
458  * Unlike pciehp_card_present(), which determines presence solely from the
459  * Presence Detect State bit, this helper also returns true if the Link Active
460  * bit is set.  This is a concession to broken hotplug ports which hardwire
461  * Presence Detect State to zero, such as Wilocity's [1ae9:0200].
462  *
463  * Returns: %1 if the slot is occupied and %0 if it is not. If the hotplug
464  *	    port is not present anymore returns %-ENODEV.
465  */
pciehp_card_present_or_link_active(struct controller * ctrl)466 int pciehp_card_present_or_link_active(struct controller *ctrl)
467 {
468 	int ret;
469 
470 	ret = pciehp_card_present(ctrl);
471 	if (ret)
472 		return ret;
473 
474 	return pciehp_check_link_active(ctrl);
475 }
476 
pciehp_query_power_fault(struct controller * ctrl)477 int pciehp_query_power_fault(struct controller *ctrl)
478 {
479 	struct pci_dev *pdev = ctrl_dev(ctrl);
480 	u16 slot_status;
481 
482 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
483 	return !!(slot_status & PCI_EXP_SLTSTA_PFD);
484 }
485 
pciehp_set_raw_indicator_status(struct hotplug_slot * hotplug_slot,u8 status)486 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
487 				    u8 status)
488 {
489 	struct controller *ctrl = to_ctrl(hotplug_slot);
490 	struct pci_dev *pdev = ctrl_dev(ctrl);
491 
492 	pci_config_pm_runtime_get(pdev);
493 	pcie_write_cmd_nowait(ctrl, status << 6,
494 			      PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
495 	pci_config_pm_runtime_put(pdev);
496 	return 0;
497 }
498 
499 /**
500  * pciehp_set_indicators() - set attention indicator, power indicator, or both
501  * @ctrl: PCIe hotplug controller
502  * @pwr: one of:
503  *	PCI_EXP_SLTCTL_PWR_IND_ON
504  *	PCI_EXP_SLTCTL_PWR_IND_BLINK
505  *	PCI_EXP_SLTCTL_PWR_IND_OFF
506  * @attn: one of:
507  *	PCI_EXP_SLTCTL_ATTN_IND_ON
508  *	PCI_EXP_SLTCTL_ATTN_IND_BLINK
509  *	PCI_EXP_SLTCTL_ATTN_IND_OFF
510  *
511  * Either @pwr or @attn can also be INDICATOR_NOOP to leave that indicator
512  * unchanged.
513  */
pciehp_set_indicators(struct controller * ctrl,int pwr,int attn)514 void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn)
515 {
516 	u16 cmd = 0, mask = 0;
517 
518 	if (PWR_LED(ctrl) && pwr != INDICATOR_NOOP) {
519 		cmd |= (pwr & PCI_EXP_SLTCTL_PIC);
520 		mask |= PCI_EXP_SLTCTL_PIC;
521 	}
522 
523 	if (ATTN_LED(ctrl) && attn != INDICATOR_NOOP) {
524 		cmd |= (attn & PCI_EXP_SLTCTL_AIC);
525 		mask |= PCI_EXP_SLTCTL_AIC;
526 	}
527 
528 	if (cmd) {
529 		pcie_write_cmd_nowait(ctrl, cmd, mask);
530 		ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
531 			 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
532 	}
533 }
534 
pciehp_power_on_slot(struct controller * ctrl)535 int pciehp_power_on_slot(struct controller *ctrl)
536 {
537 	struct pci_dev *pdev = ctrl_dev(ctrl);
538 	u16 slot_status;
539 	int retval;
540 
541 	/* Clear power-fault bit from previous power failures */
542 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
543 	if (slot_status & PCI_EXP_SLTSTA_PFD)
544 		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
545 					   PCI_EXP_SLTSTA_PFD);
546 	ctrl->power_fault_detected = 0;
547 
548 	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
549 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
550 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
551 		 PCI_EXP_SLTCTL_PWR_ON);
552 
553 	retval = pciehp_link_enable(ctrl);
554 	if (retval)
555 		ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
556 
557 	return retval;
558 }
559 
pciehp_power_off_slot(struct controller * ctrl)560 void pciehp_power_off_slot(struct controller *ctrl)
561 {
562 	pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
563 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
564 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
565 		 PCI_EXP_SLTCTL_PWR_OFF);
566 }
567 
pciehp_ignore_dpc_link_change(struct controller * ctrl,struct pci_dev * pdev,int irq)568 static void pciehp_ignore_dpc_link_change(struct controller *ctrl,
569 					  struct pci_dev *pdev, int irq)
570 {
571 	/*
572 	 * Ignore link changes which occurred while waiting for DPC recovery.
573 	 * Could be several if DPC triggered multiple times consecutively.
574 	 */
575 	synchronize_hardirq(irq);
576 	atomic_and(~PCI_EXP_SLTSTA_DLLSC, &ctrl->pending_events);
577 	if (pciehp_poll_mode)
578 		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
579 					   PCI_EXP_SLTSTA_DLLSC);
580 	ctrl_info(ctrl, "Slot(%s): Link Down/Up ignored (recovered by DPC)\n",
581 		  slot_name(ctrl));
582 
583 	/*
584 	 * If the link is unexpectedly down after successful recovery,
585 	 * the corresponding link change may have been ignored above.
586 	 * Synthesize it to ensure that it is acted on.
587 	 */
588 	down_read_nested(&ctrl->reset_lock, ctrl->depth);
589 	if (!pciehp_check_link_active(ctrl))
590 		pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
591 	up_read(&ctrl->reset_lock);
592 }
593 
pciehp_isr(int irq,void * dev_id)594 static irqreturn_t pciehp_isr(int irq, void *dev_id)
595 {
596 	struct controller *ctrl = (struct controller *)dev_id;
597 	struct pci_dev *pdev = ctrl_dev(ctrl);
598 	struct device *parent = pdev->dev.parent;
599 	u16 status, events = 0;
600 
601 	/*
602 	 * Interrupts only occur in D3hot or shallower and only if enabled
603 	 * in the Slot Control register (PCIe r4.0, sec 6.7.3.4).
604 	 */
605 	if (pdev->current_state == PCI_D3cold ||
606 	    (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
607 		return IRQ_NONE;
608 
609 	/*
610 	 * Keep the port accessible by holding a runtime PM ref on its parent.
611 	 * Defer resume of the parent to the IRQ thread if it's suspended.
612 	 * Mask the interrupt until then.
613 	 */
614 	if (parent) {
615 		pm_runtime_get_noresume(parent);
616 		if (!pm_runtime_active(parent)) {
617 			pm_runtime_put(parent);
618 			disable_irq_nosync(irq);
619 			atomic_or(RERUN_ISR, &ctrl->pending_events);
620 			return IRQ_WAKE_THREAD;
621 		}
622 	}
623 
624 read_status:
625 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
626 	if (PCI_POSSIBLE_ERROR(status)) {
627 		ctrl_info(ctrl, "%s: no response from device\n", __func__);
628 		if (parent)
629 			pm_runtime_put(parent);
630 		return IRQ_NONE;
631 	}
632 
633 	/*
634 	 * Slot Status contains plain status bits as well as event
635 	 * notification bits; right now we only want the event bits.
636 	 */
637 	status &= PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
638 		  PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
639 		  PCI_EXP_SLTSTA_DLLSC;
640 
641 	/*
642 	 * If we've already reported a power fault, don't report it again
643 	 * until we've done something to handle it.
644 	 */
645 	if (ctrl->power_fault_detected)
646 		status &= ~PCI_EXP_SLTSTA_PFD;
647 	else if (status & PCI_EXP_SLTSTA_PFD)
648 		ctrl->power_fault_detected = true;
649 
650 	events |= status;
651 	if (!events) {
652 		if (parent)
653 			pm_runtime_put(parent);
654 		return IRQ_NONE;
655 	}
656 
657 	if (status) {
658 		pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, status);
659 
660 		/*
661 		 * In MSI mode, all event bits must be zero before the port
662 		 * will send a new interrupt (PCIe Base Spec r5.0 sec 6.7.3.4).
663 		 * So re-read the Slot Status register in case a bit was set
664 		 * between read and write.
665 		 */
666 		if (pci_dev_msi_enabled(pdev) && !pciehp_poll_mode)
667 			goto read_status;
668 	}
669 
670 	ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
671 	if (parent)
672 		pm_runtime_put(parent);
673 
674 	/*
675 	 * Command Completed notifications are not deferred to the
676 	 * IRQ thread because it may be waiting for their arrival.
677 	 */
678 	if (events & PCI_EXP_SLTSTA_CC) {
679 		ctrl->cmd_busy = 0;
680 		smp_mb();
681 		wake_up(&ctrl->queue);
682 
683 		if (events == PCI_EXP_SLTSTA_CC)
684 			return IRQ_HANDLED;
685 
686 		events &= ~PCI_EXP_SLTSTA_CC;
687 	}
688 
689 	if (pdev->ignore_hotplug) {
690 		ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
691 		return IRQ_HANDLED;
692 	}
693 
694 	/* Save pending events for consumption by IRQ thread. */
695 	atomic_or(events, &ctrl->pending_events);
696 	return IRQ_WAKE_THREAD;
697 }
698 
pciehp_ist(int irq,void * dev_id)699 static irqreturn_t pciehp_ist(int irq, void *dev_id)
700 {
701 	struct controller *ctrl = (struct controller *)dev_id;
702 	struct pci_dev *pdev = ctrl_dev(ctrl);
703 	irqreturn_t ret;
704 	u32 events;
705 
706 	ctrl->ist_running = true;
707 	pci_config_pm_runtime_get(pdev);
708 
709 	/* rerun pciehp_isr() if the port was inaccessible on interrupt */
710 	if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
711 		ret = pciehp_isr(irq, dev_id);
712 		enable_irq(irq);
713 		if (ret != IRQ_WAKE_THREAD)
714 			goto out;
715 	}
716 
717 	synchronize_hardirq(irq);
718 	events = atomic_xchg(&ctrl->pending_events, 0);
719 	if (!events) {
720 		ret = IRQ_NONE;
721 		goto out;
722 	}
723 
724 	/* Check Attention Button Pressed */
725 	if (events & PCI_EXP_SLTSTA_ABP) {
726 		ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
727 			  slot_name(ctrl));
728 		pciehp_handle_button_press(ctrl);
729 	}
730 
731 	/* Check Power Fault Detected */
732 	if (events & PCI_EXP_SLTSTA_PFD) {
733 		ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl));
734 		pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
735 				      PCI_EXP_SLTCTL_ATTN_IND_ON);
736 	}
737 
738 	/*
739 	 * Ignore Link Down/Up events caused by Downstream Port Containment
740 	 * if recovery from the error succeeded.
741 	 */
742 	if ((events & PCI_EXP_SLTSTA_DLLSC) && pci_dpc_recovered(pdev) &&
743 	    ctrl->state == ON_STATE) {
744 		events &= ~PCI_EXP_SLTSTA_DLLSC;
745 		pciehp_ignore_dpc_link_change(ctrl, pdev, irq);
746 	}
747 
748 	/*
749 	 * Disable requests have higher priority than Presence Detect Changed
750 	 * or Data Link Layer State Changed events.
751 	 */
752 	down_read_nested(&ctrl->reset_lock, ctrl->depth);
753 	if (events & DISABLE_SLOT)
754 		pciehp_handle_disable_request(ctrl);
755 	else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
756 		pciehp_handle_presence_or_link_change(ctrl, events);
757 	up_read(&ctrl->reset_lock);
758 
759 	ret = IRQ_HANDLED;
760 out:
761 	pci_config_pm_runtime_put(pdev);
762 	ctrl->ist_running = false;
763 	wake_up(&ctrl->requester);
764 	return ret;
765 }
766 
pciehp_poll(void * data)767 static int pciehp_poll(void *data)
768 {
769 	struct controller *ctrl = data;
770 
771 	schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */
772 
773 	while (!kthread_should_stop()) {
774 		/* poll for interrupt events or user requests */
775 		while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD ||
776 		       atomic_read(&ctrl->pending_events))
777 			pciehp_ist(IRQ_NOTCONNECTED, ctrl);
778 
779 		if (pciehp_poll_time <= 0 || pciehp_poll_time > 60)
780 			pciehp_poll_time = 2; /* clamp to sane value */
781 
782 		schedule_timeout_idle(pciehp_poll_time * HZ);
783 	}
784 
785 	return 0;
786 }
787 
pcie_enable_notification(struct controller * ctrl)788 static void pcie_enable_notification(struct controller *ctrl)
789 {
790 	u16 cmd, mask;
791 
792 	/*
793 	 * TBD: Power fault detected software notification support.
794 	 *
795 	 * Power fault detected software notification is not enabled
796 	 * now, because it caused power fault detected interrupt storm
797 	 * on some machines. On those machines, power fault detected
798 	 * bit in the slot status register was set again immediately
799 	 * when it is cleared in the interrupt service routine, and
800 	 * next power fault detected interrupt was notified again.
801 	 */
802 
803 	/*
804 	 * Always enable link events: thus link-up and link-down shall
805 	 * always be treated as hotplug and unplug respectively. Enable
806 	 * presence detect only if Attention Button is not present.
807 	 */
808 	cmd = PCI_EXP_SLTCTL_DLLSCE;
809 	if (ATTN_BUTTN(ctrl))
810 		cmd |= PCI_EXP_SLTCTL_ABPE;
811 	else
812 		cmd |= PCI_EXP_SLTCTL_PDCE;
813 	if (!pciehp_poll_mode)
814 		cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
815 
816 	mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
817 		PCI_EXP_SLTCTL_PFDE |
818 		PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
819 		PCI_EXP_SLTCTL_DLLSCE);
820 
821 	pcie_write_cmd_nowait(ctrl, cmd, mask);
822 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
823 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
824 }
825 
pcie_disable_notification(struct controller * ctrl)826 static void pcie_disable_notification(struct controller *ctrl)
827 {
828 	u16 mask;
829 
830 	mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
831 		PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
832 		PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
833 		PCI_EXP_SLTCTL_DLLSCE);
834 	pcie_write_cmd(ctrl, 0, mask);
835 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
836 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
837 }
838 
pcie_clear_hotplug_events(struct controller * ctrl)839 void pcie_clear_hotplug_events(struct controller *ctrl)
840 {
841 	pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA,
842 				   PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
843 }
844 
pcie_enable_interrupt(struct controller * ctrl)845 void pcie_enable_interrupt(struct controller *ctrl)
846 {
847 	u16 mask;
848 
849 	mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
850 	pcie_write_cmd(ctrl, mask, mask);
851 }
852 
pcie_disable_interrupt(struct controller * ctrl)853 void pcie_disable_interrupt(struct controller *ctrl)
854 {
855 	u16 mask;
856 
857 	/*
858 	 * Mask hot-plug interrupt to prevent it triggering immediately
859 	 * when the link goes inactive (we still get PME when any of the
860 	 * enabled events is detected). Same goes with Link Layer State
861 	 * changed event which generates PME immediately when the link goes
862 	 * inactive so mask it as well.
863 	 */
864 	mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
865 	pcie_write_cmd(ctrl, 0, mask);
866 }
867 
868 /**
869  * pciehp_slot_reset() - ignore link event caused by error-induced hot reset
870  * @dev: PCI Express port service device
871  *
872  * Called from pcie_portdrv_slot_reset() after AER or DPC initiated a reset
873  * further up in the hierarchy to recover from an error.  The reset was
874  * propagated down to this hotplug port.  Ignore the resulting link flap.
875  * If the link failed to retrain successfully, synthesize the ignored event.
876  * Surprise removal during reset is detected through Presence Detect Changed.
877  */
pciehp_slot_reset(struct pcie_device * dev)878 int pciehp_slot_reset(struct pcie_device *dev)
879 {
880 	struct controller *ctrl = get_service_data(dev);
881 
882 	if (ctrl->state != ON_STATE)
883 		return 0;
884 
885 	pcie_capability_write_word(dev->port, PCI_EXP_SLTSTA,
886 				   PCI_EXP_SLTSTA_DLLSC);
887 
888 	if (!pciehp_check_link_active(ctrl))
889 		pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
890 
891 	return 0;
892 }
893 
894 /*
895  * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
896  * bus reset of the bridge, but at the same time we want to ensure that it is
897  * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
898  * disable link state notification and presence detection change notification
899  * momentarily, if we see that they could interfere. Also, clear any spurious
900  * events after.
901  */
pciehp_reset_slot(struct hotplug_slot * hotplug_slot,bool probe)902 int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe)
903 {
904 	struct controller *ctrl = to_ctrl(hotplug_slot);
905 	struct pci_dev *pdev = ctrl_dev(ctrl);
906 	u16 stat_mask = 0, ctrl_mask = 0;
907 	int rc;
908 
909 	if (probe)
910 		return 0;
911 
912 	down_write_nested(&ctrl->reset_lock, ctrl->depth);
913 
914 	if (!ATTN_BUTTN(ctrl)) {
915 		ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
916 		stat_mask |= PCI_EXP_SLTSTA_PDC;
917 	}
918 	ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
919 	stat_mask |= PCI_EXP_SLTSTA_DLLSC;
920 
921 	pcie_write_cmd(ctrl, 0, ctrl_mask);
922 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
923 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
924 
925 	rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
926 
927 	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
928 	pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
929 	ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
930 		 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
931 
932 	up_write(&ctrl->reset_lock);
933 	return rc;
934 }
935 
pcie_init_notification(struct controller * ctrl)936 int pcie_init_notification(struct controller *ctrl)
937 {
938 	if (pciehp_request_irq(ctrl))
939 		return -1;
940 	pcie_enable_notification(ctrl);
941 	ctrl->notification_enabled = 1;
942 	return 0;
943 }
944 
pcie_shutdown_notification(struct controller * ctrl)945 void pcie_shutdown_notification(struct controller *ctrl)
946 {
947 	if (ctrl->notification_enabled) {
948 		pcie_disable_notification(ctrl);
949 		pciehp_free_irq(ctrl);
950 		ctrl->notification_enabled = 0;
951 	}
952 }
953 
dbg_ctrl(struct controller * ctrl)954 static inline void dbg_ctrl(struct controller *ctrl)
955 {
956 	struct pci_dev *pdev = ctrl->pcie->port;
957 	u16 reg16;
958 
959 	ctrl_dbg(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
960 	pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
961 	ctrl_dbg(ctrl, "Slot Status            : 0x%04x\n", reg16);
962 	pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
963 	ctrl_dbg(ctrl, "Slot Control           : 0x%04x\n", reg16);
964 }
965 
966 #define FLAG(x, y)	(((x) & (y)) ? '+' : '-')
967 
pcie_hotplug_depth(struct pci_dev * dev)968 static inline int pcie_hotplug_depth(struct pci_dev *dev)
969 {
970 	struct pci_bus *bus = dev->bus;
971 	int depth = 0;
972 
973 	while (bus->parent) {
974 		bus = bus->parent;
975 		if (bus->self && bus->self->is_hotplug_bridge)
976 			depth++;
977 	}
978 
979 	return depth;
980 }
981 
pcie_init(struct pcie_device * dev)982 struct controller *pcie_init(struct pcie_device *dev)
983 {
984 	struct controller *ctrl;
985 	u32 slot_cap, slot_cap2, link_cap;
986 	u8 poweron;
987 	struct pci_dev *pdev = dev->port;
988 	struct pci_bus *subordinate = pdev->subordinate;
989 
990 	ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
991 	if (!ctrl)
992 		return NULL;
993 
994 	ctrl->pcie = dev;
995 	ctrl->depth = pcie_hotplug_depth(dev->port);
996 	pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
997 
998 	if (pdev->hotplug_user_indicators)
999 		slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
1000 
1001 	/*
1002 	 * We assume no Thunderbolt controllers support Command Complete events,
1003 	 * but some controllers falsely claim they do.
1004 	 */
1005 	if (pdev->is_thunderbolt)
1006 		slot_cap |= PCI_EXP_SLTCAP_NCCS;
1007 
1008 	ctrl->slot_cap = slot_cap;
1009 	mutex_init(&ctrl->ctrl_lock);
1010 	mutex_init(&ctrl->state_lock);
1011 	init_rwsem(&ctrl->reset_lock);
1012 	init_waitqueue_head(&ctrl->requester);
1013 	init_waitqueue_head(&ctrl->queue);
1014 	INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work);
1015 	dbg_ctrl(ctrl);
1016 
1017 	down_read(&pci_bus_sem);
1018 	ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
1019 	up_read(&pci_bus_sem);
1020 
1021 	pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP2, &slot_cap2);
1022 	if (slot_cap2 & PCI_EXP_SLTCAP2_IBPD) {
1023 		pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_IBPD_DISABLE,
1024 				      PCI_EXP_SLTCTL_IBPD_DISABLE);
1025 		ctrl->inband_presence_disabled = 1;
1026 	}
1027 
1028 	if (dmi_first_match(inband_presence_disabled_dmi_table))
1029 		ctrl->inband_presence_disabled = 1;
1030 
1031 	/* Check if Data Link Layer Link Active Reporting is implemented */
1032 	pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
1033 
1034 	/* Clear all remaining event bits in Slot Status register. */
1035 	pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
1036 		PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
1037 		PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
1038 		PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
1039 
1040 	ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c IbPresDis%c LLActRep%c%s\n",
1041 		(slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
1042 		FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
1043 		FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
1044 		FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
1045 		FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
1046 		FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
1047 		FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
1048 		FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
1049 		FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
1050 		FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
1051 		FLAG(slot_cap2, PCI_EXP_SLTCAP2_IBPD),
1052 		FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC),
1053 		pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
1054 
1055 	/*
1056 	 * If empty slot's power status is on, turn power off.  The IRQ isn't
1057 	 * requested yet, so avoid triggering a notification with this command.
1058 	 */
1059 	if (POWER_CTRL(ctrl)) {
1060 		pciehp_get_power_status(ctrl, &poweron);
1061 		if (!pciehp_card_present_or_link_active(ctrl) && poweron) {
1062 			pcie_disable_notification(ctrl);
1063 			pciehp_power_off_slot(ctrl);
1064 		}
1065 	}
1066 
1067 	return ctrl;
1068 }
1069 
pciehp_release_ctrl(struct controller * ctrl)1070 void pciehp_release_ctrl(struct controller *ctrl)
1071 {
1072 	cancel_delayed_work_sync(&ctrl->button_work);
1073 	kfree(ctrl);
1074 }
1075 
quirk_cmd_compl(struct pci_dev * pdev)1076 static void quirk_cmd_compl(struct pci_dev *pdev)
1077 {
1078 	u32 slot_cap;
1079 
1080 	if (pci_is_pcie(pdev)) {
1081 		pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
1082 		if (slot_cap & PCI_EXP_SLTCAP_HPC &&
1083 		    !(slot_cap & PCI_EXP_SLTCAP_NCCS))
1084 			pdev->broken_cmd_compl = 1;
1085 	}
1086 }
1087 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1088 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1089 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0110,
1090 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1091 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
1092 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1093 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
1094 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1095 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401,
1096 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1097