1 /*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39 #include <linux/slab.h>
40
41 #include "../pci.h"
42 #include "pciehp.h"
43
pciehp_readw(struct controller * ctrl,int reg,u16 * value)44 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
45 {
46 struct pci_dev *dev = ctrl->pcie->port;
47 return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
48 }
49
pciehp_readl(struct controller * ctrl,int reg,u32 * value)50 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
51 {
52 struct pci_dev *dev = ctrl->pcie->port;
53 return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
54 }
55
pciehp_writew(struct controller * ctrl,int reg,u16 value)56 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
57 {
58 struct pci_dev *dev = ctrl->pcie->port;
59 return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
60 }
61
pciehp_writel(struct controller * ctrl,int reg,u32 value)62 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
63 {
64 struct pci_dev *dev = ctrl->pcie->port;
65 return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
66 }
67
68 /* Power Control Command */
69 #define POWER_ON 0
70 #define POWER_OFF PCI_EXP_SLTCTL_PCC
71
72 static irqreturn_t pcie_isr(int irq, void *dev_id);
73 static void start_int_poll_timer(struct controller *ctrl, int sec);
74
75 /* This is the interrupt polling timeout function. */
int_poll_timeout(unsigned long data)76 static void int_poll_timeout(unsigned long data)
77 {
78 struct controller *ctrl = (struct controller *)data;
79
80 /* Poll for interrupt events. regs == NULL => polling */
81 pcie_isr(0, ctrl);
82
83 init_timer(&ctrl->poll_timer);
84 if (!pciehp_poll_time)
85 pciehp_poll_time = 2; /* default polling interval is 2 sec */
86
87 start_int_poll_timer(ctrl, pciehp_poll_time);
88 }
89
90 /* This function starts the interrupt polling timer. */
start_int_poll_timer(struct controller * ctrl,int sec)91 static void start_int_poll_timer(struct controller *ctrl, int sec)
92 {
93 /* Clamp to sane value */
94 if ((sec <= 0) || (sec > 60))
95 sec = 2;
96
97 ctrl->poll_timer.function = &int_poll_timeout;
98 ctrl->poll_timer.data = (unsigned long)ctrl;
99 ctrl->poll_timer.expires = jiffies + sec * HZ;
100 add_timer(&ctrl->poll_timer);
101 }
102
pciehp_request_irq(struct controller * ctrl)103 static inline int pciehp_request_irq(struct controller *ctrl)
104 {
105 int retval, irq = ctrl->pcie->irq;
106
107 /* Install interrupt polling timer. Start with 10 sec delay */
108 if (pciehp_poll_mode) {
109 init_timer(&ctrl->poll_timer);
110 start_int_poll_timer(ctrl, 10);
111 return 0;
112 }
113
114 /* Installs the interrupt handler */
115 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
116 if (retval)
117 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
118 irq);
119 return retval;
120 }
121
pciehp_free_irq(struct controller * ctrl)122 static inline void pciehp_free_irq(struct controller *ctrl)
123 {
124 if (pciehp_poll_mode)
125 del_timer_sync(&ctrl->poll_timer);
126 else
127 free_irq(ctrl->pcie->irq, ctrl);
128 }
129
pcie_poll_cmd(struct controller * ctrl)130 static int pcie_poll_cmd(struct controller *ctrl)
131 {
132 u16 slot_status;
133 int err, timeout = 1000;
134
135 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
136 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
137 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
138 return 1;
139 }
140 while (timeout > 0) {
141 msleep(10);
142 timeout -= 10;
143 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
144 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
145 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
146 return 1;
147 }
148 }
149 return 0; /* timeout */
150 }
151
pcie_wait_cmd(struct controller * ctrl,int poll)152 static void pcie_wait_cmd(struct controller *ctrl, int poll)
153 {
154 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
155 unsigned long timeout = msecs_to_jiffies(msecs);
156 int rc;
157
158 if (poll)
159 rc = pcie_poll_cmd(ctrl);
160 else
161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
162 if (!rc)
163 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
164 }
165
166 /**
167 * pcie_write_cmd - Issue controller command
168 * @ctrl: controller to which the command is issued
169 * @cmd: command value written to slot control register
170 * @mask: bitmask of slot control register to be modified
171 */
pcie_write_cmd(struct controller * ctrl,u16 cmd,u16 mask)172 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
173 {
174 int retval = 0;
175 u16 slot_status;
176 u16 slot_ctrl;
177
178 mutex_lock(&ctrl->ctrl_lock);
179
180 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
181 if (retval) {
182 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
183 __func__);
184 goto out;
185 }
186
187 if (slot_status & PCI_EXP_SLTSTA_CC) {
188 if (!ctrl->no_cmd_complete) {
189 /*
190 * After 1 sec and CMD_COMPLETED still not set, just
191 * proceed forward to issue the next command according
192 * to spec. Just print out the error message.
193 */
194 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
195 } else if (!NO_CMD_CMPL(ctrl)) {
196 /*
197 * This controller semms to notify of command completed
198 * event even though it supports none of power
199 * controller, attention led, power led and EMI.
200 */
201 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
202 "wait for command completed event.\n");
203 ctrl->no_cmd_complete = 0;
204 } else {
205 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
206 "the controller is broken.\n");
207 }
208 }
209
210 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
211 if (retval) {
212 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
213 goto out;
214 }
215
216 slot_ctrl &= ~mask;
217 slot_ctrl |= (cmd & mask);
218 ctrl->cmd_busy = 1;
219 smp_mb();
220 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
221 if (retval)
222 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
223
224 /*
225 * Wait for command completion.
226 */
227 if (!retval && !ctrl->no_cmd_complete) {
228 int poll = 0;
229 /*
230 * if hotplug interrupt is not enabled or command
231 * completed interrupt is not enabled, we need to poll
232 * command completed event.
233 */
234 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
235 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
236 poll = 1;
237 pcie_wait_cmd(ctrl, poll);
238 }
239 out:
240 mutex_unlock(&ctrl->ctrl_lock);
241 return retval;
242 }
243
check_link_active(struct controller * ctrl)244 static bool check_link_active(struct controller *ctrl)
245 {
246 bool ret = false;
247 u16 lnk_status;
248
249 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status))
250 return ret;
251
252 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
253
254 if (ret)
255 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
256
257 return ret;
258 }
259
__pcie_wait_link_active(struct controller * ctrl,bool active)260 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
261 {
262 int timeout = 1000;
263
264 if (check_link_active(ctrl) == active)
265 return;
266 while (timeout > 0) {
267 msleep(10);
268 timeout -= 10;
269 if (check_link_active(ctrl) == active)
270 return;
271 }
272 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
273 active ? "set" : "cleared");
274 }
275
pcie_wait_link_active(struct controller * ctrl)276 static void pcie_wait_link_active(struct controller *ctrl)
277 {
278 __pcie_wait_link_active(ctrl, true);
279 }
280
pcie_wait_link_not_active(struct controller * ctrl)281 static void pcie_wait_link_not_active(struct controller *ctrl)
282 {
283 __pcie_wait_link_active(ctrl, false);
284 }
285
pci_bus_check_dev(struct pci_bus * bus,int devfn)286 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
287 {
288 u32 l;
289 int count = 0;
290 int delay = 1000, step = 20;
291 bool found = false;
292
293 do {
294 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
295 count++;
296
297 if (found)
298 break;
299
300 msleep(step);
301 delay -= step;
302 } while (delay > 0);
303
304 if (count > 1 && pciehp_debug)
305 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
306 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
307 PCI_FUNC(devfn), count, step, l);
308
309 return found;
310 }
311
pciehp_check_link_status(struct controller * ctrl)312 int pciehp_check_link_status(struct controller *ctrl)
313 {
314 u16 lnk_status;
315 int retval = 0;
316 bool found = false;
317
318 /*
319 * Data Link Layer Link Active Reporting must be capable for
320 * hot-plug capable downstream port. But old controller might
321 * not implement it. In this case, we wait for 1000 ms.
322 */
323 if (ctrl->link_active_reporting)
324 pcie_wait_link_active(ctrl);
325 else
326 msleep(1000);
327
328 /* wait 100ms before read pci conf, and try in 1s */
329 msleep(100);
330 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
331 PCI_DEVFN(0, 0));
332
333 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
334 if (retval) {
335 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
336 return retval;
337 }
338
339 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
340 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
341 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
342 ctrl_err(ctrl, "Link Training Error occurs \n");
343 retval = -1;
344 return retval;
345 }
346
347 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
348
349 if (!found && !retval)
350 retval = -1;
351
352 return retval;
353 }
354
__pciehp_link_set(struct controller * ctrl,bool enable)355 static int __pciehp_link_set(struct controller *ctrl, bool enable)
356 {
357 u16 lnk_ctrl;
358 int retval = 0;
359
360 retval = pciehp_readw(ctrl, PCI_EXP_LNKCTL, &lnk_ctrl);
361 if (retval) {
362 ctrl_err(ctrl, "Cannot read LNKCTRL register\n");
363 return retval;
364 }
365
366 if (enable)
367 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
368 else
369 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
370
371 retval = pciehp_writew(ctrl, PCI_EXP_LNKCTL, lnk_ctrl);
372 if (retval) {
373 ctrl_err(ctrl, "Cannot write LNKCTRL register\n");
374 return retval;
375 }
376 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
377
378 return retval;
379 }
380
pciehp_link_enable(struct controller * ctrl)381 static int pciehp_link_enable(struct controller *ctrl)
382 {
383 return __pciehp_link_set(ctrl, true);
384 }
385
pciehp_link_disable(struct controller * ctrl)386 static int pciehp_link_disable(struct controller *ctrl)
387 {
388 return __pciehp_link_set(ctrl, false);
389 }
390
pciehp_get_attention_status(struct slot * slot,u8 * status)391 int pciehp_get_attention_status(struct slot *slot, u8 *status)
392 {
393 struct controller *ctrl = slot->ctrl;
394 u16 slot_ctrl;
395 u8 atten_led_state;
396 int retval = 0;
397
398 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
399 if (retval) {
400 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
401 return retval;
402 }
403
404 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
405 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
406
407 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
408
409 switch (atten_led_state) {
410 case 0:
411 *status = 0xFF; /* Reserved */
412 break;
413 case 1:
414 *status = 1; /* On */
415 break;
416 case 2:
417 *status = 2; /* Blink */
418 break;
419 case 3:
420 *status = 0; /* Off */
421 break;
422 default:
423 *status = 0xFF;
424 break;
425 }
426
427 return 0;
428 }
429
pciehp_get_power_status(struct slot * slot,u8 * status)430 int pciehp_get_power_status(struct slot *slot, u8 *status)
431 {
432 struct controller *ctrl = slot->ctrl;
433 u16 slot_ctrl;
434 u8 pwr_state;
435 int retval = 0;
436
437 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
438 if (retval) {
439 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
440 return retval;
441 }
442 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
443 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
444
445 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
446
447 switch (pwr_state) {
448 case 0:
449 *status = 1;
450 break;
451 case 1:
452 *status = 0;
453 break;
454 default:
455 *status = 0xFF;
456 break;
457 }
458
459 return retval;
460 }
461
pciehp_get_latch_status(struct slot * slot,u8 * status)462 int pciehp_get_latch_status(struct slot *slot, u8 *status)
463 {
464 struct controller *ctrl = slot->ctrl;
465 u16 slot_status;
466 int retval;
467
468 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
469 if (retval) {
470 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
471 __func__);
472 return retval;
473 }
474 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
475 return 0;
476 }
477
pciehp_get_adapter_status(struct slot * slot,u8 * status)478 int pciehp_get_adapter_status(struct slot *slot, u8 *status)
479 {
480 struct controller *ctrl = slot->ctrl;
481 u16 slot_status;
482 int retval;
483
484 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
485 if (retval) {
486 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
487 __func__);
488 return retval;
489 }
490 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
491 return 0;
492 }
493
pciehp_query_power_fault(struct slot * slot)494 int pciehp_query_power_fault(struct slot *slot)
495 {
496 struct controller *ctrl = slot->ctrl;
497 u16 slot_status;
498 int retval;
499
500 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
501 if (retval) {
502 ctrl_err(ctrl, "Cannot check for power fault\n");
503 return retval;
504 }
505 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
506 }
507
pciehp_set_attention_status(struct slot * slot,u8 value)508 int pciehp_set_attention_status(struct slot *slot, u8 value)
509 {
510 struct controller *ctrl = slot->ctrl;
511 u16 slot_cmd;
512 u16 cmd_mask;
513
514 cmd_mask = PCI_EXP_SLTCTL_AIC;
515 switch (value) {
516 case 0 : /* turn off */
517 slot_cmd = 0x00C0;
518 break;
519 case 1: /* turn on */
520 slot_cmd = 0x0040;
521 break;
522 case 2: /* turn blink */
523 slot_cmd = 0x0080;
524 break;
525 default:
526 return -EINVAL;
527 }
528 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
529 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
530 return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
531 }
532
pciehp_green_led_on(struct slot * slot)533 void pciehp_green_led_on(struct slot *slot)
534 {
535 struct controller *ctrl = slot->ctrl;
536 u16 slot_cmd;
537 u16 cmd_mask;
538
539 slot_cmd = 0x0100;
540 cmd_mask = PCI_EXP_SLTCTL_PIC;
541 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
542 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
543 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
544 }
545
pciehp_green_led_off(struct slot * slot)546 void pciehp_green_led_off(struct slot *slot)
547 {
548 struct controller *ctrl = slot->ctrl;
549 u16 slot_cmd;
550 u16 cmd_mask;
551
552 slot_cmd = 0x0300;
553 cmd_mask = PCI_EXP_SLTCTL_PIC;
554 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
555 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
556 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
557 }
558
pciehp_green_led_blink(struct slot * slot)559 void pciehp_green_led_blink(struct slot *slot)
560 {
561 struct controller *ctrl = slot->ctrl;
562 u16 slot_cmd;
563 u16 cmd_mask;
564
565 slot_cmd = 0x0200;
566 cmd_mask = PCI_EXP_SLTCTL_PIC;
567 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
568 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
569 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
570 }
571
pciehp_power_on_slot(struct slot * slot)572 int pciehp_power_on_slot(struct slot * slot)
573 {
574 struct controller *ctrl = slot->ctrl;
575 u16 slot_cmd;
576 u16 cmd_mask;
577 u16 slot_status;
578 int retval = 0;
579
580 /* Clear sticky power-fault bit from previous power failures */
581 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
582 if (retval) {
583 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
584 __func__);
585 return retval;
586 }
587 slot_status &= PCI_EXP_SLTSTA_PFD;
588 if (slot_status) {
589 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
590 if (retval) {
591 ctrl_err(ctrl,
592 "%s: Cannot write to SLOTSTATUS register\n",
593 __func__);
594 return retval;
595 }
596 }
597 ctrl->power_fault_detected = 0;
598
599 slot_cmd = POWER_ON;
600 cmd_mask = PCI_EXP_SLTCTL_PCC;
601 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
602 if (retval) {
603 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
604 return retval;
605 }
606 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
607 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
608
609 retval = pciehp_link_enable(ctrl);
610 if (retval)
611 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
612
613 return retval;
614 }
615
pciehp_power_off_slot(struct slot * slot)616 int pciehp_power_off_slot(struct slot * slot)
617 {
618 struct controller *ctrl = slot->ctrl;
619 u16 slot_cmd;
620 u16 cmd_mask;
621 int retval;
622
623 /* Disable the link at first */
624 pciehp_link_disable(ctrl);
625 /* wait the link is down */
626 if (ctrl->link_active_reporting)
627 pcie_wait_link_not_active(ctrl);
628 else
629 msleep(1000);
630
631 slot_cmd = POWER_OFF;
632 cmd_mask = PCI_EXP_SLTCTL_PCC;
633 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
634 if (retval) {
635 ctrl_err(ctrl, "Write command failed!\n");
636 return retval;
637 }
638 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
639 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
640 return 0;
641 }
642
pcie_isr(int irq,void * dev_id)643 static irqreturn_t pcie_isr(int irq, void *dev_id)
644 {
645 struct controller *ctrl = (struct controller *)dev_id;
646 struct slot *slot = ctrl->slot;
647 u16 detected, intr_loc;
648
649 /*
650 * In order to guarantee that all interrupt events are
651 * serviced, we need to re-inspect Slot Status register after
652 * clearing what is presumed to be the last pending interrupt.
653 */
654 intr_loc = 0;
655 do {
656 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
657 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
658 __func__);
659 return IRQ_NONE;
660 }
661
662 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
663 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
664 PCI_EXP_SLTSTA_CC);
665 detected &= ~intr_loc;
666 intr_loc |= detected;
667 if (!intr_loc)
668 return IRQ_NONE;
669 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
670 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
671 __func__);
672 return IRQ_NONE;
673 }
674 } while (detected);
675
676 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
677
678 /* Check Command Complete Interrupt Pending */
679 if (intr_loc & PCI_EXP_SLTSTA_CC) {
680 ctrl->cmd_busy = 0;
681 smp_mb();
682 wake_up(&ctrl->queue);
683 }
684
685 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
686 return IRQ_HANDLED;
687
688 /* Check MRL Sensor Changed */
689 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
690 pciehp_handle_switch_change(slot);
691
692 /* Check Attention Button Pressed */
693 if (intr_loc & PCI_EXP_SLTSTA_ABP)
694 pciehp_handle_attention_button(slot);
695
696 /* Check Presence Detect Changed */
697 if (intr_loc & PCI_EXP_SLTSTA_PDC)
698 pciehp_handle_presence_change(slot);
699
700 /* Check Power Fault Detected */
701 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
702 ctrl->power_fault_detected = 1;
703 pciehp_handle_power_fault(slot);
704 }
705 return IRQ_HANDLED;
706 }
707
pciehp_get_max_lnk_width(struct slot * slot,enum pcie_link_width * value)708 int pciehp_get_max_lnk_width(struct slot *slot,
709 enum pcie_link_width *value)
710 {
711 struct controller *ctrl = slot->ctrl;
712 enum pcie_link_width lnk_wdth;
713 u32 lnk_cap;
714 int retval = 0;
715
716 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
717 if (retval) {
718 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
719 return retval;
720 }
721
722 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
723 case 0:
724 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
725 break;
726 case 1:
727 lnk_wdth = PCIE_LNK_X1;
728 break;
729 case 2:
730 lnk_wdth = PCIE_LNK_X2;
731 break;
732 case 4:
733 lnk_wdth = PCIE_LNK_X4;
734 break;
735 case 8:
736 lnk_wdth = PCIE_LNK_X8;
737 break;
738 case 12:
739 lnk_wdth = PCIE_LNK_X12;
740 break;
741 case 16:
742 lnk_wdth = PCIE_LNK_X16;
743 break;
744 case 32:
745 lnk_wdth = PCIE_LNK_X32;
746 break;
747 default:
748 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
749 break;
750 }
751
752 *value = lnk_wdth;
753 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
754
755 return retval;
756 }
757
pciehp_get_cur_lnk_width(struct slot * slot,enum pcie_link_width * value)758 int pciehp_get_cur_lnk_width(struct slot *slot,
759 enum pcie_link_width *value)
760 {
761 struct controller *ctrl = slot->ctrl;
762 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
763 int retval = 0;
764 u16 lnk_status;
765
766 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
767 if (retval) {
768 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
769 __func__);
770 return retval;
771 }
772
773 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
774 case 0:
775 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
776 break;
777 case 1:
778 lnk_wdth = PCIE_LNK_X1;
779 break;
780 case 2:
781 lnk_wdth = PCIE_LNK_X2;
782 break;
783 case 4:
784 lnk_wdth = PCIE_LNK_X4;
785 break;
786 case 8:
787 lnk_wdth = PCIE_LNK_X8;
788 break;
789 case 12:
790 lnk_wdth = PCIE_LNK_X12;
791 break;
792 case 16:
793 lnk_wdth = PCIE_LNK_X16;
794 break;
795 case 32:
796 lnk_wdth = PCIE_LNK_X32;
797 break;
798 default:
799 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
800 break;
801 }
802
803 *value = lnk_wdth;
804 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
805
806 return retval;
807 }
808
pcie_enable_notification(struct controller * ctrl)809 int pcie_enable_notification(struct controller *ctrl)
810 {
811 u16 cmd, mask;
812
813 /*
814 * TBD: Power fault detected software notification support.
815 *
816 * Power fault detected software notification is not enabled
817 * now, because it caused power fault detected interrupt storm
818 * on some machines. On those machines, power fault detected
819 * bit in the slot status register was set again immediately
820 * when it is cleared in the interrupt service routine, and
821 * next power fault detected interrupt was notified again.
822 */
823 cmd = PCI_EXP_SLTCTL_PDCE;
824 if (ATTN_BUTTN(ctrl))
825 cmd |= PCI_EXP_SLTCTL_ABPE;
826 if (MRL_SENS(ctrl))
827 cmd |= PCI_EXP_SLTCTL_MRLSCE;
828 if (!pciehp_poll_mode)
829 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
830
831 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
832 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
833 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
834
835 if (pcie_write_cmd(ctrl, cmd, mask)) {
836 ctrl_err(ctrl, "Cannot enable software notification\n");
837 return -1;
838 }
839 return 0;
840 }
841
pcie_disable_notification(struct controller * ctrl)842 static void pcie_disable_notification(struct controller *ctrl)
843 {
844 u16 mask;
845 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
846 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
847 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
848 PCI_EXP_SLTCTL_DLLSCE);
849 if (pcie_write_cmd(ctrl, 0, mask))
850 ctrl_warn(ctrl, "Cannot disable software notification\n");
851 }
852
pcie_init_notification(struct controller * ctrl)853 int pcie_init_notification(struct controller *ctrl)
854 {
855 if (pciehp_request_irq(ctrl))
856 return -1;
857 if (pcie_enable_notification(ctrl)) {
858 pciehp_free_irq(ctrl);
859 return -1;
860 }
861 ctrl->notification_enabled = 1;
862 return 0;
863 }
864
pcie_shutdown_notification(struct controller * ctrl)865 static void pcie_shutdown_notification(struct controller *ctrl)
866 {
867 if (ctrl->notification_enabled) {
868 pcie_disable_notification(ctrl);
869 pciehp_free_irq(ctrl);
870 ctrl->notification_enabled = 0;
871 }
872 }
873
pcie_init_slot(struct controller * ctrl)874 static int pcie_init_slot(struct controller *ctrl)
875 {
876 struct slot *slot;
877 char name[32];
878
879 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
880 if (!slot)
881 return -ENOMEM;
882
883 snprintf(name, sizeof(name), "pciehp-%u", PSN(ctrl));
884 slot->wq = alloc_workqueue(name, 0, 0);
885 if (!slot->wq)
886 goto abort;
887
888 slot->ctrl = ctrl;
889 mutex_init(&slot->lock);
890 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
891 ctrl->slot = slot;
892 return 0;
893 abort:
894 kfree(slot);
895 return -ENOMEM;
896 }
897
pcie_cleanup_slot(struct controller * ctrl)898 static void pcie_cleanup_slot(struct controller *ctrl)
899 {
900 struct slot *slot = ctrl->slot;
901 cancel_delayed_work(&slot->work);
902 destroy_workqueue(slot->wq);
903 kfree(slot);
904 }
905
dbg_ctrl(struct controller * ctrl)906 static inline void dbg_ctrl(struct controller *ctrl)
907 {
908 int i;
909 u16 reg16;
910 struct pci_dev *pdev = ctrl->pcie->port;
911
912 if (!pciehp_debug)
913 return;
914
915 ctrl_info(ctrl, "Hotplug Controller:\n");
916 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
917 pci_name(pdev), pdev->irq);
918 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
919 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
920 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
921 pdev->subsystem_device);
922 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
923 pdev->subsystem_vendor);
924 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
925 pci_pcie_cap(pdev));
926 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
927 if (!pci_resource_len(pdev, i))
928 continue;
929 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
930 i, &pdev->resource[i]);
931 }
932 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
933 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
934 ctrl_info(ctrl, " Attention Button : %3s\n",
935 ATTN_BUTTN(ctrl) ? "yes" : "no");
936 ctrl_info(ctrl, " Power Controller : %3s\n",
937 POWER_CTRL(ctrl) ? "yes" : "no");
938 ctrl_info(ctrl, " MRL Sensor : %3s\n",
939 MRL_SENS(ctrl) ? "yes" : "no");
940 ctrl_info(ctrl, " Attention Indicator : %3s\n",
941 ATTN_LED(ctrl) ? "yes" : "no");
942 ctrl_info(ctrl, " Power Indicator : %3s\n",
943 PWR_LED(ctrl) ? "yes" : "no");
944 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
945 HP_SUPR_RM(ctrl) ? "yes" : "no");
946 ctrl_info(ctrl, " EMI Present : %3s\n",
947 EMI(ctrl) ? "yes" : "no");
948 ctrl_info(ctrl, " Command Completed : %3s\n",
949 NO_CMD_CMPL(ctrl) ? "no" : "yes");
950 pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16);
951 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
952 pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16);
953 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
954 }
955
pcie_init(struct pcie_device * dev)956 struct controller *pcie_init(struct pcie_device *dev)
957 {
958 struct controller *ctrl;
959 u32 slot_cap, link_cap;
960 struct pci_dev *pdev = dev->port;
961
962 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
963 if (!ctrl) {
964 dev_err(&dev->device, "%s: Out of memory\n", __func__);
965 goto abort;
966 }
967 ctrl->pcie = dev;
968 if (!pci_pcie_cap(pdev)) {
969 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
970 goto abort_ctrl;
971 }
972 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
973 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
974 goto abort_ctrl;
975 }
976
977 ctrl->slot_cap = slot_cap;
978 mutex_init(&ctrl->ctrl_lock);
979 init_waitqueue_head(&ctrl->queue);
980 dbg_ctrl(ctrl);
981 /*
982 * Controller doesn't notify of command completion if the "No
983 * Command Completed Support" bit is set in Slot Capability
984 * register or the controller supports none of power
985 * controller, attention led, power led and EMI.
986 */
987 if (NO_CMD_CMPL(ctrl) ||
988 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
989 ctrl->no_cmd_complete = 1;
990
991 /* Check if Data Link Layer Link Active Reporting is implemented */
992 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
993 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
994 goto abort_ctrl;
995 }
996 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
997 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
998 ctrl->link_active_reporting = 1;
999 }
1000
1001 /* Clear all remaining event bits in Slot Status register */
1002 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
1003 goto abort_ctrl;
1004
1005 /* Disable sotfware notification */
1006 pcie_disable_notification(ctrl);
1007
1008 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1009 pdev->vendor, pdev->device, pdev->subsystem_vendor,
1010 pdev->subsystem_device);
1011
1012 if (pcie_init_slot(ctrl))
1013 goto abort_ctrl;
1014
1015 return ctrl;
1016
1017 abort_ctrl:
1018 kfree(ctrl);
1019 abort:
1020 return NULL;
1021 }
1022
pciehp_release_ctrl(struct controller * ctrl)1023 void pciehp_release_ctrl(struct controller *ctrl)
1024 {
1025 pcie_shutdown_notification(ctrl);
1026 pcie_cleanup_slot(ctrl);
1027 kfree(ctrl);
1028 }
1029