1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI IP27 specific setup.
7 *
8 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
9 * Copyright (C) 1999, 2000 Silcon Graphics, Inc.
10 */
11 #include <linux/config.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/spinlock.h>
15 #include <linux/sched.h>
16 #include <linux/smp.h>
17
18 #include <asm/io.h>
19 #include <asm/sn/types.h>
20 #include <asm/sn/sn0/addrs.h>
21 #include <asm/sn/sn0/hubni.h>
22 #include <asm/sn/sn0/hubio.h>
23 #include <asm/sn/klconfig.h>
24 #include <asm/sn/ioc3.h>
25 #include <asm/time.h>
26 #include <asm/mipsregs.h>
27 #include <asm/sn/arch.h>
28 #include <asm/sn/sn_private.h>
29 #include <asm/pci/bridge.h>
30 #include <asm/paccess.h>
31 #include <asm/sn/sn0/ip27.h>
32 #include <asm/traps.h>
33
34 /* Check against user dumbness. */
35 #ifdef CONFIG_VT
36 #error CONFIG_VT not allowed for IP27.
37 #endif
38
39 #undef DEBUG_SETUP
40 #ifdef DEBUG_SETUP
41 #define DBG(x...) printk(x)
42 #else
43 #define DBG(x...)
44 #endif
45
46 extern void ip27_be_init(void) __init;
47
48 /*
49 * get_nasid() returns the physical node id number of the caller.
50 */
51 nasid_t
get_nasid(void)52 get_nasid(void)
53 {
54 return (nasid_t)((LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_NODEID_MASK)
55 >> NSRI_NODEID_SHFT);
56 }
57
58 /* Extracted from the IOC3 meta driver. FIXME. */
ioc3_sio_init(void)59 static inline void ioc3_sio_init(void)
60 {
61 struct ioc3 *ioc3;
62 nasid_t nid;
63 long loops;
64
65 nid = get_nasid();
66 ioc3 = (struct ioc3 *) KL_CONFIG_CH_CONS_INFO(nid)->memory_base;
67
68 ioc3->sscr_a = 0; /* PIO mode for uarta. */
69 ioc3->sscr_b = 0; /* PIO mode for uartb. */
70 ioc3->sio_iec = ~0;
71 ioc3->sio_ies = (SIO_IR_SA_INT | SIO_IR_SB_INT);
72
73 loops=1000000; while(loops--);
74 ioc3->sregs.uarta.iu_fcr = 0;
75 ioc3->sregs.uartb.iu_fcr = 0;
76 loops=1000000; while(loops--);
77 }
78
ioc3_eth_init(void)79 static inline void ioc3_eth_init(void)
80 {
81 struct ioc3 *ioc3;
82 nasid_t nid;
83
84 nid = get_nasid();
85 ioc3 = (struct ioc3 *) KL_CONFIG_CH_CONS_INFO(nid)->memory_base;
86
87 ioc3->eier = 0;
88 }
89
90 /* Try to catch kernel missconfigurations and give user an indication what
91 option to select. */
verify_mode(void)92 static void __init verify_mode(void)
93 {
94 int n_mode;
95
96 n_mode = LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_MORENODES_MASK;
97 printk("Machine is in %c mode.\n", n_mode ? 'N' : 'M');
98 #ifdef CONFIG_SGI_SN0_N_MODE
99 if (!n_mode)
100 panic("Kernel compiled for M mode.");
101 #else
102 if (n_mode)
103 panic("Kernel compiled for N mode.");
104 #endif
105 }
106
107 #define XBOW_WIDGET_PART_NUM 0x0
108 #define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */
109 #define BASE_XBOW_PORT 8 /* Lowest external port */
110
111 unsigned int bus_to_cpu[256];
112 unsigned long bus_to_baddr[256];
113
pcibr_setup(cnodeid_t nid)114 void __init pcibr_setup(cnodeid_t nid)
115 {
116 int i, start, num;
117 unsigned long masterwid;
118 bridge_t *bridge;
119 volatile u64 hubreg;
120 nasid_t nasid, masternasid;
121 xwidget_part_num_t partnum;
122 widgetreg_t widget_id;
123 static spinlock_t pcibr_setup_lock = SPIN_LOCK_UNLOCKED;
124
125 /*
126 * If the master is doing this for headless node, nothing to do.
127 * This is because currently we require at least one of the hubs
128 * (master hub) connected to the xbow to have at least one enabled
129 * cpu to receive intrs. Else we need an array bus_to_intrnasid[]
130 * that bridge_startup() needs to use to target intrs. All dma is
131 * routed thru the widget of the master hub. The master hub wid
132 * is selectable by WIDGET_A below.
133 */
134 if (nid != get_compact_nodeid())
135 return;
136 /*
137 * find what's on our local node
138 */
139 spin_lock(&pcibr_setup_lock);
140 start = num_bridges; /* Remember where we start from */
141 nasid = COMPACT_TO_NASID_NODEID(nid);
142 hubreg = REMOTE_HUB_L(nasid, IIO_LLP_CSR);
143 if (hubreg & IIO_LLP_CSR_IS_UP) {
144 /* link is up */
145 widget_id = *(volatile widgetreg_t *)
146 (RAW_NODE_SWIN_BASE(nasid, 0x0) + WIDGET_ID);
147 partnum = XWIDGET_PART_NUM(widget_id);
148 printk("Cpu %d, Nasid 0x%x, pcibr_setup(): found partnum= 0x%x",
149 smp_processor_id(), nasid, partnum);
150 if (partnum == BRIDGE_WIDGET_PART_NUM) {
151 /*
152 * found direct connected bridge so must be Origin200
153 */
154 printk("...is bridge\n");
155 num_bridges = 1;
156 bus_to_wid[0] = 0x8;
157 bus_to_nid[0] = 0;
158 masterwid = 0xa;
159 bus_to_baddr[0] = 0xa100000000000000UL;
160 } else if (partnum == XBOW_WIDGET_PART_NUM) {
161 lboard_t *brd;
162 klxbow_t *xbow_p;
163 /*
164 * found xbow, so may have multiple bridges
165 * need to probe xbow
166 */
167 printk("...is xbow\n");
168
169 if ((brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid),
170 KLTYPE_MIDPLANE8)) == NULL)
171 printk("argh\n");
172 else
173 printk("brd = 0x%lx\n", (unsigned long) brd);
174 if ((xbow_p = (klxbow_t *)
175 find_component(brd, NULL, KLSTRUCT_XBOW)) == NULL)
176 printk("argh\n");
177 else {
178 /*
179 * Okay, here's a xbow. Lets arbitrate and find
180 * out if we should initialize it. Set enabled
181 * hub connected at highest or lowest widget as
182 * master.
183 */
184 #ifdef WIDGET_A
185 i = HUB_WIDGET_ID_MAX + 1;
186 do {
187 i--;
188 } while ((!XBOW_PORT_TYPE_HUB(xbow_p, i)) ||
189 (!XBOW_PORT_IS_ENABLED(xbow_p, i)));
190 #else
191 i = HUB_WIDGET_ID_MIN - 1;
192 do {
193 i++;
194 } while ((!XBOW_PORT_TYPE_HUB(xbow_p, i)) ||
195 (!XBOW_PORT_IS_ENABLED(xbow_p, i)));
196 #endif
197 masterwid = i;
198 masternasid = XBOW_PORT_NASID(xbow_p, i);
199 if (nasid == masternasid)
200 for (i=HUB_WIDGET_ID_MIN; i<=HUB_WIDGET_ID_MAX; i++) {
201 if (!XBOW_PORT_IS_ENABLED(xbow_p, i))
202 continue;
203 if (XBOW_PORT_TYPE_IO(xbow_p, i)) {
204 widget_id = *(volatile widgetreg_t *)
205 (RAW_NODE_SWIN_BASE(nasid, i) + WIDGET_ID);
206 partnum = XWIDGET_PART_NUM(widget_id);
207 if (partnum == BRIDGE_WIDGET_PART_NUM) {
208 printk("widget 0x%x is a bridge\n", i);
209 bus_to_wid[num_bridges] = i;
210 bus_to_nid[num_bridges] = nasid;
211 bus_to_baddr[num_bridges] = ((masterwid << 60) | (1UL << 56)); /* Barrier set */
212 num_bridges++;
213 }
214 }
215 }
216 }
217 } else if (partnum == XXBOW_WIDGET_PART_NUM) {
218 /*
219 * found xbridge, assume ibrick for now
220 */
221 printk("...is xbridge\n");
222 bus_to_wid[0] = 0xb;
223 bus_to_wid[1] = 0xe;
224 bus_to_wid[2] = 0xf;
225
226 bus_to_nid[0] = 0;
227 bus_to_nid[1] = 0;
228 bus_to_nid[2] = 0;
229
230 bus_to_baddr[0] = 0xa100000000000000UL;
231 bus_to_baddr[1] = 0xa100000000000000UL;
232 bus_to_baddr[2] = 0xa100000000000000UL;
233 masterwid = 0xa;
234 num_bridges = 3;
235 }
236 }
237 num = num_bridges - start;
238 spin_unlock(&pcibr_setup_lock);
239 /*
240 * set bridge registers
241 */
242 for (i = start; i < (start + num); i++) {
243
244 DBG("pcibr_setup: bus= %d bus_to_wid[%2d]= %d bus_to_nid[%2d]= %d\n",
245 i, i, bus_to_wid[i], i, bus_to_nid[i]);
246
247 bus_to_cpu[i] = smp_processor_id();
248 /*
249 * point to this bridge
250 */
251 bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[i],bus_to_wid[i]);
252 /*
253 * Clear all pending interrupts.
254 */
255 bridge->b_int_rst_stat = (BRIDGE_IRR_ALL_CLR);
256 /*
257 * Until otherwise set up, assume all interrupts are from slot 0
258 */
259 bridge->b_int_device = (u32) 0x0;
260 /*
261 * swap pio's to pci mem and io space (big windows)
262 */
263 bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP;
264 bridge->b_wid_control |= BRIDGE_CTRL_MEM_SWAP;
265
266 /*
267 * Hmm... IRIX sets additional bits in the address which
268 * are documented as reserved in the bridge docs.
269 */
270 bridge->b_int_mode = 0x0; /* Don't clear ints */
271 bridge->b_wid_int_upper = 0x8000 | (masterwid << 16);
272 bridge->b_wid_int_lower = 0x01800090; /* PI_INT_PEND_MOD off*/
273 bridge->b_dir_map = (masterwid << 20); /* DMA */
274 bridge->b_int_enable = 0;
275
276 bridge->b_wid_tflush; /* wait until Bridge PIO complete */
277 }
278 }
279
280 extern void ip27_setup_console(void);
281 extern void ip27_time_init(void);
282 extern void ip27_reboot_setup(void);
283
ip27_setup(void)284 void __init ip27_setup(void)
285 {
286 nasid_t nid;
287 hubreg_t p, e;
288
289 ip27_setup_console();
290 ip27_reboot_setup();
291
292 num_bridges = 0;
293 /*
294 * hub_rtc init and cpu clock intr enabled for later calibrate_delay.
295 */
296 DBG("ip27_setup(): Entered.\n");
297 nid = get_nasid();
298 printk("IP27: Running on node %d.\n", nid);
299
300 p = LOCAL_HUB_L(PI_CPU_PRESENT_A) & 1;
301 e = LOCAL_HUB_L(PI_CPU_ENABLE_A) & 1;
302 printk("Node %d has %s primary CPU%s.\n", nid,
303 p ? "a" : "no",
304 e ? ", CPU is running" : "");
305
306 p = LOCAL_HUB_L(PI_CPU_PRESENT_B) & 1;
307 e = LOCAL_HUB_L(PI_CPU_ENABLE_B) & 1;
308 printk("Node %d has %s secondary CPU%s.\n", nid,
309 p ? "a" : "no",
310 e ? ", CPU is running" : "");
311
312 verify_mode();
313 ioc3_sio_init();
314 ioc3_eth_init();
315 per_cpu_init();
316
317 set_io_port_base(IO_BASE);
318
319 board_be_init = ip27_be_init;
320 board_time_init = ip27_time_init;
321 }
322