1 /* $Id$ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992-1997,2000-2003 Silicon Graphics, Inc. All rights reserved. 8 */ 9 #ifndef _ASM_SN_PCI_PCIBR_H 10 #define _ASM_SN_PCI_PCIBR_H 11 12 #if defined(__KERNEL__) 13 14 #include <linux/config.h> 15 #include <asm/sn/dmamap.h> 16 #include <asm/sn/driver.h> 17 #include <asm/sn/pio.h> 18 19 #include <asm/sn/pci/pciio.h> 20 #include <asm/sn/pci/bridge.h> 21 22 /* ===================================================================== 23 * symbolic constants used by pcibr's xtalk bus provider 24 */ 25 26 #define PCIBR_PIOMAP_BUSY 0x80000000 27 28 #define PCIBR_DMAMAP_BUSY 0x80000000 29 #define PCIBR_DMAMAP_SSRAM 0x40000000 30 31 #define PCIBR_INTR_BLOCKED 0x40000000 32 #define PCIBR_INTR_BUSY 0x80000000 33 34 #ifndef __ASSEMBLY__ 35 36 /* ===================================================================== 37 * opaque types used by pcibr's xtalk bus provider 38 */ 39 40 typedef struct pcibr_piomap_s *pcibr_piomap_t; 41 typedef struct pcibr_dmamap_s *pcibr_dmamap_t; 42 typedef struct pcibr_intr_s *pcibr_intr_t; 43 44 /* ===================================================================== 45 * primary entry points: Bridge (pcibr) device driver 46 * 47 * These functions are normal device driver entry points 48 * and are called along with the similar entry points from 49 * other device drivers. They are included here as documentation 50 * of their existence and purpose. 51 * 52 * pcibr_init() is called to inform us that there is a pcibr driver 53 * configured into the kernel; it is responsible for registering 54 * as a crosstalk widget and providing a routine to be called 55 * when a widget with the proper part number is observed. 56 * 57 * pcibr_attach() is called for each vertex in the hardware graph 58 * corresponding to a crosstalk widget with the manufacturer 59 * code and part number registered by pcibr_init(). 60 */ 61 62 extern int pcibr_attach(vertex_hdl_t); 63 64 /* ===================================================================== 65 * bus provider function table 66 * 67 * Normally, this table is only handed off explicitly 68 * during provider initialization, and the PCI generic 69 * layer will stash a pointer to it in the vertex; however, 70 * exporting it explicitly enables a performance hack in 71 * the generic PCI provider where if we know at compile 72 * time that the only possible PCI provider is a 73 * pcibr, we can go directly to this ops table. 74 */ 75 76 extern pciio_provider_t pcibr_provider; 77 extern pciio_provider_t pci_pic_provider; 78 79 /* ===================================================================== 80 * secondary entry points: pcibr PCI bus provider 81 * 82 * These functions are normally exported explicitly by 83 * a direct call from the pcibr initialization routine 84 * into the generic crosstalk provider; they are included 85 * here to enable a more aggressive performance hack in 86 * the generic crosstalk layer, where if we know that the 87 * only possible crosstalk provider is pcibr, and we can 88 * guarantee that all entry points are properly named, and 89 * we can deal with the implicit casting properly, then 90 * we can turn many of the generic provider routines into 91 * plain brances, or even eliminate them (given sufficient 92 * smarts on the part of the compilation system). 93 */ 94 95 extern pcibr_piomap_t pcibr_piomap_alloc(vertex_hdl_t dev, 96 device_desc_t dev_desc, 97 pciio_space_t space, 98 iopaddr_t pci_addr, 99 size_t byte_count, 100 size_t byte_count_max, 101 unsigned flags); 102 103 extern void pcibr_piomap_free(pcibr_piomap_t piomap); 104 105 extern caddr_t pcibr_piomap_addr(pcibr_piomap_t piomap, 106 iopaddr_t xtalk_addr, 107 size_t byte_count); 108 109 extern void pcibr_piomap_done(pcibr_piomap_t piomap); 110 111 extern caddr_t pcibr_piotrans_addr(vertex_hdl_t dev, 112 device_desc_t dev_desc, 113 pciio_space_t space, 114 iopaddr_t pci_addr, 115 size_t byte_count, 116 unsigned flags); 117 118 extern iopaddr_t pcibr_piospace_alloc(vertex_hdl_t dev, 119 device_desc_t dev_desc, 120 pciio_space_t space, 121 size_t byte_count, 122 size_t alignment); 123 extern void pcibr_piospace_free(vertex_hdl_t dev, 124 pciio_space_t space, 125 iopaddr_t pciaddr, 126 size_t byte_count); 127 128 extern pcibr_dmamap_t pcibr_dmamap_alloc(vertex_hdl_t dev, 129 device_desc_t dev_desc, 130 size_t byte_count_max, 131 unsigned flags); 132 133 extern void pcibr_dmamap_free(pcibr_dmamap_t dmamap); 134 135 extern iopaddr_t pcibr_dmamap_addr(pcibr_dmamap_t dmamap, 136 paddr_t paddr, 137 size_t byte_count); 138 139 extern alenlist_t pcibr_dmamap_list(pcibr_dmamap_t dmamap, 140 alenlist_t palenlist, 141 unsigned flags); 142 143 extern void pcibr_dmamap_done(pcibr_dmamap_t dmamap); 144 145 /* 146 * pcibr_get_dmatrans_node() will return the compact node id to which 147 * all 32-bit Direct Mapping memory accesses will be directed. 148 * (This node id can be different for each PCI bus.) 149 */ 150 151 extern cnodeid_t pcibr_get_dmatrans_node(vertex_hdl_t pconn_vhdl); 152 153 extern iopaddr_t pcibr_dmatrans_addr(vertex_hdl_t dev, 154 device_desc_t dev_desc, 155 paddr_t paddr, 156 size_t byte_count, 157 unsigned flags); 158 159 extern alenlist_t pcibr_dmatrans_list(vertex_hdl_t dev, 160 device_desc_t dev_desc, 161 alenlist_t palenlist, 162 unsigned flags); 163 164 extern void pcibr_dmamap_drain(pcibr_dmamap_t map); 165 166 extern void pcibr_dmaaddr_drain(vertex_hdl_t vhdl, 167 paddr_t addr, 168 size_t bytes); 169 170 extern void pcibr_dmalist_drain(vertex_hdl_t vhdl, 171 alenlist_t list); 172 173 typedef unsigned pcibr_intr_ibit_f(pciio_info_t info, 174 pciio_intr_line_t lines); 175 176 extern void pcibr_intr_ibit_set(vertex_hdl_t, pcibr_intr_ibit_f *); 177 178 extern pcibr_intr_t pcibr_intr_alloc(vertex_hdl_t dev, 179 device_desc_t dev_desc, 180 pciio_intr_line_t lines, 181 vertex_hdl_t owner_dev); 182 183 extern void pcibr_intr_free(pcibr_intr_t intr); 184 185 extern int pcibr_intr_connect(pcibr_intr_t intr, intr_func_t, intr_arg_t); 186 187 extern void pcibr_intr_disconnect(pcibr_intr_t intr); 188 189 extern vertex_hdl_t pcibr_intr_cpu_get(pcibr_intr_t intr); 190 191 extern void pcibr_provider_startup(vertex_hdl_t pcibr); 192 193 extern void pcibr_provider_shutdown(vertex_hdl_t pcibr); 194 195 extern int pcibr_reset(vertex_hdl_t dev); 196 197 extern pciio_endian_t pcibr_endian_set(vertex_hdl_t dev, 198 pciio_endian_t device_end, 199 pciio_endian_t desired_end); 200 201 extern uint64_t pcibr_config_get(vertex_hdl_t conn, 202 unsigned reg, 203 unsigned size); 204 205 extern void pcibr_config_set(vertex_hdl_t conn, 206 unsigned reg, 207 unsigned size, 208 uint64_t value); 209 210 extern int pcibr_error_devenable(vertex_hdl_t pconn_vhdl, 211 int error_code); 212 213 extern int pcibr_wrb_flush(vertex_hdl_t pconn_vhdl); 214 extern int pcibr_rrb_check(vertex_hdl_t pconn_vhdl, 215 int *count_vchan0, 216 int *count_vchan1, 217 int *count_reserved, 218 int *count_pool); 219 220 extern int pcibr_alloc_all_rrbs(vertex_hdl_t vhdl, int even_odd, 221 int dev_1_rrbs, int virt1, 222 int dev_2_rrbs, int virt2, 223 int dev_3_rrbs, int virt3, 224 int dev_4_rrbs, int virt4); 225 226 typedef void 227 rrb_alloc_funct_f (vertex_hdl_t xconn_vhdl, 228 int *vendor_list); 229 230 typedef rrb_alloc_funct_f *rrb_alloc_funct_t; 231 232 void pcibr_set_rrb_callback(vertex_hdl_t xconn_vhdl, 233 rrb_alloc_funct_f *func); 234 235 extern int pcibr_device_unregister(vertex_hdl_t); 236 extern int pcibr_dma_enabled(vertex_hdl_t); 237 /* 238 * Bridge-specific flags that can be set via pcibr_device_flags_set 239 * and cleared via pcibr_device_flags_clear. Other flags are 240 * more generic and are maniuplated through PCI-generic interfaces. 241 * 242 * Note that all PCI implementation-specific flags (Bridge flags, in 243 * this case) are in bits 15-31. The lower 15 bits are reserved 244 * for PCI-generic flags. 245 * 246 * Some of these flags have been "promoted" to the 247 * generic layer, so they can be used without having 248 * to "know" that the PCI bus is hosted by a Bridge. 249 * 250 * PCIBR_NO_ATE_ROUNDUP: Request that no rounding up be done when 251 * allocating ATE's. ATE count computation will assume that the 252 * address to be mapped will start on a page boundary. 253 */ 254 #define PCIBR_NO_ATE_ROUNDUP 0x00008000 255 #define PCIBR_WRITE_GATHER 0x00010000 /* please use PCIIO version */ 256 #define PCIBR_NOWRITE_GATHER 0x00020000 /* please use PCIIO version */ 257 #define PCIBR_PREFETCH 0x00040000 /* please use PCIIO version */ 258 #define PCIBR_NOPREFETCH 0x00080000 /* please use PCIIO version */ 259 #define PCIBR_PRECISE 0x00100000 260 #define PCIBR_NOPRECISE 0x00200000 261 #define PCIBR_BARRIER 0x00400000 262 #define PCIBR_NOBARRIER 0x00800000 263 #define PCIBR_VCHAN0 0x01000000 264 #define PCIBR_VCHAN1 0x02000000 265 #define PCIBR_64BIT 0x04000000 266 #define PCIBR_NO64BIT 0x08000000 267 #define PCIBR_SWAP 0x10000000 268 #define PCIBR_NOSWAP 0x20000000 269 270 #define PCIBR_EXTERNAL_ATES 0x40000000 /* uses external ATEs */ 271 #define PCIBR_ACTIVE 0x80000000 /* need a "done" */ 272 273 /* Flags that have meaning to pcibr_device_flags_{set,clear} */ 274 #define PCIBR_DEVICE_FLAGS ( \ 275 PCIBR_WRITE_GATHER |\ 276 PCIBR_NOWRITE_GATHER |\ 277 PCIBR_PREFETCH |\ 278 PCIBR_NOPREFETCH |\ 279 PCIBR_PRECISE |\ 280 PCIBR_NOPRECISE |\ 281 PCIBR_BARRIER |\ 282 PCIBR_NOBARRIER \ 283 ) 284 285 /* Flags that have meaning to *_dmamap_alloc, *_dmatrans_{addr,list} */ 286 #define PCIBR_DMA_FLAGS ( \ 287 PCIBR_PREFETCH |\ 288 PCIBR_NOPREFETCH |\ 289 PCIBR_PRECISE |\ 290 PCIBR_NOPRECISE |\ 291 PCIBR_BARRIER |\ 292 PCIBR_NOBARRIER |\ 293 PCIBR_VCHAN0 |\ 294 PCIBR_VCHAN1 \ 295 ) 296 297 typedef int pcibr_device_flags_t; 298 299 /* 300 * Set bits in the Bridge Device(x) register for this device. 301 * "flags" are defined above. NOTE: this includes turning 302 * things *OFF* as well as turning them *ON* ... 303 */ 304 extern int pcibr_device_flags_set(vertex_hdl_t dev, 305 pcibr_device_flags_t flags); 306 307 /* 308 * Allocate Read Response Buffers for use by the specified device. 309 * count_vchan0 is the total number of buffers desired for the 310 * "normal" channel. count_vchan1 is the total number of buffers 311 * desired for the "virtual" channel. Returns 0 on success, or 312 * <0 on failure, which occurs when we're unable to allocate any 313 * buffers to a channel that desires at least one buffer. 314 */ 315 extern int pcibr_rrb_alloc(vertex_hdl_t pconn_vhdl, 316 int *count_vchan0, 317 int *count_vchan1); 318 319 /* 320 * Get the starting PCIbus address out of the given DMA map. 321 * This function is supposed to be used by a close friend of PCI bridge 322 * since it relies on the fact that the starting address of the map is fixed at 323 * the allocation time in the current implementation of PCI bridge. 324 */ 325 extern iopaddr_t pcibr_dmamap_pciaddr_get(pcibr_dmamap_t); 326 327 extern xwidget_intr_preset_f pcibr_xintr_preset; 328 329 extern void pcibr_hints_fix_rrbs(vertex_hdl_t); 330 extern void pcibr_hints_dualslot(vertex_hdl_t, pciio_slot_t, pciio_slot_t); 331 extern void pcibr_hints_subdevs(vertex_hdl_t, pciio_slot_t, ulong); 332 extern void pcibr_hints_handsoff(vertex_hdl_t); 333 334 typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t, int); 335 extern void pcibr_hints_intr_bits(vertex_hdl_t, pcibr_intr_bits_f *); 336 337 extern int pcibr_asic_rev(vertex_hdl_t); 338 339 #endif /* __ASSEMBLY__ */ 340 #endif /* #if defined(__KERNEL__) */ 341 /* 342 * Some useful ioctls into the pcibr driver 343 */ 344 #define PCIBR 'p' 345 #define _PCIBR(x) ((PCIBR << 8) | (x)) 346 347 #define PCIBR_SLOT_STARTUP _PCIBR(1) 348 #define PCIBR_SLOT_SHUTDOWN _PCIBR(2) 349 #define PCIBR_SLOT_QUERY _PCIBR(3) 350 351 /* 352 * Bit defintions for variable slot_status in struct 353 * pcibr_soft_slot_s. They are here so that both 354 * the pcibr driver and the pciconfig command can 355 * reference them. 356 */ 357 #define SLOT_STARTUP_CMPLT 0x01 358 #define SLOT_STARTUP_INCMPLT 0x02 359 #define SLOT_SHUTDOWN_CMPLT 0x04 360 #define SLOT_SHUTDOWN_INCMPLT 0x08 361 #define SLOT_POWER_UP 0x10 362 #define SLOT_POWER_DOWN 0x20 363 #define SLOT_IS_SYS_CRITICAL 0x40 364 365 #define SLOT_STATUS_MASK (SLOT_STARTUP_CMPLT | SLOT_STARTUP_INCMPLT | \ 366 SLOT_SHUTDOWN_CMPLT | SLOT_SHUTDOWN_INCMPLT) 367 #define SLOT_POWER_MASK (SLOT_POWER_UP | SLOT_POWER_DOWN) 368 369 /* 370 * Bit definitions for variable resp_f_staus. 371 * They are here so that both the pcibr driver 372 * and the pciconfig command can reference them. 373 */ 374 #define FUNC_IS_VALID 0x01 375 #define FUNC_IS_SYS_CRITICAL 0x02 376 377 /* 378 * Structures for requesting PCI bridge information and receiving a response 379 */ 380 typedef struct pcibr_slot_req_s *pcibr_slot_req_t; 381 typedef struct pcibr_slot_up_resp_s *pcibr_slot_up_resp_t; 382 typedef struct pcibr_slot_down_resp_s *pcibr_slot_down_resp_t; 383 typedef struct pcibr_slot_info_resp_s *pcibr_slot_info_resp_t; 384 typedef struct pcibr_slot_func_info_resp_s *pcibr_slot_func_info_resp_t; 385 386 #define L1_QSIZE 128 /* our L1 message buffer size */ 387 struct pcibr_slot_req_s { 388 int req_slot; 389 union { 390 pcibr_slot_up_resp_t up; 391 pcibr_slot_down_resp_t down; 392 pcibr_slot_info_resp_t query; 393 void *any; 394 } req_respp; 395 int req_size; 396 }; 397 398 struct pcibr_slot_up_resp_s { 399 int resp_sub_errno; 400 char resp_l1_msg[L1_QSIZE + 1]; 401 }; 402 403 struct pcibr_slot_down_resp_s { 404 int resp_sub_errno; 405 char resp_l1_msg[L1_QSIZE + 1]; 406 }; 407 408 struct pcibr_slot_info_resp_s { 409 short resp_bs_bridge_type; 410 short resp_bs_bridge_mode; 411 int resp_has_host; 412 char resp_host_slot; 413 vertex_hdl_t resp_slot_conn; 414 char resp_slot_conn_name[MAXDEVNAME]; 415 int resp_slot_status; 416 int resp_l1_bus_num; 417 int resp_bss_ninfo; 418 char resp_bss_devio_bssd_space[16]; 419 iopaddr_t resp_bss_devio_bssd_base; 420 bridgereg_t resp_bss_device; 421 int resp_bss_pmu_uctr; 422 int resp_bss_d32_uctr; 423 int resp_bss_d64_uctr; 424 iopaddr_t resp_bss_d64_base; 425 unsigned resp_bss_d64_flags; 426 iopaddr_t resp_bss_d32_base; 427 unsigned resp_bss_d32_flags; 428 atomic_t resp_bss_ext_ates_active; 429 volatile unsigned *resp_bss_cmd_pointer; 430 unsigned resp_bss_cmd_shadow; 431 int resp_bs_rrb_valid; 432 int resp_bs_rrb_valid_v1; 433 int resp_bs_rrb_valid_v2; 434 int resp_bs_rrb_valid_v3; 435 int resp_bs_rrb_res; 436 bridgereg_t resp_b_resp; 437 bridgereg_t resp_b_int_device; 438 bridgereg_t resp_b_int_enable; 439 bridgereg_t resp_b_int_host; 440 picreg_t resp_p_int_enable; 441 picreg_t resp_p_int_host; 442 struct pcibr_slot_func_info_resp_s { 443 int resp_f_status; 444 char resp_f_slot_name[MAXDEVNAME]; 445 char resp_f_bus; 446 char resp_f_slot; 447 char resp_f_func; 448 char resp_f_master_name[MAXDEVNAME]; 449 void *resp_f_pops; 450 error_handler_f *resp_f_efunc; 451 error_handler_arg_t resp_f_einfo; 452 int resp_f_vendor; 453 int resp_f_device; 454 455 struct { 456 char resp_w_space[16]; 457 iopaddr_t resp_w_base; 458 size_t resp_w_size; 459 } resp_f_window[6]; 460 461 unsigned resp_f_rbase; 462 unsigned resp_f_rsize; 463 int resp_f_ibit[4]; 464 int resp_f_att_det_error; 465 466 } resp_func[8]; 467 }; 468 469 470 /* 471 * PCI specific errors, interpreted by pciconfig command 472 */ 473 474 /* EPERM 1 */ 475 #define PCI_SLOT_ALREADY_UP 2 /* slot already up */ 476 #define PCI_SLOT_ALREADY_DOWN 3 /* slot already down */ 477 #define PCI_IS_SYS_CRITICAL 4 /* slot is system critical */ 478 /* EIO 5 */ 479 /* ENXIO 6 */ 480 #define PCI_L1_ERR 7 /* L1 console command error */ 481 #define PCI_NOT_A_BRIDGE 8 /* device is not a bridge */ 482 #define PCI_SLOT_IN_SHOEHORN 9 /* slot is in a shorhorn */ 483 #define PCI_NOT_A_SLOT 10 /* slot is invalid */ 484 #define PCI_RESP_AREA_TOO_SMALL 11 /* slot is invalid */ 485 /* ENOMEM 12 */ 486 #define PCI_NO_DRIVER 13 /* no driver for device */ 487 /* EFAULT 14 */ 488 #define PCI_EMPTY_33MHZ 15 /* empty 33 MHz bus */ 489 /* EBUSY 16 */ 490 #define PCI_SLOT_RESET_ERR 17 /* slot reset error */ 491 #define PCI_SLOT_INFO_INIT_ERR 18 /* slot info init error */ 492 /* ENODEV 19 */ 493 #define PCI_SLOT_ADDR_INIT_ERR 20 /* slot addr space init error */ 494 #define PCI_SLOT_DEV_INIT_ERR 21 /* slot device init error */ 495 /* EINVAL 22 */ 496 #define PCI_SLOT_GUEST_INIT_ERR 23 /* slot guest info init error */ 497 #define PCI_SLOT_RRB_ALLOC_ERR 24 /* slot initial rrb alloc error */ 498 #define PCI_SLOT_DRV_ATTACH_ERR 25 /* driver attach error */ 499 #define PCI_SLOT_DRV_DETACH_ERR 26 /* driver detach error */ 500 /* EFBIG 27 */ 501 #define PCI_MULTI_FUNC_ERR 28 /* multi-function card error */ 502 #define PCI_SLOT_RBAR_ALLOC_ERR 29 /* slot PCI-X RBAR alloc error */ 503 /* ERANGE 34 */ 504 /* EUNATCH 42 */ 505 506 #endif /* _ASM_SN_PCI_PCIBR_H */ 507