1 /*
2 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
14 #include <linux/pm.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
26 #include "pci.h"
27
28 const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
30 };
31 EXPORT_SYMBOL_GPL(pci_power_names);
32
33 int isa_dma_bridge_buggy;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy);
35
36 int pci_pci_problems;
37 EXPORT_SYMBOL(pci_pci_problems);
38
39 unsigned int pci_pm_d3_delay;
40
41 static void pci_pme_list_scan(struct work_struct *work);
42
43 static LIST_HEAD(pci_pme_list);
44 static DEFINE_MUTEX(pci_pme_list_mutex);
45 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
46
47 struct pci_pme_device {
48 struct list_head list;
49 struct pci_dev *dev;
50 };
51
52 #define PME_TIMEOUT 1000 /* How long between PME checks */
53
pci_dev_d3_sleep(struct pci_dev * dev)54 static void pci_dev_d3_sleep(struct pci_dev *dev)
55 {
56 unsigned int delay = dev->d3_delay;
57
58 if (delay < pci_pm_d3_delay)
59 delay = pci_pm_d3_delay;
60
61 msleep(delay);
62 }
63
64 #ifdef CONFIG_PCI_DOMAINS
65 int pci_domains_supported = 1;
66 #endif
67
68 #define DEFAULT_CARDBUS_IO_SIZE (256)
69 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
71 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
72 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
73
74 #define DEFAULT_HOTPLUG_IO_SIZE (256)
75 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
77 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
78 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
79
80 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
81
82 /*
83 * The default CLS is used if arch didn't set CLS explicitly and not
84 * all pci devices agree on the same value. Arch can override either
85 * the dfl or actual value as it sees fit. Don't forget this is
86 * measured in 32-bit words, not bytes.
87 */
88 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
89 u8 pci_cache_line_size;
90
91 /*
92 * If we set up a device for bus mastering, we need to check the latency
93 * timer as certain BIOSes forget to set it properly.
94 */
95 unsigned int pcibios_max_latency = 255;
96
97 /* If set, the PCIe ARI capability will not be used. */
98 static bool pcie_ari_disabled;
99
100 /**
101 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
102 * @bus: pointer to PCI bus structure to search
103 *
104 * Given a PCI bus, returns the highest PCI bus number present in the set
105 * including the given PCI bus and its list of child PCI buses.
106 */
pci_bus_max_busnr(struct pci_bus * bus)107 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
108 {
109 struct list_head *tmp;
110 unsigned char max, n;
111
112 max = bus->subordinate;
113 list_for_each(tmp, &bus->children) {
114 n = pci_bus_max_busnr(pci_bus_b(tmp));
115 if(n > max)
116 max = n;
117 }
118 return max;
119 }
120 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
121
122 #ifdef CONFIG_HAS_IOMEM
pci_ioremap_bar(struct pci_dev * pdev,int bar)123 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
124 {
125 /*
126 * Make sure the BAR is actually a memory resource, not an IO resource
127 */
128 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
129 WARN_ON(1);
130 return NULL;
131 }
132 return ioremap_nocache(pci_resource_start(pdev, bar),
133 pci_resource_len(pdev, bar));
134 }
135 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
136 #endif
137
138 #if 0
139 /**
140 * pci_max_busnr - returns maximum PCI bus number
141 *
142 * Returns the highest PCI bus number present in the system global list of
143 * PCI buses.
144 */
145 unsigned char __devinit
146 pci_max_busnr(void)
147 {
148 struct pci_bus *bus = NULL;
149 unsigned char max, n;
150
151 max = 0;
152 while ((bus = pci_find_next_bus(bus)) != NULL) {
153 n = pci_bus_max_busnr(bus);
154 if(n > max)
155 max = n;
156 }
157 return max;
158 }
159
160 #endif /* 0 */
161
162 #define PCI_FIND_CAP_TTL 48
163
__pci_find_next_cap_ttl(struct pci_bus * bus,unsigned int devfn,u8 pos,int cap,int * ttl)164 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
165 u8 pos, int cap, int *ttl)
166 {
167 u8 id;
168
169 while ((*ttl)--) {
170 pci_bus_read_config_byte(bus, devfn, pos, &pos);
171 if (pos < 0x40)
172 break;
173 pos &= ~3;
174 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
175 &id);
176 if (id == 0xff)
177 break;
178 if (id == cap)
179 return pos;
180 pos += PCI_CAP_LIST_NEXT;
181 }
182 return 0;
183 }
184
__pci_find_next_cap(struct pci_bus * bus,unsigned int devfn,u8 pos,int cap)185 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
186 u8 pos, int cap)
187 {
188 int ttl = PCI_FIND_CAP_TTL;
189
190 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
191 }
192
pci_find_next_capability(struct pci_dev * dev,u8 pos,int cap)193 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
194 {
195 return __pci_find_next_cap(dev->bus, dev->devfn,
196 pos + PCI_CAP_LIST_NEXT, cap);
197 }
198 EXPORT_SYMBOL_GPL(pci_find_next_capability);
199
__pci_bus_find_cap_start(struct pci_bus * bus,unsigned int devfn,u8 hdr_type)200 static int __pci_bus_find_cap_start(struct pci_bus *bus,
201 unsigned int devfn, u8 hdr_type)
202 {
203 u16 status;
204
205 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
206 if (!(status & PCI_STATUS_CAP_LIST))
207 return 0;
208
209 switch (hdr_type) {
210 case PCI_HEADER_TYPE_NORMAL:
211 case PCI_HEADER_TYPE_BRIDGE:
212 return PCI_CAPABILITY_LIST;
213 case PCI_HEADER_TYPE_CARDBUS:
214 return PCI_CB_CAPABILITY_LIST;
215 default:
216 return 0;
217 }
218
219 return 0;
220 }
221
222 /**
223 * pci_find_capability - query for devices' capabilities
224 * @dev: PCI device to query
225 * @cap: capability code
226 *
227 * Tell if a device supports a given PCI capability.
228 * Returns the address of the requested capability structure within the
229 * device's PCI configuration space or 0 in case the device does not
230 * support it. Possible values for @cap:
231 *
232 * %PCI_CAP_ID_PM Power Management
233 * %PCI_CAP_ID_AGP Accelerated Graphics Port
234 * %PCI_CAP_ID_VPD Vital Product Data
235 * %PCI_CAP_ID_SLOTID Slot Identification
236 * %PCI_CAP_ID_MSI Message Signalled Interrupts
237 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
238 * %PCI_CAP_ID_PCIX PCI-X
239 * %PCI_CAP_ID_EXP PCI Express
240 */
pci_find_capability(struct pci_dev * dev,int cap)241 int pci_find_capability(struct pci_dev *dev, int cap)
242 {
243 int pos;
244
245 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
246 if (pos)
247 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
248
249 return pos;
250 }
251
252 /**
253 * pci_bus_find_capability - query for devices' capabilities
254 * @bus: the PCI bus to query
255 * @devfn: PCI device to query
256 * @cap: capability code
257 *
258 * Like pci_find_capability() but works for pci devices that do not have a
259 * pci_dev structure set up yet.
260 *
261 * Returns the address of the requested capability structure within the
262 * device's PCI configuration space or 0 in case the device does not
263 * support it.
264 */
pci_bus_find_capability(struct pci_bus * bus,unsigned int devfn,int cap)265 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
266 {
267 int pos;
268 u8 hdr_type;
269
270 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
271
272 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
273 if (pos)
274 pos = __pci_find_next_cap(bus, devfn, pos, cap);
275
276 return pos;
277 }
278
279 /**
280 * pci_find_ext_capability - Find an extended capability
281 * @dev: PCI device to query
282 * @cap: capability code
283 *
284 * Returns the address of the requested extended capability structure
285 * within the device's PCI configuration space or 0 if the device does
286 * not support it. Possible values for @cap:
287 *
288 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
289 * %PCI_EXT_CAP_ID_VC Virtual Channel
290 * %PCI_EXT_CAP_ID_DSN Device Serial Number
291 * %PCI_EXT_CAP_ID_PWR Power Budgeting
292 */
pci_find_ext_capability(struct pci_dev * dev,int cap)293 int pci_find_ext_capability(struct pci_dev *dev, int cap)
294 {
295 u32 header;
296 int ttl;
297 int pos = PCI_CFG_SPACE_SIZE;
298
299 /* minimum 8 bytes per capability */
300 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
301
302 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
303 return 0;
304
305 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
306 return 0;
307
308 /*
309 * If we have no capabilities, this is indicated by cap ID,
310 * cap version and next pointer all being 0.
311 */
312 if (header == 0)
313 return 0;
314
315 while (ttl-- > 0) {
316 if (PCI_EXT_CAP_ID(header) == cap)
317 return pos;
318
319 pos = PCI_EXT_CAP_NEXT(header);
320 if (pos < PCI_CFG_SPACE_SIZE)
321 break;
322
323 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
324 break;
325 }
326
327 return 0;
328 }
329 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
330
331 /**
332 * pci_bus_find_ext_capability - find an extended capability
333 * @bus: the PCI bus to query
334 * @devfn: PCI device to query
335 * @cap: capability code
336 *
337 * Like pci_find_ext_capability() but works for pci devices that do not have a
338 * pci_dev structure set up yet.
339 *
340 * Returns the address of the requested capability structure within the
341 * device's PCI configuration space or 0 in case the device does not
342 * support it.
343 */
pci_bus_find_ext_capability(struct pci_bus * bus,unsigned int devfn,int cap)344 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
345 int cap)
346 {
347 u32 header;
348 int ttl;
349 int pos = PCI_CFG_SPACE_SIZE;
350
351 /* minimum 8 bytes per capability */
352 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
353
354 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
355 return 0;
356 if (header == 0xffffffff || header == 0)
357 return 0;
358
359 while (ttl-- > 0) {
360 if (PCI_EXT_CAP_ID(header) == cap)
361 return pos;
362
363 pos = PCI_EXT_CAP_NEXT(header);
364 if (pos < PCI_CFG_SPACE_SIZE)
365 break;
366
367 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
368 break;
369 }
370
371 return 0;
372 }
373
__pci_find_next_ht_cap(struct pci_dev * dev,int pos,int ht_cap)374 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
375 {
376 int rc, ttl = PCI_FIND_CAP_TTL;
377 u8 cap, mask;
378
379 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
380 mask = HT_3BIT_CAP_MASK;
381 else
382 mask = HT_5BIT_CAP_MASK;
383
384 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
385 PCI_CAP_ID_HT, &ttl);
386 while (pos) {
387 rc = pci_read_config_byte(dev, pos + 3, &cap);
388 if (rc != PCIBIOS_SUCCESSFUL)
389 return 0;
390
391 if ((cap & mask) == ht_cap)
392 return pos;
393
394 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
395 pos + PCI_CAP_LIST_NEXT,
396 PCI_CAP_ID_HT, &ttl);
397 }
398
399 return 0;
400 }
401 /**
402 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
403 * @dev: PCI device to query
404 * @pos: Position from which to continue searching
405 * @ht_cap: Hypertransport capability code
406 *
407 * To be used in conjunction with pci_find_ht_capability() to search for
408 * all capabilities matching @ht_cap. @pos should always be a value returned
409 * from pci_find_ht_capability().
410 *
411 * NB. To be 100% safe against broken PCI devices, the caller should take
412 * steps to avoid an infinite loop.
413 */
pci_find_next_ht_capability(struct pci_dev * dev,int pos,int ht_cap)414 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
415 {
416 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
417 }
418 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
419
420 /**
421 * pci_find_ht_capability - query a device's Hypertransport capabilities
422 * @dev: PCI device to query
423 * @ht_cap: Hypertransport capability code
424 *
425 * Tell if a device supports a given Hypertransport capability.
426 * Returns an address within the device's PCI configuration space
427 * or 0 in case the device does not support the request capability.
428 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
429 * which has a Hypertransport capability matching @ht_cap.
430 */
pci_find_ht_capability(struct pci_dev * dev,int ht_cap)431 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
432 {
433 int pos;
434
435 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
436 if (pos)
437 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
438
439 return pos;
440 }
441 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
442
443 /**
444 * pci_find_parent_resource - return resource region of parent bus of given region
445 * @dev: PCI device structure contains resources to be searched
446 * @res: child resource record for which parent is sought
447 *
448 * For given resource region of given device, return the resource
449 * region of parent bus the given region is contained in or where
450 * it should be allocated from.
451 */
452 struct resource *
pci_find_parent_resource(const struct pci_dev * dev,struct resource * res)453 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
454 {
455 const struct pci_bus *bus = dev->bus;
456 int i;
457 struct resource *best = NULL, *r;
458
459 pci_bus_for_each_resource(bus, r, i) {
460 if (!r)
461 continue;
462 if (res->start && !(res->start >= r->start && res->end <= r->end))
463 continue; /* Not contained */
464 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
465 continue; /* Wrong type */
466 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
467 return r; /* Exact match */
468 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
469 if (r->flags & IORESOURCE_PREFETCH)
470 continue;
471 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
472 if (!best)
473 best = r;
474 }
475 return best;
476 }
477
478 /**
479 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
480 * @dev: PCI device to have its BARs restored
481 *
482 * Restore the BAR values for a given device, so as to make it
483 * accessible by its driver.
484 */
485 static void
pci_restore_bars(struct pci_dev * dev)486 pci_restore_bars(struct pci_dev *dev)
487 {
488 int i;
489
490 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
491 pci_update_resource(dev, i);
492 }
493
494 static struct pci_platform_pm_ops *pci_platform_pm;
495
pci_set_platform_pm(struct pci_platform_pm_ops * ops)496 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
497 {
498 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
499 || !ops->sleep_wake || !ops->can_wakeup)
500 return -EINVAL;
501 pci_platform_pm = ops;
502 return 0;
503 }
504
platform_pci_power_manageable(struct pci_dev * dev)505 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
506 {
507 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
508 }
509
platform_pci_set_power_state(struct pci_dev * dev,pci_power_t t)510 static inline int platform_pci_set_power_state(struct pci_dev *dev,
511 pci_power_t t)
512 {
513 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
514 }
515
platform_pci_choose_state(struct pci_dev * dev)516 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
517 {
518 return pci_platform_pm ?
519 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
520 }
521
platform_pci_can_wakeup(struct pci_dev * dev)522 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
523 {
524 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
525 }
526
platform_pci_sleep_wake(struct pci_dev * dev,bool enable)527 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
528 {
529 return pci_platform_pm ?
530 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
531 }
532
platform_pci_run_wake(struct pci_dev * dev,bool enable)533 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
534 {
535 return pci_platform_pm ?
536 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
537 }
538
539 /**
540 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
541 * given PCI device
542 * @dev: PCI device to handle.
543 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
544 *
545 * RETURN VALUE:
546 * -EINVAL if the requested state is invalid.
547 * -EIO if device does not support PCI PM or its PM capabilities register has a
548 * wrong version, or device doesn't support the requested state.
549 * 0 if device already is in the requested state.
550 * 0 if device's power state has been successfully changed.
551 */
pci_raw_set_power_state(struct pci_dev * dev,pci_power_t state)552 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
553 {
554 u16 pmcsr;
555 bool need_restore = false;
556
557 /* Check if we're already there */
558 if (dev->current_state == state)
559 return 0;
560
561 if (!dev->pm_cap)
562 return -EIO;
563
564 if (state < PCI_D0 || state > PCI_D3hot)
565 return -EINVAL;
566
567 /* Validate current state:
568 * Can enter D0 from any state, but if we can only go deeper
569 * to sleep if we're already in a low power state
570 */
571 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
572 && dev->current_state > state) {
573 dev_err(&dev->dev, "invalid power transition "
574 "(from state %d to %d)\n", dev->current_state, state);
575 return -EINVAL;
576 }
577
578 /* check if this device supports the desired state */
579 if ((state == PCI_D1 && !dev->d1_support)
580 || (state == PCI_D2 && !dev->d2_support))
581 return -EIO;
582
583 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
584
585 /* If we're (effectively) in D3, force entire word to 0.
586 * This doesn't affect PME_Status, disables PME_En, and
587 * sets PowerState to 0.
588 */
589 switch (dev->current_state) {
590 case PCI_D0:
591 case PCI_D1:
592 case PCI_D2:
593 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
594 pmcsr |= state;
595 break;
596 case PCI_D3hot:
597 case PCI_D3cold:
598 case PCI_UNKNOWN: /* Boot-up */
599 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
600 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
601 need_restore = true;
602 /* Fall-through: force to D0 */
603 default:
604 pmcsr = 0;
605 break;
606 }
607
608 /* enter specified state */
609 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
610
611 /* Mandatory power management transition delays */
612 /* see PCI PM 1.1 5.6.1 table 18 */
613 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
614 pci_dev_d3_sleep(dev);
615 else if (state == PCI_D2 || dev->current_state == PCI_D2)
616 udelay(PCI_PM_D2_DELAY);
617
618 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
619 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
620 if (dev->current_state != state && printk_ratelimit())
621 dev_info(&dev->dev, "Refused to change power state, "
622 "currently in D%d\n", dev->current_state);
623
624 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
625 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
626 * from D3hot to D0 _may_ perform an internal reset, thereby
627 * going to "D0 Uninitialized" rather than "D0 Initialized".
628 * For example, at least some versions of the 3c905B and the
629 * 3c556B exhibit this behaviour.
630 *
631 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
632 * devices in a D3hot state at boot. Consequently, we need to
633 * restore at least the BARs so that the device will be
634 * accessible to its driver.
635 */
636 if (need_restore)
637 pci_restore_bars(dev);
638
639 if (dev->bus->self)
640 pcie_aspm_pm_state_change(dev->bus->self);
641
642 return 0;
643 }
644
645 /**
646 * pci_update_current_state - Read PCI power state of given device from its
647 * PCI PM registers and cache it
648 * @dev: PCI device to handle.
649 * @state: State to cache in case the device doesn't have the PM capability
650 */
pci_update_current_state(struct pci_dev * dev,pci_power_t state)651 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
652 {
653 if (dev->pm_cap) {
654 u16 pmcsr;
655
656 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
657 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
658 } else {
659 dev->current_state = state;
660 }
661 }
662
663 /**
664 * pci_platform_power_transition - Use platform to change device power state
665 * @dev: PCI device to handle.
666 * @state: State to put the device into.
667 */
pci_platform_power_transition(struct pci_dev * dev,pci_power_t state)668 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
669 {
670 int error;
671
672 if (platform_pci_power_manageable(dev)) {
673 error = platform_pci_set_power_state(dev, state);
674 if (!error)
675 pci_update_current_state(dev, state);
676 } else
677 error = -ENODEV;
678
679 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
680 dev->current_state = PCI_D0;
681
682 return error;
683 }
684
685 /**
686 * __pci_start_power_transition - Start power transition of a PCI device
687 * @dev: PCI device to handle.
688 * @state: State to put the device into.
689 */
__pci_start_power_transition(struct pci_dev * dev,pci_power_t state)690 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
691 {
692 if (state == PCI_D0)
693 pci_platform_power_transition(dev, PCI_D0);
694 }
695
696 /**
697 * __pci_complete_power_transition - Complete power transition of a PCI device
698 * @dev: PCI device to handle.
699 * @state: State to put the device into.
700 *
701 * This function should not be called directly by device drivers.
702 */
__pci_complete_power_transition(struct pci_dev * dev,pci_power_t state)703 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
704 {
705 return state >= PCI_D0 ?
706 pci_platform_power_transition(dev, state) : -EINVAL;
707 }
708 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
709
710 /**
711 * pci_set_power_state - Set the power state of a PCI device
712 * @dev: PCI device to handle.
713 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
714 *
715 * Transition a device to a new power state, using the platform firmware and/or
716 * the device's PCI PM registers.
717 *
718 * RETURN VALUE:
719 * -EINVAL if the requested state is invalid.
720 * -EIO if device does not support PCI PM or its PM capabilities register has a
721 * wrong version, or device doesn't support the requested state.
722 * 0 if device already is in the requested state.
723 * 0 if device's power state has been successfully changed.
724 */
pci_set_power_state(struct pci_dev * dev,pci_power_t state)725 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
726 {
727 int error;
728
729 /* bound the state we're entering */
730 if (state > PCI_D3hot)
731 state = PCI_D3hot;
732 else if (state < PCI_D0)
733 state = PCI_D0;
734 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
735 /*
736 * If the device or the parent bridge do not support PCI PM,
737 * ignore the request if we're doing anything other than putting
738 * it into D0 (which would only happen on boot).
739 */
740 return 0;
741
742 __pci_start_power_transition(dev, state);
743
744 /* This device is quirked not to be put into D3, so
745 don't put it in D3 */
746 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
747 return 0;
748
749 error = pci_raw_set_power_state(dev, state);
750
751 if (!__pci_complete_power_transition(dev, state))
752 error = 0;
753 /*
754 * When aspm_policy is "powersave" this call ensures
755 * that ASPM is configured.
756 */
757 if (!error && dev->bus->self)
758 pcie_aspm_powersave_config_link(dev->bus->self);
759
760 return error;
761 }
762
763 /**
764 * pci_choose_state - Choose the power state of a PCI device
765 * @dev: PCI device to be suspended
766 * @state: target sleep state for the whole system. This is the value
767 * that is passed to suspend() function.
768 *
769 * Returns PCI power state suitable for given device and given system
770 * message.
771 */
772
pci_choose_state(struct pci_dev * dev,pm_message_t state)773 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
774 {
775 pci_power_t ret;
776
777 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
778 return PCI_D0;
779
780 ret = platform_pci_choose_state(dev);
781 if (ret != PCI_POWER_ERROR)
782 return ret;
783
784 switch (state.event) {
785 case PM_EVENT_ON:
786 return PCI_D0;
787 case PM_EVENT_FREEZE:
788 case PM_EVENT_PRETHAW:
789 /* REVISIT both freeze and pre-thaw "should" use D0 */
790 case PM_EVENT_SUSPEND:
791 case PM_EVENT_HIBERNATE:
792 return PCI_D3hot;
793 default:
794 dev_info(&dev->dev, "unrecognized suspend event %d\n",
795 state.event);
796 BUG();
797 }
798 return PCI_D0;
799 }
800
801 EXPORT_SYMBOL(pci_choose_state);
802
803 #define PCI_EXP_SAVE_REGS 7
804
805 #define pcie_cap_has_devctl(type, flags) 1
806 #define pcie_cap_has_lnkctl(type, flags) \
807 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
808 (type == PCI_EXP_TYPE_ROOT_PORT || \
809 type == PCI_EXP_TYPE_ENDPOINT || \
810 type == PCI_EXP_TYPE_LEG_END))
811 #define pcie_cap_has_sltctl(type, flags) \
812 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
813 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
814 (type == PCI_EXP_TYPE_DOWNSTREAM && \
815 (flags & PCI_EXP_FLAGS_SLOT))))
816 #define pcie_cap_has_rtctl(type, flags) \
817 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
818 (type == PCI_EXP_TYPE_ROOT_PORT || \
819 type == PCI_EXP_TYPE_RC_EC))
820 #define pcie_cap_has_devctl2(type, flags) \
821 ((flags & PCI_EXP_FLAGS_VERS) > 1)
822 #define pcie_cap_has_lnkctl2(type, flags) \
823 ((flags & PCI_EXP_FLAGS_VERS) > 1)
824 #define pcie_cap_has_sltctl2(type, flags) \
825 ((flags & PCI_EXP_FLAGS_VERS) > 1)
826
pci_find_saved_cap(struct pci_dev * pci_dev,char cap)827 static struct pci_cap_saved_state *pci_find_saved_cap(
828 struct pci_dev *pci_dev, char cap)
829 {
830 struct pci_cap_saved_state *tmp;
831 struct hlist_node *pos;
832
833 hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
834 if (tmp->cap.cap_nr == cap)
835 return tmp;
836 }
837 return NULL;
838 }
839
pci_save_pcie_state(struct pci_dev * dev)840 static int pci_save_pcie_state(struct pci_dev *dev)
841 {
842 int pos, i = 0;
843 struct pci_cap_saved_state *save_state;
844 u16 *cap;
845 u16 flags;
846
847 pos = pci_pcie_cap(dev);
848 if (!pos)
849 return 0;
850
851 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
852 if (!save_state) {
853 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
854 return -ENOMEM;
855 }
856 cap = (u16 *)&save_state->cap.data[0];
857
858 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
859
860 if (pcie_cap_has_devctl(dev->pcie_type, flags))
861 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
862 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
863 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
864 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
865 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
866 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
867 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
868 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
869 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
870 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
871 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
872 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
873 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
874
875 return 0;
876 }
877
pci_restore_pcie_state(struct pci_dev * dev)878 static void pci_restore_pcie_state(struct pci_dev *dev)
879 {
880 int i = 0, pos;
881 struct pci_cap_saved_state *save_state;
882 u16 *cap;
883 u16 flags;
884
885 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
886 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
887 if (!save_state || pos <= 0)
888 return;
889 cap = (u16 *)&save_state->cap.data[0];
890
891 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
892
893 if (pcie_cap_has_devctl(dev->pcie_type, flags))
894 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
895 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
896 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
897 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
898 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
899 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
900 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
901 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
902 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
903 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
904 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
905 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
906 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
907 }
908
909
pci_save_pcix_state(struct pci_dev * dev)910 static int pci_save_pcix_state(struct pci_dev *dev)
911 {
912 int pos;
913 struct pci_cap_saved_state *save_state;
914
915 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
916 if (pos <= 0)
917 return 0;
918
919 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
920 if (!save_state) {
921 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
922 return -ENOMEM;
923 }
924
925 pci_read_config_word(dev, pos + PCI_X_CMD,
926 (u16 *)save_state->cap.data);
927
928 return 0;
929 }
930
pci_restore_pcix_state(struct pci_dev * dev)931 static void pci_restore_pcix_state(struct pci_dev *dev)
932 {
933 int i = 0, pos;
934 struct pci_cap_saved_state *save_state;
935 u16 *cap;
936
937 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
938 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
939 if (!save_state || pos <= 0)
940 return;
941 cap = (u16 *)&save_state->cap.data[0];
942
943 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
944 }
945
946
947 /**
948 * pci_save_state - save the PCI configuration space of a device before suspending
949 * @dev: - PCI device that we're dealing with
950 */
951 int
pci_save_state(struct pci_dev * dev)952 pci_save_state(struct pci_dev *dev)
953 {
954 int i;
955 /* XXX: 100% dword access ok here? */
956 for (i = 0; i < 16; i++)
957 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
958 dev->state_saved = true;
959 if ((i = pci_save_pcie_state(dev)) != 0)
960 return i;
961 if ((i = pci_save_pcix_state(dev)) != 0)
962 return i;
963 return 0;
964 }
965
pci_restore_config_dword(struct pci_dev * pdev,int offset,u32 saved_val,int retry)966 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
967 u32 saved_val, int retry)
968 {
969 u32 val;
970
971 pci_read_config_dword(pdev, offset, &val);
972 if (val == saved_val)
973 return;
974
975 for (;;) {
976 dev_dbg(&pdev->dev, "restoring config space at offset "
977 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
978 pci_write_config_dword(pdev, offset, saved_val);
979 if (retry-- <= 0)
980 return;
981
982 pci_read_config_dword(pdev, offset, &val);
983 if (val == saved_val)
984 return;
985
986 mdelay(1);
987 }
988 }
989
pci_restore_config_space_range(struct pci_dev * pdev,int start,int end,int retry)990 static void pci_restore_config_space_range(struct pci_dev *pdev,
991 int start, int end, int retry)
992 {
993 int index;
994
995 for (index = end; index >= start; index--)
996 pci_restore_config_dword(pdev, 4 * index,
997 pdev->saved_config_space[index],
998 retry);
999 }
1000
pci_restore_config_space(struct pci_dev * pdev)1001 static void pci_restore_config_space(struct pci_dev *pdev)
1002 {
1003 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1004 pci_restore_config_space_range(pdev, 10, 15, 0);
1005 /* Restore BARs before the command register. */
1006 pci_restore_config_space_range(pdev, 4, 9, 10);
1007 pci_restore_config_space_range(pdev, 0, 3, 0);
1008 } else {
1009 pci_restore_config_space_range(pdev, 0, 15, 0);
1010 }
1011 }
1012
1013 /**
1014 * pci_restore_state - Restore the saved state of a PCI device
1015 * @dev: - PCI device that we're dealing with
1016 */
pci_restore_state(struct pci_dev * dev)1017 void pci_restore_state(struct pci_dev *dev)
1018 {
1019 if (!dev->state_saved)
1020 return;
1021
1022 /* PCI Express register must be restored first */
1023 pci_restore_pcie_state(dev);
1024 pci_restore_ats_state(dev);
1025
1026 pci_restore_config_space(dev);
1027
1028 pci_restore_pcix_state(dev);
1029 pci_restore_msi_state(dev);
1030 pci_restore_iov_state(dev);
1031
1032 dev->state_saved = false;
1033 }
1034
1035 struct pci_saved_state {
1036 u32 config_space[16];
1037 struct pci_cap_saved_data cap[0];
1038 };
1039
1040 /**
1041 * pci_store_saved_state - Allocate and return an opaque struct containing
1042 * the device saved state.
1043 * @dev: PCI device that we're dealing with
1044 *
1045 * Rerturn NULL if no state or error.
1046 */
pci_store_saved_state(struct pci_dev * dev)1047 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1048 {
1049 struct pci_saved_state *state;
1050 struct pci_cap_saved_state *tmp;
1051 struct pci_cap_saved_data *cap;
1052 struct hlist_node *pos;
1053 size_t size;
1054
1055 if (!dev->state_saved)
1056 return NULL;
1057
1058 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1059
1060 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
1061 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1062
1063 state = kzalloc(size, GFP_KERNEL);
1064 if (!state)
1065 return NULL;
1066
1067 memcpy(state->config_space, dev->saved_config_space,
1068 sizeof(state->config_space));
1069
1070 cap = state->cap;
1071 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
1072 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1073 memcpy(cap, &tmp->cap, len);
1074 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1075 }
1076 /* Empty cap_save terminates list */
1077
1078 return state;
1079 }
1080 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1081
1082 /**
1083 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1084 * @dev: PCI device that we're dealing with
1085 * @state: Saved state returned from pci_store_saved_state()
1086 */
pci_load_saved_state(struct pci_dev * dev,struct pci_saved_state * state)1087 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1088 {
1089 struct pci_cap_saved_data *cap;
1090
1091 dev->state_saved = false;
1092
1093 if (!state)
1094 return 0;
1095
1096 memcpy(dev->saved_config_space, state->config_space,
1097 sizeof(state->config_space));
1098
1099 cap = state->cap;
1100 while (cap->size) {
1101 struct pci_cap_saved_state *tmp;
1102
1103 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1104 if (!tmp || tmp->cap.size != cap->size)
1105 return -EINVAL;
1106
1107 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1108 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1109 sizeof(struct pci_cap_saved_data) + cap->size);
1110 }
1111
1112 dev->state_saved = true;
1113 return 0;
1114 }
1115 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1116
1117 /**
1118 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1119 * and free the memory allocated for it.
1120 * @dev: PCI device that we're dealing with
1121 * @state: Pointer to saved state returned from pci_store_saved_state()
1122 */
pci_load_and_free_saved_state(struct pci_dev * dev,struct pci_saved_state ** state)1123 int pci_load_and_free_saved_state(struct pci_dev *dev,
1124 struct pci_saved_state **state)
1125 {
1126 int ret = pci_load_saved_state(dev, *state);
1127 kfree(*state);
1128 *state = NULL;
1129 return ret;
1130 }
1131 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1132
do_pci_enable_device(struct pci_dev * dev,int bars)1133 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1134 {
1135 int err;
1136
1137 err = pci_set_power_state(dev, PCI_D0);
1138 if (err < 0 && err != -EIO)
1139 return err;
1140 err = pcibios_enable_device(dev, bars);
1141 if (err < 0)
1142 return err;
1143 pci_fixup_device(pci_fixup_enable, dev);
1144
1145 return 0;
1146 }
1147
1148 /**
1149 * pci_reenable_device - Resume abandoned device
1150 * @dev: PCI device to be resumed
1151 *
1152 * Note this function is a backend of pci_default_resume and is not supposed
1153 * to be called by normal code, write proper resume handler and use it instead.
1154 */
pci_reenable_device(struct pci_dev * dev)1155 int pci_reenable_device(struct pci_dev *dev)
1156 {
1157 if (pci_is_enabled(dev))
1158 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1159 return 0;
1160 }
1161
__pci_enable_device_flags(struct pci_dev * dev,resource_size_t flags)1162 static int __pci_enable_device_flags(struct pci_dev *dev,
1163 resource_size_t flags)
1164 {
1165 int err;
1166 int i, bars = 0;
1167
1168 /*
1169 * Power state could be unknown at this point, either due to a fresh
1170 * boot or a device removal call. So get the current power state
1171 * so that things like MSI message writing will behave as expected
1172 * (e.g. if the device really is in D0 at enable time).
1173 */
1174 if (dev->pm_cap) {
1175 u16 pmcsr;
1176 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1177 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1178 }
1179
1180 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1181 return 0; /* already enabled */
1182
1183 /* only skip sriov related */
1184 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1185 if (dev->resource[i].flags & flags)
1186 bars |= (1 << i);
1187 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1188 if (dev->resource[i].flags & flags)
1189 bars |= (1 << i);
1190
1191 err = do_pci_enable_device(dev, bars);
1192 if (err < 0)
1193 atomic_dec(&dev->enable_cnt);
1194 return err;
1195 }
1196
1197 /**
1198 * pci_enable_device_io - Initialize a device for use with IO space
1199 * @dev: PCI device to be initialized
1200 *
1201 * Initialize device before it's used by a driver. Ask low-level code
1202 * to enable I/O resources. Wake up the device if it was suspended.
1203 * Beware, this function can fail.
1204 */
pci_enable_device_io(struct pci_dev * dev)1205 int pci_enable_device_io(struct pci_dev *dev)
1206 {
1207 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1208 }
1209
1210 /**
1211 * pci_enable_device_mem - Initialize a device for use with Memory space
1212 * @dev: PCI device to be initialized
1213 *
1214 * Initialize device before it's used by a driver. Ask low-level code
1215 * to enable Memory resources. Wake up the device if it was suspended.
1216 * Beware, this function can fail.
1217 */
pci_enable_device_mem(struct pci_dev * dev)1218 int pci_enable_device_mem(struct pci_dev *dev)
1219 {
1220 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1221 }
1222
1223 /**
1224 * pci_enable_device - Initialize device before it's used by a driver.
1225 * @dev: PCI device to be initialized
1226 *
1227 * Initialize device before it's used by a driver. Ask low-level code
1228 * to enable I/O and memory. Wake up the device if it was suspended.
1229 * Beware, this function can fail.
1230 *
1231 * Note we don't actually enable the device many times if we call
1232 * this function repeatedly (we just increment the count).
1233 */
pci_enable_device(struct pci_dev * dev)1234 int pci_enable_device(struct pci_dev *dev)
1235 {
1236 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1237 }
1238
1239 /*
1240 * Managed PCI resources. This manages device on/off, intx/msi/msix
1241 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1242 * there's no need to track it separately. pci_devres is initialized
1243 * when a device is enabled using managed PCI device enable interface.
1244 */
1245 struct pci_devres {
1246 unsigned int enabled:1;
1247 unsigned int pinned:1;
1248 unsigned int orig_intx:1;
1249 unsigned int restore_intx:1;
1250 u32 region_mask;
1251 };
1252
pcim_release(struct device * gendev,void * res)1253 static void pcim_release(struct device *gendev, void *res)
1254 {
1255 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1256 struct pci_devres *this = res;
1257 int i;
1258
1259 if (dev->msi_enabled)
1260 pci_disable_msi(dev);
1261 if (dev->msix_enabled)
1262 pci_disable_msix(dev);
1263
1264 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1265 if (this->region_mask & (1 << i))
1266 pci_release_region(dev, i);
1267
1268 if (this->restore_intx)
1269 pci_intx(dev, this->orig_intx);
1270
1271 if (this->enabled && !this->pinned)
1272 pci_disable_device(dev);
1273 }
1274
get_pci_dr(struct pci_dev * pdev)1275 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1276 {
1277 struct pci_devres *dr, *new_dr;
1278
1279 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1280 if (dr)
1281 return dr;
1282
1283 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1284 if (!new_dr)
1285 return NULL;
1286 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1287 }
1288
find_pci_dr(struct pci_dev * pdev)1289 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1290 {
1291 if (pci_is_managed(pdev))
1292 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1293 return NULL;
1294 }
1295
1296 /**
1297 * pcim_enable_device - Managed pci_enable_device()
1298 * @pdev: PCI device to be initialized
1299 *
1300 * Managed pci_enable_device().
1301 */
pcim_enable_device(struct pci_dev * pdev)1302 int pcim_enable_device(struct pci_dev *pdev)
1303 {
1304 struct pci_devres *dr;
1305 int rc;
1306
1307 dr = get_pci_dr(pdev);
1308 if (unlikely(!dr))
1309 return -ENOMEM;
1310 if (dr->enabled)
1311 return 0;
1312
1313 rc = pci_enable_device(pdev);
1314 if (!rc) {
1315 pdev->is_managed = 1;
1316 dr->enabled = 1;
1317 }
1318 return rc;
1319 }
1320
1321 /**
1322 * pcim_pin_device - Pin managed PCI device
1323 * @pdev: PCI device to pin
1324 *
1325 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1326 * driver detach. @pdev must have been enabled with
1327 * pcim_enable_device().
1328 */
pcim_pin_device(struct pci_dev * pdev)1329 void pcim_pin_device(struct pci_dev *pdev)
1330 {
1331 struct pci_devres *dr;
1332
1333 dr = find_pci_dr(pdev);
1334 WARN_ON(!dr || !dr->enabled);
1335 if (dr)
1336 dr->pinned = 1;
1337 }
1338
1339 /**
1340 * pcibios_disable_device - disable arch specific PCI resources for device dev
1341 * @dev: the PCI device to disable
1342 *
1343 * Disables architecture specific PCI resources for the device. This
1344 * is the default implementation. Architecture implementations can
1345 * override this.
1346 */
pcibios_disable_device(struct pci_dev * dev)1347 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1348
do_pci_disable_device(struct pci_dev * dev)1349 static void do_pci_disable_device(struct pci_dev *dev)
1350 {
1351 u16 pci_command;
1352
1353 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1354 if (pci_command & PCI_COMMAND_MASTER) {
1355 pci_command &= ~PCI_COMMAND_MASTER;
1356 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1357 }
1358
1359 pcibios_disable_device(dev);
1360 }
1361
1362 /**
1363 * pci_disable_enabled_device - Disable device without updating enable_cnt
1364 * @dev: PCI device to disable
1365 *
1366 * NOTE: This function is a backend of PCI power management routines and is
1367 * not supposed to be called drivers.
1368 */
pci_disable_enabled_device(struct pci_dev * dev)1369 void pci_disable_enabled_device(struct pci_dev *dev)
1370 {
1371 if (pci_is_enabled(dev))
1372 do_pci_disable_device(dev);
1373 }
1374
1375 /**
1376 * pci_disable_device - Disable PCI device after use
1377 * @dev: PCI device to be disabled
1378 *
1379 * Signal to the system that the PCI device is not in use by the system
1380 * anymore. This only involves disabling PCI bus-mastering, if active.
1381 *
1382 * Note we don't actually disable the device until all callers of
1383 * pci_enable_device() have called pci_disable_device().
1384 */
1385 void
pci_disable_device(struct pci_dev * dev)1386 pci_disable_device(struct pci_dev *dev)
1387 {
1388 struct pci_devres *dr;
1389
1390 dr = find_pci_dr(dev);
1391 if (dr)
1392 dr->enabled = 0;
1393
1394 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1395 return;
1396
1397 do_pci_disable_device(dev);
1398
1399 dev->is_busmaster = 0;
1400 }
1401
1402 /**
1403 * pcibios_set_pcie_reset_state - set reset state for device dev
1404 * @dev: the PCIe device reset
1405 * @state: Reset state to enter into
1406 *
1407 *
1408 * Sets the PCIe reset state for the device. This is the default
1409 * implementation. Architecture implementations can override this.
1410 */
pcibios_set_pcie_reset_state(struct pci_dev * dev,enum pcie_reset_state state)1411 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1412 enum pcie_reset_state state)
1413 {
1414 return -EINVAL;
1415 }
1416
1417 /**
1418 * pci_set_pcie_reset_state - set reset state for device dev
1419 * @dev: the PCIe device reset
1420 * @state: Reset state to enter into
1421 *
1422 *
1423 * Sets the PCI reset state for the device.
1424 */
pci_set_pcie_reset_state(struct pci_dev * dev,enum pcie_reset_state state)1425 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1426 {
1427 return pcibios_set_pcie_reset_state(dev, state);
1428 }
1429
1430 /**
1431 * pci_check_pme_status - Check if given device has generated PME.
1432 * @dev: Device to check.
1433 *
1434 * Check the PME status of the device and if set, clear it and clear PME enable
1435 * (if set). Return 'true' if PME status and PME enable were both set or
1436 * 'false' otherwise.
1437 */
pci_check_pme_status(struct pci_dev * dev)1438 bool pci_check_pme_status(struct pci_dev *dev)
1439 {
1440 int pmcsr_pos;
1441 u16 pmcsr;
1442 bool ret = false;
1443
1444 if (!dev->pm_cap)
1445 return false;
1446
1447 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1448 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1449 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1450 return false;
1451
1452 /* Clear PME status. */
1453 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1454 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1455 /* Disable PME to avoid interrupt flood. */
1456 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1457 ret = true;
1458 }
1459
1460 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1461
1462 return ret;
1463 }
1464
1465 /**
1466 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1467 * @dev: Device to handle.
1468 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1469 *
1470 * Check if @dev has generated PME and queue a resume request for it in that
1471 * case.
1472 */
pci_pme_wakeup(struct pci_dev * dev,void * pme_poll_reset)1473 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1474 {
1475 if (pme_poll_reset && dev->pme_poll)
1476 dev->pme_poll = false;
1477
1478 if (pci_check_pme_status(dev)) {
1479 pci_wakeup_event(dev);
1480 pm_request_resume(&dev->dev);
1481 }
1482 return 0;
1483 }
1484
1485 /**
1486 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1487 * @bus: Top bus of the subtree to walk.
1488 */
pci_pme_wakeup_bus(struct pci_bus * bus)1489 void pci_pme_wakeup_bus(struct pci_bus *bus)
1490 {
1491 if (bus)
1492 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1493 }
1494
1495 /**
1496 * pci_pme_capable - check the capability of PCI device to generate PME#
1497 * @dev: PCI device to handle.
1498 * @state: PCI state from which device will issue PME#.
1499 */
pci_pme_capable(struct pci_dev * dev,pci_power_t state)1500 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1501 {
1502 if (!dev->pm_cap)
1503 return false;
1504
1505 return !!(dev->pme_support & (1 << state));
1506 }
1507
pci_pme_list_scan(struct work_struct * work)1508 static void pci_pme_list_scan(struct work_struct *work)
1509 {
1510 struct pci_pme_device *pme_dev, *n;
1511
1512 mutex_lock(&pci_pme_list_mutex);
1513 if (!list_empty(&pci_pme_list)) {
1514 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1515 if (pme_dev->dev->pme_poll) {
1516 pci_pme_wakeup(pme_dev->dev, NULL);
1517 } else {
1518 list_del(&pme_dev->list);
1519 kfree(pme_dev);
1520 }
1521 }
1522 if (!list_empty(&pci_pme_list))
1523 schedule_delayed_work(&pci_pme_work,
1524 msecs_to_jiffies(PME_TIMEOUT));
1525 }
1526 mutex_unlock(&pci_pme_list_mutex);
1527 }
1528
1529 /**
1530 * pci_pme_active - enable or disable PCI device's PME# function
1531 * @dev: PCI device to handle.
1532 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1533 *
1534 * The caller must verify that the device is capable of generating PME# before
1535 * calling this function with @enable equal to 'true'.
1536 */
pci_pme_active(struct pci_dev * dev,bool enable)1537 void pci_pme_active(struct pci_dev *dev, bool enable)
1538 {
1539 u16 pmcsr;
1540
1541 if (!dev->pm_cap)
1542 return;
1543
1544 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1545 /* Clear PME_Status by writing 1 to it and enable PME# */
1546 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1547 if (!enable)
1548 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1549
1550 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1551
1552 /* PCI (as opposed to PCIe) PME requires that the device have
1553 its PME# line hooked up correctly. Not all hardware vendors
1554 do this, so the PME never gets delivered and the device
1555 remains asleep. The easiest way around this is to
1556 periodically walk the list of suspended devices and check
1557 whether any have their PME flag set. The assumption is that
1558 we'll wake up often enough anyway that this won't be a huge
1559 hit, and the power savings from the devices will still be a
1560 win. */
1561
1562 if (dev->pme_poll) {
1563 struct pci_pme_device *pme_dev;
1564 if (enable) {
1565 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1566 GFP_KERNEL);
1567 if (!pme_dev)
1568 goto out;
1569 pme_dev->dev = dev;
1570 mutex_lock(&pci_pme_list_mutex);
1571 list_add(&pme_dev->list, &pci_pme_list);
1572 if (list_is_singular(&pci_pme_list))
1573 schedule_delayed_work(&pci_pme_work,
1574 msecs_to_jiffies(PME_TIMEOUT));
1575 mutex_unlock(&pci_pme_list_mutex);
1576 } else {
1577 mutex_lock(&pci_pme_list_mutex);
1578 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1579 if (pme_dev->dev == dev) {
1580 list_del(&pme_dev->list);
1581 kfree(pme_dev);
1582 break;
1583 }
1584 }
1585 mutex_unlock(&pci_pme_list_mutex);
1586 }
1587 }
1588
1589 out:
1590 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1591 }
1592
1593 /**
1594 * __pci_enable_wake - enable PCI device as wakeup event source
1595 * @dev: PCI device affected
1596 * @state: PCI state from which device will issue wakeup events
1597 * @runtime: True if the events are to be generated at run time
1598 * @enable: True to enable event generation; false to disable
1599 *
1600 * This enables the device as a wakeup event source, or disables it.
1601 * When such events involves platform-specific hooks, those hooks are
1602 * called automatically by this routine.
1603 *
1604 * Devices with legacy power management (no standard PCI PM capabilities)
1605 * always require such platform hooks.
1606 *
1607 * RETURN VALUE:
1608 * 0 is returned on success
1609 * -EINVAL is returned if device is not supposed to wake up the system
1610 * Error code depending on the platform is returned if both the platform and
1611 * the native mechanism fail to enable the generation of wake-up events
1612 */
__pci_enable_wake(struct pci_dev * dev,pci_power_t state,bool runtime,bool enable)1613 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1614 bool runtime, bool enable)
1615 {
1616 int ret = 0;
1617
1618 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1619 return -EINVAL;
1620
1621 /* Don't do the same thing twice in a row for one device. */
1622 if (!!enable == !!dev->wakeup_prepared)
1623 return 0;
1624
1625 /*
1626 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1627 * Anderson we should be doing PME# wake enable followed by ACPI wake
1628 * enable. To disable wake-up we call the platform first, for symmetry.
1629 */
1630
1631 if (enable) {
1632 int error;
1633
1634 if (pci_pme_capable(dev, state))
1635 pci_pme_active(dev, true);
1636 else
1637 ret = 1;
1638 error = runtime ? platform_pci_run_wake(dev, true) :
1639 platform_pci_sleep_wake(dev, true);
1640 if (ret)
1641 ret = error;
1642 if (!ret)
1643 dev->wakeup_prepared = true;
1644 } else {
1645 if (runtime)
1646 platform_pci_run_wake(dev, false);
1647 else
1648 platform_pci_sleep_wake(dev, false);
1649 pci_pme_active(dev, false);
1650 dev->wakeup_prepared = false;
1651 }
1652
1653 return ret;
1654 }
1655 EXPORT_SYMBOL(__pci_enable_wake);
1656
1657 /**
1658 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1659 * @dev: PCI device to prepare
1660 * @enable: True to enable wake-up event generation; false to disable
1661 *
1662 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1663 * and this function allows them to set that up cleanly - pci_enable_wake()
1664 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1665 * ordering constraints.
1666 *
1667 * This function only returns error code if the device is not capable of
1668 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1669 * enable wake-up power for it.
1670 */
pci_wake_from_d3(struct pci_dev * dev,bool enable)1671 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1672 {
1673 return pci_pme_capable(dev, PCI_D3cold) ?
1674 pci_enable_wake(dev, PCI_D3cold, enable) :
1675 pci_enable_wake(dev, PCI_D3hot, enable);
1676 }
1677
1678 /**
1679 * pci_target_state - find an appropriate low power state for a given PCI dev
1680 * @dev: PCI device
1681 *
1682 * Use underlying platform code to find a supported low power state for @dev.
1683 * If the platform can't manage @dev, return the deepest state from which it
1684 * can generate wake events, based on any available PME info.
1685 */
pci_target_state(struct pci_dev * dev)1686 pci_power_t pci_target_state(struct pci_dev *dev)
1687 {
1688 pci_power_t target_state = PCI_D3hot;
1689
1690 if (platform_pci_power_manageable(dev)) {
1691 /*
1692 * Call the platform to choose the target state of the device
1693 * and enable wake-up from this state if supported.
1694 */
1695 pci_power_t state = platform_pci_choose_state(dev);
1696
1697 switch (state) {
1698 case PCI_POWER_ERROR:
1699 case PCI_UNKNOWN:
1700 break;
1701 case PCI_D1:
1702 case PCI_D2:
1703 if (pci_no_d1d2(dev))
1704 break;
1705 default:
1706 target_state = state;
1707 }
1708 } else if (!dev->pm_cap) {
1709 target_state = PCI_D0;
1710 } else if (device_may_wakeup(&dev->dev)) {
1711 /*
1712 * Find the deepest state from which the device can generate
1713 * wake-up events, make it the target state and enable device
1714 * to generate PME#.
1715 */
1716 if (dev->pme_support) {
1717 while (target_state
1718 && !(dev->pme_support & (1 << target_state)))
1719 target_state--;
1720 }
1721 }
1722
1723 return target_state;
1724 }
1725
1726 /**
1727 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1728 * @dev: Device to handle.
1729 *
1730 * Choose the power state appropriate for the device depending on whether
1731 * it can wake up the system and/or is power manageable by the platform
1732 * (PCI_D3hot is the default) and put the device into that state.
1733 */
pci_prepare_to_sleep(struct pci_dev * dev)1734 int pci_prepare_to_sleep(struct pci_dev *dev)
1735 {
1736 pci_power_t target_state = pci_target_state(dev);
1737 int error;
1738
1739 if (target_state == PCI_POWER_ERROR)
1740 return -EIO;
1741
1742 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1743
1744 error = pci_set_power_state(dev, target_state);
1745
1746 if (error)
1747 pci_enable_wake(dev, target_state, false);
1748
1749 return error;
1750 }
1751
1752 /**
1753 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1754 * @dev: Device to handle.
1755 *
1756 * Disable device's system wake-up capability and put it into D0.
1757 */
pci_back_from_sleep(struct pci_dev * dev)1758 int pci_back_from_sleep(struct pci_dev *dev)
1759 {
1760 pci_enable_wake(dev, PCI_D0, false);
1761 return pci_set_power_state(dev, PCI_D0);
1762 }
1763
1764 /**
1765 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1766 * @dev: PCI device being suspended.
1767 *
1768 * Prepare @dev to generate wake-up events at run time and put it into a low
1769 * power state.
1770 */
pci_finish_runtime_suspend(struct pci_dev * dev)1771 int pci_finish_runtime_suspend(struct pci_dev *dev)
1772 {
1773 pci_power_t target_state = pci_target_state(dev);
1774 int error;
1775
1776 if (target_state == PCI_POWER_ERROR)
1777 return -EIO;
1778
1779 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1780
1781 error = pci_set_power_state(dev, target_state);
1782
1783 if (error)
1784 __pci_enable_wake(dev, target_state, true, false);
1785
1786 return error;
1787 }
1788
1789 /**
1790 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1791 * @dev: Device to check.
1792 *
1793 * Return true if the device itself is cabable of generating wake-up events
1794 * (through the platform or using the native PCIe PME) or if the device supports
1795 * PME and one of its upstream bridges can generate wake-up events.
1796 */
pci_dev_run_wake(struct pci_dev * dev)1797 bool pci_dev_run_wake(struct pci_dev *dev)
1798 {
1799 struct pci_bus *bus = dev->bus;
1800
1801 if (device_run_wake(&dev->dev))
1802 return true;
1803
1804 if (!dev->pme_support)
1805 return false;
1806
1807 while (bus->parent) {
1808 struct pci_dev *bridge = bus->self;
1809
1810 if (device_run_wake(&bridge->dev))
1811 return true;
1812
1813 bus = bus->parent;
1814 }
1815
1816 /* We have reached the root bus. */
1817 if (bus->bridge)
1818 return device_run_wake(bus->bridge);
1819
1820 return false;
1821 }
1822 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1823
1824 /**
1825 * pci_pm_init - Initialize PM functions of given PCI device
1826 * @dev: PCI device to handle.
1827 */
pci_pm_init(struct pci_dev * dev)1828 void pci_pm_init(struct pci_dev *dev)
1829 {
1830 int pm;
1831 u16 pmc;
1832
1833 pm_runtime_forbid(&dev->dev);
1834 device_enable_async_suspend(&dev->dev);
1835 dev->wakeup_prepared = false;
1836
1837 dev->pm_cap = 0;
1838
1839 /* find PCI PM capability in list */
1840 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1841 if (!pm)
1842 return;
1843 /* Check device's ability to generate PME# */
1844 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1845
1846 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1847 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1848 pmc & PCI_PM_CAP_VER_MASK);
1849 return;
1850 }
1851
1852 dev->pm_cap = pm;
1853 dev->d3_delay = PCI_PM_D3_WAIT;
1854
1855 dev->d1_support = false;
1856 dev->d2_support = false;
1857 if (!pci_no_d1d2(dev)) {
1858 if (pmc & PCI_PM_CAP_D1)
1859 dev->d1_support = true;
1860 if (pmc & PCI_PM_CAP_D2)
1861 dev->d2_support = true;
1862
1863 if (dev->d1_support || dev->d2_support)
1864 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1865 dev->d1_support ? " D1" : "",
1866 dev->d2_support ? " D2" : "");
1867 }
1868
1869 pmc &= PCI_PM_CAP_PME_MASK;
1870 if (pmc) {
1871 dev_printk(KERN_DEBUG, &dev->dev,
1872 "PME# supported from%s%s%s%s%s\n",
1873 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1874 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1875 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1876 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1877 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1878 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1879 dev->pme_poll = true;
1880 /*
1881 * Make device's PM flags reflect the wake-up capability, but
1882 * let the user space enable it to wake up the system as needed.
1883 */
1884 device_set_wakeup_capable(&dev->dev, true);
1885 /* Disable the PME# generation functionality */
1886 pci_pme_active(dev, false);
1887 } else {
1888 dev->pme_support = 0;
1889 }
1890 }
1891
1892 /**
1893 * platform_pci_wakeup_init - init platform wakeup if present
1894 * @dev: PCI device
1895 *
1896 * Some devices don't have PCI PM caps but can still generate wakeup
1897 * events through platform methods (like ACPI events). If @dev supports
1898 * platform wakeup events, set the device flag to indicate as much. This
1899 * may be redundant if the device also supports PCI PM caps, but double
1900 * initialization should be safe in that case.
1901 */
platform_pci_wakeup_init(struct pci_dev * dev)1902 void platform_pci_wakeup_init(struct pci_dev *dev)
1903 {
1904 if (!platform_pci_can_wakeup(dev))
1905 return;
1906
1907 device_set_wakeup_capable(&dev->dev, true);
1908 platform_pci_sleep_wake(dev, false);
1909 }
1910
pci_add_saved_cap(struct pci_dev * pci_dev,struct pci_cap_saved_state * new_cap)1911 static void pci_add_saved_cap(struct pci_dev *pci_dev,
1912 struct pci_cap_saved_state *new_cap)
1913 {
1914 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
1915 }
1916
1917 /**
1918 * pci_add_save_buffer - allocate buffer for saving given capability registers
1919 * @dev: the PCI device
1920 * @cap: the capability to allocate the buffer for
1921 * @size: requested size of the buffer
1922 */
pci_add_cap_save_buffer(struct pci_dev * dev,char cap,unsigned int size)1923 static int pci_add_cap_save_buffer(
1924 struct pci_dev *dev, char cap, unsigned int size)
1925 {
1926 int pos;
1927 struct pci_cap_saved_state *save_state;
1928
1929 pos = pci_find_capability(dev, cap);
1930 if (pos <= 0)
1931 return 0;
1932
1933 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1934 if (!save_state)
1935 return -ENOMEM;
1936
1937 save_state->cap.cap_nr = cap;
1938 save_state->cap.size = size;
1939 pci_add_saved_cap(dev, save_state);
1940
1941 return 0;
1942 }
1943
1944 /**
1945 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1946 * @dev: the PCI device
1947 */
pci_allocate_cap_save_buffers(struct pci_dev * dev)1948 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1949 {
1950 int error;
1951
1952 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1953 PCI_EXP_SAVE_REGS * sizeof(u16));
1954 if (error)
1955 dev_err(&dev->dev,
1956 "unable to preallocate PCI Express save buffer\n");
1957
1958 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1959 if (error)
1960 dev_err(&dev->dev,
1961 "unable to preallocate PCI-X save buffer\n");
1962 }
1963
pci_free_cap_save_buffers(struct pci_dev * dev)1964 void pci_free_cap_save_buffers(struct pci_dev *dev)
1965 {
1966 struct pci_cap_saved_state *tmp;
1967 struct hlist_node *pos, *n;
1968
1969 hlist_for_each_entry_safe(tmp, pos, n, &dev->saved_cap_space, next)
1970 kfree(tmp);
1971 }
1972
1973 /**
1974 * pci_enable_ari - enable ARI forwarding if hardware support it
1975 * @dev: the PCI device
1976 */
pci_enable_ari(struct pci_dev * dev)1977 void pci_enable_ari(struct pci_dev *dev)
1978 {
1979 int pos;
1980 u32 cap;
1981 u16 flags, ctrl;
1982 struct pci_dev *bridge;
1983
1984 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
1985 return;
1986
1987 bridge = dev->bus->self;
1988 if (!bridge || !pci_is_pcie(bridge))
1989 return;
1990
1991 pos = pci_pcie_cap(bridge);
1992 if (!pos)
1993 return;
1994
1995 /* ARI is a PCIe v2 feature */
1996 pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
1997 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
1998 return;
1999
2000 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
2001 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2002 return;
2003
2004 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
2005 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2006 ctrl |= PCI_EXP_DEVCTL2_ARI;
2007 bridge->ari_enabled = 1;
2008 } else {
2009 ctrl &= ~PCI_EXP_DEVCTL2_ARI;
2010 bridge->ari_enabled = 0;
2011 }
2012 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
2013 }
2014
2015 /**
2016 * pci_enable_ido - enable ID-based ordering on a device
2017 * @dev: the PCI device
2018 * @type: which types of IDO to enable
2019 *
2020 * Enable ID-based ordering on @dev. @type can contain the bits
2021 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
2022 * which types of transactions are allowed to be re-ordered.
2023 */
pci_enable_ido(struct pci_dev * dev,unsigned long type)2024 void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2025 {
2026 int pos;
2027 u16 ctrl;
2028
2029 pos = pci_pcie_cap(dev);
2030 if (!pos)
2031 return;
2032
2033 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2034 if (type & PCI_EXP_IDO_REQUEST)
2035 ctrl |= PCI_EXP_IDO_REQ_EN;
2036 if (type & PCI_EXP_IDO_COMPLETION)
2037 ctrl |= PCI_EXP_IDO_CMP_EN;
2038 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2039 }
2040 EXPORT_SYMBOL(pci_enable_ido);
2041
2042 /**
2043 * pci_disable_ido - disable ID-based ordering on a device
2044 * @dev: the PCI device
2045 * @type: which types of IDO to disable
2046 */
pci_disable_ido(struct pci_dev * dev,unsigned long type)2047 void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2048 {
2049 int pos;
2050 u16 ctrl;
2051
2052 if (!pci_is_pcie(dev))
2053 return;
2054
2055 pos = pci_pcie_cap(dev);
2056 if (!pos)
2057 return;
2058
2059 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2060 if (type & PCI_EXP_IDO_REQUEST)
2061 ctrl &= ~PCI_EXP_IDO_REQ_EN;
2062 if (type & PCI_EXP_IDO_COMPLETION)
2063 ctrl &= ~PCI_EXP_IDO_CMP_EN;
2064 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2065 }
2066 EXPORT_SYMBOL(pci_disable_ido);
2067
2068 /**
2069 * pci_enable_obff - enable optimized buffer flush/fill
2070 * @dev: PCI device
2071 * @type: type of signaling to use
2072 *
2073 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2074 * signaling if possible, falling back to message signaling only if
2075 * WAKE# isn't supported. @type should indicate whether the PCIe link
2076 * be brought out of L0s or L1 to send the message. It should be either
2077 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2078 *
2079 * If your device can benefit from receiving all messages, even at the
2080 * power cost of bringing the link back up from a low power state, use
2081 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2082 * preferred type).
2083 *
2084 * RETURNS:
2085 * Zero on success, appropriate error number on failure.
2086 */
pci_enable_obff(struct pci_dev * dev,enum pci_obff_signal_type type)2087 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2088 {
2089 int pos;
2090 u32 cap;
2091 u16 ctrl;
2092 int ret;
2093
2094 if (!pci_is_pcie(dev))
2095 return -ENOTSUPP;
2096
2097 pos = pci_pcie_cap(dev);
2098 if (!pos)
2099 return -ENOTSUPP;
2100
2101 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2102 if (!(cap & PCI_EXP_OBFF_MASK))
2103 return -ENOTSUPP; /* no OBFF support at all */
2104
2105 /* Make sure the topology supports OBFF as well */
2106 if (dev->bus) {
2107 ret = pci_enable_obff(dev->bus->self, type);
2108 if (ret)
2109 return ret;
2110 }
2111
2112 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2113 if (cap & PCI_EXP_OBFF_WAKE)
2114 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2115 else {
2116 switch (type) {
2117 case PCI_EXP_OBFF_SIGNAL_L0:
2118 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2119 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2120 break;
2121 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2122 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2123 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2124 break;
2125 default:
2126 WARN(1, "bad OBFF signal type\n");
2127 return -ENOTSUPP;
2128 }
2129 }
2130 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2131
2132 return 0;
2133 }
2134 EXPORT_SYMBOL(pci_enable_obff);
2135
2136 /**
2137 * pci_disable_obff - disable optimized buffer flush/fill
2138 * @dev: PCI device
2139 *
2140 * Disable OBFF on @dev.
2141 */
pci_disable_obff(struct pci_dev * dev)2142 void pci_disable_obff(struct pci_dev *dev)
2143 {
2144 int pos;
2145 u16 ctrl;
2146
2147 if (!pci_is_pcie(dev))
2148 return;
2149
2150 pos = pci_pcie_cap(dev);
2151 if (!pos)
2152 return;
2153
2154 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2155 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2156 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2157 }
2158 EXPORT_SYMBOL(pci_disable_obff);
2159
2160 /**
2161 * pci_ltr_supported - check whether a device supports LTR
2162 * @dev: PCI device
2163 *
2164 * RETURNS:
2165 * True if @dev supports latency tolerance reporting, false otherwise.
2166 */
pci_ltr_supported(struct pci_dev * dev)2167 bool pci_ltr_supported(struct pci_dev *dev)
2168 {
2169 int pos;
2170 u32 cap;
2171
2172 if (!pci_is_pcie(dev))
2173 return false;
2174
2175 pos = pci_pcie_cap(dev);
2176 if (!pos)
2177 return false;
2178
2179 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2180
2181 return cap & PCI_EXP_DEVCAP2_LTR;
2182 }
2183 EXPORT_SYMBOL(pci_ltr_supported);
2184
2185 /**
2186 * pci_enable_ltr - enable latency tolerance reporting
2187 * @dev: PCI device
2188 *
2189 * Enable LTR on @dev if possible, which means enabling it first on
2190 * upstream ports.
2191 *
2192 * RETURNS:
2193 * Zero on success, errno on failure.
2194 */
pci_enable_ltr(struct pci_dev * dev)2195 int pci_enable_ltr(struct pci_dev *dev)
2196 {
2197 int pos;
2198 u16 ctrl;
2199 int ret;
2200
2201 if (!pci_ltr_supported(dev))
2202 return -ENOTSUPP;
2203
2204 pos = pci_pcie_cap(dev);
2205 if (!pos)
2206 return -ENOTSUPP;
2207
2208 /* Only primary function can enable/disable LTR */
2209 if (PCI_FUNC(dev->devfn) != 0)
2210 return -EINVAL;
2211
2212 /* Enable upstream ports first */
2213 if (dev->bus) {
2214 ret = pci_enable_ltr(dev->bus->self);
2215 if (ret)
2216 return ret;
2217 }
2218
2219 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2220 ctrl |= PCI_EXP_LTR_EN;
2221 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2222
2223 return 0;
2224 }
2225 EXPORT_SYMBOL(pci_enable_ltr);
2226
2227 /**
2228 * pci_disable_ltr - disable latency tolerance reporting
2229 * @dev: PCI device
2230 */
pci_disable_ltr(struct pci_dev * dev)2231 void pci_disable_ltr(struct pci_dev *dev)
2232 {
2233 int pos;
2234 u16 ctrl;
2235
2236 if (!pci_ltr_supported(dev))
2237 return;
2238
2239 pos = pci_pcie_cap(dev);
2240 if (!pos)
2241 return;
2242
2243 /* Only primary function can enable/disable LTR */
2244 if (PCI_FUNC(dev->devfn) != 0)
2245 return;
2246
2247 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2248 ctrl &= ~PCI_EXP_LTR_EN;
2249 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2250 }
2251 EXPORT_SYMBOL(pci_disable_ltr);
2252
__pci_ltr_scale(int * val)2253 static int __pci_ltr_scale(int *val)
2254 {
2255 int scale = 0;
2256
2257 while (*val > 1023) {
2258 *val = (*val + 31) / 32;
2259 scale++;
2260 }
2261 return scale;
2262 }
2263
2264 /**
2265 * pci_set_ltr - set LTR latency values
2266 * @dev: PCI device
2267 * @snoop_lat_ns: snoop latency in nanoseconds
2268 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2269 *
2270 * Figure out the scale and set the LTR values accordingly.
2271 */
pci_set_ltr(struct pci_dev * dev,int snoop_lat_ns,int nosnoop_lat_ns)2272 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2273 {
2274 int pos, ret, snoop_scale, nosnoop_scale;
2275 u16 val;
2276
2277 if (!pci_ltr_supported(dev))
2278 return -ENOTSUPP;
2279
2280 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2281 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2282
2283 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2284 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2285 return -EINVAL;
2286
2287 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2288 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2289 return -EINVAL;
2290
2291 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2292 if (!pos)
2293 return -ENOTSUPP;
2294
2295 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2296 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2297 if (ret != 4)
2298 return -EIO;
2299
2300 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2301 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2302 if (ret != 4)
2303 return -EIO;
2304
2305 return 0;
2306 }
2307 EXPORT_SYMBOL(pci_set_ltr);
2308
2309 static int pci_acs_enable;
2310
2311 /**
2312 * pci_request_acs - ask for ACS to be enabled if supported
2313 */
pci_request_acs(void)2314 void pci_request_acs(void)
2315 {
2316 pci_acs_enable = 1;
2317 }
2318
2319 /**
2320 * pci_enable_acs - enable ACS if hardware support it
2321 * @dev: the PCI device
2322 */
pci_enable_acs(struct pci_dev * dev)2323 void pci_enable_acs(struct pci_dev *dev)
2324 {
2325 int pos;
2326 u16 cap;
2327 u16 ctrl;
2328
2329 if (!pci_acs_enable)
2330 return;
2331
2332 if (!pci_is_pcie(dev))
2333 return;
2334
2335 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2336 if (!pos)
2337 return;
2338
2339 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2340 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2341
2342 /* Source Validation */
2343 ctrl |= (cap & PCI_ACS_SV);
2344
2345 /* P2P Request Redirect */
2346 ctrl |= (cap & PCI_ACS_RR);
2347
2348 /* P2P Completion Redirect */
2349 ctrl |= (cap & PCI_ACS_CR);
2350
2351 /* Upstream Forwarding */
2352 ctrl |= (cap & PCI_ACS_UF);
2353
2354 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2355 }
2356
2357 /**
2358 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2359 * @dev: the PCI device
2360 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2361 *
2362 * Perform INTx swizzling for a device behind one level of bridge. This is
2363 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2364 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2365 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2366 * the PCI Express Base Specification, Revision 2.1)
2367 */
pci_swizzle_interrupt_pin(struct pci_dev * dev,u8 pin)2368 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
2369 {
2370 int slot;
2371
2372 if (pci_ari_enabled(dev->bus))
2373 slot = 0;
2374 else
2375 slot = PCI_SLOT(dev->devfn);
2376
2377 return (((pin - 1) + slot) % 4) + 1;
2378 }
2379
2380 int
pci_get_interrupt_pin(struct pci_dev * dev,struct pci_dev ** bridge)2381 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2382 {
2383 u8 pin;
2384
2385 pin = dev->pin;
2386 if (!pin)
2387 return -1;
2388
2389 while (!pci_is_root_bus(dev->bus)) {
2390 pin = pci_swizzle_interrupt_pin(dev, pin);
2391 dev = dev->bus->self;
2392 }
2393 *bridge = dev;
2394 return pin;
2395 }
2396
2397 /**
2398 * pci_common_swizzle - swizzle INTx all the way to root bridge
2399 * @dev: the PCI device
2400 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2401 *
2402 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2403 * bridges all the way up to a PCI root bus.
2404 */
pci_common_swizzle(struct pci_dev * dev,u8 * pinp)2405 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2406 {
2407 u8 pin = *pinp;
2408
2409 while (!pci_is_root_bus(dev->bus)) {
2410 pin = pci_swizzle_interrupt_pin(dev, pin);
2411 dev = dev->bus->self;
2412 }
2413 *pinp = pin;
2414 return PCI_SLOT(dev->devfn);
2415 }
2416
2417 /**
2418 * pci_release_region - Release a PCI bar
2419 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2420 * @bar: BAR to release
2421 *
2422 * Releases the PCI I/O and memory resources previously reserved by a
2423 * successful call to pci_request_region. Call this function only
2424 * after all use of the PCI regions has ceased.
2425 */
pci_release_region(struct pci_dev * pdev,int bar)2426 void pci_release_region(struct pci_dev *pdev, int bar)
2427 {
2428 struct pci_devres *dr;
2429
2430 if (pci_resource_len(pdev, bar) == 0)
2431 return;
2432 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2433 release_region(pci_resource_start(pdev, bar),
2434 pci_resource_len(pdev, bar));
2435 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2436 release_mem_region(pci_resource_start(pdev, bar),
2437 pci_resource_len(pdev, bar));
2438
2439 dr = find_pci_dr(pdev);
2440 if (dr)
2441 dr->region_mask &= ~(1 << bar);
2442 }
2443
2444 /**
2445 * __pci_request_region - Reserved PCI I/O and memory resource
2446 * @pdev: PCI device whose resources are to be reserved
2447 * @bar: BAR to be reserved
2448 * @res_name: Name to be associated with resource.
2449 * @exclusive: whether the region access is exclusive or not
2450 *
2451 * Mark the PCI region associated with PCI device @pdev BR @bar as
2452 * being reserved by owner @res_name. Do not access any
2453 * address inside the PCI regions unless this call returns
2454 * successfully.
2455 *
2456 * If @exclusive is set, then the region is marked so that userspace
2457 * is explicitly not allowed to map the resource via /dev/mem or
2458 * sysfs MMIO access.
2459 *
2460 * Returns 0 on success, or %EBUSY on error. A warning
2461 * message is also printed on failure.
2462 */
__pci_request_region(struct pci_dev * pdev,int bar,const char * res_name,int exclusive)2463 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2464 int exclusive)
2465 {
2466 struct pci_devres *dr;
2467
2468 if (pci_resource_len(pdev, bar) == 0)
2469 return 0;
2470
2471 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2472 if (!request_region(pci_resource_start(pdev, bar),
2473 pci_resource_len(pdev, bar), res_name))
2474 goto err_out;
2475 }
2476 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2477 if (!__request_mem_region(pci_resource_start(pdev, bar),
2478 pci_resource_len(pdev, bar), res_name,
2479 exclusive))
2480 goto err_out;
2481 }
2482
2483 dr = find_pci_dr(pdev);
2484 if (dr)
2485 dr->region_mask |= 1 << bar;
2486
2487 return 0;
2488
2489 err_out:
2490 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2491 &pdev->resource[bar]);
2492 return -EBUSY;
2493 }
2494
2495 /**
2496 * pci_request_region - Reserve PCI I/O and memory resource
2497 * @pdev: PCI device whose resources are to be reserved
2498 * @bar: BAR to be reserved
2499 * @res_name: Name to be associated with resource
2500 *
2501 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2502 * being reserved by owner @res_name. Do not access any
2503 * address inside the PCI regions unless this call returns
2504 * successfully.
2505 *
2506 * Returns 0 on success, or %EBUSY on error. A warning
2507 * message is also printed on failure.
2508 */
pci_request_region(struct pci_dev * pdev,int bar,const char * res_name)2509 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2510 {
2511 return __pci_request_region(pdev, bar, res_name, 0);
2512 }
2513
2514 /**
2515 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2516 * @pdev: PCI device whose resources are to be reserved
2517 * @bar: BAR to be reserved
2518 * @res_name: Name to be associated with resource.
2519 *
2520 * Mark the PCI region associated with PCI device @pdev BR @bar as
2521 * being reserved by owner @res_name. Do not access any
2522 * address inside the PCI regions unless this call returns
2523 * successfully.
2524 *
2525 * Returns 0 on success, or %EBUSY on error. A warning
2526 * message is also printed on failure.
2527 *
2528 * The key difference that _exclusive makes it that userspace is
2529 * explicitly not allowed to map the resource via /dev/mem or
2530 * sysfs.
2531 */
pci_request_region_exclusive(struct pci_dev * pdev,int bar,const char * res_name)2532 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2533 {
2534 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2535 }
2536 /**
2537 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2538 * @pdev: PCI device whose resources were previously reserved
2539 * @bars: Bitmask of BARs to be released
2540 *
2541 * Release selected PCI I/O and memory resources previously reserved.
2542 * Call this function only after all use of the PCI regions has ceased.
2543 */
pci_release_selected_regions(struct pci_dev * pdev,int bars)2544 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2545 {
2546 int i;
2547
2548 for (i = 0; i < 6; i++)
2549 if (bars & (1 << i))
2550 pci_release_region(pdev, i);
2551 }
2552
__pci_request_selected_regions(struct pci_dev * pdev,int bars,const char * res_name,int excl)2553 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2554 const char *res_name, int excl)
2555 {
2556 int i;
2557
2558 for (i = 0; i < 6; i++)
2559 if (bars & (1 << i))
2560 if (__pci_request_region(pdev, i, res_name, excl))
2561 goto err_out;
2562 return 0;
2563
2564 err_out:
2565 while(--i >= 0)
2566 if (bars & (1 << i))
2567 pci_release_region(pdev, i);
2568
2569 return -EBUSY;
2570 }
2571
2572
2573 /**
2574 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2575 * @pdev: PCI device whose resources are to be reserved
2576 * @bars: Bitmask of BARs to be requested
2577 * @res_name: Name to be associated with resource
2578 */
pci_request_selected_regions(struct pci_dev * pdev,int bars,const char * res_name)2579 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2580 const char *res_name)
2581 {
2582 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2583 }
2584
pci_request_selected_regions_exclusive(struct pci_dev * pdev,int bars,const char * res_name)2585 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2586 int bars, const char *res_name)
2587 {
2588 return __pci_request_selected_regions(pdev, bars, res_name,
2589 IORESOURCE_EXCLUSIVE);
2590 }
2591
2592 /**
2593 * pci_release_regions - Release reserved PCI I/O and memory resources
2594 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2595 *
2596 * Releases all PCI I/O and memory resources previously reserved by a
2597 * successful call to pci_request_regions. Call this function only
2598 * after all use of the PCI regions has ceased.
2599 */
2600
pci_release_regions(struct pci_dev * pdev)2601 void pci_release_regions(struct pci_dev *pdev)
2602 {
2603 pci_release_selected_regions(pdev, (1 << 6) - 1);
2604 }
2605
2606 /**
2607 * pci_request_regions - Reserved PCI I/O and memory resources
2608 * @pdev: PCI device whose resources are to be reserved
2609 * @res_name: Name to be associated with resource.
2610 *
2611 * Mark all PCI regions associated with PCI device @pdev as
2612 * being reserved by owner @res_name. Do not access any
2613 * address inside the PCI regions unless this call returns
2614 * successfully.
2615 *
2616 * Returns 0 on success, or %EBUSY on error. A warning
2617 * message is also printed on failure.
2618 */
pci_request_regions(struct pci_dev * pdev,const char * res_name)2619 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2620 {
2621 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2622 }
2623
2624 /**
2625 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2626 * @pdev: PCI device whose resources are to be reserved
2627 * @res_name: Name to be associated with resource.
2628 *
2629 * Mark all PCI regions associated with PCI device @pdev as
2630 * being reserved by owner @res_name. Do not access any
2631 * address inside the PCI regions unless this call returns
2632 * successfully.
2633 *
2634 * pci_request_regions_exclusive() will mark the region so that
2635 * /dev/mem and the sysfs MMIO access will not be allowed.
2636 *
2637 * Returns 0 on success, or %EBUSY on error. A warning
2638 * message is also printed on failure.
2639 */
pci_request_regions_exclusive(struct pci_dev * pdev,const char * res_name)2640 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2641 {
2642 return pci_request_selected_regions_exclusive(pdev,
2643 ((1 << 6) - 1), res_name);
2644 }
2645
__pci_set_master(struct pci_dev * dev,bool enable)2646 static void __pci_set_master(struct pci_dev *dev, bool enable)
2647 {
2648 u16 old_cmd, cmd;
2649
2650 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2651 if (enable)
2652 cmd = old_cmd | PCI_COMMAND_MASTER;
2653 else
2654 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2655 if (cmd != old_cmd) {
2656 dev_dbg(&dev->dev, "%s bus mastering\n",
2657 enable ? "enabling" : "disabling");
2658 pci_write_config_word(dev, PCI_COMMAND, cmd);
2659 }
2660 dev->is_busmaster = enable;
2661 }
2662
2663 /**
2664 * pcibios_set_master - enable PCI bus-mastering for device dev
2665 * @dev: the PCI device to enable
2666 *
2667 * Enables PCI bus-mastering for the device. This is the default
2668 * implementation. Architecture specific implementations can override
2669 * this if necessary.
2670 */
pcibios_set_master(struct pci_dev * dev)2671 void __weak pcibios_set_master(struct pci_dev *dev)
2672 {
2673 u8 lat;
2674
2675 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2676 if (pci_is_pcie(dev))
2677 return;
2678
2679 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2680 if (lat < 16)
2681 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2682 else if (lat > pcibios_max_latency)
2683 lat = pcibios_max_latency;
2684 else
2685 return;
2686 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
2687 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2688 }
2689
2690 /**
2691 * pci_set_master - enables bus-mastering for device dev
2692 * @dev: the PCI device to enable
2693 *
2694 * Enables bus-mastering on the device and calls pcibios_set_master()
2695 * to do the needed arch specific settings.
2696 */
pci_set_master(struct pci_dev * dev)2697 void pci_set_master(struct pci_dev *dev)
2698 {
2699 __pci_set_master(dev, true);
2700 pcibios_set_master(dev);
2701 }
2702
2703 /**
2704 * pci_clear_master - disables bus-mastering for device dev
2705 * @dev: the PCI device to disable
2706 */
pci_clear_master(struct pci_dev * dev)2707 void pci_clear_master(struct pci_dev *dev)
2708 {
2709 __pci_set_master(dev, false);
2710 }
2711
2712 /**
2713 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2714 * @dev: the PCI device for which MWI is to be enabled
2715 *
2716 * Helper function for pci_set_mwi.
2717 * Originally copied from drivers/net/acenic.c.
2718 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2719 *
2720 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2721 */
pci_set_cacheline_size(struct pci_dev * dev)2722 int pci_set_cacheline_size(struct pci_dev *dev)
2723 {
2724 u8 cacheline_size;
2725
2726 if (!pci_cache_line_size)
2727 return -EINVAL;
2728
2729 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2730 equal to or multiple of the right value. */
2731 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2732 if (cacheline_size >= pci_cache_line_size &&
2733 (cacheline_size % pci_cache_line_size) == 0)
2734 return 0;
2735
2736 /* Write the correct value. */
2737 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2738 /* Read it back. */
2739 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2740 if (cacheline_size == pci_cache_line_size)
2741 return 0;
2742
2743 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2744 "supported\n", pci_cache_line_size << 2);
2745
2746 return -EINVAL;
2747 }
2748 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2749
2750 #ifdef PCI_DISABLE_MWI
pci_set_mwi(struct pci_dev * dev)2751 int pci_set_mwi(struct pci_dev *dev)
2752 {
2753 return 0;
2754 }
2755
pci_try_set_mwi(struct pci_dev * dev)2756 int pci_try_set_mwi(struct pci_dev *dev)
2757 {
2758 return 0;
2759 }
2760
pci_clear_mwi(struct pci_dev * dev)2761 void pci_clear_mwi(struct pci_dev *dev)
2762 {
2763 }
2764
2765 #else
2766
2767 /**
2768 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2769 * @dev: the PCI device for which MWI is enabled
2770 *
2771 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2772 *
2773 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2774 */
2775 int
pci_set_mwi(struct pci_dev * dev)2776 pci_set_mwi(struct pci_dev *dev)
2777 {
2778 int rc;
2779 u16 cmd;
2780
2781 rc = pci_set_cacheline_size(dev);
2782 if (rc)
2783 return rc;
2784
2785 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2786 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2787 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2788 cmd |= PCI_COMMAND_INVALIDATE;
2789 pci_write_config_word(dev, PCI_COMMAND, cmd);
2790 }
2791
2792 return 0;
2793 }
2794
2795 /**
2796 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2797 * @dev: the PCI device for which MWI is enabled
2798 *
2799 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2800 * Callers are not required to check the return value.
2801 *
2802 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2803 */
pci_try_set_mwi(struct pci_dev * dev)2804 int pci_try_set_mwi(struct pci_dev *dev)
2805 {
2806 int rc = pci_set_mwi(dev);
2807 return rc;
2808 }
2809
2810 /**
2811 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2812 * @dev: the PCI device to disable
2813 *
2814 * Disables PCI Memory-Write-Invalidate transaction on the device
2815 */
2816 void
pci_clear_mwi(struct pci_dev * dev)2817 pci_clear_mwi(struct pci_dev *dev)
2818 {
2819 u16 cmd;
2820
2821 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2822 if (cmd & PCI_COMMAND_INVALIDATE) {
2823 cmd &= ~PCI_COMMAND_INVALIDATE;
2824 pci_write_config_word(dev, PCI_COMMAND, cmd);
2825 }
2826 }
2827 #endif /* ! PCI_DISABLE_MWI */
2828
2829 /**
2830 * pci_intx - enables/disables PCI INTx for device dev
2831 * @pdev: the PCI device to operate on
2832 * @enable: boolean: whether to enable or disable PCI INTx
2833 *
2834 * Enables/disables PCI INTx for device dev
2835 */
2836 void
pci_intx(struct pci_dev * pdev,int enable)2837 pci_intx(struct pci_dev *pdev, int enable)
2838 {
2839 u16 pci_command, new;
2840
2841 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2842
2843 if (enable) {
2844 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2845 } else {
2846 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2847 }
2848
2849 if (new != pci_command) {
2850 struct pci_devres *dr;
2851
2852 pci_write_config_word(pdev, PCI_COMMAND, new);
2853
2854 dr = find_pci_dr(pdev);
2855 if (dr && !dr->restore_intx) {
2856 dr->restore_intx = 1;
2857 dr->orig_intx = !enable;
2858 }
2859 }
2860 }
2861
2862 /**
2863 * pci_intx_mask_supported - probe for INTx masking support
2864 * @dev: the PCI device to operate on
2865 *
2866 * Check if the device dev support INTx masking via the config space
2867 * command word.
2868 */
pci_intx_mask_supported(struct pci_dev * dev)2869 bool pci_intx_mask_supported(struct pci_dev *dev)
2870 {
2871 bool mask_supported = false;
2872 u16 orig, new;
2873
2874 pci_cfg_access_lock(dev);
2875
2876 pci_read_config_word(dev, PCI_COMMAND, &orig);
2877 pci_write_config_word(dev, PCI_COMMAND,
2878 orig ^ PCI_COMMAND_INTX_DISABLE);
2879 pci_read_config_word(dev, PCI_COMMAND, &new);
2880
2881 /*
2882 * There's no way to protect against hardware bugs or detect them
2883 * reliably, but as long as we know what the value should be, let's
2884 * go ahead and check it.
2885 */
2886 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2887 dev_err(&dev->dev, "Command register changed from "
2888 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
2889 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2890 mask_supported = true;
2891 pci_write_config_word(dev, PCI_COMMAND, orig);
2892 }
2893
2894 pci_cfg_access_unlock(dev);
2895 return mask_supported;
2896 }
2897 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
2898
pci_check_and_set_intx_mask(struct pci_dev * dev,bool mask)2899 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
2900 {
2901 struct pci_bus *bus = dev->bus;
2902 bool mask_updated = true;
2903 u32 cmd_status_dword;
2904 u16 origcmd, newcmd;
2905 unsigned long flags;
2906 bool irq_pending;
2907
2908 /*
2909 * We do a single dword read to retrieve both command and status.
2910 * Document assumptions that make this possible.
2911 */
2912 BUILD_BUG_ON(PCI_COMMAND % 4);
2913 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
2914
2915 raw_spin_lock_irqsave(&pci_lock, flags);
2916
2917 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
2918
2919 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
2920
2921 /*
2922 * Check interrupt status register to see whether our device
2923 * triggered the interrupt (when masking) or the next IRQ is
2924 * already pending (when unmasking).
2925 */
2926 if (mask != irq_pending) {
2927 mask_updated = false;
2928 goto done;
2929 }
2930
2931 origcmd = cmd_status_dword;
2932 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
2933 if (mask)
2934 newcmd |= PCI_COMMAND_INTX_DISABLE;
2935 if (newcmd != origcmd)
2936 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
2937
2938 done:
2939 raw_spin_unlock_irqrestore(&pci_lock, flags);
2940
2941 return mask_updated;
2942 }
2943
2944 /**
2945 * pci_check_and_mask_intx - mask INTx on pending interrupt
2946 * @dev: the PCI device to operate on
2947 *
2948 * Check if the device dev has its INTx line asserted, mask it and
2949 * return true in that case. False is returned if not interrupt was
2950 * pending.
2951 */
pci_check_and_mask_intx(struct pci_dev * dev)2952 bool pci_check_and_mask_intx(struct pci_dev *dev)
2953 {
2954 return pci_check_and_set_intx_mask(dev, true);
2955 }
2956 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
2957
2958 /**
2959 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
2960 * @dev: the PCI device to operate on
2961 *
2962 * Check if the device dev has its INTx line asserted, unmask it if not
2963 * and return true. False is returned and the mask remains active if
2964 * there was still an interrupt pending.
2965 */
pci_check_and_unmask_intx(struct pci_dev * dev)2966 bool pci_check_and_unmask_intx(struct pci_dev *dev)
2967 {
2968 return pci_check_and_set_intx_mask(dev, false);
2969 }
2970 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
2971
2972 /**
2973 * pci_msi_off - disables any msi or msix capabilities
2974 * @dev: the PCI device to operate on
2975 *
2976 * If you want to use msi see pci_enable_msi and friends.
2977 * This is a lower level primitive that allows us to disable
2978 * msi operation at the device level.
2979 */
pci_msi_off(struct pci_dev * dev)2980 void pci_msi_off(struct pci_dev *dev)
2981 {
2982 int pos;
2983 u16 control;
2984
2985 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2986 if (pos) {
2987 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2988 control &= ~PCI_MSI_FLAGS_ENABLE;
2989 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2990 }
2991 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2992 if (pos) {
2993 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2994 control &= ~PCI_MSIX_FLAGS_ENABLE;
2995 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2996 }
2997 }
2998 EXPORT_SYMBOL_GPL(pci_msi_off);
2999
pci_set_dma_max_seg_size(struct pci_dev * dev,unsigned int size)3000 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3001 {
3002 return dma_set_max_seg_size(&dev->dev, size);
3003 }
3004 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3005
pci_set_dma_seg_boundary(struct pci_dev * dev,unsigned long mask)3006 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3007 {
3008 return dma_set_seg_boundary(&dev->dev, mask);
3009 }
3010 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3011
pcie_flr(struct pci_dev * dev,int probe)3012 static int pcie_flr(struct pci_dev *dev, int probe)
3013 {
3014 int i;
3015 int pos;
3016 u32 cap;
3017 u16 status, control;
3018
3019 pos = pci_pcie_cap(dev);
3020 if (!pos)
3021 return -ENOTTY;
3022
3023 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
3024 if (!(cap & PCI_EXP_DEVCAP_FLR))
3025 return -ENOTTY;
3026
3027 if (probe)
3028 return 0;
3029
3030 /* Wait for Transaction Pending bit clean */
3031 for (i = 0; i < 4; i++) {
3032 if (i)
3033 msleep((1 << (i - 1)) * 100);
3034
3035 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
3036 if (!(status & PCI_EXP_DEVSTA_TRPND))
3037 goto clear;
3038 }
3039
3040 dev_err(&dev->dev, "transaction is not cleared; "
3041 "proceeding with reset anyway\n");
3042
3043 clear:
3044 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
3045 control |= PCI_EXP_DEVCTL_BCR_FLR;
3046 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
3047
3048 msleep(100);
3049
3050 return 0;
3051 }
3052
pci_af_flr(struct pci_dev * dev,int probe)3053 static int pci_af_flr(struct pci_dev *dev, int probe)
3054 {
3055 int i;
3056 int pos;
3057 u8 cap;
3058 u8 status;
3059
3060 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3061 if (!pos)
3062 return -ENOTTY;
3063
3064 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3065 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3066 return -ENOTTY;
3067
3068 if (probe)
3069 return 0;
3070
3071 /* Wait for Transaction Pending bit clean */
3072 for (i = 0; i < 4; i++) {
3073 if (i)
3074 msleep((1 << (i - 1)) * 100);
3075
3076 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
3077 if (!(status & PCI_AF_STATUS_TP))
3078 goto clear;
3079 }
3080
3081 dev_err(&dev->dev, "transaction is not cleared; "
3082 "proceeding with reset anyway\n");
3083
3084 clear:
3085 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3086 msleep(100);
3087
3088 return 0;
3089 }
3090
3091 /**
3092 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3093 * @dev: Device to reset.
3094 * @probe: If set, only check if the device can be reset this way.
3095 *
3096 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3097 * unset, it will be reinitialized internally when going from PCI_D3hot to
3098 * PCI_D0. If that's the case and the device is not in a low-power state
3099 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3100 *
3101 * NOTE: This causes the caller to sleep for twice the device power transition
3102 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3103 * by devault (i.e. unless the @dev's d3_delay field has a different value).
3104 * Moreover, only devices in D0 can be reset by this function.
3105 */
pci_pm_reset(struct pci_dev * dev,int probe)3106 static int pci_pm_reset(struct pci_dev *dev, int probe)
3107 {
3108 u16 csr;
3109
3110 if (!dev->pm_cap)
3111 return -ENOTTY;
3112
3113 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3114 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3115 return -ENOTTY;
3116
3117 if (probe)
3118 return 0;
3119
3120 if (dev->current_state != PCI_D0)
3121 return -EINVAL;
3122
3123 csr &= ~PCI_PM_CTRL_STATE_MASK;
3124 csr |= PCI_D3hot;
3125 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3126 pci_dev_d3_sleep(dev);
3127
3128 csr &= ~PCI_PM_CTRL_STATE_MASK;
3129 csr |= PCI_D0;
3130 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3131 pci_dev_d3_sleep(dev);
3132
3133 return 0;
3134 }
3135
pci_parent_bus_reset(struct pci_dev * dev,int probe)3136 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3137 {
3138 u16 ctrl;
3139 struct pci_dev *pdev;
3140
3141 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3142 return -ENOTTY;
3143
3144 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3145 if (pdev != dev)
3146 return -ENOTTY;
3147
3148 if (probe)
3149 return 0;
3150
3151 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
3152 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3153 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3154 msleep(100);
3155
3156 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3157 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
3158 msleep(100);
3159
3160 return 0;
3161 }
3162
pci_dev_reset(struct pci_dev * dev,int probe)3163 static int pci_dev_reset(struct pci_dev *dev, int probe)
3164 {
3165 int rc;
3166
3167 might_sleep();
3168
3169 if (!probe) {
3170 pci_cfg_access_lock(dev);
3171 /* block PM suspend, driver probe, etc. */
3172 device_lock(&dev->dev);
3173 }
3174
3175 rc = pci_dev_specific_reset(dev, probe);
3176 if (rc != -ENOTTY)
3177 goto done;
3178
3179 rc = pcie_flr(dev, probe);
3180 if (rc != -ENOTTY)
3181 goto done;
3182
3183 rc = pci_af_flr(dev, probe);
3184 if (rc != -ENOTTY)
3185 goto done;
3186
3187 rc = pci_pm_reset(dev, probe);
3188 if (rc != -ENOTTY)
3189 goto done;
3190
3191 rc = pci_parent_bus_reset(dev, probe);
3192 done:
3193 if (!probe) {
3194 device_unlock(&dev->dev);
3195 pci_cfg_access_unlock(dev);
3196 }
3197
3198 return rc;
3199 }
3200
3201 /**
3202 * __pci_reset_function - reset a PCI device function
3203 * @dev: PCI device to reset
3204 *
3205 * Some devices allow an individual function to be reset without affecting
3206 * other functions in the same device. The PCI device must be responsive
3207 * to PCI config space in order to use this function.
3208 *
3209 * The device function is presumed to be unused when this function is called.
3210 * Resetting the device will make the contents of PCI configuration space
3211 * random, so any caller of this must be prepared to reinitialise the
3212 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3213 * etc.
3214 *
3215 * Returns 0 if the device function was successfully reset or negative if the
3216 * device doesn't support resetting a single function.
3217 */
__pci_reset_function(struct pci_dev * dev)3218 int __pci_reset_function(struct pci_dev *dev)
3219 {
3220 return pci_dev_reset(dev, 0);
3221 }
3222 EXPORT_SYMBOL_GPL(__pci_reset_function);
3223
3224 /**
3225 * __pci_reset_function_locked - reset a PCI device function while holding
3226 * the @dev mutex lock.
3227 * @dev: PCI device to reset
3228 *
3229 * Some devices allow an individual function to be reset without affecting
3230 * other functions in the same device. The PCI device must be responsive
3231 * to PCI config space in order to use this function.
3232 *
3233 * The device function is presumed to be unused and the caller is holding
3234 * the device mutex lock when this function is called.
3235 * Resetting the device will make the contents of PCI configuration space
3236 * random, so any caller of this must be prepared to reinitialise the
3237 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3238 * etc.
3239 *
3240 * Returns 0 if the device function was successfully reset or negative if the
3241 * device doesn't support resetting a single function.
3242 */
__pci_reset_function_locked(struct pci_dev * dev)3243 int __pci_reset_function_locked(struct pci_dev *dev)
3244 {
3245 return pci_dev_reset(dev, 1);
3246 }
3247 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3248
3249 /**
3250 * pci_probe_reset_function - check whether the device can be safely reset
3251 * @dev: PCI device to reset
3252 *
3253 * Some devices allow an individual function to be reset without affecting
3254 * other functions in the same device. The PCI device must be responsive
3255 * to PCI config space in order to use this function.
3256 *
3257 * Returns 0 if the device function can be reset or negative if the
3258 * device doesn't support resetting a single function.
3259 */
pci_probe_reset_function(struct pci_dev * dev)3260 int pci_probe_reset_function(struct pci_dev *dev)
3261 {
3262 return pci_dev_reset(dev, 1);
3263 }
3264
3265 /**
3266 * pci_reset_function - quiesce and reset a PCI device function
3267 * @dev: PCI device to reset
3268 *
3269 * Some devices allow an individual function to be reset without affecting
3270 * other functions in the same device. The PCI device must be responsive
3271 * to PCI config space in order to use this function.
3272 *
3273 * This function does not just reset the PCI portion of a device, but
3274 * clears all the state associated with the device. This function differs
3275 * from __pci_reset_function in that it saves and restores device state
3276 * over the reset.
3277 *
3278 * Returns 0 if the device function was successfully reset or negative if the
3279 * device doesn't support resetting a single function.
3280 */
pci_reset_function(struct pci_dev * dev)3281 int pci_reset_function(struct pci_dev *dev)
3282 {
3283 int rc;
3284
3285 rc = pci_dev_reset(dev, 1);
3286 if (rc)
3287 return rc;
3288
3289 pci_save_state(dev);
3290
3291 /*
3292 * both INTx and MSI are disabled after the Interrupt Disable bit
3293 * is set and the Bus Master bit is cleared.
3294 */
3295 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3296
3297 rc = pci_dev_reset(dev, 0);
3298
3299 pci_restore_state(dev);
3300
3301 return rc;
3302 }
3303 EXPORT_SYMBOL_GPL(pci_reset_function);
3304
3305 /**
3306 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3307 * @dev: PCI device to query
3308 *
3309 * Returns mmrbc: maximum designed memory read count in bytes
3310 * or appropriate error value.
3311 */
pcix_get_max_mmrbc(struct pci_dev * dev)3312 int pcix_get_max_mmrbc(struct pci_dev *dev)
3313 {
3314 int cap;
3315 u32 stat;
3316
3317 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3318 if (!cap)
3319 return -EINVAL;
3320
3321 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3322 return -EINVAL;
3323
3324 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3325 }
3326 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3327
3328 /**
3329 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3330 * @dev: PCI device to query
3331 *
3332 * Returns mmrbc: maximum memory read count in bytes
3333 * or appropriate error value.
3334 */
pcix_get_mmrbc(struct pci_dev * dev)3335 int pcix_get_mmrbc(struct pci_dev *dev)
3336 {
3337 int cap;
3338 u16 cmd;
3339
3340 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3341 if (!cap)
3342 return -EINVAL;
3343
3344 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3345 return -EINVAL;
3346
3347 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3348 }
3349 EXPORT_SYMBOL(pcix_get_mmrbc);
3350
3351 /**
3352 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3353 * @dev: PCI device to query
3354 * @mmrbc: maximum memory read count in bytes
3355 * valid values are 512, 1024, 2048, 4096
3356 *
3357 * If possible sets maximum memory read byte count, some bridges have erratas
3358 * that prevent this.
3359 */
pcix_set_mmrbc(struct pci_dev * dev,int mmrbc)3360 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3361 {
3362 int cap;
3363 u32 stat, v, o;
3364 u16 cmd;
3365
3366 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3367 return -EINVAL;
3368
3369 v = ffs(mmrbc) - 10;
3370
3371 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3372 if (!cap)
3373 return -EINVAL;
3374
3375 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3376 return -EINVAL;
3377
3378 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3379 return -E2BIG;
3380
3381 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3382 return -EINVAL;
3383
3384 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3385 if (o != v) {
3386 if (v > o && dev->bus &&
3387 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3388 return -EIO;
3389
3390 cmd &= ~PCI_X_CMD_MAX_READ;
3391 cmd |= v << 2;
3392 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3393 return -EIO;
3394 }
3395 return 0;
3396 }
3397 EXPORT_SYMBOL(pcix_set_mmrbc);
3398
3399 /**
3400 * pcie_get_readrq - get PCI Express read request size
3401 * @dev: PCI device to query
3402 *
3403 * Returns maximum memory read request in bytes
3404 * or appropriate error value.
3405 */
pcie_get_readrq(struct pci_dev * dev)3406 int pcie_get_readrq(struct pci_dev *dev)
3407 {
3408 int ret, cap;
3409 u16 ctl;
3410
3411 cap = pci_pcie_cap(dev);
3412 if (!cap)
3413 return -EINVAL;
3414
3415 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3416 if (!ret)
3417 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3418
3419 return ret;
3420 }
3421 EXPORT_SYMBOL(pcie_get_readrq);
3422
3423 /**
3424 * pcie_set_readrq - set PCI Express maximum memory read request
3425 * @dev: PCI device to query
3426 * @rq: maximum memory read count in bytes
3427 * valid values are 128, 256, 512, 1024, 2048, 4096
3428 *
3429 * If possible sets maximum memory read request in bytes
3430 */
pcie_set_readrq(struct pci_dev * dev,int rq)3431 int pcie_set_readrq(struct pci_dev *dev, int rq)
3432 {
3433 int cap, err = -EINVAL;
3434 u16 ctl, v;
3435
3436 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3437 goto out;
3438
3439 cap = pci_pcie_cap(dev);
3440 if (!cap)
3441 goto out;
3442
3443 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3444 if (err)
3445 goto out;
3446 /*
3447 * If using the "performance" PCIe config, we clamp the
3448 * read rq size to the max packet size to prevent the
3449 * host bridge generating requests larger than we can
3450 * cope with
3451 */
3452 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3453 int mps = pcie_get_mps(dev);
3454
3455 if (mps < 0)
3456 return mps;
3457 if (mps < rq)
3458 rq = mps;
3459 }
3460
3461 v = (ffs(rq) - 8) << 12;
3462
3463 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
3464 ctl &= ~PCI_EXP_DEVCTL_READRQ;
3465 ctl |= v;
3466 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3467 }
3468
3469 out:
3470 return err;
3471 }
3472 EXPORT_SYMBOL(pcie_set_readrq);
3473
3474 /**
3475 * pcie_get_mps - get PCI Express maximum payload size
3476 * @dev: PCI device to query
3477 *
3478 * Returns maximum payload size in bytes
3479 * or appropriate error value.
3480 */
pcie_get_mps(struct pci_dev * dev)3481 int pcie_get_mps(struct pci_dev *dev)
3482 {
3483 int ret, cap;
3484 u16 ctl;
3485
3486 cap = pci_pcie_cap(dev);
3487 if (!cap)
3488 return -EINVAL;
3489
3490 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3491 if (!ret)
3492 ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3493
3494 return ret;
3495 }
3496
3497 /**
3498 * pcie_set_mps - set PCI Express maximum payload size
3499 * @dev: PCI device to query
3500 * @mps: maximum payload size in bytes
3501 * valid values are 128, 256, 512, 1024, 2048, 4096
3502 *
3503 * If possible sets maximum payload size
3504 */
pcie_set_mps(struct pci_dev * dev,int mps)3505 int pcie_set_mps(struct pci_dev *dev, int mps)
3506 {
3507 int cap, err = -EINVAL;
3508 u16 ctl, v;
3509
3510 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3511 goto out;
3512
3513 v = ffs(mps) - 8;
3514 if (v > dev->pcie_mpss)
3515 goto out;
3516 v <<= 5;
3517
3518 cap = pci_pcie_cap(dev);
3519 if (!cap)
3520 goto out;
3521
3522 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3523 if (err)
3524 goto out;
3525
3526 if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
3527 ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
3528 ctl |= v;
3529 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3530 }
3531 out:
3532 return err;
3533 }
3534
3535 /**
3536 * pci_select_bars - Make BAR mask from the type of resource
3537 * @dev: the PCI device for which BAR mask is made
3538 * @flags: resource type mask to be selected
3539 *
3540 * This helper routine makes bar mask from the type of resource.
3541 */
pci_select_bars(struct pci_dev * dev,unsigned long flags)3542 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3543 {
3544 int i, bars = 0;
3545 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3546 if (pci_resource_flags(dev, i) & flags)
3547 bars |= (1 << i);
3548 return bars;
3549 }
3550
3551 /**
3552 * pci_resource_bar - get position of the BAR associated with a resource
3553 * @dev: the PCI device
3554 * @resno: the resource number
3555 * @type: the BAR type to be filled in
3556 *
3557 * Returns BAR position in config space, or 0 if the BAR is invalid.
3558 */
pci_resource_bar(struct pci_dev * dev,int resno,enum pci_bar_type * type)3559 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3560 {
3561 int reg;
3562
3563 if (resno < PCI_ROM_RESOURCE) {
3564 *type = pci_bar_unknown;
3565 return PCI_BASE_ADDRESS_0 + 4 * resno;
3566 } else if (resno == PCI_ROM_RESOURCE) {
3567 *type = pci_bar_mem32;
3568 return dev->rom_base_reg;
3569 } else if (resno < PCI_BRIDGE_RESOURCES) {
3570 /* device specific resource */
3571 reg = pci_iov_resource_bar(dev, resno, type);
3572 if (reg)
3573 return reg;
3574 }
3575
3576 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
3577 return 0;
3578 }
3579
3580 /* Some architectures require additional programming to enable VGA */
3581 static arch_set_vga_state_t arch_set_vga_state;
3582
pci_register_set_vga_state(arch_set_vga_state_t func)3583 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3584 {
3585 arch_set_vga_state = func; /* NULL disables */
3586 }
3587
pci_set_vga_state_arch(struct pci_dev * dev,bool decode,unsigned int command_bits,u32 flags)3588 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3589 unsigned int command_bits, u32 flags)
3590 {
3591 if (arch_set_vga_state)
3592 return arch_set_vga_state(dev, decode, command_bits,
3593 flags);
3594 return 0;
3595 }
3596
3597 /**
3598 * pci_set_vga_state - set VGA decode state on device and parents if requested
3599 * @dev: the PCI device
3600 * @decode: true = enable decoding, false = disable decoding
3601 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3602 * @flags: traverse ancestors and change bridges
3603 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3604 */
pci_set_vga_state(struct pci_dev * dev,bool decode,unsigned int command_bits,u32 flags)3605 int pci_set_vga_state(struct pci_dev *dev, bool decode,
3606 unsigned int command_bits, u32 flags)
3607 {
3608 struct pci_bus *bus;
3609 struct pci_dev *bridge;
3610 u16 cmd;
3611 int rc;
3612
3613 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
3614
3615 /* ARCH specific VGA enables */
3616 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
3617 if (rc)
3618 return rc;
3619
3620 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3621 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3622 if (decode == true)
3623 cmd |= command_bits;
3624 else
3625 cmd &= ~command_bits;
3626 pci_write_config_word(dev, PCI_COMMAND, cmd);
3627 }
3628
3629 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
3630 return 0;
3631
3632 bus = dev->bus;
3633 while (bus) {
3634 bridge = bus->self;
3635 if (bridge) {
3636 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3637 &cmd);
3638 if (decode == true)
3639 cmd |= PCI_BRIDGE_CTL_VGA;
3640 else
3641 cmd &= ~PCI_BRIDGE_CTL_VGA;
3642 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3643 cmd);
3644 }
3645 bus = bus->parent;
3646 }
3647 return 0;
3648 }
3649
3650 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3651 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
3652 static DEFINE_SPINLOCK(resource_alignment_lock);
3653
3654 /**
3655 * pci_specified_resource_alignment - get resource alignment specified by user.
3656 * @dev: the PCI device to get
3657 *
3658 * RETURNS: Resource alignment if it is specified.
3659 * Zero if it is not specified.
3660 */
pci_specified_resource_alignment(struct pci_dev * dev)3661 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3662 {
3663 int seg, bus, slot, func, align_order, count;
3664 resource_size_t align = 0;
3665 char *p;
3666
3667 spin_lock(&resource_alignment_lock);
3668 p = resource_alignment_param;
3669 while (*p) {
3670 count = 0;
3671 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3672 p[count] == '@') {
3673 p += count + 1;
3674 } else {
3675 align_order = -1;
3676 }
3677 if (sscanf(p, "%x:%x:%x.%x%n",
3678 &seg, &bus, &slot, &func, &count) != 4) {
3679 seg = 0;
3680 if (sscanf(p, "%x:%x.%x%n",
3681 &bus, &slot, &func, &count) != 3) {
3682 /* Invalid format */
3683 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3684 p);
3685 break;
3686 }
3687 }
3688 p += count;
3689 if (seg == pci_domain_nr(dev->bus) &&
3690 bus == dev->bus->number &&
3691 slot == PCI_SLOT(dev->devfn) &&
3692 func == PCI_FUNC(dev->devfn)) {
3693 if (align_order == -1) {
3694 align = PAGE_SIZE;
3695 } else {
3696 align = 1 << align_order;
3697 }
3698 /* Found */
3699 break;
3700 }
3701 if (*p != ';' && *p != ',') {
3702 /* End of param or invalid format */
3703 break;
3704 }
3705 p++;
3706 }
3707 spin_unlock(&resource_alignment_lock);
3708 return align;
3709 }
3710
3711 /**
3712 * pci_is_reassigndev - check if specified PCI is target device to reassign
3713 * @dev: the PCI device to check
3714 *
3715 * RETURNS: non-zero for PCI device is a target device to reassign,
3716 * or zero is not.
3717 */
pci_is_reassigndev(struct pci_dev * dev)3718 int pci_is_reassigndev(struct pci_dev *dev)
3719 {
3720 return (pci_specified_resource_alignment(dev) != 0);
3721 }
3722
3723 /*
3724 * This function disables memory decoding and releases memory resources
3725 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
3726 * It also rounds up size to specified alignment.
3727 * Later on, the kernel will assign page-aligned memory resource back
3728 * to the device.
3729 */
pci_reassigndev_resource_alignment(struct pci_dev * dev)3730 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
3731 {
3732 int i;
3733 struct resource *r;
3734 resource_size_t align, size;
3735 u16 command;
3736
3737 if (!pci_is_reassigndev(dev))
3738 return;
3739
3740 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
3741 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
3742 dev_warn(&dev->dev,
3743 "Can't reassign resources to host bridge.\n");
3744 return;
3745 }
3746
3747 dev_info(&dev->dev,
3748 "Disabling memory decoding and releasing memory resources.\n");
3749 pci_read_config_word(dev, PCI_COMMAND, &command);
3750 command &= ~PCI_COMMAND_MEMORY;
3751 pci_write_config_word(dev, PCI_COMMAND, command);
3752
3753 align = pci_specified_resource_alignment(dev);
3754 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
3755 r = &dev->resource[i];
3756 if (!(r->flags & IORESOURCE_MEM))
3757 continue;
3758 size = resource_size(r);
3759 if (size < align) {
3760 size = align;
3761 dev_info(&dev->dev,
3762 "Rounding up size of resource #%d to %#llx.\n",
3763 i, (unsigned long long)size);
3764 }
3765 r->end = size - 1;
3766 r->start = 0;
3767 }
3768 /* Need to disable bridge's resource window,
3769 * to enable the kernel to reassign new resource
3770 * window later on.
3771 */
3772 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3773 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
3774 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
3775 r = &dev->resource[i];
3776 if (!(r->flags & IORESOURCE_MEM))
3777 continue;
3778 r->end = resource_size(r) - 1;
3779 r->start = 0;
3780 }
3781 pci_disable_bridge_window(dev);
3782 }
3783 }
3784
pci_set_resource_alignment_param(const char * buf,size_t count)3785 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3786 {
3787 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3788 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3789 spin_lock(&resource_alignment_lock);
3790 strncpy(resource_alignment_param, buf, count);
3791 resource_alignment_param[count] = '\0';
3792 spin_unlock(&resource_alignment_lock);
3793 return count;
3794 }
3795
pci_get_resource_alignment_param(char * buf,size_t size)3796 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3797 {
3798 size_t count;
3799 spin_lock(&resource_alignment_lock);
3800 count = snprintf(buf, size, "%s", resource_alignment_param);
3801 spin_unlock(&resource_alignment_lock);
3802 return count;
3803 }
3804
pci_resource_alignment_show(struct bus_type * bus,char * buf)3805 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3806 {
3807 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3808 }
3809
pci_resource_alignment_store(struct bus_type * bus,const char * buf,size_t count)3810 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3811 const char *buf, size_t count)
3812 {
3813 return pci_set_resource_alignment_param(buf, count);
3814 }
3815
3816 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3817 pci_resource_alignment_store);
3818
pci_resource_alignment_sysfs_init(void)3819 static int __init pci_resource_alignment_sysfs_init(void)
3820 {
3821 return bus_create_file(&pci_bus_type,
3822 &bus_attr_resource_alignment);
3823 }
3824
3825 late_initcall(pci_resource_alignment_sysfs_init);
3826
pci_no_domains(void)3827 static void __devinit pci_no_domains(void)
3828 {
3829 #ifdef CONFIG_PCI_DOMAINS
3830 pci_domains_supported = 0;
3831 #endif
3832 }
3833
3834 /**
3835 * pci_ext_cfg_enabled - can we access extended PCI config space?
3836 * @dev: The PCI device of the root bridge.
3837 *
3838 * Returns 1 if we can access PCI extended config space (offsets
3839 * greater than 0xff). This is the default implementation. Architecture
3840 * implementations can override this.
3841 */
pci_ext_cfg_avail(struct pci_dev * dev)3842 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
3843 {
3844 return 1;
3845 }
3846
pci_fixup_cardbus(struct pci_bus * bus)3847 void __weak pci_fixup_cardbus(struct pci_bus *bus)
3848 {
3849 }
3850 EXPORT_SYMBOL(pci_fixup_cardbus);
3851
pci_setup(char * str)3852 static int __init pci_setup(char *str)
3853 {
3854 while (str) {
3855 char *k = strchr(str, ',');
3856 if (k)
3857 *k++ = 0;
3858 if (*str && (str = pcibios_setup(str)) && *str) {
3859 if (!strcmp(str, "nomsi")) {
3860 pci_no_msi();
3861 } else if (!strcmp(str, "noaer")) {
3862 pci_no_aer();
3863 } else if (!strncmp(str, "realloc=", 8)) {
3864 pci_realloc_get_opt(str + 8);
3865 } else if (!strncmp(str, "realloc", 7)) {
3866 pci_realloc_get_opt("on");
3867 } else if (!strcmp(str, "nodomains")) {
3868 pci_no_domains();
3869 } else if (!strncmp(str, "noari", 5)) {
3870 pcie_ari_disabled = true;
3871 } else if (!strncmp(str, "cbiosize=", 9)) {
3872 pci_cardbus_io_size = memparse(str + 9, &str);
3873 } else if (!strncmp(str, "cbmemsize=", 10)) {
3874 pci_cardbus_mem_size = memparse(str + 10, &str);
3875 } else if (!strncmp(str, "resource_alignment=", 19)) {
3876 pci_set_resource_alignment_param(str + 19,
3877 strlen(str + 19));
3878 } else if (!strncmp(str, "ecrc=", 5)) {
3879 pcie_ecrc_get_policy(str + 5);
3880 } else if (!strncmp(str, "hpiosize=", 9)) {
3881 pci_hotplug_io_size = memparse(str + 9, &str);
3882 } else if (!strncmp(str, "hpmemsize=", 10)) {
3883 pci_hotplug_mem_size = memparse(str + 10, &str);
3884 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
3885 pcie_bus_config = PCIE_BUS_TUNE_OFF;
3886 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
3887 pcie_bus_config = PCIE_BUS_SAFE;
3888 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
3889 pcie_bus_config = PCIE_BUS_PERFORMANCE;
3890 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
3891 pcie_bus_config = PCIE_BUS_PEER2PEER;
3892 } else {
3893 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3894 str);
3895 }
3896 }
3897 str = k;
3898 }
3899 return 0;
3900 }
3901 early_param("pci", pci_setup);
3902
3903 EXPORT_SYMBOL(pci_reenable_device);
3904 EXPORT_SYMBOL(pci_enable_device_io);
3905 EXPORT_SYMBOL(pci_enable_device_mem);
3906 EXPORT_SYMBOL(pci_enable_device);
3907 EXPORT_SYMBOL(pcim_enable_device);
3908 EXPORT_SYMBOL(pcim_pin_device);
3909 EXPORT_SYMBOL(pci_disable_device);
3910 EXPORT_SYMBOL(pci_find_capability);
3911 EXPORT_SYMBOL(pci_bus_find_capability);
3912 EXPORT_SYMBOL(pci_release_regions);
3913 EXPORT_SYMBOL(pci_request_regions);
3914 EXPORT_SYMBOL(pci_request_regions_exclusive);
3915 EXPORT_SYMBOL(pci_release_region);
3916 EXPORT_SYMBOL(pci_request_region);
3917 EXPORT_SYMBOL(pci_request_region_exclusive);
3918 EXPORT_SYMBOL(pci_release_selected_regions);
3919 EXPORT_SYMBOL(pci_request_selected_regions);
3920 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3921 EXPORT_SYMBOL(pci_set_master);
3922 EXPORT_SYMBOL(pci_clear_master);
3923 EXPORT_SYMBOL(pci_set_mwi);
3924 EXPORT_SYMBOL(pci_try_set_mwi);
3925 EXPORT_SYMBOL(pci_clear_mwi);
3926 EXPORT_SYMBOL_GPL(pci_intx);
3927 EXPORT_SYMBOL(pci_assign_resource);
3928 EXPORT_SYMBOL(pci_find_parent_resource);
3929 EXPORT_SYMBOL(pci_select_bars);
3930
3931 EXPORT_SYMBOL(pci_set_power_state);
3932 EXPORT_SYMBOL(pci_save_state);
3933 EXPORT_SYMBOL(pci_restore_state);
3934 EXPORT_SYMBOL(pci_pme_capable);
3935 EXPORT_SYMBOL(pci_pme_active);
3936 EXPORT_SYMBOL(pci_wake_from_d3);
3937 EXPORT_SYMBOL(pci_target_state);
3938 EXPORT_SYMBOL(pci_prepare_to_sleep);
3939 EXPORT_SYMBOL(pci_back_from_sleep);
3940 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
3941