1 /*
2 * $Id: pci.h,v 1.87 1998/10/11 15:13:12 mj Exp $
3 *
4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
15 */
16
17 #ifndef LINUX_PCI_H
18 #define LINUX_PCI_H
19
20 /*
21 * Under PCI, each device has 256 bytes of configuration address space,
22 * of which the first 64 bytes are standardized as follows:
23 */
24 #define PCI_VENDOR_ID 0x00 /* 16 bits */
25 #define PCI_DEVICE_ID 0x02 /* 16 bits */
26 #define PCI_COMMAND 0x04 /* 16 bits */
27 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
28 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
29 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
30 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
31 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
32 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
33 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
34 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
35 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
36 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
37 #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
38
39 #define PCI_STATUS 0x06 /* 16 bits */
40 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
41 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
42 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
43 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
44 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
45 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
46 #define PCI_STATUS_DEVSEL_FAST 0x000
47 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
48 #define PCI_STATUS_DEVSEL_SLOW 0x400
49 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
50 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
51 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
52 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
53 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
54
55 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
56 revision */
57 #define PCI_REVISION_ID 0x08 /* Revision ID */
58 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
59 #define PCI_CLASS_DEVICE 0x0a /* Device class */
60
61 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
62 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
63 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
64 #define PCI_HEADER_TYPE_NORMAL 0
65 #define PCI_HEADER_TYPE_BRIDGE 1
66 #define PCI_HEADER_TYPE_CARDBUS 2
67
68 #define PCI_BIST 0x0f /* 8 bits */
69 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
70 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
71 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
72
73 /*
74 * Base addresses specify locations in memory or I/O space.
75 * Decoded size can be determined by writing a value of
76 * 0xffffffff to the register, and reading it back. Only
77 * 1 bits are decoded.
78 */
79 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
80 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
81 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
82 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
83 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
84 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
85 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
86 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
87 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
88 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
89 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
90 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
91 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
92 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
93 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
94 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
95 /* bit 1 is reserved if address_space = 1 */
96
97 /* Header type 0 (normal devices) */
98 #define PCI_CARDBUS_CIS 0x28
99 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
100 #define PCI_SUBSYSTEM_ID 0x2e
101 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
102 #define PCI_ROM_ADDRESS_ENABLE 0x01
103 #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
104
105 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
106
107 /* 0x35-0x3b are reserved */
108 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
109 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
110 #define PCI_MIN_GNT 0x3e /* 8 bits */
111 #define PCI_MAX_LAT 0x3f /* 8 bits */
112
113 /* Header type 1 (PCI-to-PCI bridges) */
114 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
115 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
116 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
117 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
118 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
119 #define PCI_IO_LIMIT 0x1d
120 #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
121 #define PCI_IO_RANGE_TYPE_16 0x00
122 #define PCI_IO_RANGE_TYPE_32 0x01
123 #define PCI_IO_RANGE_MASK (~0x0fUL)
124 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
125 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
126 #define PCI_MEMORY_LIMIT 0x22
127 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
128 #define PCI_MEMORY_RANGE_MASK (~0x0fUL)
129 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
130 #define PCI_PREF_MEMORY_LIMIT 0x26
131 #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
132 #define PCI_PREF_RANGE_TYPE_32 0x00
133 #define PCI_PREF_RANGE_TYPE_64 0x01
134 #define PCI_PREF_RANGE_MASK (~0x0fUL)
135 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
136 #define PCI_PREF_LIMIT_UPPER32 0x2c
137 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
138 #define PCI_IO_LIMIT_UPPER16 0x32
139 /* 0x34 same as for htype 0 */
140 /* 0x35-0x3b is reserved */
141 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
142 /* 0x3c-0x3d are same as for htype 0 */
143 #define PCI_BRIDGE_CONTROL 0x3e
144 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
145 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
146 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
147 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
148 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
149 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
150 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
151
152 /* Header type 2 (CardBus bridges) */
153 #define PCI_CB_CAPABILITY_LIST 0x14
154 /* 0x15 reserved */
155 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
156 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
157 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
158 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
159 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
160 #define PCI_CB_MEMORY_BASE_0 0x1c
161 #define PCI_CB_MEMORY_LIMIT_0 0x20
162 #define PCI_CB_MEMORY_BASE_1 0x24
163 #define PCI_CB_MEMORY_LIMIT_1 0x28
164 #define PCI_CB_IO_BASE_0 0x2c
165 #define PCI_CB_IO_BASE_0_HI 0x2e
166 #define PCI_CB_IO_LIMIT_0 0x30
167 #define PCI_CB_IO_LIMIT_0_HI 0x32
168 #define PCI_CB_IO_BASE_1 0x34
169 #define PCI_CB_IO_BASE_1_HI 0x36
170 #define PCI_CB_IO_LIMIT_1 0x38
171 #define PCI_CB_IO_LIMIT_1_HI 0x3a
172 #define PCI_CB_IO_RANGE_MASK (~0x03UL)
173 /* 0x3c-0x3d are same as for htype 0 */
174 #define PCI_CB_BRIDGE_CONTROL 0x3e
175 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
176 #define PCI_CB_BRIDGE_CTL_SERR 0x02
177 #define PCI_CB_BRIDGE_CTL_ISA 0x04
178 #define PCI_CB_BRIDGE_CTL_VGA 0x08
179 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
180 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
181 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
182 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
183 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
184 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
185 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
186 #define PCI_CB_SUBSYSTEM_ID 0x42
187 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
188 /* 0x48-0x7f reserved */
189
190 /* Capability lists */
191
192 #define PCI_CAP_LIST_ID 0 /* Capability ID */
193 #define PCI_CAP_ID_PM 0x01 /* Power Management */
194 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
195 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
196 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
197 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
198 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
199 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
200 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
201 #define PCI_CAP_ID_EXP 0x10 /* PCI-EXPRESS */
202 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
203 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
204 #define PCI_CAP_SIZEOF 4
205
206 /* Power Management Registers */
207
208 #define PCI_PM_PMC 2 /* PM Capabilities Register */
209 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
210 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
211 #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
212 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
213 #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
214 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
215 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
216 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
217 #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
218 #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
219 #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
220 #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
221 #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
222 #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
223 #define PCI_PM_CTRL 4 /* PM control and status register */
224 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
225 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
226 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
227 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
228 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
229 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
230 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
231 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
232 #define PCI_PM_DATA_REGISTER 7 /* (??) */
233 #define PCI_PM_SIZEOF 8
234
235 /* AGP registers */
236
237 #define PCI_AGP_VERSION 2 /* BCD version number */
238 #define PCI_AGP_RFU 3 /* Rest of capability flags */
239 #define PCI_AGP_STATUS 4 /* Status register */
240 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
241 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
242 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
243 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
244 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
245 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
246 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
247 #define PCI_AGP_COMMAND 8 /* Control register */
248 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
249 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
250 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
251 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
252 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
253 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
254 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
255 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
256 #define PCI_AGP_SIZEOF 12
257
258 /* Slot Identification */
259
260 #define PCI_SID_ESR 2 /* Expansion Slot Register */
261 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
262 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
263 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
264
265 /* Message Signalled Interrupts registers */
266
267 #define PCI_MSI_FLAGS 2 /* Various flags */
268 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
269 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
270 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
271 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
272 #define PCI_MSI_RFU 3 /* Rest of capability flags */
273 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
274 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
275 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
276 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
277
278 /* CompactPCI Hotswap Register */
279
280 #define PCI_CHSWP_CSR 2 /* Control and Status Register */
281 #define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
282 #define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
283 #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
284 #define PCI_CHSWP_LOO 0x08 /* LED On / Off */
285 #define PCI_CHSWP_PI 0x30 /* Programming Interface */
286 #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
287 #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
288
289 /* PCI-X registers */
290
291 #define PCI_X_CMD 2 /* Modes & Features */
292 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
293 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
294 #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
295 #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
296 #define PCI_X_DEVFN 4 /* A copy of devfn. */
297 #define PCI_X_BUSNR 5 /* Bus segment number */
298 #define PCI_X_STATUS 6 /* PCI-X capabilities */
299 #define PCI_X_STATUS_64BIT 0x0001 /* 64-bit device */
300 #define PCI_X_STATUS_133MHZ 0x0002 /* 133 MHz capable */
301 #define PCI_X_STATUS_SPL_DISC 0x0004 /* Split Completion Discarded */
302 #define PCI_X_STATUS_UNX_SPL 0x0008 /* Unexpected Split Completion */
303 #define PCI_X_STATUS_COMPLEX 0x0010 /* Device Complexity */
304 #define PCI_X_STATUS_MAX_READ 0x0060 /* Designed Maximum Memory Read Count */
305 #define PCI_X_STATUS_MAX_SPLIT 0x0380 /* Design Max Outstanding Split Trans */
306 #define PCI_X_STATUS_MAX_CUM 0x1c00 /* Designed Max Cumulative Read Size */
307 #define PCI_X_STATUS_SPL_ERR 0x2000 /* Rcvd Split Completion Error Msg */
308
309 /* Include the ID list */
310
311 #include <linux/pci_ids.h>
312
313 /*
314 * The PCI interface treats multi-function devices as independent
315 * devices. The slot/function address of each device is encoded
316 * in a single byte as follows:
317 *
318 * 7:3 = slot
319 * 2:0 = function
320 */
321 #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
322 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
323 #define PCI_FUNC(devfn) ((devfn) & 0x07)
324
325 /* Ioctls for /proc/bus/pci/X/Y nodes. */
326 #define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8)
327 #define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */
328 #define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */
329 #define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */
330 #define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */
331
332 #ifdef __KERNEL__
333
334 #include <linux/types.h>
335 #include <linux/config.h>
336 #include <linux/ioport.h>
337 #include <linux/list.h>
338 #include <linux/errno.h>
339
340 /* File state for mmap()s on /proc/bus/pci/X/Y */
341 enum pci_mmap_state {
342 pci_mmap_io,
343 pci_mmap_mem
344 };
345
346 /* This defines the direction arg to the DMA mapping routines. */
347 #define PCI_DMA_BIDIRECTIONAL 0
348 #define PCI_DMA_TODEVICE 1
349 #define PCI_DMA_FROMDEVICE 2
350 #define PCI_DMA_NONE 3
351
352 #define DEVICE_COUNT_COMPATIBLE 4
353 #define DEVICE_COUNT_IRQ 2
354 #define DEVICE_COUNT_DMA 2
355 #define DEVICE_COUNT_RESOURCE 12
356
357 #define PCI_ANY_ID (~0)
358
359 #define pci_present pcibios_present
360
361
362 #define pci_for_each_dev_reverse(dev) \
363 for(dev = pci_dev_g(pci_devices.prev); dev != pci_dev_g(&pci_devices); dev = pci_dev_g(dev->global_list.prev))
364
365 #define pci_for_each_bus(bus) \
366 for(bus = pci_bus_b(pci_root_buses.next); bus != pci_bus_b(&pci_root_buses); bus = pci_bus_b(bus->node.next))
367
368 /*
369 * The pci_dev structure is used to describe both PCI and ISAPnP devices.
370 */
371 struct pci_dev {
372 struct list_head global_list; /* node in list of all PCI devices */
373 struct list_head bus_list; /* node in per-bus list */
374 struct pci_bus *bus; /* bus this device is on */
375 struct pci_bus *subordinate; /* bus this device bridges to */
376
377 void *sysdata; /* hook for sys-specific extension */
378 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
379
380 unsigned int devfn; /* encoded device & function index */
381 unsigned short vendor;
382 unsigned short device;
383 unsigned short subsystem_vendor;
384 unsigned short subsystem_device;
385 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
386 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
387 u8 rom_base_reg; /* which config register controls the ROM */
388
389 struct pci_driver *driver; /* which driver has allocated this device */
390 void *driver_data; /* data private to the driver */
391 u64 dma_mask; /* Mask of the bits of bus address this
392 device implements. Normally this is
393 0xffffffff. You only need to change
394 this if your device has broken DMA
395 or supports 64-bit transfers. */
396
397 u32 current_state; /* Current operating state. In ACPI-speak,
398 this is D0-D3, D0 being fully functional,
399 and D3 being off. */
400
401 /* device is compatible with these IDs */
402 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE];
403 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE];
404
405 /*
406 * Instead of touching interrupt line and base address registers
407 * directly, use the values stored here. They might be different!
408 */
409 unsigned int irq;
410 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
411 struct resource dma_resource[DEVICE_COUNT_DMA];
412 struct resource irq_resource[DEVICE_COUNT_IRQ];
413
414 char name[90]; /* device name */
415 char slot_name[8]; /* slot name */
416 int active; /* ISAPnP: device is active */
417 int ro; /* ISAPnP: read only */
418 unsigned short regs; /* ISAPnP: supported registers */
419
420 /* These fields are used by common fixups */
421 unsigned short transparent:1; /* Transparent PCI bridge */
422
423 int (*prepare)(struct pci_dev *dev); /* ISAPnP hooks */
424 int (*activate)(struct pci_dev *dev);
425 int (*deactivate)(struct pci_dev *dev);
426 };
427
428 #define pci_dev_g(n) list_entry(n, struct pci_dev, global_list)
429 #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list)
430
431 /*
432 * For PCI devices, the region numbers are assigned this way:
433 *
434 * 0-5 standard PCI regions
435 * 6 expansion ROM
436 * 7-10 bridges: address space assigned to buses behind the bridge
437 */
438
439 #define PCI_ROM_RESOURCE 6
440 #define PCI_BRIDGE_RESOURCES 7
441 #define PCI_NUM_RESOURCES 11
442
443 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
444
445 struct pci_bus {
446 struct list_head node; /* node in list of buses */
447 struct pci_bus *parent; /* parent bus this bridge is on */
448 struct list_head children; /* list of child buses */
449 struct list_head devices; /* list of devices on this bus */
450 struct pci_dev *self; /* bridge device as seen by parent */
451 struct resource *resource[4]; /* address space routed to this bus */
452
453 struct pci_ops *ops; /* configuration access functions */
454 void *sysdata; /* hook for sys-specific extension */
455 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
456
457 unsigned char number; /* bus number */
458 unsigned char primary; /* number of primary bridge */
459 unsigned char secondary; /* number of secondary bridge */
460 unsigned char subordinate; /* max number of subordinate buses */
461
462 char name[48];
463 unsigned short vendor;
464 unsigned short device;
465 unsigned int serial; /* serial number */
466 unsigned char pnpver; /* Plug & Play version */
467 unsigned char productver; /* product version */
468 unsigned char checksum; /* if zero - checksum passed */
469 unsigned char pad1;
470 };
471
472 #define pci_bus_b(n) list_entry(n, struct pci_bus, node)
473
474 extern struct list_head pci_root_buses; /* list of all known PCI buses */
475 extern struct list_head pci_devices; /* list of all devices */
476
477 extern struct proc_dir_entry *proc_bus_pci_dir;
478 /*
479 * Error values that may be returned by PCI functions.
480 */
481 #define PCIBIOS_SUCCESSFUL 0x00
482 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
483 #define PCIBIOS_BAD_VENDOR_ID 0x83
484 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
485 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
486 #define PCIBIOS_SET_FAILED 0x88
487 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
488
489 /* Low-level architecture-dependent routines */
490
491 struct pci_ops {
492 int (*read_byte)(struct pci_dev *, int where, u8 *val);
493 int (*read_word)(struct pci_dev *, int where, u16 *val);
494 int (*read_dword)(struct pci_dev *, int where, u32 *val);
495 int (*write_byte)(struct pci_dev *, int where, u8 val);
496 int (*write_word)(struct pci_dev *, int where, u16 val);
497 int (*write_dword)(struct pci_dev *, int where, u32 val);
498 };
499
500 struct pbus_set_ranges_data
501 {
502 unsigned long io_start, io_end;
503 unsigned long mem_start, mem_end;
504 unsigned long prefetch_start, prefetch_end;
505 };
506
507 struct pci_device_id {
508 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
509 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
510 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
511 unsigned long driver_data; /* Data private to the driver */
512 };
513
514 struct pci_driver {
515 struct list_head node;
516 char *name;
517 const struct pci_device_id *id_table; /* NULL if wants all devices */
518 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
519 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
520 int (*save_state) (struct pci_dev *dev, u32 state); /* Save Device Context */
521 int (*suspend) (struct pci_dev *dev, u32 state); /* Device suspended */
522 int (*resume) (struct pci_dev *dev); /* Device woken up */
523 int (*enable_wake) (struct pci_dev *dev, u32 state, int enable); /* Enable wake event */
524 };
525
526 /**
527 * PCI_DEVICE - macro used to describe a specific pci device
528 * @vend: the 16 bit PCI Vendor ID
529 * @dev: the 16 bit PCI Device ID
530 *
531 * This macro is used to create a struct pci_device_id that matches a
532 * specific device. The subvendor and subdevice fields will be set to
533 * PCI_ANY_ID.
534 */
535 #define PCI_DEVICE(vend,dev) \
536 .vendor = (vend), .device = (dev), \
537 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
538
539 /**
540 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
541 * @dev_class: the class, subclass, prog-if triple for this device
542 * @dev_class_mask: the class mask for this device
543 *
544 * This macro is used to create a struct pci_device_id that matches a
545 * specific PCI class. The vendor, device, subvendor, and subdevice
546 * fields will be set to PCI_ANY_ID.
547 */
548 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
549 .class = (dev_class), .class_mask = (dev_class_mask), \
550 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
551 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
552
553 /* these external functions are only available when PCI support is enabled */
554 #ifdef CONFIG_PCI
555
556 #define pci_for_each_dev(dev) \
557 for(dev = pci_dev_g(pci_devices.next); dev != pci_dev_g(&pci_devices); dev = pci_dev_g(dev->global_list.next))
558
559 void pcibios_init(void);
560 void pcibios_fixup_bus(struct pci_bus *);
561 int pcibios_enable_device(struct pci_dev *, int mask);
562 char *pcibios_setup (char *str);
563
564 /* Used only when drivers/pci/setup.c is used */
565 void pcibios_align_resource(void *, struct resource *,
566 unsigned long, unsigned long);
567 void pcibios_update_resource(struct pci_dev *, struct resource *,
568 struct resource *, int);
569 void pcibios_update_irq(struct pci_dev *, int irq);
570 void pcibios_fixup_pbus_ranges(struct pci_bus *, struct pbus_set_ranges_data *);
571
572 /* Backward compatibility, don't use in new code! */
573
574 int pcibios_present(void);
575 int pcibios_read_config_byte (unsigned char bus, unsigned char dev_fn,
576 unsigned char where, unsigned char *val);
577 int pcibios_read_config_word (unsigned char bus, unsigned char dev_fn,
578 unsigned char where, unsigned short *val);
579 int pcibios_read_config_dword (unsigned char bus, unsigned char dev_fn,
580 unsigned char where, unsigned int *val);
581 int pcibios_write_config_byte (unsigned char bus, unsigned char dev_fn,
582 unsigned char where, unsigned char val);
583 int pcibios_write_config_word (unsigned char bus, unsigned char dev_fn,
584 unsigned char where, unsigned short val);
585 int pcibios_write_config_dword (unsigned char bus, unsigned char dev_fn,
586 unsigned char where, unsigned int val);
587 int pcibios_find_class (unsigned int class_code, unsigned short index, unsigned char *bus, unsigned char *dev_fn);
588 int pcibios_find_device (unsigned short vendor, unsigned short dev_id,
589 unsigned short index, unsigned char *bus,
590 unsigned char *dev_fn);
591
592 /* Generic PCI functions used internally */
593
594 void pci_init(void);
595 int pci_bus_exists(const struct list_head *list, int nr);
596 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
597 struct pci_bus *pci_alloc_primary_bus(int bus);
598 struct pci_dev *pci_scan_device(struct pci_dev *temp);
599 struct pci_dev *pci_scan_slot(struct pci_dev *temp);
600 int pci_proc_attach_device(struct pci_dev *dev);
601 int pci_proc_detach_device(struct pci_dev *dev);
602 int pci_proc_attach_bus(struct pci_bus *bus);
603 int pci_proc_detach_bus(struct pci_bus *bus);
604 void pci_name_device(struct pci_dev *dev);
605 char *pci_class_name(u32 class);
606 void pci_read_bridge_bases(struct pci_bus *child);
607 struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res);
608 int pci_setup_device(struct pci_dev *dev);
609 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
610
611 /* Generic PCI functions exported to card drivers */
612
613 struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from);
614 struct pci_dev *pci_find_subsys (unsigned int vendor, unsigned int device,
615 unsigned int ss_vendor, unsigned int ss_device,
616 const struct pci_dev *from);
617 struct pci_dev *pci_find_class (unsigned int class, const struct pci_dev *from);
618 struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
619 int pci_find_capability (struct pci_dev *dev, int cap);
620
621 int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val);
622 int pci_read_config_word(struct pci_dev *dev, int where, u16 *val);
623 int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val);
624 int pci_write_config_byte(struct pci_dev *dev, int where, u8 val);
625 int pci_write_config_word(struct pci_dev *dev, int where, u16 val);
626 int pci_write_config_dword(struct pci_dev *dev, int where, u32 val);
627
628 int pci_enable_device(struct pci_dev *dev);
629 int pci_enable_device_bars(struct pci_dev *dev, int mask);
630 void pci_disable_device(struct pci_dev *dev);
631 void pci_set_master(struct pci_dev *dev);
632 #define HAVE_PCI_SET_MWI
633 int pci_set_mwi(struct pci_dev *dev);
634 void pci_clear_mwi(struct pci_dev *dev);
635 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
636 int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask);
637 int pci_assign_resource(struct pci_dev *dev, int i);
638
639 /* Power management related routines */
640 int pci_save_state(struct pci_dev *dev, u32 *buffer);
641 int pci_restore_state(struct pci_dev *dev, u32 *buffer);
642 int pci_set_power_state(struct pci_dev *dev, int state);
643 int pci_enable_wake(struct pci_dev *dev, u32 state, int enable);
644
645 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
646
647 int pci_claim_resource(struct pci_dev *, int);
648 void pci_assign_unassigned_resources(void);
649 void pdev_enable_device(struct pci_dev *);
650 void pdev_sort_resources(struct pci_dev *, struct resource_list *);
651 unsigned long pci_bridge_check_io(struct pci_dev *);
652 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
653 int (*)(struct pci_dev *, u8, u8));
654 #define HAVE_PCI_REQ_REGIONS 2
655 int pci_request_regions(struct pci_dev *, char *);
656 void pci_release_regions(struct pci_dev *);
657 int pci_request_region(struct pci_dev *, int, char *);
658 void pci_release_region(struct pci_dev *, int);
659
660 /* New-style probing supporting hot-pluggable devices */
661 int pci_register_driver(struct pci_driver *);
662 void pci_unregister_driver(struct pci_driver *);
663 void pci_insert_device(struct pci_dev *, struct pci_bus *);
664 void pci_remove_device(struct pci_dev *);
665 struct pci_driver *pci_dev_driver(const struct pci_dev *);
666 const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev);
667 void pci_announce_device_to_drivers(struct pci_dev *);
668 unsigned int pci_do_scan_bus(struct pci_bus *bus);
669 struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr);
670
671 /* kmem_cache style wrapper around pci_alloc_consistent() */
672 struct pci_pool *pci_pool_create (const char *name, struct pci_dev *dev,
673 size_t size, size_t align, size_t allocation, int flags);
674 void pci_pool_destroy (struct pci_pool *pool);
675
676 void *pci_pool_alloc (struct pci_pool *pool, int flags, dma_addr_t *handle);
677 void pci_pool_free (struct pci_pool *pool, void *vaddr, dma_addr_t addr);
678
679 #endif /* CONFIG_PCI */
680
681 /* Include architecture-dependent settings and functions */
682
683 #include <asm/pci.h>
684
685 /*
686 * If the system does not have PCI, clearly these return errors. Define
687 * these as simple inline functions to avoid hair in drivers.
688 */
689
690 #ifndef CONFIG_PCI
pcibios_present(void)691 static inline int pcibios_present(void) { return 0; }
pcibios_find_class(unsigned int class_code,unsigned short index,unsigned char * bus,unsigned char * dev_fn)692 static inline int pcibios_find_class (unsigned int class_code, unsigned short index, unsigned char *bus, unsigned char *dev_fn)
693 { return PCIBIOS_DEVICE_NOT_FOUND; }
694
695 #define _PCI_NOP(o,s,t) \
696 static inline int pcibios_##o##_config_##s (u8 bus, u8 dfn, u8 where, t val) \
697 { return PCIBIOS_FUNC_NOT_SUPPORTED; } \
698 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \
699 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
700 #define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \
701 _PCI_NOP(o,word,u16 x) \
702 _PCI_NOP(o,dword,u32 x)
703 _PCI_NOP_ALL(read, *)
704 _PCI_NOP_ALL(write,)
705
pci_find_device(unsigned int vendor,unsigned int device,const struct pci_dev * from)706 static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
707 { return NULL; }
708
pci_find_class(unsigned int class,const struct pci_dev * from)709 static inline struct pci_dev *pci_find_class(unsigned int class, const struct pci_dev *from)
710 { return NULL; }
711
pci_find_slot(unsigned int bus,unsigned int devfn)712 static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn)
713 { return NULL; }
714
pci_find_subsys(unsigned int vendor,unsigned int device,unsigned int ss_vendor,unsigned int ss_device,const struct pci_dev * from)715 static inline struct pci_dev *pci_find_subsys(unsigned int vendor, unsigned int device,
716 unsigned int ss_vendor, unsigned int ss_device, const struct pci_dev *from)
717 { return NULL; }
718
pci_set_master(struct pci_dev * dev)719 static inline void pci_set_master(struct pci_dev *dev) { }
pci_enable_device_bars(struct pci_dev * dev,int mask)720 static inline int pci_enable_device_bars(struct pci_dev *dev, int mask) { return -EBUSY; }
pci_enable_device(struct pci_dev * dev)721 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
pci_disable_device(struct pci_dev * dev)722 static inline void pci_disable_device(struct pci_dev *dev) { }
pci_module_init(struct pci_driver * drv)723 static inline int pci_module_init(struct pci_driver *drv) { return -ENODEV; }
pci_set_dma_mask(struct pci_dev * dev,u64 mask)724 static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
pci_dac_set_dma_mask(struct pci_dev * dev,u64 mask)725 static inline int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; }
pci_assign_resource(struct pci_dev * dev,int i)726 static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;}
pci_register_driver(struct pci_driver * drv)727 static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
pci_unregister_driver(struct pci_driver * drv)728 static inline void pci_unregister_driver(struct pci_driver *drv) { }
scsi_to_pci_dma_dir(unsigned char scsi_dir)729 static inline int scsi_to_pci_dma_dir(unsigned char scsi_dir) { return scsi_dir; }
pci_find_capability(struct pci_dev * dev,int cap)730 static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
pci_match_device(const struct pci_device_id * ids,const struct pci_dev * dev)731 static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
732
733 /* Power management related routines */
pci_save_state(struct pci_dev * dev,u32 * buffer)734 static inline int pci_save_state(struct pci_dev *dev, u32 *buffer) { return 0; }
pci_restore_state(struct pci_dev * dev,u32 * buffer)735 static inline int pci_restore_state(struct pci_dev *dev, u32 *buffer) { return 0; }
pci_set_power_state(struct pci_dev * dev,int state)736 static inline int pci_set_power_state(struct pci_dev *dev, int state) { return 0; }
pci_enable_wake(struct pci_dev * dev,u32 state,int enable)737 static inline int pci_enable_wake(struct pci_dev *dev, u32 state, int enable) { return 0; }
738
739 #define pci_for_each_dev(dev) \
740 for(dev = NULL; 0; )
741
742 #else
743
744 /*
745 * a helper function which helps ensure correct pci_driver
746 * setup and cleanup for commonly-encountered hotplug/modular cases
747 *
748 * This MUST stay in a header, as it checks for -DMODULE
749 */
pci_module_init(struct pci_driver * drv)750 static inline int pci_module_init(struct pci_driver *drv)
751 {
752 int rc = pci_register_driver (drv);
753
754 if (rc > 0)
755 return 0;
756
757 /* iff CONFIG_HOTPLUG and built into kernel, we should
758 * leave the driver around for future hotplug events.
759 * For the module case, a hotplug daemon of some sort
760 * should load a module in response to an insert event. */
761 #if defined(CONFIG_HOTPLUG) && !defined(MODULE)
762 if (rc == 0)
763 return 0;
764 #else
765 if (rc == 0)
766 rc = -ENODEV;
767 #endif
768
769 /* if we get here, we need to clean up pci driver instance
770 * and return some sort of error */
771 pci_unregister_driver (drv);
772
773 return rc;
774 }
775
776 #endif /* !CONFIG_PCI */
777
778 /* these helpers provide future and backwards compatibility
779 * for accessing popular PCI BAR info */
780 #define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start)
781 #define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end)
782 #define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags)
783 #define pci_resource_len(dev,bar) \
784 ((pci_resource_start((dev),(bar)) == 0 && \
785 pci_resource_end((dev),(bar)) == \
786 pci_resource_start((dev),(bar))) ? 0 : \
787 \
788 (pci_resource_end((dev),(bar)) - \
789 pci_resource_start((dev),(bar)) + 1))
790
791 /* Similar to the helpers above, these manipulate per-pci_dev
792 * driver-specific data. Currently stored as pci_dev::driver_data,
793 * a void pointer, but it is not present on older kernels.
794 */
pci_get_drvdata(struct pci_dev * pdev)795 static inline void *pci_get_drvdata (struct pci_dev *pdev)
796 {
797 return pdev->driver_data;
798 }
799
pci_set_drvdata(struct pci_dev * pdev,void * data)800 static inline void pci_set_drvdata (struct pci_dev *pdev, void *data)
801 {
802 pdev->driver_data = data;
803 }
804
pci_name(struct pci_dev * pdev)805 static inline char *pci_name(struct pci_dev *pdev)
806 {
807 return pdev->slot_name;
808 }
809
810 /*
811 * The world is not perfect and supplies us with broken PCI devices.
812 * For at least a part of these bugs we need a work-around, so both
813 * generic (drivers/pci/quirks.c) and per-architecture code can define
814 * fixup hooks to be called for particular buggy devices.
815 */
816
817 struct pci_fixup {
818 int pass;
819 u16 vendor, device; /* You can use PCI_ANY_ID here of course */
820 void (*hook)(struct pci_dev *dev);
821 };
822
823 extern struct pci_fixup pcibios_fixups[];
824
825 #define PCI_FIXUP_HEADER 1 /* Called immediately after reading configuration header */
826 #define PCI_FIXUP_FINAL 2 /* Final phase of device fixups */
827
828 void pci_fixup_device(int pass, struct pci_dev *dev);
829
830 extern int pci_pci_problems;
831 #define PCIPCI_FAIL 1
832 #define PCIPCI_TRITON 2
833 #define PCIPCI_NATOMA 4
834 #define PCIPCI_VIAETBF 8
835 #define PCIPCI_VSFX 16
836 #define PCIPCI_ALIMAGIK 32
837
838 #endif /* __KERNEL__ */
839 #endif /* LINUX_PCI_H */
840