1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef DRIVERS_PCI_H
3 #define DRIVERS_PCI_H
4
5 #include <linux/pci.h>
6
7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
8 #define MAX_NR_DEVFNS 256
9
10 #define PCI_FIND_CAP_TTL 48
11
12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
13
14 extern const unsigned char pcie_link_speed[];
15 extern bool pci_early_dump;
16
17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
18 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
19
20 /* Functions internal to the PCI core code */
21
22 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
23 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
24 void pci_cleanup_rom(struct pci_dev *dev);
25 #ifdef CONFIG_DMI
26 extern const struct attribute_group pci_dev_smbios_attr_group;
27 #endif
28
29 enum pci_mmap_api {
30 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
31 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
32 };
33 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
34 enum pci_mmap_api mmap_api);
35
36 bool pci_reset_supported(struct pci_dev *dev);
37 void pci_init_reset_methods(struct pci_dev *dev);
38 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
39 int pci_bus_error_reset(struct pci_dev *dev);
40
41 struct pci_cap_saved_data {
42 u16 cap_nr;
43 bool cap_extended;
44 unsigned int size;
45 u32 data[];
46 };
47
48 struct pci_cap_saved_state {
49 struct hlist_node next;
50 struct pci_cap_saved_data cap;
51 };
52
53 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
54 void pci_free_cap_save_buffers(struct pci_dev *dev);
55 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
56 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
57 u16 cap, unsigned int size);
58 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
59 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
60 u16 cap);
61
62 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
63 #define PCI_PM_D3HOT_WAIT 10 /* msec */
64 #define PCI_PM_D3COLD_WAIT 100 /* msec */
65
66 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
67 void pci_refresh_power_state(struct pci_dev *dev);
68 int pci_power_up(struct pci_dev *dev);
69 void pci_disable_enabled_device(struct pci_dev *dev);
70 int pci_finish_runtime_suspend(struct pci_dev *dev);
71 void pcie_clear_device_status(struct pci_dev *dev);
72 void pcie_clear_root_pme_status(struct pci_dev *dev);
73 bool pci_check_pme_status(struct pci_dev *dev);
74 void pci_pme_wakeup_bus(struct pci_bus *bus);
75 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
76 void pci_pme_restore(struct pci_dev *dev);
77 bool pci_dev_need_resume(struct pci_dev *dev);
78 void pci_dev_adjust_pme(struct pci_dev *dev);
79 void pci_dev_complete_resume(struct pci_dev *pci_dev);
80 void pci_config_pm_runtime_get(struct pci_dev *dev);
81 void pci_config_pm_runtime_put(struct pci_dev *dev);
82 void pci_pm_init(struct pci_dev *dev);
83 void pci_ea_init(struct pci_dev *dev);
84 void pci_msi_init(struct pci_dev *dev);
85 void pci_msix_init(struct pci_dev *dev);
86 bool pci_bridge_d3_possible(struct pci_dev *dev);
87 void pci_bridge_d3_update(struct pci_dev *dev);
88 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
89 void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
90
pci_wakeup_event(struct pci_dev * dev)91 static inline void pci_wakeup_event(struct pci_dev *dev)
92 {
93 /* Wait 100 ms before the system can be put into a sleep state. */
94 pm_wakeup_event(&dev->dev, 100);
95 }
96
pci_has_subordinate(struct pci_dev * pci_dev)97 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
98 {
99 return !!(pci_dev->subordinate);
100 }
101
pci_power_manageable(struct pci_dev * pci_dev)102 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
103 {
104 /*
105 * Currently we allow normal PCI devices and PCI bridges transition
106 * into D3 if their bridge_d3 is set.
107 */
108 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
109 }
110
pcie_downstream_port(const struct pci_dev * dev)111 static inline bool pcie_downstream_port(const struct pci_dev *dev)
112 {
113 int type = pci_pcie_type(dev);
114
115 return type == PCI_EXP_TYPE_ROOT_PORT ||
116 type == PCI_EXP_TYPE_DOWNSTREAM ||
117 type == PCI_EXP_TYPE_PCIE_BRIDGE;
118 }
119
120 void pci_vpd_init(struct pci_dev *dev);
121 void pci_vpd_release(struct pci_dev *dev);
122 extern const struct attribute_group pci_dev_vpd_attr_group;
123
124 /* PCI Virtual Channel */
125 int pci_save_vc_state(struct pci_dev *dev);
126 void pci_restore_vc_state(struct pci_dev *dev);
127 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
128
129 /* PCI /proc functions */
130 #ifdef CONFIG_PROC_FS
131 int pci_proc_attach_device(struct pci_dev *dev);
132 int pci_proc_detach_device(struct pci_dev *dev);
133 int pci_proc_detach_bus(struct pci_bus *bus);
134 #else
pci_proc_attach_device(struct pci_dev * dev)135 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_device(struct pci_dev * dev)136 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
pci_proc_detach_bus(struct pci_bus * bus)137 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
138 #endif
139
140 /* Functions for PCI Hotplug drivers to use */
141 int pci_hp_add_bridge(struct pci_dev *dev);
142
143 #ifdef HAVE_PCI_LEGACY
144 void pci_create_legacy_files(struct pci_bus *bus);
145 void pci_remove_legacy_files(struct pci_bus *bus);
146 #else
pci_create_legacy_files(struct pci_bus * bus)147 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
pci_remove_legacy_files(struct pci_bus * bus)148 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
149 #endif
150
151 /* Lock for read/write access to pci device and bus lists */
152 extern struct rw_semaphore pci_bus_sem;
153 extern struct mutex pci_slot_mutex;
154
155 extern raw_spinlock_t pci_lock;
156
157 extern unsigned int pci_pm_d3hot_delay;
158
159 #ifdef CONFIG_PCI_MSI
160 void pci_no_msi(void);
161 #else
pci_no_msi(void)162 static inline void pci_no_msi(void) { }
163 #endif
164
165 void pci_realloc_get_opt(char *);
166
pci_no_d1d2(struct pci_dev * dev)167 static inline int pci_no_d1d2(struct pci_dev *dev)
168 {
169 unsigned int parent_dstates = 0;
170
171 if (dev->bus->self)
172 parent_dstates = dev->bus->self->no_d1d2;
173 return (dev->no_d1d2 || parent_dstates);
174
175 }
176 extern const struct attribute_group *pci_dev_groups[];
177 extern const struct attribute_group *pcibus_groups[];
178 extern const struct device_type pci_dev_type;
179 extern const struct attribute_group *pci_bus_groups[];
180
181 extern unsigned long pci_hotplug_io_size;
182 extern unsigned long pci_hotplug_mmio_size;
183 extern unsigned long pci_hotplug_mmio_pref_size;
184 extern unsigned long pci_hotplug_bus_size;
185
186 /**
187 * pci_match_one_device - Tell if a PCI device structure has a matching
188 * PCI device id structure
189 * @id: single PCI device id structure to match
190 * @dev: the PCI device structure to match against
191 *
192 * Returns the matching pci_device_id structure or %NULL if there is no match.
193 */
194 static inline const struct pci_device_id *
pci_match_one_device(const struct pci_device_id * id,const struct pci_dev * dev)195 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
196 {
197 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
198 (id->device == PCI_ANY_ID || id->device == dev->device) &&
199 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
200 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
201 !((id->class ^ dev->class) & id->class_mask))
202 return id;
203 return NULL;
204 }
205
206 /* PCI slot sysfs helper code */
207 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
208
209 extern struct kset *pci_slots_kset;
210
211 struct pci_slot_attribute {
212 struct attribute attr;
213 ssize_t (*show)(struct pci_slot *, char *);
214 ssize_t (*store)(struct pci_slot *, const char *, size_t);
215 };
216 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
217
218 enum pci_bar_type {
219 pci_bar_unknown, /* Standard PCI BAR probe */
220 pci_bar_io, /* An I/O port BAR */
221 pci_bar_mem32, /* A 32-bit memory BAR */
222 pci_bar_mem64, /* A 64-bit memory BAR */
223 };
224
225 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
226 void pci_put_host_bridge_device(struct device *dev);
227
228 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
229 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
230 int crs_timeout);
231 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
232 int crs_timeout);
233 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
234
235 int pci_setup_device(struct pci_dev *dev);
236 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
237 struct resource *res, unsigned int reg);
238 void pci_configure_ari(struct pci_dev *dev);
239 void __pci_bus_size_bridges(struct pci_bus *bus,
240 struct list_head *realloc_head);
241 void __pci_bus_assign_resources(const struct pci_bus *bus,
242 struct list_head *realloc_head,
243 struct list_head *fail_head);
244 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
245
246 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
247 void pci_disable_bridge_window(struct pci_dev *dev);
248 struct pci_bus *pci_bus_get(struct pci_bus *bus);
249 void pci_bus_put(struct pci_bus *bus);
250
251 /* PCIe link information from Link Capabilities 2 */
252 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
253 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
254 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
255 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
256 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
257 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
258 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
259 PCI_SPEED_UNKNOWN)
260
261 /* PCIe speed to Mb/s reduced by encoding overhead */
262 #define PCIE_SPEED2MBS_ENC(speed) \
263 ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \
264 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
265 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
266 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
267 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
268 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
269 0)
270
271 const char *pci_speed_string(enum pci_bus_speed speed);
272 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
273 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
274 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
275 enum pcie_link_width *width);
276 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
277 void pcie_report_downtraining(struct pci_dev *dev);
278 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
279
280 /* Single Root I/O Virtualization */
281 struct pci_sriov {
282 int pos; /* Capability position */
283 int nres; /* Number of resources */
284 u32 cap; /* SR-IOV Capabilities */
285 u16 ctrl; /* SR-IOV Control */
286 u16 total_VFs; /* Total VFs associated with the PF */
287 u16 initial_VFs; /* Initial VFs associated with the PF */
288 u16 num_VFs; /* Number of VFs available */
289 u16 offset; /* First VF Routing ID offset */
290 u16 stride; /* Following VF stride */
291 u16 vf_device; /* VF device ID */
292 u32 pgsz; /* Page size for BAR alignment */
293 u8 link; /* Function Dependency Link */
294 u8 max_VF_buses; /* Max buses consumed by VFs */
295 u16 driver_max_VFs; /* Max num VFs driver supports */
296 struct pci_dev *dev; /* Lowest numbered PF */
297 struct pci_dev *self; /* This PF */
298 u32 class; /* VF device */
299 u8 hdr_type; /* VF header type */
300 u16 subsystem_vendor; /* VF subsystem vendor */
301 u16 subsystem_device; /* VF subsystem device */
302 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
303 bool drivers_autoprobe; /* Auto probing of VFs by driver */
304 };
305
306 /**
307 * pci_dev_set_io_state - Set the new error state if possible.
308 *
309 * @dev: PCI device to set new error_state
310 * @new: the state we want dev to be in
311 *
312 * Must be called with device_lock held.
313 *
314 * Returns true if state has been changed to the requested state.
315 */
pci_dev_set_io_state(struct pci_dev * dev,pci_channel_state_t new)316 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
317 pci_channel_state_t new)
318 {
319 bool changed = false;
320
321 device_lock_assert(&dev->dev);
322 switch (new) {
323 case pci_channel_io_perm_failure:
324 switch (dev->error_state) {
325 case pci_channel_io_frozen:
326 case pci_channel_io_normal:
327 case pci_channel_io_perm_failure:
328 changed = true;
329 break;
330 }
331 break;
332 case pci_channel_io_frozen:
333 switch (dev->error_state) {
334 case pci_channel_io_frozen:
335 case pci_channel_io_normal:
336 changed = true;
337 break;
338 }
339 break;
340 case pci_channel_io_normal:
341 switch (dev->error_state) {
342 case pci_channel_io_frozen:
343 case pci_channel_io_normal:
344 changed = true;
345 break;
346 }
347 break;
348 }
349 if (changed)
350 dev->error_state = new;
351 return changed;
352 }
353
pci_dev_set_disconnected(struct pci_dev * dev,void * unused)354 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
355 {
356 device_lock(&dev->dev);
357 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
358 device_unlock(&dev->dev);
359
360 return 0;
361 }
362
pci_dev_is_disconnected(const struct pci_dev * dev)363 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
364 {
365 return dev->error_state == pci_channel_io_perm_failure;
366 }
367
368 /* pci_dev priv_flags */
369 #define PCI_DEV_ADDED 0
370 #define PCI_DPC_RECOVERED 1
371 #define PCI_DPC_RECOVERING 2
372
pci_dev_assign_added(struct pci_dev * dev,bool added)373 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
374 {
375 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
376 }
377
pci_dev_is_added(const struct pci_dev * dev)378 static inline bool pci_dev_is_added(const struct pci_dev *dev)
379 {
380 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
381 }
382
383 #ifdef CONFIG_PCIEAER
384 #include <linux/aer.h>
385
386 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
387
388 struct aer_err_info {
389 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
390 int error_dev_num;
391
392 unsigned int id:16;
393
394 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
395 unsigned int __pad1:5;
396 unsigned int multi_error_valid:1;
397
398 unsigned int first_error:5;
399 unsigned int __pad2:2;
400 unsigned int tlp_header_valid:1;
401
402 unsigned int status; /* COR/UNCOR Error Status */
403 unsigned int mask; /* COR/UNCOR Error Mask */
404 struct aer_header_log_regs tlp; /* TLP Header */
405 };
406
407 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
408 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
409 #endif /* CONFIG_PCIEAER */
410
411 #ifdef CONFIG_PCIEPORTBUS
412 /* Cached RCEC Endpoint Association */
413 struct rcec_ea {
414 u8 nextbusn;
415 u8 lastbusn;
416 u32 bitmap;
417 };
418 #endif
419
420 #ifdef CONFIG_PCIE_DPC
421 void pci_save_dpc_state(struct pci_dev *dev);
422 void pci_restore_dpc_state(struct pci_dev *dev);
423 void pci_dpc_init(struct pci_dev *pdev);
424 void dpc_process_error(struct pci_dev *pdev);
425 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
426 bool pci_dpc_recovered(struct pci_dev *pdev);
427 #else
pci_save_dpc_state(struct pci_dev * dev)428 static inline void pci_save_dpc_state(struct pci_dev *dev) {}
pci_restore_dpc_state(struct pci_dev * dev)429 static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
pci_dpc_init(struct pci_dev * pdev)430 static inline void pci_dpc_init(struct pci_dev *pdev) {}
pci_dpc_recovered(struct pci_dev * pdev)431 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
432 #endif
433
434 #ifdef CONFIG_PCIEPORTBUS
435 void pci_rcec_init(struct pci_dev *dev);
436 void pci_rcec_exit(struct pci_dev *dev);
437 void pcie_link_rcec(struct pci_dev *rcec);
438 void pcie_walk_rcec(struct pci_dev *rcec,
439 int (*cb)(struct pci_dev *, void *),
440 void *userdata);
441 #else
pci_rcec_init(struct pci_dev * dev)442 static inline void pci_rcec_init(struct pci_dev *dev) {}
pci_rcec_exit(struct pci_dev * dev)443 static inline void pci_rcec_exit(struct pci_dev *dev) {}
pcie_link_rcec(struct pci_dev * rcec)444 static inline void pcie_link_rcec(struct pci_dev *rcec) {}
pcie_walk_rcec(struct pci_dev * rcec,int (* cb)(struct pci_dev *,void *),void * userdata)445 static inline void pcie_walk_rcec(struct pci_dev *rcec,
446 int (*cb)(struct pci_dev *, void *),
447 void *userdata) {}
448 #endif
449
450 #ifdef CONFIG_PCI_ATS
451 /* Address Translation Service */
452 void pci_ats_init(struct pci_dev *dev);
453 void pci_restore_ats_state(struct pci_dev *dev);
454 #else
pci_ats_init(struct pci_dev * d)455 static inline void pci_ats_init(struct pci_dev *d) { }
pci_restore_ats_state(struct pci_dev * dev)456 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
457 #endif /* CONFIG_PCI_ATS */
458
459 #ifdef CONFIG_PCI_PRI
460 void pci_pri_init(struct pci_dev *dev);
461 void pci_restore_pri_state(struct pci_dev *pdev);
462 #else
pci_pri_init(struct pci_dev * dev)463 static inline void pci_pri_init(struct pci_dev *dev) { }
pci_restore_pri_state(struct pci_dev * pdev)464 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
465 #endif
466
467 #ifdef CONFIG_PCI_PASID
468 void pci_pasid_init(struct pci_dev *dev);
469 void pci_restore_pasid_state(struct pci_dev *pdev);
470 #else
pci_pasid_init(struct pci_dev * dev)471 static inline void pci_pasid_init(struct pci_dev *dev) { }
pci_restore_pasid_state(struct pci_dev * pdev)472 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
473 #endif
474
475 #ifdef CONFIG_PCI_IOV
476 int pci_iov_init(struct pci_dev *dev);
477 void pci_iov_release(struct pci_dev *dev);
478 void pci_iov_remove(struct pci_dev *dev);
479 void pci_iov_update_resource(struct pci_dev *dev, int resno);
480 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
481 void pci_restore_iov_state(struct pci_dev *dev);
482 int pci_iov_bus_range(struct pci_bus *bus);
483 extern const struct attribute_group sriov_pf_dev_attr_group;
484 extern const struct attribute_group sriov_vf_dev_attr_group;
485 #else
pci_iov_init(struct pci_dev * dev)486 static inline int pci_iov_init(struct pci_dev *dev)
487 {
488 return -ENODEV;
489 }
pci_iov_release(struct pci_dev * dev)490 static inline void pci_iov_release(struct pci_dev *dev)
491
492 {
493 }
pci_iov_remove(struct pci_dev * dev)494 static inline void pci_iov_remove(struct pci_dev *dev)
495 {
496 }
pci_restore_iov_state(struct pci_dev * dev)497 static inline void pci_restore_iov_state(struct pci_dev *dev)
498 {
499 }
pci_iov_bus_range(struct pci_bus * bus)500 static inline int pci_iov_bus_range(struct pci_bus *bus)
501 {
502 return 0;
503 }
504
505 #endif /* CONFIG_PCI_IOV */
506
507 #ifdef CONFIG_PCIE_PTM
508 void pci_save_ptm_state(struct pci_dev *dev);
509 void pci_restore_ptm_state(struct pci_dev *dev);
510 void pci_disable_ptm(struct pci_dev *dev);
511 #else
pci_save_ptm_state(struct pci_dev * dev)512 static inline void pci_save_ptm_state(struct pci_dev *dev) { }
pci_restore_ptm_state(struct pci_dev * dev)513 static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
pci_disable_ptm(struct pci_dev * dev)514 static inline void pci_disable_ptm(struct pci_dev *dev) { }
515 #endif
516
517 unsigned long pci_cardbus_resource_alignment(struct resource *);
518
pci_resource_alignment(struct pci_dev * dev,struct resource * res)519 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
520 struct resource *res)
521 {
522 #ifdef CONFIG_PCI_IOV
523 int resno = res - dev->resource;
524
525 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
526 return pci_sriov_resource_alignment(dev, resno);
527 #endif
528 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
529 return pci_cardbus_resource_alignment(res);
530 return resource_alignment(res);
531 }
532
533 void pci_acs_init(struct pci_dev *dev);
534 #ifdef CONFIG_PCI_QUIRKS
535 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
536 int pci_dev_specific_enable_acs(struct pci_dev *dev);
537 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
538 #else
pci_dev_specific_acs_enabled(struct pci_dev * dev,u16 acs_flags)539 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
540 u16 acs_flags)
541 {
542 return -ENOTTY;
543 }
pci_dev_specific_enable_acs(struct pci_dev * dev)544 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
545 {
546 return -ENOTTY;
547 }
pci_dev_specific_disable_acs_redir(struct pci_dev * dev)548 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
549 {
550 return -ENOTTY;
551 }
552 #endif
553
554 /* PCI error reporting and recovery */
555 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
556 pci_channel_state_t state,
557 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
558
559 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
560 #ifdef CONFIG_PCIEASPM
561 void pcie_aspm_init_link_state(struct pci_dev *pdev);
562 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
563 void pcie_aspm_pm_state_change(struct pci_dev *pdev);
564 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
565 #else
pcie_aspm_init_link_state(struct pci_dev * pdev)566 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
pcie_aspm_exit_link_state(struct pci_dev * pdev)567 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
pcie_aspm_pm_state_change(struct pci_dev * pdev)568 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
pcie_aspm_powersave_config_link(struct pci_dev * pdev)569 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
570 #endif
571
572 #ifdef CONFIG_PCIE_ECRC
573 void pcie_set_ecrc_checking(struct pci_dev *dev);
574 void pcie_ecrc_get_policy(char *str);
575 #else
pcie_set_ecrc_checking(struct pci_dev * dev)576 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
pcie_ecrc_get_policy(char * str)577 static inline void pcie_ecrc_get_policy(char *str) { }
578 #endif
579
580 #ifdef CONFIG_PCIE_PTM
581 void pci_ptm_init(struct pci_dev *dev);
582 #else
pci_ptm_init(struct pci_dev * dev)583 static inline void pci_ptm_init(struct pci_dev *dev) { }
584 #endif
585
586 struct pci_dev_reset_methods {
587 u16 vendor;
588 u16 device;
589 int (*reset)(struct pci_dev *dev, bool probe);
590 };
591
592 struct pci_reset_fn_method {
593 int (*reset_fn)(struct pci_dev *pdev, bool probe);
594 char *name;
595 };
596
597 #ifdef CONFIG_PCI_QUIRKS
598 int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
599 #else
pci_dev_specific_reset(struct pci_dev * dev,bool probe)600 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
601 {
602 return -ENOTTY;
603 }
604 #endif
605
606 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
607 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
608 struct resource *res);
609 #else
acpi_get_rc_resources(struct device * dev,const char * hid,u16 segment,struct resource * res)610 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
611 u16 segment, struct resource *res)
612 {
613 return -ENODEV;
614 }
615 #endif
616
617 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
618 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
pci_rebar_size_to_bytes(int size)619 static inline u64 pci_rebar_size_to_bytes(int size)
620 {
621 return 1ULL << (size + 20);
622 }
623
624 struct device_node;
625
626 #ifdef CONFIG_OF
627 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
628 int of_get_pci_domain_nr(struct device_node *node);
629 int of_pci_get_max_link_speed(struct device_node *node);
630 u32 of_pci_get_slot_power_limit(struct device_node *node,
631 u8 *slot_power_limit_value,
632 u8 *slot_power_limit_scale);
633 void pci_set_of_node(struct pci_dev *dev);
634 void pci_release_of_node(struct pci_dev *dev);
635 void pci_set_bus_of_node(struct pci_bus *bus);
636 void pci_release_bus_of_node(struct pci_bus *bus);
637
638 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
639
640 #else
641 static inline int
of_pci_parse_bus_range(struct device_node * node,struct resource * res)642 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
643 {
644 return -EINVAL;
645 }
646
647 static inline int
of_get_pci_domain_nr(struct device_node * node)648 of_get_pci_domain_nr(struct device_node *node)
649 {
650 return -1;
651 }
652
653 static inline int
of_pci_get_max_link_speed(struct device_node * node)654 of_pci_get_max_link_speed(struct device_node *node)
655 {
656 return -EINVAL;
657 }
658
659 static inline u32
of_pci_get_slot_power_limit(struct device_node * node,u8 * slot_power_limit_value,u8 * slot_power_limit_scale)660 of_pci_get_slot_power_limit(struct device_node *node,
661 u8 *slot_power_limit_value,
662 u8 *slot_power_limit_scale)
663 {
664 if (slot_power_limit_value)
665 *slot_power_limit_value = 0;
666 if (slot_power_limit_scale)
667 *slot_power_limit_scale = 0;
668 return 0;
669 }
670
pci_set_of_node(struct pci_dev * dev)671 static inline void pci_set_of_node(struct pci_dev *dev) { }
pci_release_of_node(struct pci_dev * dev)672 static inline void pci_release_of_node(struct pci_dev *dev) { }
pci_set_bus_of_node(struct pci_bus * bus)673 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
pci_release_bus_of_node(struct pci_bus * bus)674 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
675
devm_of_pci_bridge_init(struct device * dev,struct pci_host_bridge * bridge)676 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
677 {
678 return 0;
679 }
680
681 #endif /* CONFIG_OF */
682
683 #ifdef CONFIG_PCIEAER
684 void pci_no_aer(void);
685 void pci_aer_init(struct pci_dev *dev);
686 void pci_aer_exit(struct pci_dev *dev);
687 extern const struct attribute_group aer_stats_attr_group;
688 void pci_aer_clear_fatal_status(struct pci_dev *dev);
689 int pci_aer_clear_status(struct pci_dev *dev);
690 int pci_aer_raw_clear_status(struct pci_dev *dev);
691 #else
pci_no_aer(void)692 static inline void pci_no_aer(void) { }
pci_aer_init(struct pci_dev * d)693 static inline void pci_aer_init(struct pci_dev *d) { }
pci_aer_exit(struct pci_dev * d)694 static inline void pci_aer_exit(struct pci_dev *d) { }
pci_aer_clear_fatal_status(struct pci_dev * dev)695 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
pci_aer_clear_status(struct pci_dev * dev)696 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
pci_aer_raw_clear_status(struct pci_dev * dev)697 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
698 #endif
699
700 #ifdef CONFIG_ACPI
701 int pci_acpi_program_hp_params(struct pci_dev *dev);
702 extern const struct attribute_group pci_dev_acpi_attr_group;
703 void pci_set_acpi_fwnode(struct pci_dev *dev);
704 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
705 bool acpi_pci_power_manageable(struct pci_dev *dev);
706 bool acpi_pci_bridge_d3(struct pci_dev *dev);
707 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
708 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
709 void acpi_pci_refresh_power_state(struct pci_dev *dev);
710 int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
711 bool acpi_pci_need_resume(struct pci_dev *dev);
712 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
713 #else
pci_dev_acpi_reset(struct pci_dev * dev,bool probe)714 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
715 {
716 return -ENOTTY;
717 }
pci_set_acpi_fwnode(struct pci_dev * dev)718 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {}
pci_acpi_program_hp_params(struct pci_dev * dev)719 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
720 {
721 return -ENODEV;
722 }
acpi_pci_power_manageable(struct pci_dev * dev)723 static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
724 {
725 return false;
726 }
acpi_pci_bridge_d3(struct pci_dev * dev)727 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
728 {
729 return false;
730 }
acpi_pci_set_power_state(struct pci_dev * dev,pci_power_t state)731 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
732 {
733 return -ENODEV;
734 }
acpi_pci_get_power_state(struct pci_dev * dev)735 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
736 {
737 return PCI_UNKNOWN;
738 }
acpi_pci_refresh_power_state(struct pci_dev * dev)739 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) {}
acpi_pci_wakeup(struct pci_dev * dev,bool enable)740 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
741 {
742 return -ENODEV;
743 }
acpi_pci_need_resume(struct pci_dev * dev)744 static inline bool acpi_pci_need_resume(struct pci_dev *dev)
745 {
746 return false;
747 }
acpi_pci_choose_state(struct pci_dev * pdev)748 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
749 {
750 return PCI_POWER_ERROR;
751 }
752 #endif
753
754 #ifdef CONFIG_PCIEASPM
755 extern const struct attribute_group aspm_ctrl_attr_group;
756 #endif
757
758 extern const struct attribute_group pci_dev_reset_method_attr_group;
759
760 #ifdef CONFIG_X86_INTEL_MID
761 bool pci_use_mid_pm(void);
762 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
763 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
764 #else
pci_use_mid_pm(void)765 static inline bool pci_use_mid_pm(void)
766 {
767 return false;
768 }
mid_pci_set_power_state(struct pci_dev * pdev,pci_power_t state)769 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
770 {
771 return -ENODEV;
772 }
mid_pci_get_power_state(struct pci_dev * pdev)773 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
774 {
775 return PCI_UNKNOWN;
776 }
777 #endif
778
779 #endif /* DRIVERS_PCI_H */
780