1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * This file contains work-arounds for many known PCI hardware bugs.
4  * Devices present only on certain architectures (host bridges et cetera)
5  * should be handled in arch-specific code.
6  *
7  * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8  *
9  * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10  *
11  * Init/reset quirks for USB host controllers should be in the USB quirks
12  * file, where their drivers can use them.
13  */
14 
15 #include <linux/bitfield.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/export.h>
19 #include <linux/pci.h>
20 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
24 #include <linux/dmi.h>
25 #include <linux/ioport.h>
26 #include <linux/sched.h>
27 #include <linux/ktime.h>
28 #include <linux/mm.h>
29 #include <linux/nvme.h>
30 #include <linux/platform_data/x86/apple.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/suspend.h>
33 #include <linux/switchtec.h>
34 #include "pci.h"
35 
36 /*
37  * Retrain the link of a downstream PCIe port by hand if necessary.
38  *
39  * This is needed at least where a downstream port of the ASMedia ASM2824
40  * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304
41  * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 >
42  * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched
43  * board.
44  *
45  * In such a configuration the switches are supposed to negotiate the link
46  * speed of preferably 5.0GT/s, falling back to 2.5GT/s.  However the link
47  * continues switching between the two speeds indefinitely and the data
48  * link layer never reaches the active state, with link training reported
49  * repeatedly active ~84% of the time.  Forcing the target link speed to
50  * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to
51  * each other correctly however.  And more interestingly retraining with a
52  * higher target link speed afterwards lets the two successfully negotiate
53  * 5.0GT/s.
54  *
55  * With the ASM2824 we can rely on the otherwise optional Data Link Layer
56  * Link Active status bit and in the failed link training scenario it will
57  * be off along with the Link Bandwidth Management Status indicating that
58  * hardware has changed the link speed or width in an attempt to correct
59  * unreliable link operation.  For a port that has been left unconnected
60  * both bits will be clear.  So use this information to detect the problem
61  * rather than polling the Link Training bit and watching out for flips or
62  * at least the active status.
63  *
64  * Since the exact nature of the problem isn't known and in principle this
65  * could trigger where an ASM2824 device is downstream rather upstream,
66  * apply this erratum workaround to any downstream ports as long as they
67  * support Link Active reporting and have the Link Control 2 register.
68  * Restrict the speed to 2.5GT/s then with the Target Link Speed field,
69  * request a retrain and wait 200ms for the data link to go up.
70  *
71  * If this turns out successful and we know by the Vendor:Device ID it is
72  * safe to do so, then lift the restriction, letting the devices negotiate
73  * a higher speed.  Also check for a similar 2.5GT/s speed restriction the
74  * firmware may have already arranged and lift it with ports that already
75  * report their data link being up.
76  *
77  * Return TRUE if the link has been successfully retrained, otherwise FALSE.
78  */
pcie_failed_link_retrain(struct pci_dev * dev)79 bool pcie_failed_link_retrain(struct pci_dev *dev)
80 {
81 	static const struct pci_device_id ids[] = {
82 		{ PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */
83 		{}
84 	};
85 	u16 lnksta, lnkctl2;
86 
87 	if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) ||
88 	    !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting)
89 		return false;
90 
91 	pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2);
92 	pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
93 	if ((lnksta & (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_DLLLA)) ==
94 	    PCI_EXP_LNKSTA_LBMS) {
95 		pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n");
96 
97 		lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS;
98 		lnkctl2 |= PCI_EXP_LNKCTL2_TLS_2_5GT;
99 		pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2);
100 
101 		if (pcie_retrain_link(dev, false)) {
102 			pci_info(dev, "retraining failed\n");
103 			return false;
104 		}
105 
106 		pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
107 	}
108 
109 	if ((lnksta & PCI_EXP_LNKSTA_DLLLA) &&
110 	    (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT &&
111 	    pci_match_id(ids, dev)) {
112 		u32 lnkcap;
113 
114 		pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n");
115 		pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
116 		lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS;
117 		lnkctl2 |= lnkcap & PCI_EXP_LNKCAP_SLS;
118 		pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, lnkctl2);
119 
120 		if (pcie_retrain_link(dev, false)) {
121 			pci_info(dev, "retraining failed\n");
122 			return false;
123 		}
124 	}
125 
126 	return true;
127 }
128 
fixup_debug_start(struct pci_dev * dev,void (* fn)(struct pci_dev * dev))129 static ktime_t fixup_debug_start(struct pci_dev *dev,
130 				 void (*fn)(struct pci_dev *dev))
131 {
132 	if (initcall_debug)
133 		pci_info(dev, "calling  %pS @ %i\n", fn, task_pid_nr(current));
134 
135 	return ktime_get();
136 }
137 
fixup_debug_report(struct pci_dev * dev,ktime_t calltime,void (* fn)(struct pci_dev * dev))138 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
139 			       void (*fn)(struct pci_dev *dev))
140 {
141 	ktime_t delta, rettime;
142 	unsigned long long duration;
143 
144 	rettime = ktime_get();
145 	delta = ktime_sub(rettime, calltime);
146 	duration = (unsigned long long) ktime_to_ns(delta) >> 10;
147 	if (initcall_debug || duration > 10000)
148 		pci_info(dev, "%pS took %lld usecs\n", fn, duration);
149 }
150 
pci_do_fixups(struct pci_dev * dev,struct pci_fixup * f,struct pci_fixup * end)151 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
152 			  struct pci_fixup *end)
153 {
154 	ktime_t calltime;
155 
156 	for (; f < end; f++)
157 		if ((f->class == (u32) (dev->class >> f->class_shift) ||
158 		     f->class == (u32) PCI_ANY_ID) &&
159 		    (f->vendor == dev->vendor ||
160 		     f->vendor == (u16) PCI_ANY_ID) &&
161 		    (f->device == dev->device ||
162 		     f->device == (u16) PCI_ANY_ID)) {
163 			void (*hook)(struct pci_dev *dev);
164 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
165 			hook = offset_to_ptr(&f->hook_offset);
166 #else
167 			hook = f->hook;
168 #endif
169 			calltime = fixup_debug_start(dev, hook);
170 			hook(dev);
171 			fixup_debug_report(dev, calltime, hook);
172 		}
173 }
174 
175 extern struct pci_fixup __start_pci_fixups_early[];
176 extern struct pci_fixup __end_pci_fixups_early[];
177 extern struct pci_fixup __start_pci_fixups_header[];
178 extern struct pci_fixup __end_pci_fixups_header[];
179 extern struct pci_fixup __start_pci_fixups_final[];
180 extern struct pci_fixup __end_pci_fixups_final[];
181 extern struct pci_fixup __start_pci_fixups_enable[];
182 extern struct pci_fixup __end_pci_fixups_enable[];
183 extern struct pci_fixup __start_pci_fixups_resume[];
184 extern struct pci_fixup __end_pci_fixups_resume[];
185 extern struct pci_fixup __start_pci_fixups_resume_early[];
186 extern struct pci_fixup __end_pci_fixups_resume_early[];
187 extern struct pci_fixup __start_pci_fixups_suspend[];
188 extern struct pci_fixup __end_pci_fixups_suspend[];
189 extern struct pci_fixup __start_pci_fixups_suspend_late[];
190 extern struct pci_fixup __end_pci_fixups_suspend_late[];
191 
192 static bool pci_apply_fixup_final_quirks;
193 
pci_fixup_device(enum pci_fixup_pass pass,struct pci_dev * dev)194 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
195 {
196 	struct pci_fixup *start, *end;
197 
198 	switch (pass) {
199 	case pci_fixup_early:
200 		start = __start_pci_fixups_early;
201 		end = __end_pci_fixups_early;
202 		break;
203 
204 	case pci_fixup_header:
205 		start = __start_pci_fixups_header;
206 		end = __end_pci_fixups_header;
207 		break;
208 
209 	case pci_fixup_final:
210 		if (!pci_apply_fixup_final_quirks)
211 			return;
212 		start = __start_pci_fixups_final;
213 		end = __end_pci_fixups_final;
214 		break;
215 
216 	case pci_fixup_enable:
217 		start = __start_pci_fixups_enable;
218 		end = __end_pci_fixups_enable;
219 		break;
220 
221 	case pci_fixup_resume:
222 		start = __start_pci_fixups_resume;
223 		end = __end_pci_fixups_resume;
224 		break;
225 
226 	case pci_fixup_resume_early:
227 		start = __start_pci_fixups_resume_early;
228 		end = __end_pci_fixups_resume_early;
229 		break;
230 
231 	case pci_fixup_suspend:
232 		start = __start_pci_fixups_suspend;
233 		end = __end_pci_fixups_suspend;
234 		break;
235 
236 	case pci_fixup_suspend_late:
237 		start = __start_pci_fixups_suspend_late;
238 		end = __end_pci_fixups_suspend_late;
239 		break;
240 
241 	default:
242 		/* stupid compiler warning, you would think with an enum... */
243 		return;
244 	}
245 	pci_do_fixups(dev, start, end);
246 }
247 EXPORT_SYMBOL(pci_fixup_device);
248 
pci_apply_final_quirks(void)249 static int __init pci_apply_final_quirks(void)
250 {
251 	struct pci_dev *dev = NULL;
252 	u8 cls = 0;
253 	u8 tmp;
254 
255 	if (pci_cache_line_size)
256 		pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
257 
258 	pci_apply_fixup_final_quirks = true;
259 	for_each_pci_dev(dev) {
260 		pci_fixup_device(pci_fixup_final, dev);
261 		/*
262 		 * If arch hasn't set it explicitly yet, use the CLS
263 		 * value shared by all PCI devices.  If there's a
264 		 * mismatch, fall back to the default value.
265 		 */
266 		if (!pci_cache_line_size) {
267 			pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
268 			if (!cls)
269 				cls = tmp;
270 			if (!tmp || cls == tmp)
271 				continue;
272 
273 			pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
274 			         cls << 2, tmp << 2,
275 				 pci_dfl_cache_line_size << 2);
276 			pci_cache_line_size = pci_dfl_cache_line_size;
277 		}
278 	}
279 
280 	if (!pci_cache_line_size) {
281 		pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
282 			pci_dfl_cache_line_size << 2);
283 		pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
284 	}
285 
286 	return 0;
287 }
288 fs_initcall_sync(pci_apply_final_quirks);
289 
290 /*
291  * Decoding should be disabled for a PCI device during BAR sizing to avoid
292  * conflict. But doing so may cause problems on host bridge and perhaps other
293  * key system devices. For devices that need to have mmio decoding always-on,
294  * we need to set the dev->mmio_always_on bit.
295  */
quirk_mmio_always_on(struct pci_dev * dev)296 static void quirk_mmio_always_on(struct pci_dev *dev)
297 {
298 	dev->mmio_always_on = 1;
299 }
300 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
301 				PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
302 
303 /*
304  * The Mellanox Tavor device gives false positive parity errors.  Disable
305  * parity error reporting.
306  */
307 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity);
308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity);
309 
310 /*
311  * Deal with broken BIOSes that neglect to enable passive release,
312  * which can cause problems in combination with the 82441FX/PPro MTRRs
313  */
quirk_passive_release(struct pci_dev * dev)314 static void quirk_passive_release(struct pci_dev *dev)
315 {
316 	struct pci_dev *d = NULL;
317 	unsigned char dlc;
318 
319 	/*
320 	 * We have to make sure a particular bit is set in the PIIX3
321 	 * ISA bridge, so we have to go out and find it.
322 	 */
323 	while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
324 		pci_read_config_byte(d, 0x82, &dlc);
325 		if (!(dlc & 1<<1)) {
326 			pci_info(d, "PIIX3: Enabling Passive Release\n");
327 			dlc |= 1<<1;
328 			pci_write_config_byte(d, 0x82, dlc);
329 		}
330 	}
331 }
332 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_passive_release);
333 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_passive_release);
334 
335 #ifdef CONFIG_X86_32
336 /*
337  * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
338  * workaround but VIA don't answer queries. If you happen to have good
339  * contacts at VIA ask them for me please -- Alan
340  *
341  * This appears to be BIOS not version dependent. So presumably there is a
342  * chipset level fix.
343  */
quirk_isa_dma_hangs(struct pci_dev * dev)344 static void quirk_isa_dma_hangs(struct pci_dev *dev)
345 {
346 	if (!isa_dma_bridge_buggy) {
347 		isa_dma_bridge_buggy = 1;
348 		pci_info(dev, "Activating ISA DMA hang workarounds\n");
349 	}
350 }
351 /*
352  * It's not totally clear which chipsets are the problematic ones.  We know
353  * 82C586 and 82C596 variants are affected.
354  */
355 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_0,	quirk_isa_dma_hangs);
356 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C596,	quirk_isa_dma_hangs);
357 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82371SB_0,  quirk_isa_dma_hangs);
358 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1533,		quirk_isa_dma_hangs);
359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_1,	quirk_isa_dma_hangs);
360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_2,	quirk_isa_dma_hangs);
361 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC,	PCI_DEVICE_ID_NEC_CBUS_3,	quirk_isa_dma_hangs);
362 #endif
363 
364 #ifdef CONFIG_HAS_IOPORT
365 /*
366  * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear
367  * for some HT machines to use C4 w/o hanging.
368  */
quirk_tigerpoint_bm_sts(struct pci_dev * dev)369 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
370 {
371 	u32 pmbase;
372 	u16 pm1a;
373 
374 	pci_read_config_dword(dev, 0x40, &pmbase);
375 	pmbase = pmbase & 0xff80;
376 	pm1a = inw(pmbase);
377 
378 	if (pm1a & 0x10) {
379 		pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n");
380 		outw(0x10, pmbase);
381 	}
382 }
383 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
384 #endif
385 
386 /* Chipsets where PCI->PCI transfers vanish or hang */
quirk_nopcipci(struct pci_dev * dev)387 static void quirk_nopcipci(struct pci_dev *dev)
388 {
389 	if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
390 		pci_info(dev, "Disabling direct PCI/PCI transfers\n");
391 		pci_pci_problems |= PCIPCI_FAIL;
392 	}
393 }
394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_5597,		quirk_nopcipci);
395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_496,		quirk_nopcipci);
396 
quirk_nopciamd(struct pci_dev * dev)397 static void quirk_nopciamd(struct pci_dev *dev)
398 {
399 	u8 rev;
400 	pci_read_config_byte(dev, 0x08, &rev);
401 	if (rev == 0x13) {
402 		/* Erratum 24 */
403 		pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
404 		pci_pci_problems |= PCIAGP_FAIL;
405 	}
406 }
407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8151_0,	quirk_nopciamd);
408 
409 /* Triton requires workarounds to be used by the drivers */
quirk_triton(struct pci_dev * dev)410 static void quirk_triton(struct pci_dev *dev)
411 {
412 	if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
413 		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
414 		pci_pci_problems |= PCIPCI_TRITON;
415 	}
416 }
417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82437,	quirk_triton);
418 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82437VX,	quirk_triton);
419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82439,	quirk_triton);
420 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82439TX,	quirk_triton);
421 
422 /*
423  * VIA Apollo KT133 needs PCI latency patch
424  * Made according to a Windows driver-based patch by George E. Breese;
425  * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
426  * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
427  * which Mr Breese based his work.
428  *
429  * Updated based on further information from the site and also on
430  * information provided by VIA
431  */
quirk_vialatency(struct pci_dev * dev)432 static void quirk_vialatency(struct pci_dev *dev)
433 {
434 	struct pci_dev *p;
435 	u8 busarb;
436 
437 	/*
438 	 * Ok, we have a potential problem chipset here. Now see if we have
439 	 * a buggy southbridge.
440 	 */
441 	p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
442 	if (p != NULL) {
443 
444 		/*
445 		 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
446 		 * thanks Dan Hollis.
447 		 * Check for buggy part revisions
448 		 */
449 		if (p->revision < 0x40 || p->revision > 0x42)
450 			goto exit;
451 	} else {
452 		p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
453 		if (p == NULL)	/* No problem parts */
454 			goto exit;
455 
456 		/* Check for buggy part revisions */
457 		if (p->revision < 0x10 || p->revision > 0x12)
458 			goto exit;
459 	}
460 
461 	/*
462 	 * Ok we have the problem. Now set the PCI master grant to occur
463 	 * every master grant. The apparent bug is that under high PCI load
464 	 * (quite common in Linux of course) you can get data loss when the
465 	 * CPU is held off the bus for 3 bus master requests.  This happens
466 	 * to include the IDE controllers....
467 	 *
468 	 * VIA only apply this fix when an SB Live! is present but under
469 	 * both Linux and Windows this isn't enough, and we have seen
470 	 * corruption without SB Live! but with things like 3 UDMA IDE
471 	 * controllers. So we ignore that bit of the VIA recommendation..
472 	 */
473 	pci_read_config_byte(dev, 0x76, &busarb);
474 
475 	/*
476 	 * Set bit 4 and bit 5 of byte 76 to 0x01
477 	 * "Master priority rotation on every PCI master grant"
478 	 */
479 	busarb &= ~(1<<5);
480 	busarb |= (1<<4);
481 	pci_write_config_byte(dev, 0x76, busarb);
482 	pci_info(dev, "Applying VIA southbridge workaround\n");
483 exit:
484 	pci_dev_put(p);
485 }
486 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency);
487 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8371_1,	quirk_vialatency);
488 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_vialatency);
489 /* Must restore this on a resume from RAM */
490 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8363_0,	quirk_vialatency);
491 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8371_1,	quirk_vialatency);
492 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_vialatency);
493 
494 /* VIA Apollo VP3 needs ETBF on BT848/878 */
quirk_viaetbf(struct pci_dev * dev)495 static void quirk_viaetbf(struct pci_dev *dev)
496 {
497 	if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
498 		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
499 		pci_pci_problems |= PCIPCI_VIAETBF;
500 	}
501 }
502 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C597_0,	quirk_viaetbf);
503 
quirk_vsfx(struct pci_dev * dev)504 static void quirk_vsfx(struct pci_dev *dev)
505 {
506 	if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
507 		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
508 		pci_pci_problems |= PCIPCI_VSFX;
509 	}
510 }
511 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C576,	quirk_vsfx);
512 
513 /*
514  * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
515  * space. Latency must be set to 0xA and Triton workaround applied too.
516  * [Info kindly provided by ALi]
517  */
quirk_alimagik(struct pci_dev * dev)518 static void quirk_alimagik(struct pci_dev *dev)
519 {
520 	if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
521 		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
522 		pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
523 	}
524 }
525 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1647,		quirk_alimagik);
526 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1651,		quirk_alimagik);
527 
528 /* Natoma has some interesting boundary conditions with Zoran stuff at least */
quirk_natoma(struct pci_dev * dev)529 static void quirk_natoma(struct pci_dev *dev)
530 {
531 	if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
532 		pci_info(dev, "Limiting direct PCI/PCI transfers\n");
533 		pci_pci_problems |= PCIPCI_NATOMA;
534 	}
535 }
536 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82441,	quirk_natoma);
537 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443LX_0,	quirk_natoma);
538 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443LX_1,	quirk_natoma);
539 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_0,	quirk_natoma);
540 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_1,	quirk_natoma);
541 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443BX_2,	quirk_natoma);
542 
543 /*
544  * This chip can cause PCI parity errors if config register 0xA0 is read
545  * while DMAs are occurring.
546  */
quirk_citrine(struct pci_dev * dev)547 static void quirk_citrine(struct pci_dev *dev)
548 {
549 	dev->cfg_size = 0xA0;
550 }
551 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM,	PCI_DEVICE_ID_IBM_CITRINE,	quirk_citrine);
552 
553 /*
554  * This chip can cause bus lockups if config addresses above 0x600
555  * are read or written.
556  */
quirk_nfp6000(struct pci_dev * dev)557 static void quirk_nfp6000(struct pci_dev *dev)
558 {
559 	dev->cfg_size = 0x600;
560 }
561 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP4000,	quirk_nfp6000);
562 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP6000,	quirk_nfp6000);
563 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP5000,	quirk_nfp6000);
564 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME,	PCI_DEVICE_ID_NETRONOME_NFP6000_VF,	quirk_nfp6000);
565 
566 /*  On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
quirk_extend_bar_to_page(struct pci_dev * dev)567 static void quirk_extend_bar_to_page(struct pci_dev *dev)
568 {
569 	int i;
570 
571 	for (i = 0; i < PCI_STD_NUM_BARS; i++) {
572 		struct resource *r = &dev->resource[i];
573 
574 		if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
575 			r->end = PAGE_SIZE - 1;
576 			r->start = 0;
577 			r->flags |= IORESOURCE_UNSET;
578 			pci_info(dev, "expanded BAR %d to page size: %pR\n",
579 				 i, r);
580 		}
581 	}
582 }
583 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
584 
585 /*
586  * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
587  * If it's needed, re-allocate the region.
588  */
quirk_s3_64M(struct pci_dev * dev)589 static void quirk_s3_64M(struct pci_dev *dev)
590 {
591 	struct resource *r = &dev->resource[0];
592 
593 	if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
594 		r->flags |= IORESOURCE_UNSET;
595 		r->start = 0;
596 		r->end = 0x3ffffff;
597 	}
598 }
599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,	PCI_DEVICE_ID_S3_868,		quirk_s3_64M);
600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3,	PCI_DEVICE_ID_S3_968,		quirk_s3_64M);
601 
quirk_io(struct pci_dev * dev,int pos,unsigned int size,const char * name)602 static void quirk_io(struct pci_dev *dev, int pos, unsigned int size,
603 		     const char *name)
604 {
605 	u32 region;
606 	struct pci_bus_region bus_region;
607 	struct resource *res = dev->resource + pos;
608 
609 	pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
610 
611 	if (!region)
612 		return;
613 
614 	res->name = pci_name(dev);
615 	res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
616 	res->flags |=
617 		(IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
618 	region &= ~(size - 1);
619 
620 	/* Convert from PCI bus to resource space */
621 	bus_region.start = region;
622 	bus_region.end = region + size - 1;
623 	pcibios_bus_to_resource(dev->bus, res, &bus_region);
624 
625 	pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
626 		 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
627 }
628 
629 /*
630  * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
631  * ver. 1.33  20070103) don't set the correct ISA PCI region header info.
632  * BAR0 should be 8 bytes; instead, it may be set to something like 8k
633  * (which conflicts w/ BAR1's memory range).
634  *
635  * CS553x's ISA PCI BARs may also be read-only (ref:
636  * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
637  */
quirk_cs5536_vsa(struct pci_dev * dev)638 static void quirk_cs5536_vsa(struct pci_dev *dev)
639 {
640 	static char *name = "CS5536 ISA bridge";
641 
642 	if (pci_resource_len(dev, 0) != 8) {
643 		quirk_io(dev, 0,   8, name);	/* SMB */
644 		quirk_io(dev, 1, 256, name);	/* GPIO */
645 		quirk_io(dev, 2,  64, name);	/* MFGPT */
646 		pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
647 			 name);
648 	}
649 }
650 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
651 
quirk_io_region(struct pci_dev * dev,int port,unsigned int size,int nr,const char * name)652 static void quirk_io_region(struct pci_dev *dev, int port,
653 			    unsigned int size, int nr, const char *name)
654 {
655 	u16 region;
656 	struct pci_bus_region bus_region;
657 	struct resource *res = dev->resource + nr;
658 
659 	pci_read_config_word(dev, port, &region);
660 	region &= ~(size - 1);
661 
662 	if (!region)
663 		return;
664 
665 	res->name = pci_name(dev);
666 	res->flags = IORESOURCE_IO;
667 
668 	/* Convert from PCI bus to resource space */
669 	bus_region.start = region;
670 	bus_region.end = region + size - 1;
671 	pcibios_bus_to_resource(dev->bus, res, &bus_region);
672 
673 	if (!pci_claim_resource(dev, nr))
674 		pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
675 }
676 
677 /*
678  * ATI Northbridge setups MCE the processor if you even read somewhere
679  * between 0x3b0->0x3bb or read 0x3d3
680  */
quirk_ati_exploding_mce(struct pci_dev * dev)681 static void quirk_ati_exploding_mce(struct pci_dev *dev)
682 {
683 	pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
684 	/* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
685 	request_region(0x3b0, 0x0C, "RadeonIGP");
686 	request_region(0x3d3, 0x01, "RadeonIGP");
687 }
688 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI,	PCI_DEVICE_ID_ATI_RS100,   quirk_ati_exploding_mce);
689 
690 /*
691  * In the AMD NL platform, this device ([1022:7912]) has a class code of
692  * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
693  * claim it. The same applies on the VanGogh platform device ([1022:163a]).
694  *
695  * But the dwc3 driver is a more specific driver for this device, and we'd
696  * prefer to use it instead of xhci. To prevent xhci from claiming the
697  * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
698  * defines as "USB device (not host controller)". The dwc3 driver can then
699  * claim it based on its Vendor and Device ID.
700  */
quirk_amd_dwc_class(struct pci_dev * pdev)701 static void quirk_amd_dwc_class(struct pci_dev *pdev)
702 {
703 	u32 class = pdev->class;
704 
705 	if (class != PCI_CLASS_SERIAL_USB_DEVICE) {
706 		/* Use "USB Device (not host controller)" class */
707 		pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
708 		pci_info(pdev,
709 			"PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
710 			class, pdev->class);
711 	}
712 }
713 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
714 		quirk_amd_dwc_class);
715 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB,
716 		quirk_amd_dwc_class);
717 
718 /*
719  * Synopsys USB 3.x host HAPS platform has a class code of
720  * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it.  However, these
721  * devices should use dwc3-haps driver.  Change these devices' class code to
722  * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
723  * them.
724  */
quirk_synopsys_haps(struct pci_dev * pdev)725 static void quirk_synopsys_haps(struct pci_dev *pdev)
726 {
727 	u32 class = pdev->class;
728 
729 	switch (pdev->device) {
730 	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
731 	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
732 	case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
733 		pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
734 		pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
735 			 class, pdev->class);
736 		break;
737 	}
738 }
739 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
740 			       PCI_CLASS_SERIAL_USB_XHCI, 0,
741 			       quirk_synopsys_haps);
742 
743 /*
744  * Let's make the southbridge information explicit instead of having to
745  * worry about people probing the ACPI areas, for example.. (Yes, it
746  * happens, and if you read the wrong ACPI register it will put the machine
747  * to sleep with no way of waking it up again. Bummer).
748  *
749  * ALI M7101: Two IO regions pointed to by words at
750  *	0xE0 (64 bytes of ACPI registers)
751  *	0xE2 (32 bytes of SMB registers)
752  */
quirk_ali7101_acpi(struct pci_dev * dev)753 static void quirk_ali7101_acpi(struct pci_dev *dev)
754 {
755 	quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
756 	quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
757 }
758 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M7101,		quirk_ali7101_acpi);
759 
piix4_io_quirk(struct pci_dev * dev,const char * name,unsigned int port,unsigned int enable)760 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
761 {
762 	u32 devres;
763 	u32 mask, size, base;
764 
765 	pci_read_config_dword(dev, port, &devres);
766 	if ((devres & enable) != enable)
767 		return;
768 	mask = (devres >> 16) & 15;
769 	base = devres & 0xffff;
770 	size = 16;
771 	for (;;) {
772 		unsigned int bit = size >> 1;
773 		if ((bit & mask) == bit)
774 			break;
775 		size = bit;
776 	}
777 	/*
778 	 * For now we only print it out. Eventually we'll want to
779 	 * reserve it (at least if it's in the 0x1000+ range), but
780 	 * let's get enough confirmation reports first.
781 	 */
782 	base &= -size;
783 	pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
784 }
785 
piix4_mem_quirk(struct pci_dev * dev,const char * name,unsigned int port,unsigned int enable)786 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
787 {
788 	u32 devres;
789 	u32 mask, size, base;
790 
791 	pci_read_config_dword(dev, port, &devres);
792 	if ((devres & enable) != enable)
793 		return;
794 	base = devres & 0xffff0000;
795 	mask = (devres & 0x3f) << 16;
796 	size = 128 << 16;
797 	for (;;) {
798 		unsigned int bit = size >> 1;
799 		if ((bit & mask) == bit)
800 			break;
801 		size = bit;
802 	}
803 
804 	/*
805 	 * For now we only print it out. Eventually we'll want to
806 	 * reserve it, but let's get enough confirmation reports first.
807 	 */
808 	base &= -size;
809 	pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
810 }
811 
812 /*
813  * PIIX4 ACPI: Two IO regions pointed to by longwords at
814  *	0x40 (64 bytes of ACPI registers)
815  *	0x90 (16 bytes of SMB registers)
816  * and a few strange programmable PIIX4 device resources.
817  */
quirk_piix4_acpi(struct pci_dev * dev)818 static void quirk_piix4_acpi(struct pci_dev *dev)
819 {
820 	u32 res_a;
821 
822 	quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
823 	quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
824 
825 	/* Device resource A has enables for some of the other ones */
826 	pci_read_config_dword(dev, 0x5c, &res_a);
827 
828 	piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
829 	piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
830 
831 	/* Device resource D is just bitfields for static resources */
832 
833 	/* Device 12 enabled? */
834 	if (res_a & (1 << 29)) {
835 		piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
836 		piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
837 	}
838 	/* Device 13 enabled? */
839 	if (res_a & (1 << 30)) {
840 		piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
841 		piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
842 	}
843 	piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
844 	piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
845 }
846 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82371AB_3,	quirk_piix4_acpi);
847 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82443MX_3,	quirk_piix4_acpi);
848 
849 #define ICH_PMBASE	0x40
850 #define ICH_ACPI_CNTL	0x44
851 #define  ICH4_ACPI_EN	0x10
852 #define  ICH6_ACPI_EN	0x80
853 #define ICH4_GPIOBASE	0x58
854 #define ICH4_GPIO_CNTL	0x5c
855 #define  ICH4_GPIO_EN	0x10
856 #define ICH6_GPIOBASE	0x48
857 #define ICH6_GPIO_CNTL	0x4c
858 #define  ICH6_GPIO_EN	0x10
859 
860 /*
861  * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
862  *	0x40 (128 bytes of ACPI, GPIO & TCO registers)
863  *	0x58 (64 bytes of GPIO I/O space)
864  */
quirk_ich4_lpc_acpi(struct pci_dev * dev)865 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
866 {
867 	u8 enable;
868 
869 	/*
870 	 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
871 	 * with low legacy (and fixed) ports. We don't know the decoding
872 	 * priority and can't tell whether the legacy device or the one created
873 	 * here is really at that address.  This happens on boards with broken
874 	 * BIOSes.
875 	 */
876 	pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
877 	if (enable & ICH4_ACPI_EN)
878 		quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
879 				 "ICH4 ACPI/GPIO/TCO");
880 
881 	pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
882 	if (enable & ICH4_GPIO_EN)
883 		quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
884 				"ICH4 GPIO");
885 }
886 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AA_0,		quirk_ich4_lpc_acpi);
887 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801AB_0,		quirk_ich4_lpc_acpi);
888 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_0,		quirk_ich4_lpc_acpi);
889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801BA_10,	quirk_ich4_lpc_acpi);
890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_0,		quirk_ich4_lpc_acpi);
891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801CA_12,	quirk_ich4_lpc_acpi);
892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_0,		quirk_ich4_lpc_acpi);
893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801DB_12,	quirk_ich4_lpc_acpi);
894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82801EB_0,		quirk_ich4_lpc_acpi);
895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_ESB_1,		quirk_ich4_lpc_acpi);
896 
ich6_lpc_acpi_gpio(struct pci_dev * dev)897 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
898 {
899 	u8 enable;
900 
901 	pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
902 	if (enable & ICH6_ACPI_EN)
903 		quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
904 				 "ICH6 ACPI/GPIO/TCO");
905 
906 	pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
907 	if (enable & ICH6_GPIO_EN)
908 		quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
909 				"ICH6 GPIO");
910 }
911 
ich6_lpc_generic_decode(struct pci_dev * dev,unsigned int reg,const char * name,int dynsize)912 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg,
913 				    const char *name, int dynsize)
914 {
915 	u32 val;
916 	u32 size, base;
917 
918 	pci_read_config_dword(dev, reg, &val);
919 
920 	/* Enabled? */
921 	if (!(val & 1))
922 		return;
923 	base = val & 0xfffc;
924 	if (dynsize) {
925 		/*
926 		 * This is not correct. It is 16, 32 or 64 bytes depending on
927 		 * register D31:F0:ADh bits 5:4.
928 		 *
929 		 * But this gets us at least _part_ of it.
930 		 */
931 		size = 16;
932 	} else {
933 		size = 128;
934 	}
935 	base &= ~(size-1);
936 
937 	/*
938 	 * Just print it out for now. We should reserve it after more
939 	 * debugging.
940 	 */
941 	pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
942 }
943 
quirk_ich6_lpc(struct pci_dev * dev)944 static void quirk_ich6_lpc(struct pci_dev *dev)
945 {
946 	/* Shared ACPI/GPIO decode with all ICH6+ */
947 	ich6_lpc_acpi_gpio(dev);
948 
949 	/* ICH6-specific generic IO decode */
950 	ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
951 	ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
952 }
953 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
954 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
955 
ich7_lpc_generic_decode(struct pci_dev * dev,unsigned int reg,const char * name)956 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg,
957 				    const char *name)
958 {
959 	u32 val;
960 	u32 mask, base;
961 
962 	pci_read_config_dword(dev, reg, &val);
963 
964 	/* Enabled? */
965 	if (!(val & 1))
966 		return;
967 
968 	/* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
969 	base = val & 0xfffc;
970 	mask = (val >> 16) & 0xfc;
971 	mask |= 3;
972 
973 	/*
974 	 * Just print it out for now. We should reserve it after more
975 	 * debugging.
976 	 */
977 	pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
978 }
979 
980 /* ICH7-10 has the same common LPC generic IO decode registers */
quirk_ich7_lpc(struct pci_dev * dev)981 static void quirk_ich7_lpc(struct pci_dev *dev)
982 {
983 	/* We share the common ACPI/GPIO decode with ICH6 */
984 	ich6_lpc_acpi_gpio(dev);
985 
986 	/* And have 4 ICH7+ generic decodes */
987 	ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
988 	ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
989 	ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
990 	ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
991 }
992 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
993 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
994 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
995 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
996 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
997 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
998 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
999 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
1000 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
1001 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
1002 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
1003 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
1004 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
1005 
1006 /*
1007  * VIA ACPI: One IO region pointed to by longword at
1008  *	0x48 or 0x20 (256 bytes of ACPI registers)
1009  */
quirk_vt82c586_acpi(struct pci_dev * dev)1010 static void quirk_vt82c586_acpi(struct pci_dev *dev)
1011 {
1012 	if (dev->revision & 0x10)
1013 		quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
1014 				"vt82c586 ACPI");
1015 }
1016 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_3,	quirk_vt82c586_acpi);
1017 
1018 /*
1019  * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
1020  *	0x48 (256 bytes of ACPI registers)
1021  *	0x70 (128 bytes of hardware monitoring register)
1022  *	0x90 (16 bytes of SMB registers)
1023  */
quirk_vt82c686_acpi(struct pci_dev * dev)1024 static void quirk_vt82c686_acpi(struct pci_dev *dev)
1025 {
1026 	quirk_vt82c586_acpi(dev);
1027 
1028 	quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
1029 				 "vt82c686 HW-mon");
1030 
1031 	quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
1032 }
1033 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_vt82c686_acpi);
1034 
1035 /*
1036  * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
1037  *	0x88 (128 bytes of power management registers)
1038  *	0xd0 (16 bytes of SMB registers)
1039  */
quirk_vt8235_acpi(struct pci_dev * dev)1040 static void quirk_vt8235_acpi(struct pci_dev *dev)
1041 {
1042 	quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
1043 	quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
1044 }
1045 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8235,	quirk_vt8235_acpi);
1046 
1047 /*
1048  * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
1049  * back-to-back: Disable fast back-to-back on the secondary bus segment
1050  */
quirk_xio2000a(struct pci_dev * dev)1051 static void quirk_xio2000a(struct pci_dev *dev)
1052 {
1053 	struct pci_dev *pdev;
1054 	u16 command;
1055 
1056 	pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
1057 	list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
1058 		pci_read_config_word(pdev, PCI_COMMAND, &command);
1059 		if (command & PCI_COMMAND_FAST_BACK)
1060 			pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
1061 	}
1062 }
1063 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
1064 			quirk_xio2000a);
1065 
1066 #ifdef CONFIG_X86_IO_APIC
1067 
1068 #include <asm/io_apic.h>
1069 
1070 /*
1071  * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
1072  * devices to the external APIC.
1073  *
1074  * TODO: When we have device-specific interrupt routers, this code will go
1075  * away from quirks.
1076  */
quirk_via_ioapic(struct pci_dev * dev)1077 static void quirk_via_ioapic(struct pci_dev *dev)
1078 {
1079 	u8 tmp;
1080 
1081 	if (nr_ioapics < 1)
1082 		tmp = 0;    /* nothing routed to external APIC */
1083 	else
1084 		tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
1085 
1086 	pci_info(dev, "%s VIA external APIC routing\n",
1087 		 tmp ? "Enabling" : "Disabling");
1088 
1089 	/* Offset 0x58: External APIC IRQ output control */
1090 	pci_write_config_byte(dev, 0x58, tmp);
1091 }
1092 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_ioapic);
1093 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_ioapic);
1094 
1095 /*
1096  * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1097  * This leads to doubled level interrupt rates.
1098  * Set this bit to get rid of cycle wastage.
1099  * Otherwise uncritical.
1100  */
quirk_via_vt8237_bypass_apic_deassert(struct pci_dev * dev)1101 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
1102 {
1103 	u8 misc_control2;
1104 #define BYPASS_APIC_DEASSERT 8
1105 
1106 	pci_read_config_byte(dev, 0x5B, &misc_control2);
1107 	if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1108 		pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1109 		pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
1110 	}
1111 }
1112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_vt8237_bypass_apic_deassert);
1113 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_vt8237_bypass_apic_deassert);
1114 
1115 /*
1116  * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1117  * We check all revs >= B0 (yet not in the pre production!) as the bug
1118  * is currently marked NoFix
1119  *
1120  * We have multiple reports of hangs with this chipset that went away with
1121  * noapic specified. For the moment we assume it's the erratum. We may be wrong
1122  * of course. However the advice is demonstrably good even if so.
1123  */
quirk_amd_ioapic(struct pci_dev * dev)1124 static void quirk_amd_ioapic(struct pci_dev *dev)
1125 {
1126 	if (dev->revision >= 0x02) {
1127 		pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1128 		pci_warn(dev, "        : booting with the \"noapic\" option\n");
1129 	}
1130 }
1131 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_VIPER_7410,	quirk_amd_ioapic);
1132 #endif /* CONFIG_X86_IO_APIC */
1133 
1134 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1135 
quirk_cavium_sriov_rnm_link(struct pci_dev * dev)1136 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1137 {
1138 	/* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1139 	if (dev->subsystem_device == 0xa118)
1140 		dev->sriov->link = dev->devfn;
1141 }
1142 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1143 #endif
1144 
1145 /*
1146  * Some settings of MMRBC can lead to data corruption so block changes.
1147  * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1148  */
quirk_amd_8131_mmrbc(struct pci_dev * dev)1149 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1150 {
1151 	if (dev->subordinate && dev->revision <= 0x12) {
1152 		pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1153 			 dev->revision);
1154 		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1155 	}
1156 }
1157 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1158 
1159 /*
1160  * FIXME: it is questionable that quirk_via_acpi() is needed.  It shows up
1161  * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1162  * at all.  Therefore it seems like setting the pci_dev's IRQ to the value
1163  * of the ACPI SCI interrupt is only done for convenience.
1164  *	-jgarzik
1165  */
quirk_via_acpi(struct pci_dev * d)1166 static void quirk_via_acpi(struct pci_dev *d)
1167 {
1168 	u8 irq;
1169 
1170 	/* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1171 	pci_read_config_byte(d, 0x42, &irq);
1172 	irq &= 0xf;
1173 	if (irq && (irq != 2))
1174 		d->irq = irq;
1175 }
1176 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C586_3,	quirk_via_acpi);
1177 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686_4,	quirk_via_acpi);
1178 
1179 /* VIA bridges which have VLink */
1180 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1181 
quirk_via_bridge(struct pci_dev * dev)1182 static void quirk_via_bridge(struct pci_dev *dev)
1183 {
1184 	/* See what bridge we have and find the device ranges */
1185 	switch (dev->device) {
1186 	case PCI_DEVICE_ID_VIA_82C686:
1187 		/*
1188 		 * The VT82C686 is special; it attaches to PCI and can have
1189 		 * any device number. All its subdevices are functions of
1190 		 * that single device.
1191 		 */
1192 		via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1193 		via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1194 		break;
1195 	case PCI_DEVICE_ID_VIA_8237:
1196 	case PCI_DEVICE_ID_VIA_8237A:
1197 		via_vlink_dev_lo = 15;
1198 		break;
1199 	case PCI_DEVICE_ID_VIA_8235:
1200 		via_vlink_dev_lo = 16;
1201 		break;
1202 	case PCI_DEVICE_ID_VIA_8231:
1203 	case PCI_DEVICE_ID_VIA_8233_0:
1204 	case PCI_DEVICE_ID_VIA_8233A:
1205 	case PCI_DEVICE_ID_VIA_8233C_0:
1206 		via_vlink_dev_lo = 17;
1207 		break;
1208 	}
1209 }
1210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C686,	quirk_via_bridge);
1211 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8231,		quirk_via_bridge);
1212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233_0,	quirk_via_bridge);
1213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233A,	quirk_via_bridge);
1214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8233C_0,	quirk_via_bridge);
1215 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8235,		quirk_via_bridge);
1216 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk_via_bridge);
1217 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237A,	quirk_via_bridge);
1218 
1219 /*
1220  * quirk_via_vlink		-	VIA VLink IRQ number update
1221  * @dev: PCI device
1222  *
1223  * If the device we are dealing with is on a PIC IRQ we need to ensure that
1224  * the IRQ line register which usually is not relevant for PCI cards, is
1225  * actually written so that interrupts get sent to the right place.
1226  *
1227  * We only do this on systems where a VIA south bridge was detected, and
1228  * only for VIA devices on the motherboard (see quirk_via_bridge above).
1229  */
quirk_via_vlink(struct pci_dev * dev)1230 static void quirk_via_vlink(struct pci_dev *dev)
1231 {
1232 	u8 irq, new_irq;
1233 
1234 	/* Check if we have VLink at all */
1235 	if (via_vlink_dev_lo == -1)
1236 		return;
1237 
1238 	new_irq = dev->irq;
1239 
1240 	/* Don't quirk interrupts outside the legacy IRQ range */
1241 	if (!new_irq || new_irq > 15)
1242 		return;
1243 
1244 	/* Internal device ? */
1245 	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1246 	    PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1247 		return;
1248 
1249 	/*
1250 	 * This is an internal VLink device on a PIC interrupt. The BIOS
1251 	 * ought to have set this but may not have, so we redo it.
1252 	 */
1253 	pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1254 	if (new_irq != irq) {
1255 		pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1256 			irq, new_irq);
1257 		udelay(15);	/* unknown if delay really needed */
1258 		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1259 	}
1260 }
1261 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1262 
1263 /*
1264  * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1265  * of VT82C597 for backward compatibility.  We need to switch it off to be
1266  * able to recognize the real type of the chip.
1267  */
quirk_vt82c598_id(struct pci_dev * dev)1268 static void quirk_vt82c598_id(struct pci_dev *dev)
1269 {
1270 	pci_write_config_byte(dev, 0xfc, 0);
1271 	pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1272 }
1273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C597_0,	quirk_vt82c598_id);
1274 
1275 /*
1276  * CardBus controllers have a legacy base address that enables them to
1277  * respond as i82365 pcmcia controllers.  We don't want them to do this
1278  * even if the Linux CardBus driver is not loaded, because the Linux i82365
1279  * driver does not (and should not) handle CardBus.
1280  */
quirk_cardbus_legacy(struct pci_dev * dev)1281 static void quirk_cardbus_legacy(struct pci_dev *dev)
1282 {
1283 	pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1284 }
1285 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1286 			PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1287 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1288 			PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1289 
1290 /*
1291  * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1292  * what the designers were smoking but let's not inhale...
1293  *
1294  * To be fair to AMD, it follows the spec by default, it's BIOS people who
1295  * turn it off!
1296  */
quirk_amd_ordering(struct pci_dev * dev)1297 static void quirk_amd_ordering(struct pci_dev *dev)
1298 {
1299 	u32 pcic;
1300 	pci_read_config_dword(dev, 0x4C, &pcic);
1301 	if ((pcic & 6) != 6) {
1302 		pcic |= 6;
1303 		pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1304 		pci_write_config_dword(dev, 0x4C, pcic);
1305 		pci_read_config_dword(dev, 0x84, &pcic);
1306 		pcic |= (1 << 23);	/* Required in this mode */
1307 		pci_write_config_dword(dev, 0x84, pcic);
1308 	}
1309 }
1310 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1311 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1312 
1313 /*
1314  * DreamWorks-provided workaround for Dunord I-3000 problem
1315  *
1316  * This card decodes and responds to addresses not apparently assigned to
1317  * it.  We force a larger allocation to ensure that nothing gets put too
1318  * close to it.
1319  */
quirk_dunord(struct pci_dev * dev)1320 static void quirk_dunord(struct pci_dev *dev)
1321 {
1322 	struct resource *r = &dev->resource[1];
1323 
1324 	r->flags |= IORESOURCE_UNSET;
1325 	r->start = 0;
1326 	r->end = 0xffffff;
1327 }
1328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD,	PCI_DEVICE_ID_DUNORD_I3000,	quirk_dunord);
1329 
1330 /*
1331  * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1332  * decoding (transparent), and does indicate this in the ProgIf.
1333  * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1334  */
quirk_transparent_bridge(struct pci_dev * dev)1335 static void quirk_transparent_bridge(struct pci_dev *dev)
1336 {
1337 	dev->transparent = 1;
1338 }
1339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82380FB,	quirk_transparent_bridge);
1340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA,	0x605,	quirk_transparent_bridge);
1341 
1342 /*
1343  * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1344  * PCI bandwidth from 70MB/s to 25MB/s.  See the GXM/GXLV/GX1 datasheets
1345  * found at http://www.national.com/analog for info on what these bits do.
1346  * <christer@weinigel.se>
1347  */
quirk_mediagx_master(struct pci_dev * dev)1348 static void quirk_mediagx_master(struct pci_dev *dev)
1349 {
1350 	u8 reg;
1351 
1352 	pci_read_config_byte(dev, 0x41, &reg);
1353 	if (reg & 2) {
1354 		reg &= ~2;
1355 		pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1356 			 reg);
1357 		pci_write_config_byte(dev, 0x41, reg);
1358 	}
1359 }
1360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX,	PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1361 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX,	PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1362 
1363 /*
1364  * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1365  * in the odd case it is not the results are corruption hence the presence
1366  * of a Linux check.
1367  */
quirk_disable_pxb(struct pci_dev * pdev)1368 static void quirk_disable_pxb(struct pci_dev *pdev)
1369 {
1370 	u16 config;
1371 
1372 	if (pdev->revision != 0x04)		/* Only C0 requires this */
1373 		return;
1374 	pci_read_config_word(pdev, 0x40, &config);
1375 	if (config & (1<<6)) {
1376 		config &= ~(1<<6);
1377 		pci_write_config_word(pdev, 0x40, config);
1378 		pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1379 	}
1380 }
1381 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82454NX,	quirk_disable_pxb);
1382 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82454NX,	quirk_disable_pxb);
1383 
quirk_amd_ide_mode(struct pci_dev * pdev)1384 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1385 {
1386 	/* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1387 	u8 tmp;
1388 
1389 	pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1390 	if (tmp == 0x01) {
1391 		pci_read_config_byte(pdev, 0x40, &tmp);
1392 		pci_write_config_byte(pdev, 0x40, tmp|1);
1393 		pci_write_config_byte(pdev, 0x9, 1);
1394 		pci_write_config_byte(pdev, 0xa, 6);
1395 		pci_write_config_byte(pdev, 0x40, tmp);
1396 
1397 		pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1398 		pci_info(pdev, "set SATA to AHCI mode\n");
1399 	}
1400 }
1401 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1402 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1403 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1404 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1405 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1406 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1407 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1408 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1409 
1410 /* Serverworks CSB5 IDE does not fully support native mode */
quirk_svwks_csb5ide(struct pci_dev * pdev)1411 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1412 {
1413 	u8 prog;
1414 	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1415 	if (prog & 5) {
1416 		prog &= ~5;
1417 		pdev->class &= ~5;
1418 		pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1419 		/* PCI layer will sort out resources */
1420 	}
1421 }
1422 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1423 
1424 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
quirk_ide_samemode(struct pci_dev * pdev)1425 static void quirk_ide_samemode(struct pci_dev *pdev)
1426 {
1427 	u8 prog;
1428 
1429 	pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1430 
1431 	if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1432 		pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1433 		prog &= ~5;
1434 		pdev->class &= ~5;
1435 		pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1436 	}
1437 }
1438 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1439 
1440 /* Some ATA devices break if put into D3 */
quirk_no_ata_d3(struct pci_dev * pdev)1441 static void quirk_no_ata_d3(struct pci_dev *pdev)
1442 {
1443 	pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1444 }
1445 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1446 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1447 				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1448 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1449 				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1450 /* ALi loses some register settings that we cannot then restore */
1451 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1452 				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1453 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1454    occur when mode detecting */
1455 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1456 				PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1457 
1458 /*
1459  * This was originally an Alpha-specific thing, but it really fits here.
1460  * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1461  */
quirk_eisa_bridge(struct pci_dev * dev)1462 static void quirk_eisa_bridge(struct pci_dev *dev)
1463 {
1464 	dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1465 }
1466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82375,	quirk_eisa_bridge);
1467 
1468 /*
1469  * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1470  * is not activated. The myth is that Asus said that they do not want the
1471  * users to be irritated by just another PCI Device in the Win98 device
1472  * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1473  * package 2.7.0 for details)
1474  *
1475  * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1476  * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1477  * becomes necessary to do this tweak in two steps -- the chosen trigger
1478  * is either the Host bridge (preferred) or on-board VGA controller.
1479  *
1480  * Note that we used to unhide the SMBus that way on Toshiba laptops
1481  * (Satellite A40 and Tecra M2) but then found that the thermal management
1482  * was done by SMM code, which could cause unsynchronized concurrent
1483  * accesses to the SMBus registers, with potentially bad effects. Thus you
1484  * should be very careful when adding new entries: if SMM is accessing the
1485  * Intel SMBus, this is a very good reason to leave it hidden.
1486  *
1487  * Likewise, many recent laptops use ACPI for thermal management. If the
1488  * ACPI DSDT code accesses the SMBus, then Linux should not access it
1489  * natively, and keeping the SMBus hidden is the right thing to do. If you
1490  * are about to add an entry in the table below, please first disassemble
1491  * the DSDT and double-check that there is no code accessing the SMBus.
1492  */
1493 static int asus_hides_smbus;
1494 
asus_hides_smbus_hostbridge(struct pci_dev * dev)1495 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1496 {
1497 	if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1498 		if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1499 			switch (dev->subsystem_device) {
1500 			case 0x8025: /* P4B-LX */
1501 			case 0x8070: /* P4B */
1502 			case 0x8088: /* P4B533 */
1503 			case 0x1626: /* L3C notebook */
1504 				asus_hides_smbus = 1;
1505 			}
1506 		else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1507 			switch (dev->subsystem_device) {
1508 			case 0x80b1: /* P4GE-V */
1509 			case 0x80b2: /* P4PE */
1510 			case 0x8093: /* P4B533-V */
1511 				asus_hides_smbus = 1;
1512 			}
1513 		else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1514 			switch (dev->subsystem_device) {
1515 			case 0x8030: /* P4T533 */
1516 				asus_hides_smbus = 1;
1517 			}
1518 		else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1519 			switch (dev->subsystem_device) {
1520 			case 0x8070: /* P4G8X Deluxe */
1521 				asus_hides_smbus = 1;
1522 			}
1523 		else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1524 			switch (dev->subsystem_device) {
1525 			case 0x80c9: /* PU-DLS */
1526 				asus_hides_smbus = 1;
1527 			}
1528 		else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1529 			switch (dev->subsystem_device) {
1530 			case 0x1751: /* M2N notebook */
1531 			case 0x1821: /* M5N notebook */
1532 			case 0x1897: /* A6L notebook */
1533 				asus_hides_smbus = 1;
1534 			}
1535 		else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1536 			switch (dev->subsystem_device) {
1537 			case 0x184b: /* W1N notebook */
1538 			case 0x186a: /* M6Ne notebook */
1539 				asus_hides_smbus = 1;
1540 			}
1541 		else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1542 			switch (dev->subsystem_device) {
1543 			case 0x80f2: /* P4P800-X */
1544 				asus_hides_smbus = 1;
1545 			}
1546 		else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1547 			switch (dev->subsystem_device) {
1548 			case 0x1882: /* M6V notebook */
1549 			case 0x1977: /* A6VA notebook */
1550 				asus_hides_smbus = 1;
1551 			}
1552 	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1553 		if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
1554 			switch (dev->subsystem_device) {
1555 			case 0x088C: /* HP Compaq nc8000 */
1556 			case 0x0890: /* HP Compaq nc6000 */
1557 				asus_hides_smbus = 1;
1558 			}
1559 		else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1560 			switch (dev->subsystem_device) {
1561 			case 0x12bc: /* HP D330L */
1562 			case 0x12bd: /* HP D530 */
1563 			case 0x006a: /* HP Compaq nx9500 */
1564 				asus_hides_smbus = 1;
1565 			}
1566 		else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1567 			switch (dev->subsystem_device) {
1568 			case 0x12bf: /* HP xw4100 */
1569 				asus_hides_smbus = 1;
1570 			}
1571 	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1572 		if (dev->device ==  PCI_DEVICE_ID_INTEL_82855PM_HB)
1573 			switch (dev->subsystem_device) {
1574 			case 0xC00C: /* Samsung P35 notebook */
1575 				asus_hides_smbus = 1;
1576 		}
1577 	} else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1578 		if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1579 			switch (dev->subsystem_device) {
1580 			case 0x0058: /* Compaq Evo N620c */
1581 				asus_hides_smbus = 1;
1582 			}
1583 		else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1584 			switch (dev->subsystem_device) {
1585 			case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1586 				/* Motherboard doesn't have Host bridge
1587 				 * subvendor/subdevice IDs, therefore checking
1588 				 * its on-board VGA controller */
1589 				asus_hides_smbus = 1;
1590 			}
1591 		else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1592 			switch (dev->subsystem_device) {
1593 			case 0x00b8: /* Compaq Evo D510 CMT */
1594 			case 0x00b9: /* Compaq Evo D510 SFF */
1595 			case 0x00ba: /* Compaq Evo D510 USDT */
1596 				/* Motherboard doesn't have Host bridge
1597 				 * subvendor/subdevice IDs and on-board VGA
1598 				 * controller is disabled if an AGP card is
1599 				 * inserted, therefore checking USB UHCI
1600 				 * Controller #1 */
1601 				asus_hides_smbus = 1;
1602 			}
1603 		else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1604 			switch (dev->subsystem_device) {
1605 			case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1606 				/* Motherboard doesn't have host bridge
1607 				 * subvendor/subdevice IDs, therefore checking
1608 				 * its on-board VGA controller */
1609 				asus_hides_smbus = 1;
1610 			}
1611 	}
1612 }
1613 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82845_HB,	asus_hides_smbus_hostbridge);
1614 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82845G_HB,	asus_hides_smbus_hostbridge);
1615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82850_HB,	asus_hides_smbus_hostbridge);
1616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82865_HB,	asus_hides_smbus_hostbridge);
1617 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82875_HB,	asus_hides_smbus_hostbridge);
1618 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_7205_0,	asus_hides_smbus_hostbridge);
1619 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7501_MCH,	asus_hides_smbus_hostbridge);
1620 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855PM_HB,	asus_hides_smbus_hostbridge);
1621 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82855GM_HB,	asus_hides_smbus_hostbridge);
1622 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1623 
1624 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82810_IG3,	asus_hides_smbus_hostbridge);
1625 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_2,	asus_hides_smbus_hostbridge);
1626 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82815_CGC,	asus_hides_smbus_hostbridge);
1627 
asus_hides_smbus_lpc(struct pci_dev * dev)1628 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1629 {
1630 	u16 val;
1631 
1632 	if (likely(!asus_hides_smbus))
1633 		return;
1634 
1635 	pci_read_config_word(dev, 0xF2, &val);
1636 	if (val & 0x8) {
1637 		pci_write_config_word(dev, 0xF2, val & (~0x8));
1638 		pci_read_config_word(dev, 0xF2, &val);
1639 		if (val & 0x8)
1640 			pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1641 				 val);
1642 		else
1643 			pci_info(dev, "Enabled i801 SMBus device\n");
1644 	}
1645 }
1646 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801AA_0,	asus_hides_smbus_lpc);
1647 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_0,	asus_hides_smbus_lpc);
1648 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801BA_0,	asus_hides_smbus_lpc);
1649 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_0,	asus_hides_smbus_lpc);
1650 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_12,	asus_hides_smbus_lpc);
1651 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_12,	asus_hides_smbus_lpc);
1652 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801EB_0,	asus_hides_smbus_lpc);
1653 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801AA_0,	asus_hides_smbus_lpc);
1654 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_0,	asus_hides_smbus_lpc);
1655 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801BA_0,	asus_hides_smbus_lpc);
1656 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_0,	asus_hides_smbus_lpc);
1657 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801CA_12,	asus_hides_smbus_lpc);
1658 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801DB_12,	asus_hides_smbus_lpc);
1659 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_82801EB_0,	asus_hides_smbus_lpc);
1660 
1661 /* It appears we just have one such device. If not, we have a warning */
1662 static void __iomem *asus_rcba_base;
asus_hides_smbus_lpc_ich6_suspend(struct pci_dev * dev)1663 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1664 {
1665 	u32 rcba;
1666 
1667 	if (likely(!asus_hides_smbus))
1668 		return;
1669 	WARN_ON(asus_rcba_base);
1670 
1671 	pci_read_config_dword(dev, 0xF0, &rcba);
1672 	/* use bits 31:14, 16 kB aligned */
1673 	asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000);
1674 	if (asus_rcba_base == NULL)
1675 		return;
1676 }
1677 
asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev * dev)1678 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1679 {
1680 	u32 val;
1681 
1682 	if (likely(!asus_hides_smbus || !asus_rcba_base))
1683 		return;
1684 
1685 	/* read the Function Disable register, dword mode only */
1686 	val = readl(asus_rcba_base + 0x3418);
1687 
1688 	/* enable the SMBus device */
1689 	writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1690 }
1691 
asus_hides_smbus_lpc_ich6_resume(struct pci_dev * dev)1692 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1693 {
1694 	if (likely(!asus_hides_smbus || !asus_rcba_base))
1695 		return;
1696 
1697 	iounmap(asus_rcba_base);
1698 	asus_rcba_base = NULL;
1699 	pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1700 }
1701 
asus_hides_smbus_lpc_ich6(struct pci_dev * dev)1702 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1703 {
1704 	asus_hides_smbus_lpc_ich6_suspend(dev);
1705 	asus_hides_smbus_lpc_ich6_resume_early(dev);
1706 	asus_hides_smbus_lpc_ich6_resume(dev);
1707 }
1708 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6);
1709 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_suspend);
1710 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_resume);
1711 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ICH6_1,	asus_hides_smbus_lpc_ich6_resume_early);
1712 
1713 /* SiS 96x south bridge: BIOS typically hides SMBus device...  */
quirk_sis_96x_smbus(struct pci_dev * dev)1714 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1715 {
1716 	u8 val = 0;
1717 	pci_read_config_byte(dev, 0x77, &val);
1718 	if (val & 0x10) {
1719 		pci_info(dev, "Enabling SiS 96x SMBus\n");
1720 		pci_write_config_byte(dev, 0x77, val & ~0x10);
1721 	}
1722 }
1723 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_961,		quirk_sis_96x_smbus);
1724 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_962,		quirk_sis_96x_smbus);
1725 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_963,		quirk_sis_96x_smbus);
1726 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_LPC,		quirk_sis_96x_smbus);
1727 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_961,		quirk_sis_96x_smbus);
1728 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_962,		quirk_sis_96x_smbus);
1729 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_963,		quirk_sis_96x_smbus);
1730 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_LPC,		quirk_sis_96x_smbus);
1731 
1732 /*
1733  * ... This is further complicated by the fact that some SiS96x south
1734  * bridges pretend to be 85C503/5513 instead.  In that case see if we
1735  * spotted a compatible north bridge to make sure.
1736  * (pci_find_device() doesn't work yet)
1737  *
1738  * We can also enable the sis96x bit in the discovery register..
1739  */
1740 #define SIS_DETECT_REGISTER 0x40
1741 
quirk_sis_503(struct pci_dev * dev)1742 static void quirk_sis_503(struct pci_dev *dev)
1743 {
1744 	u8 reg;
1745 	u16 devid;
1746 
1747 	pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1748 	pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1749 	pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1750 	if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1751 		pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1752 		return;
1753 	}
1754 
1755 	/*
1756 	 * Ok, it now shows up as a 96x.  Run the 96x quirk by hand in case
1757 	 * it has already been processed.  (Depends on link order, which is
1758 	 * apparently not guaranteed)
1759 	 */
1760 	dev->device = devid;
1761 	quirk_sis_96x_smbus(dev);
1762 }
1763 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_503,		quirk_sis_503);
1764 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI,	PCI_DEVICE_ID_SI_503,		quirk_sis_503);
1765 
1766 /*
1767  * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1768  * and MC97 modem controller are disabled when a second PCI soundcard is
1769  * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1770  * -- bjd
1771  */
asus_hides_ac97_lpc(struct pci_dev * dev)1772 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1773 {
1774 	u8 val;
1775 	int asus_hides_ac97 = 0;
1776 
1777 	if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1778 		if (dev->device == PCI_DEVICE_ID_VIA_8237)
1779 			asus_hides_ac97 = 1;
1780 	}
1781 
1782 	if (!asus_hides_ac97)
1783 		return;
1784 
1785 	pci_read_config_byte(dev, 0x50, &val);
1786 	if (val & 0xc0) {
1787 		pci_write_config_byte(dev, 0x50, val & (~0xc0));
1788 		pci_read_config_byte(dev, 0x50, &val);
1789 		if (val & 0xc0)
1790 			pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1791 				 val);
1792 		else
1793 			pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1794 	}
1795 }
1796 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1797 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1798 
1799 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1800 
1801 /*
1802  * If we are using libata we can drive this chip properly but must do this
1803  * early on to make the additional device appear during the PCI scanning.
1804  */
quirk_jmicron_ata(struct pci_dev * pdev)1805 static void quirk_jmicron_ata(struct pci_dev *pdev)
1806 {
1807 	u32 conf1, conf5, class;
1808 	u8 hdr;
1809 
1810 	/* Only poke fn 0 */
1811 	if (PCI_FUNC(pdev->devfn))
1812 		return;
1813 
1814 	pci_read_config_dword(pdev, 0x40, &conf1);
1815 	pci_read_config_dword(pdev, 0x80, &conf5);
1816 
1817 	conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1818 	conf5 &= ~(1 << 24);  /* Clear bit 24 */
1819 
1820 	switch (pdev->device) {
1821 	case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1822 	case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1823 	case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1824 		/* The controller should be in single function ahci mode */
1825 		conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1826 		break;
1827 
1828 	case PCI_DEVICE_ID_JMICRON_JMB365:
1829 	case PCI_DEVICE_ID_JMICRON_JMB366:
1830 		/* Redirect IDE second PATA port to the right spot */
1831 		conf5 |= (1 << 24);
1832 		fallthrough;
1833 	case PCI_DEVICE_ID_JMICRON_JMB361:
1834 	case PCI_DEVICE_ID_JMICRON_JMB363:
1835 	case PCI_DEVICE_ID_JMICRON_JMB369:
1836 		/* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1837 		/* Set the class codes correctly and then direct IDE 0 */
1838 		conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1839 		break;
1840 
1841 	case PCI_DEVICE_ID_JMICRON_JMB368:
1842 		/* The controller should be in single function IDE mode */
1843 		conf1 |= 0x00C00000; /* Set 22, 23 */
1844 		break;
1845 	}
1846 
1847 	pci_write_config_dword(pdev, 0x40, conf1);
1848 	pci_write_config_dword(pdev, 0x80, conf5);
1849 
1850 	/* Update pdev accordingly */
1851 	pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1852 	pdev->hdr_type = hdr & 0x7f;
1853 	pdev->multifunction = !!(hdr & 0x80);
1854 
1855 	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1856 	pdev->class = class >> 8;
1857 }
1858 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1859 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1860 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1861 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1862 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1863 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1864 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1865 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1866 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1867 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1868 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1869 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1870 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1871 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1872 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1873 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1874 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1875 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1876 
1877 #endif
1878 
quirk_jmicron_async_suspend(struct pci_dev * dev)1879 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1880 {
1881 	if (dev->multifunction) {
1882 		device_disable_async_suspend(&dev->dev);
1883 		pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1884 	}
1885 }
1886 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1887 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1888 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1889 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1890 
1891 #ifdef CONFIG_X86_IO_APIC
quirk_alder_ioapic(struct pci_dev * pdev)1892 static void quirk_alder_ioapic(struct pci_dev *pdev)
1893 {
1894 	int i;
1895 
1896 	if ((pdev->class >> 8) != 0xff00)
1897 		return;
1898 
1899 	/*
1900 	 * The first BAR is the location of the IO-APIC... we must
1901 	 * not touch this (and it's already covered by the fixmap), so
1902 	 * forcibly insert it into the resource tree.
1903 	 */
1904 	if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1905 		insert_resource(&iomem_resource, &pdev->resource[0]);
1906 
1907 	/*
1908 	 * The next five BARs all seem to be rubbish, so just clean
1909 	 * them out.
1910 	 */
1911 	for (i = 1; i < PCI_STD_NUM_BARS; i++)
1912 		memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1913 }
1914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_EESSC,	quirk_alder_ioapic);
1915 #endif
1916 
quirk_no_msi(struct pci_dev * dev)1917 static void quirk_no_msi(struct pci_dev *dev)
1918 {
1919 	pci_info(dev, "avoiding MSI to work around a hardware defect\n");
1920 	dev->no_msi = 1;
1921 }
1922 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi);
1923 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi);
1924 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi);
1925 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi);
1926 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi);
1927 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi);
1928 
quirk_pcie_mch(struct pci_dev * pdev)1929 static void quirk_pcie_mch(struct pci_dev *pdev)
1930 {
1931 	pdev->no_msi = 1;
1932 }
1933 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7520_MCH,	quirk_pcie_mch);
1934 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7320_MCH,	quirk_pcie_mch);
1935 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_E7525_MCH,	quirk_pcie_mch);
1936 
1937 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1938 
1939 /*
1940  * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are
1941  * actually on the AMBA bus. These fake PCI devices can support SVA via
1942  * SMMU stall feature, by setting dma-can-stall for ACPI platforms.
1943  *
1944  * Normally stalling must not be enabled for PCI devices, since it would
1945  * break the PCI requirement for free-flowing writes and may lead to
1946  * deadlock.  We expect PCI devices to support ATS and PRI if they want to
1947  * be fault-tolerant, so there's no ACPI binding to describe anything else,
1948  * even when a "PCI" device turns out to be a regular old SoC device
1949  * dressed up as a RCiEP and normal rules don't apply.
1950  */
quirk_huawei_pcie_sva(struct pci_dev * pdev)1951 static void quirk_huawei_pcie_sva(struct pci_dev *pdev)
1952 {
1953 	struct property_entry properties[] = {
1954 		PROPERTY_ENTRY_BOOL("dma-can-stall"),
1955 		{},
1956 	};
1957 
1958 	if (pdev->revision != 0x21 && pdev->revision != 0x30)
1959 		return;
1960 
1961 	pdev->pasid_no_tlp = 1;
1962 
1963 	/*
1964 	 * Set the dma-can-stall property on ACPI platforms. Device tree
1965 	 * can set it directly.
1966 	 */
1967 	if (!pdev->dev.of_node &&
1968 	    device_create_managed_software_node(&pdev->dev, properties, NULL))
1969 		pci_warn(pdev, "could not add stall property");
1970 }
1971 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva);
1972 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva);
1973 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva);
1974 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva);
1975 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva);
1976 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva);
1977 
1978 /*
1979  * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1980  * together on certain PXH-based systems.
1981  */
quirk_pcie_pxh(struct pci_dev * dev)1982 static void quirk_pcie_pxh(struct pci_dev *dev)
1983 {
1984 	dev->no_msi = 1;
1985 	pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1986 }
1987 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHD_0,	quirk_pcie_pxh);
1988 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHD_1,	quirk_pcie_pxh);
1989 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_pcie_pxh);
1990 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_pcie_pxh);
1991 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_pcie_pxh);
1992 
1993 /*
1994  * Some Intel PCI Express chipsets have trouble with downstream device
1995  * power management.
1996  */
quirk_intel_pcie_pm(struct pci_dev * dev)1997 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1998 {
1999 	pci_pm_d3hot_delay = 120;
2000 	dev->no_d1d2 = 1;
2001 }
2002 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e2, quirk_intel_pcie_pm);
2003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e3, quirk_intel_pcie_pm);
2004 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e4, quirk_intel_pcie_pm);
2005 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e5, quirk_intel_pcie_pm);
2006 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e6, quirk_intel_pcie_pm);
2007 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25e7, quirk_intel_pcie_pm);
2008 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f7, quirk_intel_pcie_pm);
2009 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f8, quirk_intel_pcie_pm);
2010 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25f9, quirk_intel_pcie_pm);
2011 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x25fa, quirk_intel_pcie_pm);
2012 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2601, quirk_intel_pcie_pm);
2013 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2602, quirk_intel_pcie_pm);
2014 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2603, quirk_intel_pcie_pm);
2015 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2604, quirk_intel_pcie_pm);
2016 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2605, quirk_intel_pcie_pm);
2017 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2606, quirk_intel_pcie_pm);
2018 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2607, quirk_intel_pcie_pm);
2019 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2608, quirk_intel_pcie_pm);
2020 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2609, quirk_intel_pcie_pm);
2021 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260a, quirk_intel_pcie_pm);
2022 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260b, quirk_intel_pcie_pm);
2023 
quirk_d3hot_delay(struct pci_dev * dev,unsigned int delay)2024 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
2025 {
2026 	if (dev->d3hot_delay >= delay)
2027 		return;
2028 
2029 	dev->d3hot_delay = delay;
2030 	pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
2031 		 dev->d3hot_delay);
2032 }
2033 
quirk_radeon_pm(struct pci_dev * dev)2034 static void quirk_radeon_pm(struct pci_dev *dev)
2035 {
2036 	if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
2037 	    dev->subsystem_device == 0x00e2)
2038 		quirk_d3hot_delay(dev, 20);
2039 }
2040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
2041 
2042 /*
2043  * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus
2044  * reset is performed too soon after transition to D0, extend d3hot_delay
2045  * to previous effective default for all NVIDIA HDA controllers.
2046  */
quirk_nvidia_hda_pm(struct pci_dev * dev)2047 static void quirk_nvidia_hda_pm(struct pci_dev *dev)
2048 {
2049 	quirk_d3hot_delay(dev, 20);
2050 }
2051 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
2052 			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8,
2053 			      quirk_nvidia_hda_pm);
2054 
2055 /*
2056  * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
2057  * https://bugzilla.kernel.org/show_bug.cgi?id=205587
2058  *
2059  * The kernel attempts to transition these devices to D3cold, but that seems
2060  * to be ineffective on the platforms in question; the PCI device appears to
2061  * remain on in D3hot state. The D3hot-to-D0 transition then requires an
2062  * extended delay in order to succeed.
2063  */
quirk_ryzen_xhci_d3hot(struct pci_dev * dev)2064 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
2065 {
2066 	quirk_d3hot_delay(dev, 20);
2067 }
2068 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
2069 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
2070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot);
2071 
2072 #ifdef CONFIG_X86_IO_APIC
dmi_disable_ioapicreroute(const struct dmi_system_id * d)2073 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
2074 {
2075 	noioapicreroute = 1;
2076 	pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
2077 
2078 	return 0;
2079 }
2080 
2081 static const struct dmi_system_id boot_interrupt_dmi_table[] = {
2082 	/*
2083 	 * Systems to exclude from boot interrupt reroute quirks
2084 	 */
2085 	{
2086 		.callback = dmi_disable_ioapicreroute,
2087 		.ident = "ASUSTek Computer INC. M2N-LR",
2088 		.matches = {
2089 			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
2090 			DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
2091 		},
2092 	},
2093 	{}
2094 };
2095 
2096 /*
2097  * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
2098  * remap the original interrupt in the Linux kernel to the boot interrupt, so
2099  * that a PCI device's interrupt handler is installed on the boot interrupt
2100  * line instead.
2101  */
quirk_reroute_to_boot_interrupts_intel(struct pci_dev * dev)2102 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
2103 {
2104 	dmi_check_system(boot_interrupt_dmi_table);
2105 	if (noioapicquirk || noioapicreroute)
2106 		return;
2107 
2108 	dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
2109 	pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
2110 		 dev->vendor, dev->device);
2111 }
2112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_0,	quirk_reroute_to_boot_interrupts_intel);
2113 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_1,	quirk_reroute_to_boot_interrupts_intel);
2114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ESB2_0,	quirk_reroute_to_boot_interrupts_intel);
2115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_reroute_to_boot_interrupts_intel);
2116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_reroute_to_boot_interrupts_intel);
2117 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_reroute_to_boot_interrupts_intel);
2118 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_0,	quirk_reroute_to_boot_interrupts_intel);
2119 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_1,	quirk_reroute_to_boot_interrupts_intel);
2120 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_0,	quirk_reroute_to_boot_interrupts_intel);
2121 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80333_1,	quirk_reroute_to_boot_interrupts_intel);
2122 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ESB2_0,	quirk_reroute_to_boot_interrupts_intel);
2123 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_0,	quirk_reroute_to_boot_interrupts_intel);
2124 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXH_1,	quirk_reroute_to_boot_interrupts_intel);
2125 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_PXHV,	quirk_reroute_to_boot_interrupts_intel);
2126 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_0,	quirk_reroute_to_boot_interrupts_intel);
2127 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_80332_1,	quirk_reroute_to_boot_interrupts_intel);
2128 
2129 /*
2130  * On some chipsets we can disable the generation of legacy INTx boot
2131  * interrupts.
2132  */
2133 
2134 /*
2135  * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
2136  * 300641-004US, section 5.7.3.
2137  *
2138  * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
2139  * Core IO on Xeon E5 v2, see Intel order no 329188-003.
2140  * Core IO on Xeon E7 v2, see Intel order no 329595-002.
2141  * Core IO on Xeon E5 v3, see Intel order no 330784-003.
2142  * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
2143  * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
2144  * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
2145  * Core IO on Xeon D-1500, see Intel order no 332051-001.
2146  * Core IO on Xeon Scalable, see Intel order no 610950.
2147  */
2148 #define INTEL_6300_IOAPIC_ABAR		0x40	/* Bus 0, Dev 29, Func 5 */
2149 #define INTEL_6300_DISABLE_BOOT_IRQ	(1<<14)
2150 
2151 #define INTEL_CIPINTRC_CFG_OFFSET	0x14C	/* Bus 0, Dev 5, Func 0 */
2152 #define INTEL_CIPINTRC_DIS_INTX_ICH	(1<<25)
2153 
quirk_disable_intel_boot_interrupt(struct pci_dev * dev)2154 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
2155 {
2156 	u16 pci_config_word;
2157 	u32 pci_config_dword;
2158 
2159 	if (noioapicquirk)
2160 		return;
2161 
2162 	switch (dev->device) {
2163 	case PCI_DEVICE_ID_INTEL_ESB_10:
2164 		pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2165 				     &pci_config_word);
2166 		pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
2167 		pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2168 				      pci_config_word);
2169 		break;
2170 	case 0x3c28:	/* Xeon E5 1600/2600/4600	*/
2171 	case 0x0e28:	/* Xeon E5/E7 V2		*/
2172 	case 0x2f28:	/* Xeon E5/E7 V3,V4		*/
2173 	case 0x6f28:	/* Xeon D-1500			*/
2174 	case 0x2034:	/* Xeon Scalable Family		*/
2175 		pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2176 				      &pci_config_dword);
2177 		pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
2178 		pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2179 				       pci_config_dword);
2180 		break;
2181 	default:
2182 		return;
2183 	}
2184 	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2185 		 dev->vendor, dev->device);
2186 }
2187 /*
2188  * Device 29 Func 5 Device IDs of IO-APIC
2189  * containing ABAR—APIC1 Alternate Base Address Register
2190  */
2191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ESB_10,
2192 		quirk_disable_intel_boot_interrupt);
2193 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	PCI_DEVICE_ID_INTEL_ESB_10,
2194 		quirk_disable_intel_boot_interrupt);
2195 
2196 /*
2197  * Device 5 Func 0 Device IDs of Core IO modules/hubs
2198  * containing Coherent Interface Protocol Interrupt Control
2199  *
2200  * Device IDs obtained from volume 2 datasheets of commented
2201  * families above.
2202  */
2203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x3c28,
2204 		quirk_disable_intel_boot_interrupt);
2205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x0e28,
2206 		quirk_disable_intel_boot_interrupt);
2207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2f28,
2208 		quirk_disable_intel_boot_interrupt);
2209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x6f28,
2210 		quirk_disable_intel_boot_interrupt);
2211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x2034,
2212 		quirk_disable_intel_boot_interrupt);
2213 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	0x3c28,
2214 		quirk_disable_intel_boot_interrupt);
2215 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	0x0e28,
2216 		quirk_disable_intel_boot_interrupt);
2217 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	0x2f28,
2218 		quirk_disable_intel_boot_interrupt);
2219 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	0x6f28,
2220 		quirk_disable_intel_boot_interrupt);
2221 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL,	0x2034,
2222 		quirk_disable_intel_boot_interrupt);
2223 
2224 /* Disable boot interrupts on HT-1000 */
2225 #define BC_HT1000_FEATURE_REG		0x64
2226 #define BC_HT1000_PIC_REGS_ENABLE	(1<<0)
2227 #define BC_HT1000_MAP_IDX		0xC00
2228 #define BC_HT1000_MAP_DATA		0xC01
2229 
quirk_disable_broadcom_boot_interrupt(struct pci_dev * dev)2230 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
2231 {
2232 	u32 pci_config_dword;
2233 	u8 irq;
2234 
2235 	if (noioapicquirk)
2236 		return;
2237 
2238 	pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
2239 	pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
2240 			BC_HT1000_PIC_REGS_ENABLE);
2241 
2242 	for (irq = 0x10; irq < 0x10 + 32; irq++) {
2243 		outb(irq, BC_HT1000_MAP_IDX);
2244 		outb(0x00, BC_HT1000_MAP_DATA);
2245 	}
2246 
2247 	pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
2248 
2249 	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2250 		 dev->vendor, dev->device);
2251 }
2252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,	quirk_disable_broadcom_boot_interrupt);
2253 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,	quirk_disable_broadcom_boot_interrupt);
2254 
2255 /* Disable boot interrupts on AMD and ATI chipsets */
2256 
2257 /*
2258  * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2259  * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2260  * (due to an erratum).
2261  */
2262 #define AMD_813X_MISC			0x40
2263 #define AMD_813X_NOIOAMODE		(1<<0)
2264 #define AMD_813X_REV_B1			0x12
2265 #define AMD_813X_REV_B2			0x13
2266 
quirk_disable_amd_813x_boot_interrupt(struct pci_dev * dev)2267 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2268 {
2269 	u32 pci_config_dword;
2270 
2271 	if (noioapicquirk)
2272 		return;
2273 	if ((dev->revision == AMD_813X_REV_B1) ||
2274 	    (dev->revision == AMD_813X_REV_B2))
2275 		return;
2276 
2277 	pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2278 	pci_config_dword &= ~AMD_813X_NOIOAMODE;
2279 	pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2280 
2281 	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2282 		 dev->vendor, dev->device);
2283 }
2284 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8131_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
2285 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8131_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
2286 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8132_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
2287 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8132_BRIDGE,	quirk_disable_amd_813x_boot_interrupt);
2288 
2289 #define AMD_8111_PCI_IRQ_ROUTING	0x56
2290 
quirk_disable_amd_8111_boot_interrupt(struct pci_dev * dev)2291 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2292 {
2293 	u16 pci_config_word;
2294 
2295 	if (noioapicquirk)
2296 		return;
2297 
2298 	pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2299 	if (!pci_config_word) {
2300 		pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2301 			 dev->vendor, dev->device);
2302 		return;
2303 	}
2304 	pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2305 	pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2306 		 dev->vendor, dev->device);
2307 }
2308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,	quirk_disable_amd_8111_boot_interrupt);
2309 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,	quirk_disable_amd_8111_boot_interrupt);
2310 #endif /* CONFIG_X86_IO_APIC */
2311 
2312 /*
2313  * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2314  * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2315  * Re-allocate the region if needed...
2316  */
quirk_tc86c001_ide(struct pci_dev * dev)2317 static void quirk_tc86c001_ide(struct pci_dev *dev)
2318 {
2319 	struct resource *r = &dev->resource[0];
2320 
2321 	if (r->start & 0x8) {
2322 		r->flags |= IORESOURCE_UNSET;
2323 		r->start = 0;
2324 		r->end = 0xf;
2325 	}
2326 }
2327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2328 			 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2329 			 quirk_tc86c001_ide);
2330 
2331 /*
2332  * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2333  * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2334  * being read correctly if bit 7 of the base address is set.
2335  * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2336  * Re-allocate the regions to a 256-byte boundary if necessary.
2337  */
quirk_plx_pci9050(struct pci_dev * dev)2338 static void quirk_plx_pci9050(struct pci_dev *dev)
2339 {
2340 	unsigned int bar;
2341 
2342 	/* Fixed in revision 2 (PCI 9052). */
2343 	if (dev->revision >= 2)
2344 		return;
2345 	for (bar = 0; bar <= 1; bar++)
2346 		if (pci_resource_len(dev, bar) == 0x80 &&
2347 		    (pci_resource_start(dev, bar) & 0x80)) {
2348 			struct resource *r = &dev->resource[bar];
2349 			pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2350 				 bar);
2351 			r->flags |= IORESOURCE_UNSET;
2352 			r->start = 0;
2353 			r->end = 0xff;
2354 		}
2355 }
2356 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2357 			 quirk_plx_pci9050);
2358 /*
2359  * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2360  * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2361  * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2362  * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2363  *
2364  * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2365  * driver.
2366  */
2367 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2368 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2369 
quirk_netmos(struct pci_dev * dev)2370 static void quirk_netmos(struct pci_dev *dev)
2371 {
2372 	unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2373 	unsigned int num_serial = dev->subsystem_device & 0xf;
2374 
2375 	/*
2376 	 * These Netmos parts are multiport serial devices with optional
2377 	 * parallel ports.  Even when parallel ports are present, they
2378 	 * are identified as class SERIAL, which means the serial driver
2379 	 * will claim them.  To prevent this, mark them as class OTHER.
2380 	 * These combo devices should be claimed by parport_serial.
2381 	 *
2382 	 * The subdevice ID is of the form 0x00PS, where <P> is the number
2383 	 * of parallel ports and <S> is the number of serial ports.
2384 	 */
2385 	switch (dev->device) {
2386 	case PCI_DEVICE_ID_NETMOS_9835:
2387 		/* Well, this rule doesn't hold for the following 9835 device */
2388 		if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2389 				dev->subsystem_device == 0x0299)
2390 			return;
2391 		fallthrough;
2392 	case PCI_DEVICE_ID_NETMOS_9735:
2393 	case PCI_DEVICE_ID_NETMOS_9745:
2394 	case PCI_DEVICE_ID_NETMOS_9845:
2395 	case PCI_DEVICE_ID_NETMOS_9855:
2396 		if (num_parallel) {
2397 			pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2398 				dev->device, num_parallel, num_serial);
2399 			dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2400 			    (dev->class & 0xff);
2401 		}
2402 	}
2403 }
2404 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2405 			 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2406 
quirk_e100_interrupt(struct pci_dev * dev)2407 static void quirk_e100_interrupt(struct pci_dev *dev)
2408 {
2409 	u16 command, pmcsr;
2410 	u8 __iomem *csr;
2411 	u8 cmd_hi;
2412 
2413 	switch (dev->device) {
2414 	/* PCI IDs taken from drivers/net/e100.c */
2415 	case 0x1029:
2416 	case 0x1030 ... 0x1034:
2417 	case 0x1038 ... 0x103E:
2418 	case 0x1050 ... 0x1057:
2419 	case 0x1059:
2420 	case 0x1064 ... 0x106B:
2421 	case 0x1091 ... 0x1095:
2422 	case 0x1209:
2423 	case 0x1229:
2424 	case 0x2449:
2425 	case 0x2459:
2426 	case 0x245D:
2427 	case 0x27DC:
2428 		break;
2429 	default:
2430 		return;
2431 	}
2432 
2433 	/*
2434 	 * Some firmware hands off the e100 with interrupts enabled,
2435 	 * which can cause a flood of interrupts if packets are
2436 	 * received before the driver attaches to the device.  So
2437 	 * disable all e100 interrupts here.  The driver will
2438 	 * re-enable them when it's ready.
2439 	 */
2440 	pci_read_config_word(dev, PCI_COMMAND, &command);
2441 
2442 	if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2443 		return;
2444 
2445 	/*
2446 	 * Check that the device is in the D0 power state. If it's not,
2447 	 * there is no point to look any further.
2448 	 */
2449 	if (dev->pm_cap) {
2450 		pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2451 		if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2452 			return;
2453 	}
2454 
2455 	/* Convert from PCI bus to resource space.  */
2456 	csr = ioremap(pci_resource_start(dev, 0), 8);
2457 	if (!csr) {
2458 		pci_warn(dev, "Can't map e100 registers\n");
2459 		return;
2460 	}
2461 
2462 	cmd_hi = readb(csr + 3);
2463 	if (cmd_hi == 0) {
2464 		pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2465 		writeb(1, csr + 3);
2466 	}
2467 
2468 	iounmap(csr);
2469 }
2470 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2471 			PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2472 
2473 /*
2474  * The 82575 and 82598 may experience data corruption issues when transitioning
2475  * out of L0S.  To prevent this we need to disable L0S on the PCIe link.
2476  */
quirk_disable_aspm_l0s(struct pci_dev * dev)2477 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2478 {
2479 	pci_info(dev, "Disabling L0s\n");
2480 	pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2481 }
2482 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2483 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2484 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2485 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2486 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2487 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2488 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2489 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2490 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2491 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2492 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2493 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2494 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2495 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2496 
quirk_disable_aspm_l0s_l1(struct pci_dev * dev)2497 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2498 {
2499 	pci_info(dev, "Disabling ASPM L0s/L1\n");
2500 	pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2501 }
2502 
2503 /*
2504  * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2505  * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2506  * disable both L0s and L1 for now to be safe.
2507  */
2508 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2509 
2510 /*
2511  * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2512  * Link bit cleared after starting the link retrain process to allow this
2513  * process to finish.
2514  *
2515  * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130.  See also the
2516  * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2517  */
quirk_enable_clear_retrain_link(struct pci_dev * dev)2518 static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2519 {
2520 	dev->clear_retrain_link = 1;
2521 	pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2522 }
2523 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link);
2524 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link);
2525 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link);
2526 
fixup_rev1_53c810(struct pci_dev * dev)2527 static void fixup_rev1_53c810(struct pci_dev *dev)
2528 {
2529 	u32 class = dev->class;
2530 
2531 	/*
2532 	 * rev 1 ncr53c810 chips don't set the class at all which means
2533 	 * they don't get their resources remapped. Fix that here.
2534 	 */
2535 	if (class)
2536 		return;
2537 
2538 	dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2539 	pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2540 		 class, dev->class);
2541 }
2542 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2543 
2544 /* Enable 1k I/O space granularity on the Intel P64H2 */
quirk_p64h2_1k_io(struct pci_dev * dev)2545 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2546 {
2547 	u16 en1k;
2548 
2549 	pci_read_config_word(dev, 0x40, &en1k);
2550 
2551 	if (en1k & 0x200) {
2552 		pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2553 		dev->io_window_1k = 1;
2554 	}
2555 }
2556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2557 
2558 /*
2559  * Under some circumstances, AER is not linked with extended capabilities.
2560  * Force it to be linked by setting the corresponding control bit in the
2561  * config space.
2562  */
quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev * dev)2563 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2564 {
2565 	uint8_t b;
2566 
2567 	if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2568 		if (!(b & 0x20)) {
2569 			pci_write_config_byte(dev, 0xf41, b | 0x20);
2570 			pci_info(dev, "Linking AER extended capability\n");
2571 		}
2572 	}
2573 }
2574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2575 			quirk_nvidia_ck804_pcie_aer_ext_cap);
2576 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA,  PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2577 			quirk_nvidia_ck804_pcie_aer_ext_cap);
2578 
quirk_via_cx700_pci_parking_caching(struct pci_dev * dev)2579 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2580 {
2581 	/*
2582 	 * Disable PCI Bus Parking and PCI Master read caching on CX700
2583 	 * which causes unspecified timing errors with a VT6212L on the PCI
2584 	 * bus leading to USB2.0 packet loss.
2585 	 *
2586 	 * This quirk is only enabled if a second (on the external PCI bus)
2587 	 * VT6212L is found -- the CX700 core itself also contains a USB
2588 	 * host controller with the same PCI ID as the VT6212L.
2589 	 */
2590 
2591 	/* Count VT6212L instances */
2592 	struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2593 		PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2594 	uint8_t b;
2595 
2596 	/*
2597 	 * p should contain the first (internal) VT6212L -- see if we have
2598 	 * an external one by searching again.
2599 	 */
2600 	p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2601 	if (!p)
2602 		return;
2603 	pci_dev_put(p);
2604 
2605 	if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2606 		if (b & 0x40) {
2607 			/* Turn off PCI Bus Parking */
2608 			pci_write_config_byte(dev, 0x76, b ^ 0x40);
2609 
2610 			pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2611 		}
2612 	}
2613 
2614 	if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2615 		if (b != 0) {
2616 			/* Turn off PCI Master read caching */
2617 			pci_write_config_byte(dev, 0x72, 0x0);
2618 
2619 			/* Set PCI Master Bus time-out to "1x16 PCLK" */
2620 			pci_write_config_byte(dev, 0x75, 0x1);
2621 
2622 			/* Disable "Read FIFO Timer" */
2623 			pci_write_config_byte(dev, 0x77, 0x0);
2624 
2625 			pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2626 		}
2627 	}
2628 }
2629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2630 
quirk_brcm_5719_limit_mrrs(struct pci_dev * dev)2631 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2632 {
2633 	u32 rev;
2634 
2635 	pci_read_config_dword(dev, 0xf4, &rev);
2636 
2637 	/* Only CAP the MRRS if the device is a 5719 A0 */
2638 	if (rev == 0x05719000) {
2639 		int readrq = pcie_get_readrq(dev);
2640 		if (readrq > 2048)
2641 			pcie_set_readrq(dev, 2048);
2642 	}
2643 }
2644 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2645 			 PCI_DEVICE_ID_TIGON3_5719,
2646 			 quirk_brcm_5719_limit_mrrs);
2647 
2648 /*
2649  * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2650  * hide device 6 which configures the overflow device access containing the
2651  * DRBs - this is where we expose device 6.
2652  * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2653  */
quirk_unhide_mch_dev6(struct pci_dev * dev)2654 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2655 {
2656 	u8 reg;
2657 
2658 	if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2659 		pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2660 		pci_write_config_byte(dev, 0xF4, reg | 0x02);
2661 	}
2662 }
2663 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2664 			quirk_unhide_mch_dev6);
2665 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2666 			quirk_unhide_mch_dev6);
2667 
2668 #ifdef CONFIG_PCI_MSI
2669 /*
2670  * Some chipsets do not support MSI. We cannot easily rely on setting
2671  * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2672  * other buses controlled by the chipset even if Linux is not aware of it.
2673  * Instead of setting the flag on all buses in the machine, simply disable
2674  * MSI globally.
2675  */
quirk_disable_all_msi(struct pci_dev * dev)2676 static void quirk_disable_all_msi(struct pci_dev *dev)
2677 {
2678 	pci_no_msi();
2679 	pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2680 }
2681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2688 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2689 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi);
2690 
2691 /* Disable MSI on chipsets that are known to not support it */
quirk_disable_msi(struct pci_dev * dev)2692 static void quirk_disable_msi(struct pci_dev *dev)
2693 {
2694 	if (dev->subordinate) {
2695 		pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2696 		dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2697 	}
2698 }
2699 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2700 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2702 
2703 /*
2704  * The APC bridge device in AMD 780 family northbridges has some random
2705  * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2706  * we use the possible vendor/device IDs of the host bridge for the
2707  * declared quirk, and search for the APC bridge by slot number.
2708  */
quirk_amd_780_apc_msi(struct pci_dev * host_bridge)2709 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2710 {
2711 	struct pci_dev *apc_bridge;
2712 
2713 	apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2714 	if (apc_bridge) {
2715 		if (apc_bridge->device == 0x9602)
2716 			quirk_disable_msi(apc_bridge);
2717 		pci_dev_put(apc_bridge);
2718 	}
2719 }
2720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2721 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2722 
2723 /*
2724  * Go through the list of HyperTransport capabilities and return 1 if a HT
2725  * MSI capability is found and enabled.
2726  */
msi_ht_cap_enabled(struct pci_dev * dev)2727 static int msi_ht_cap_enabled(struct pci_dev *dev)
2728 {
2729 	int pos, ttl = PCI_FIND_CAP_TTL;
2730 
2731 	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2732 	while (pos && ttl--) {
2733 		u8 flags;
2734 
2735 		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2736 					 &flags) == 0) {
2737 			pci_info(dev, "Found %s HT MSI Mapping\n",
2738 				flags & HT_MSI_FLAGS_ENABLE ?
2739 				"enabled" : "disabled");
2740 			return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2741 		}
2742 
2743 		pos = pci_find_next_ht_capability(dev, pos,
2744 						  HT_CAPTYPE_MSI_MAPPING);
2745 	}
2746 	return 0;
2747 }
2748 
2749 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
quirk_msi_ht_cap(struct pci_dev * dev)2750 static void quirk_msi_ht_cap(struct pci_dev *dev)
2751 {
2752 	if (!msi_ht_cap_enabled(dev))
2753 		quirk_disable_msi(dev);
2754 }
2755 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2756 			quirk_msi_ht_cap);
2757 
2758 /*
2759  * The nVidia CK804 chipset may have 2 HT MSI mappings.  MSI is supported
2760  * if the MSI capability is set in any of these mappings.
2761  */
quirk_nvidia_ck804_msi_ht_cap(struct pci_dev * dev)2762 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2763 {
2764 	struct pci_dev *pdev;
2765 
2766 	/*
2767 	 * Check HT MSI cap on this chipset and the root one.  A single one
2768 	 * having MSI is enough to be sure that MSI is supported.
2769 	 */
2770 	pdev = pci_get_slot(dev->bus, 0);
2771 	if (!pdev)
2772 		return;
2773 	if (!msi_ht_cap_enabled(pdev))
2774 		quirk_msi_ht_cap(dev);
2775 	pci_dev_put(pdev);
2776 }
2777 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2778 			quirk_nvidia_ck804_msi_ht_cap);
2779 
2780 /* Force enable MSI mapping capability on HT bridges */
ht_enable_msi_mapping(struct pci_dev * dev)2781 static void ht_enable_msi_mapping(struct pci_dev *dev)
2782 {
2783 	int pos, ttl = PCI_FIND_CAP_TTL;
2784 
2785 	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2786 	while (pos && ttl--) {
2787 		u8 flags;
2788 
2789 		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2790 					 &flags) == 0) {
2791 			pci_info(dev, "Enabling HT MSI Mapping\n");
2792 
2793 			pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2794 					      flags | HT_MSI_FLAGS_ENABLE);
2795 		}
2796 		pos = pci_find_next_ht_capability(dev, pos,
2797 						  HT_CAPTYPE_MSI_MAPPING);
2798 	}
2799 }
2800 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2801 			 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2802 			 ht_enable_msi_mapping);
2803 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2804 			 ht_enable_msi_mapping);
2805 
2806 /*
2807  * The P5N32-SLI motherboards from Asus have a problem with MSI
2808  * for the MCP55 NIC. It is not yet determined whether the MSI problem
2809  * also affects other devices. As for now, turn off MSI for this device.
2810  */
nvenet_msi_disable(struct pci_dev * dev)2811 static void nvenet_msi_disable(struct pci_dev *dev)
2812 {
2813 	const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2814 
2815 	if (board_name &&
2816 	    (strstr(board_name, "P5N32-SLI PREMIUM") ||
2817 	     strstr(board_name, "P5N32-E SLI"))) {
2818 		pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2819 		dev->no_msi = 1;
2820 	}
2821 }
2822 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2823 			PCI_DEVICE_ID_NVIDIA_NVENET_15,
2824 			nvenet_msi_disable);
2825 
2826 /*
2827  * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device
2828  * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI
2829  * interrupts for PME and AER events; instead only INTx interrupts are
2830  * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts
2831  * for other events, since PCIe specification doesn't support using a mix of
2832  * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2833  * service drivers registering their respective ISRs for MSIs.
2834  */
pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev * dev)2835 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2836 {
2837 	dev->no_msi = 1;
2838 }
2839 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2840 			      PCI_CLASS_BRIDGE_PCI, 8,
2841 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2842 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2843 			      PCI_CLASS_BRIDGE_PCI, 8,
2844 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2845 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2846 			      PCI_CLASS_BRIDGE_PCI, 8,
2847 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2848 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2849 			      PCI_CLASS_BRIDGE_PCI, 8,
2850 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2851 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2852 			      PCI_CLASS_BRIDGE_PCI, 8,
2853 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2854 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2855 			      PCI_CLASS_BRIDGE_PCI, 8,
2856 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2857 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2858 			      PCI_CLASS_BRIDGE_PCI, 8,
2859 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2860 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2861 			      PCI_CLASS_BRIDGE_PCI, 8,
2862 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2863 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2864 			      PCI_CLASS_BRIDGE_PCI, 8,
2865 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2866 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2867 			      PCI_CLASS_BRIDGE_PCI, 8,
2868 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2869 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2870 			      PCI_CLASS_BRIDGE_PCI, 8,
2871 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2872 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2873 			      PCI_CLASS_BRIDGE_PCI, 8,
2874 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2875 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2876 			      PCI_CLASS_BRIDGE_PCI, 8,
2877 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2878 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a,
2879 			      PCI_CLASS_BRIDGE_PCI, 8,
2880 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2881 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c,
2882 			      PCI_CLASS_BRIDGE_PCI, 8,
2883 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2884 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e,
2885 			      PCI_CLASS_BRIDGE_PCI, 8,
2886 			      pci_quirk_nvidia_tegra_disable_rp_msi);
2887 
2888 /*
2889  * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2890  * config register.  This register controls the routing of legacy
2891  * interrupts from devices that route through the MCP55.  If this register
2892  * is misprogrammed, interrupts are only sent to the BSP, unlike
2893  * conventional systems where the IRQ is broadcast to all online CPUs.  Not
2894  * having this register set properly prevents kdump from booting up
2895  * properly, so let's make sure that we have it set correctly.
2896  * Note that this is an undocumented register.
2897  */
nvbridge_check_legacy_irq_routing(struct pci_dev * dev)2898 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2899 {
2900 	u32 cfg;
2901 
2902 	if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2903 		return;
2904 
2905 	pci_read_config_dword(dev, 0x74, &cfg);
2906 
2907 	if (cfg & ((1 << 2) | (1 << 15))) {
2908 		pr_info("Rewriting IRQ routing register on MCP55\n");
2909 		cfg &= ~((1 << 2) | (1 << 15));
2910 		pci_write_config_dword(dev, 0x74, cfg);
2911 	}
2912 }
2913 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2914 			PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2915 			nvbridge_check_legacy_irq_routing);
2916 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2917 			PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2918 			nvbridge_check_legacy_irq_routing);
2919 
ht_check_msi_mapping(struct pci_dev * dev)2920 static int ht_check_msi_mapping(struct pci_dev *dev)
2921 {
2922 	int pos, ttl = PCI_FIND_CAP_TTL;
2923 	int found = 0;
2924 
2925 	/* Check if there is HT MSI cap or enabled on this device */
2926 	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2927 	while (pos && ttl--) {
2928 		u8 flags;
2929 
2930 		if (found < 1)
2931 			found = 1;
2932 		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2933 					 &flags) == 0) {
2934 			if (flags & HT_MSI_FLAGS_ENABLE) {
2935 				if (found < 2) {
2936 					found = 2;
2937 					break;
2938 				}
2939 			}
2940 		}
2941 		pos = pci_find_next_ht_capability(dev, pos,
2942 						  HT_CAPTYPE_MSI_MAPPING);
2943 	}
2944 
2945 	return found;
2946 }
2947 
host_bridge_with_leaf(struct pci_dev * host_bridge)2948 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2949 {
2950 	struct pci_dev *dev;
2951 	int pos;
2952 	int i, dev_no;
2953 	int found = 0;
2954 
2955 	dev_no = host_bridge->devfn >> 3;
2956 	for (i = dev_no + 1; i < 0x20; i++) {
2957 		dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2958 		if (!dev)
2959 			continue;
2960 
2961 		/* found next host bridge? */
2962 		pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2963 		if (pos != 0) {
2964 			pci_dev_put(dev);
2965 			break;
2966 		}
2967 
2968 		if (ht_check_msi_mapping(dev)) {
2969 			found = 1;
2970 			pci_dev_put(dev);
2971 			break;
2972 		}
2973 		pci_dev_put(dev);
2974 	}
2975 
2976 	return found;
2977 }
2978 
2979 #define PCI_HT_CAP_SLAVE_CTRL0     4    /* link control */
2980 #define PCI_HT_CAP_SLAVE_CTRL1     8    /* link control to */
2981 
is_end_of_ht_chain(struct pci_dev * dev)2982 static int is_end_of_ht_chain(struct pci_dev *dev)
2983 {
2984 	int pos, ctrl_off;
2985 	int end = 0;
2986 	u16 flags, ctrl;
2987 
2988 	pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2989 
2990 	if (!pos)
2991 		goto out;
2992 
2993 	pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2994 
2995 	ctrl_off = ((flags >> 10) & 1) ?
2996 			PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2997 	pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2998 
2999 	if (ctrl & (1 << 6))
3000 		end = 1;
3001 
3002 out:
3003 	return end;
3004 }
3005 
nv_ht_enable_msi_mapping(struct pci_dev * dev)3006 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
3007 {
3008 	struct pci_dev *host_bridge;
3009 	int pos;
3010 	int i, dev_no;
3011 	int found = 0;
3012 
3013 	dev_no = dev->devfn >> 3;
3014 	for (i = dev_no; i >= 0; i--) {
3015 		host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
3016 		if (!host_bridge)
3017 			continue;
3018 
3019 		pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
3020 		if (pos != 0) {
3021 			found = 1;
3022 			break;
3023 		}
3024 		pci_dev_put(host_bridge);
3025 	}
3026 
3027 	if (!found)
3028 		return;
3029 
3030 	/* don't enable end_device/host_bridge with leaf directly here */
3031 	if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
3032 	    host_bridge_with_leaf(host_bridge))
3033 		goto out;
3034 
3035 	/* root did that ! */
3036 	if (msi_ht_cap_enabled(host_bridge))
3037 		goto out;
3038 
3039 	ht_enable_msi_mapping(dev);
3040 
3041 out:
3042 	pci_dev_put(host_bridge);
3043 }
3044 
ht_disable_msi_mapping(struct pci_dev * dev)3045 static void ht_disable_msi_mapping(struct pci_dev *dev)
3046 {
3047 	int pos, ttl = PCI_FIND_CAP_TTL;
3048 
3049 	pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
3050 	while (pos && ttl--) {
3051 		u8 flags;
3052 
3053 		if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
3054 					 &flags) == 0) {
3055 			pci_info(dev, "Disabling HT MSI Mapping\n");
3056 
3057 			pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
3058 					      flags & ~HT_MSI_FLAGS_ENABLE);
3059 		}
3060 		pos = pci_find_next_ht_capability(dev, pos,
3061 						  HT_CAPTYPE_MSI_MAPPING);
3062 	}
3063 }
3064 
__nv_msi_ht_cap_quirk(struct pci_dev * dev,int all)3065 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
3066 {
3067 	struct pci_dev *host_bridge;
3068 	int pos;
3069 	int found;
3070 
3071 	if (!pci_msi_enabled())
3072 		return;
3073 
3074 	/* check if there is HT MSI cap or enabled on this device */
3075 	found = ht_check_msi_mapping(dev);
3076 
3077 	/* no HT MSI CAP */
3078 	if (found == 0)
3079 		return;
3080 
3081 	/*
3082 	 * HT MSI mapping should be disabled on devices that are below
3083 	 * a non-HyperTransport host bridge. Locate the host bridge.
3084 	 */
3085 	host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
3086 						  PCI_DEVFN(0, 0));
3087 	if (host_bridge == NULL) {
3088 		pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
3089 		return;
3090 	}
3091 
3092 	pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
3093 	if (pos != 0) {
3094 		/* Host bridge is to HT */
3095 		if (found == 1) {
3096 			/* it is not enabled, try to enable it */
3097 			if (all)
3098 				ht_enable_msi_mapping(dev);
3099 			else
3100 				nv_ht_enable_msi_mapping(dev);
3101 		}
3102 		goto out;
3103 	}
3104 
3105 	/* HT MSI is not enabled */
3106 	if (found == 1)
3107 		goto out;
3108 
3109 	/* Host bridge is not to HT, disable HT MSI mapping on this device */
3110 	ht_disable_msi_mapping(dev);
3111 
3112 out:
3113 	pci_dev_put(host_bridge);
3114 }
3115 
nv_msi_ht_cap_quirk_all(struct pci_dev * dev)3116 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
3117 {
3118 	return __nv_msi_ht_cap_quirk(dev, 1);
3119 }
3120 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
3121 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
3122 
nv_msi_ht_cap_quirk_leaf(struct pci_dev * dev)3123 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
3124 {
3125 	return __nv_msi_ht_cap_quirk(dev, 0);
3126 }
3127 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
3128 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
3129 
quirk_msi_intx_disable_bug(struct pci_dev * dev)3130 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
3131 {
3132 	dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3133 }
3134 
quirk_msi_intx_disable_ati_bug(struct pci_dev * dev)3135 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
3136 {
3137 	struct pci_dev *p;
3138 
3139 	/*
3140 	 * SB700 MSI issue will be fixed at HW level from revision A21;
3141 	 * we need check PCI REVISION ID of SMBus controller to get SB700
3142 	 * revision.
3143 	 */
3144 	p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3145 			   NULL);
3146 	if (!p)
3147 		return;
3148 
3149 	if ((p->revision < 0x3B) && (p->revision >= 0x30))
3150 		dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3151 	pci_dev_put(p);
3152 }
3153 
quirk_msi_intx_disable_qca_bug(struct pci_dev * dev)3154 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
3155 {
3156 	/* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
3157 	if (dev->revision < 0x18) {
3158 		pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
3159 		dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
3160 	}
3161 }
3162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3163 			PCI_DEVICE_ID_TIGON3_5780,
3164 			quirk_msi_intx_disable_bug);
3165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3166 			PCI_DEVICE_ID_TIGON3_5780S,
3167 			quirk_msi_intx_disable_bug);
3168 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3169 			PCI_DEVICE_ID_TIGON3_5714,
3170 			quirk_msi_intx_disable_bug);
3171 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3172 			PCI_DEVICE_ID_TIGON3_5714S,
3173 			quirk_msi_intx_disable_bug);
3174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3175 			PCI_DEVICE_ID_TIGON3_5715,
3176 			quirk_msi_intx_disable_bug);
3177 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3178 			PCI_DEVICE_ID_TIGON3_5715S,
3179 			quirk_msi_intx_disable_bug);
3180 
3181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3182 			quirk_msi_intx_disable_ati_bug);
3183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3184 			quirk_msi_intx_disable_ati_bug);
3185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3186 			quirk_msi_intx_disable_ati_bug);
3187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3188 			quirk_msi_intx_disable_ati_bug);
3189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3190 			quirk_msi_intx_disable_ati_bug);
3191 
3192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3193 			quirk_msi_intx_disable_bug);
3194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3195 			quirk_msi_intx_disable_bug);
3196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3197 			quirk_msi_intx_disable_bug);
3198 
3199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3200 			quirk_msi_intx_disable_bug);
3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3202 			quirk_msi_intx_disable_bug);
3203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3204 			quirk_msi_intx_disable_bug);
3205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3206 			quirk_msi_intx_disable_bug);
3207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3208 			quirk_msi_intx_disable_bug);
3209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3210 			quirk_msi_intx_disable_bug);
3211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3212 			quirk_msi_intx_disable_qca_bug);
3213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3214 			quirk_msi_intx_disable_qca_bug);
3215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3216 			quirk_msi_intx_disable_qca_bug);
3217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3218 			quirk_msi_intx_disable_qca_bug);
3219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3220 			quirk_msi_intx_disable_qca_bug);
3221 
3222 /*
3223  * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3224  * should be disabled on platforms where the device (mistakenly) advertises it.
3225  *
3226  * Notice that this quirk also disables MSI (which may work, but hasn't been
3227  * tested), since currently there is no standard way to disable only MSI-X.
3228  *
3229  * The 0031 device id is reused for other non Root Port device types,
3230  * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3231  */
quirk_al_msi_disable(struct pci_dev * dev)3232 static void quirk_al_msi_disable(struct pci_dev *dev)
3233 {
3234 	dev->no_msi = 1;
3235 	pci_warn(dev, "Disabling MSI/MSI-X\n");
3236 }
3237 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3238 			      PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
3239 #endif /* CONFIG_PCI_MSI */
3240 
3241 /*
3242  * Allow manual resource allocation for PCI hotplug bridges via
3243  * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3244  * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3245  * allocate resources when hotplug device is inserted and PCI bus is
3246  * rescanned.
3247  */
quirk_hotplug_bridge(struct pci_dev * dev)3248 static void quirk_hotplug_bridge(struct pci_dev *dev)
3249 {
3250 	dev->is_hotplug_bridge = 1;
3251 }
3252 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3253 
3254 /*
3255  * This is a quirk for the Ricoh MMC controller found as a part of some
3256  * multifunction chips.
3257  *
3258  * This is very similar and based on the ricoh_mmc driver written by
3259  * Philip Langdale. Thank you for these magic sequences.
3260  *
3261  * These chips implement the four main memory card controllers (SD, MMC,
3262  * MS, xD) and one or both of CardBus or FireWire.
3263  *
3264  * It happens that they implement SD and MMC support as separate
3265  * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3266  * cards but the chip detects MMC cards in hardware and directs them to the
3267  * MMC controller - so the SDHCI driver never sees them.
3268  *
3269  * To get around this, we must disable the useless MMC controller.  At that
3270  * point, the SDHCI controller will start seeing them.  It seems to be the
3271  * case that the relevant PCI registers to deactivate the MMC controller
3272  * live on PCI function 0, which might be the CardBus controller or the
3273  * FireWire controller, depending on the particular chip in question
3274  *
3275  * This has to be done early, because as soon as we disable the MMC controller
3276  * other PCI functions shift up one level, e.g. function #2 becomes function
3277  * #1, and this will confuse the PCI core.
3278  */
3279 #ifdef CONFIG_MMC_RICOH_MMC
ricoh_mmc_fixup_rl5c476(struct pci_dev * dev)3280 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3281 {
3282 	u8 write_enable;
3283 	u8 write_target;
3284 	u8 disable;
3285 
3286 	/*
3287 	 * Disable via CardBus interface
3288 	 *
3289 	 * This must be done via function #0
3290 	 */
3291 	if (PCI_FUNC(dev->devfn))
3292 		return;
3293 
3294 	pci_read_config_byte(dev, 0xB7, &disable);
3295 	if (disable & 0x02)
3296 		return;
3297 
3298 	pci_read_config_byte(dev, 0x8E, &write_enable);
3299 	pci_write_config_byte(dev, 0x8E, 0xAA);
3300 	pci_read_config_byte(dev, 0x8D, &write_target);
3301 	pci_write_config_byte(dev, 0x8D, 0xB7);
3302 	pci_write_config_byte(dev, 0xB7, disable | 0x02);
3303 	pci_write_config_byte(dev, 0x8E, write_enable);
3304 	pci_write_config_byte(dev, 0x8D, write_target);
3305 
3306 	pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3307 	pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3308 }
3309 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3310 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3311 
ricoh_mmc_fixup_r5c832(struct pci_dev * dev)3312 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3313 {
3314 	u8 write_enable;
3315 	u8 disable;
3316 
3317 	/*
3318 	 * Disable via FireWire interface
3319 	 *
3320 	 * This must be done via function #0
3321 	 */
3322 	if (PCI_FUNC(dev->devfn))
3323 		return;
3324 	/*
3325 	 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3326 	 * certain types of SD/MMC cards. Lowering the SD base clock
3327 	 * frequency from 200Mhz to 50Mhz fixes this issue.
3328 	 *
3329 	 * 0x150 - SD2.0 mode enable for changing base clock
3330 	 *	   frequency to 50Mhz
3331 	 * 0xe1  - Base clock frequency
3332 	 * 0x32  - 50Mhz new clock frequency
3333 	 * 0xf9  - Key register for 0x150
3334 	 * 0xfc  - key register for 0xe1
3335 	 */
3336 	if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3337 	    dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3338 		pci_write_config_byte(dev, 0xf9, 0xfc);
3339 		pci_write_config_byte(dev, 0x150, 0x10);
3340 		pci_write_config_byte(dev, 0xf9, 0x00);
3341 		pci_write_config_byte(dev, 0xfc, 0x01);
3342 		pci_write_config_byte(dev, 0xe1, 0x32);
3343 		pci_write_config_byte(dev, 0xfc, 0x00);
3344 
3345 		pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3346 	}
3347 
3348 	pci_read_config_byte(dev, 0xCB, &disable);
3349 
3350 	if (disable & 0x02)
3351 		return;
3352 
3353 	pci_read_config_byte(dev, 0xCA, &write_enable);
3354 	pci_write_config_byte(dev, 0xCA, 0x57);
3355 	pci_write_config_byte(dev, 0xCB, disable | 0x02);
3356 	pci_write_config_byte(dev, 0xCA, write_enable);
3357 
3358 	pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3359 	pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3360 
3361 }
3362 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3363 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3364 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3365 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3366 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3367 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3368 #endif /*CONFIG_MMC_RICOH_MMC*/
3369 
3370 #ifdef CONFIG_DMAR_TABLE
3371 #define VTUNCERRMSK_REG	0x1ac
3372 #define VTD_MSK_SPEC_ERRORS	(1 << 31)
3373 /*
3374  * This is a quirk for masking VT-d spec-defined errors to platform error
3375  * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3376  * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3377  * on the RAS config settings of the platform) when a VT-d fault happens.
3378  * The resulting SMI caused the system to hang.
3379  *
3380  * VT-d spec-related errors are already handled by the VT-d OS code, so no
3381  * need to report the same error through other channels.
3382  */
vtd_mask_spec_errors(struct pci_dev * dev)3383 static void vtd_mask_spec_errors(struct pci_dev *dev)
3384 {
3385 	u32 word;
3386 
3387 	pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3388 	pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3389 }
3390 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3391 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3392 #endif
3393 
fixup_ti816x_class(struct pci_dev * dev)3394 static void fixup_ti816x_class(struct pci_dev *dev)
3395 {
3396 	u32 class = dev->class;
3397 
3398 	/* TI 816x devices do not have class code set when in PCIe boot mode */
3399 	dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3400 	pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3401 		 class, dev->class);
3402 }
3403 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3404 			      PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3405 
3406 /*
3407  * Some PCIe devices do not work reliably with the claimed maximum
3408  * payload size supported.
3409  */
fixup_mpss_256(struct pci_dev * dev)3410 static void fixup_mpss_256(struct pci_dev *dev)
3411 {
3412 	dev->pcie_mpss = 1; /* 256 bytes */
3413 }
3414 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3415 			PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3416 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3417 			PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3418 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE,
3419 			PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3420 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256);
3421 
3422 /*
3423  * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3424  * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3425  * Since there is no way of knowing what the PCIe MPS on each fabric will be
3426  * until all of the devices are discovered and buses walked, read completion
3427  * coalescing must be disabled.  Unfortunately, it cannot be re-enabled because
3428  * it is possible to hotplug a device with MPS of 256B.
3429  */
quirk_intel_mc_errata(struct pci_dev * dev)3430 static void quirk_intel_mc_errata(struct pci_dev *dev)
3431 {
3432 	int err;
3433 	u16 rcc;
3434 
3435 	if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3436 	    pcie_bus_config == PCIE_BUS_DEFAULT)
3437 		return;
3438 
3439 	/*
3440 	 * Intel erratum specifies bits to change but does not say what
3441 	 * they are.  Keeping them magical until such time as the registers
3442 	 * and values can be explained.
3443 	 */
3444 	err = pci_read_config_word(dev, 0x48, &rcc);
3445 	if (err) {
3446 		pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3447 		return;
3448 	}
3449 
3450 	if (!(rcc & (1 << 10)))
3451 		return;
3452 
3453 	rcc &= ~(1 << 10);
3454 
3455 	err = pci_write_config_word(dev, 0x48, rcc);
3456 	if (err) {
3457 		pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3458 		return;
3459 	}
3460 
3461 	pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3462 }
3463 /* Intel 5000 series memory controllers and ports 2-7 */
3464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3467 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3469 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3471 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3472 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3473 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3474 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3475 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3476 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3477 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3478 /* Intel 5100 series memory controllers and ports 2-7 */
3479 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3490 
3491 /*
3492  * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3493  * To work around this, query the size it should be configured to by the
3494  * device and modify the resource end to correspond to this new size.
3495  */
quirk_intel_ntb(struct pci_dev * dev)3496 static void quirk_intel_ntb(struct pci_dev *dev)
3497 {
3498 	int rc;
3499 	u8 val;
3500 
3501 	rc = pci_read_config_byte(dev, 0x00D0, &val);
3502 	if (rc)
3503 		return;
3504 
3505 	dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3506 
3507 	rc = pci_read_config_byte(dev, 0x00D1, &val);
3508 	if (rc)
3509 		return;
3510 
3511 	dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3512 }
3513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3515 
3516 /*
3517  * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3518  * though no one is handling them (e.g., if the i915 driver is never
3519  * loaded).  Additionally the interrupt destination is not set up properly
3520  * and the interrupt ends up -somewhere-.
3521  *
3522  * These spurious interrupts are "sticky" and the kernel disables the
3523  * (shared) interrupt line after 100,000+ generated interrupts.
3524  *
3525  * Fix it by disabling the still enabled interrupts.  This resolves crashes
3526  * often seen on monitor unplug.
3527  */
3528 #define I915_DEIER_REG 0x4400c
disable_igfx_irq(struct pci_dev * dev)3529 static void disable_igfx_irq(struct pci_dev *dev)
3530 {
3531 	void __iomem *regs = pci_iomap(dev, 0, 0);
3532 	if (regs == NULL) {
3533 		pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3534 		return;
3535 	}
3536 
3537 	/* Check if any interrupt line is still enabled */
3538 	if (readl(regs + I915_DEIER_REG) != 0) {
3539 		pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3540 
3541 		writel(0, regs + I915_DEIER_REG);
3542 	}
3543 
3544 	pci_iounmap(dev, regs);
3545 }
3546 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3547 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3548 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3549 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3550 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3551 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3552 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3553 
3554 /*
3555  * PCI devices which are on Intel chips can skip the 10ms delay
3556  * before entering D3 mode.
3557  */
quirk_remove_d3hot_delay(struct pci_dev * dev)3558 static void quirk_remove_d3hot_delay(struct pci_dev *dev)
3559 {
3560 	dev->d3hot_delay = 0;
3561 }
3562 /* C600 Series devices do not need 10ms d3hot_delay */
3563 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
3564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
3565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
3566 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
3568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
3569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
3570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
3571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
3572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
3573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
3574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
3575 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
3576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
3577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
3578 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */
3579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
3580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
3581 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
3582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
3583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
3584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
3585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
3586 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
3587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
3588 
3589 /*
3590  * Some devices may pass our check in pci_intx_mask_supported() if
3591  * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3592  * support this feature.
3593  */
quirk_broken_intx_masking(struct pci_dev * dev)3594 static void quirk_broken_intx_masking(struct pci_dev *dev)
3595 {
3596 	dev->broken_intx_masking = 1;
3597 }
3598 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3599 			quirk_broken_intx_masking);
3600 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3601 			quirk_broken_intx_masking);
3602 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3603 			quirk_broken_intx_masking);
3604 
3605 /*
3606  * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3607  * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3608  *
3609  * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3610  */
3611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3612 			quirk_broken_intx_masking);
3613 
3614 /*
3615  * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3616  * DisINTx can be set but the interrupt status bit is non-functional.
3617  */
3618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3620 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3621 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3622 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3623 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3631 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3634 
3635 static u16 mellanox_broken_intx_devs[] = {
3636 	PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3637 	PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3638 	PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3639 	PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3640 	PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3641 	PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3642 	PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3643 	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3644 	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3645 	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3646 	PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3647 	PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3648 	PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3649 	PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3650 };
3651 
3652 #define CONNECTX_4_CURR_MAX_MINOR 99
3653 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3654 
3655 /*
3656  * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3657  * If so, don't mark it as broken.
3658  * FW minor > 99 means older FW version format and no INTx masking support.
3659  * FW minor < 14 means new FW version format and no INTx masking support.
3660  */
mellanox_check_broken_intx_masking(struct pci_dev * pdev)3661 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3662 {
3663 	__be32 __iomem *fw_ver;
3664 	u16 fw_major;
3665 	u16 fw_minor;
3666 	u16 fw_subminor;
3667 	u32 fw_maj_min;
3668 	u32 fw_sub_min;
3669 	int i;
3670 
3671 	for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3672 		if (pdev->device == mellanox_broken_intx_devs[i]) {
3673 			pdev->broken_intx_masking = 1;
3674 			return;
3675 		}
3676 	}
3677 
3678 	/*
3679 	 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3680 	 * support so shouldn't be checked further
3681 	 */
3682 	if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3683 		return;
3684 
3685 	if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3686 	    pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3687 		return;
3688 
3689 	/* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3690 	if (pci_enable_device_mem(pdev)) {
3691 		pci_warn(pdev, "Can't enable device memory\n");
3692 		return;
3693 	}
3694 
3695 	fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3696 	if (!fw_ver) {
3697 		pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3698 		goto out;
3699 	}
3700 
3701 	/* Reading from resource space should be 32b aligned */
3702 	fw_maj_min = ioread32be(fw_ver);
3703 	fw_sub_min = ioread32be(fw_ver + 1);
3704 	fw_major = fw_maj_min & 0xffff;
3705 	fw_minor = fw_maj_min >> 16;
3706 	fw_subminor = fw_sub_min & 0xffff;
3707 	if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3708 	    fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3709 		pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3710 			 fw_major, fw_minor, fw_subminor, pdev->device ==
3711 			 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3712 		pdev->broken_intx_masking = 1;
3713 	}
3714 
3715 	iounmap(fw_ver);
3716 
3717 out:
3718 	pci_disable_device(pdev);
3719 }
3720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3721 			mellanox_check_broken_intx_masking);
3722 
quirk_no_bus_reset(struct pci_dev * dev)3723 static void quirk_no_bus_reset(struct pci_dev *dev)
3724 {
3725 	dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3726 }
3727 
3728 /*
3729  * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
3730  * prevented for those affected devices.
3731  */
quirk_nvidia_no_bus_reset(struct pci_dev * dev)3732 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
3733 {
3734 	if ((dev->device & 0xffc0) == 0x2340)
3735 		quirk_no_bus_reset(dev);
3736 }
3737 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
3738 			 quirk_nvidia_no_bus_reset);
3739 
3740 /*
3741  * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3742  * The device will throw a Link Down error on AER-capable systems and
3743  * regardless of AER, config space of the device is never accessible again
3744  * and typically causes the system to hang or reset when access is attempted.
3745  * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
3746  */
3747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3749 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3750 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3751 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3752 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
3753 
3754 /*
3755  * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3756  * reset when used with certain child devices.  After the reset, config
3757  * accesses to the child may fail.
3758  */
3759 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3760 
3761 /*
3762  * Some TI KeyStone C667X devices do not support bus/hot reset.  The PCIESS
3763  * automatically disables LTSSM when Secondary Bus Reset is received and
3764  * the device stops working.  Prevent bus reset for these devices.  With
3765  * this change, the device can be assigned to VMs with VFIO, but it will
3766  * leak state between VMs.  Reference
3767  * https://e2e.ti.com/support/processors/f/791/t/954382
3768  */
3769 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3770 
quirk_no_pm_reset(struct pci_dev * dev)3771 static void quirk_no_pm_reset(struct pci_dev *dev)
3772 {
3773 	/*
3774 	 * We can't do a bus reset on root bus devices, but an ineffective
3775 	 * PM reset may be better than nothing.
3776 	 */
3777 	if (!pci_is_root_bus(dev->bus))
3778 		dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3779 }
3780 
3781 /*
3782  * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3783  * causes a reset (i.e., they advertise NoSoftRst-).  This transition seems
3784  * to have no effect on the device: it retains the framebuffer contents and
3785  * monitor sync.  Advertising this support makes other layers, like VFIO,
3786  * assume pci_reset_function() is viable for this device.  Mark it as
3787  * unavailable to skip it when testing reset methods.
3788  */
3789 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3790 			       PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3791 
3792 /*
3793  * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset
3794  * (i.e., they advertise NoSoftRst-). However, this transition does not have
3795  * any effect on the device: It continues to be operational and network ports
3796  * remain up. Advertising this support makes it seem as if a PM reset is viable
3797  * for these devices. Mark it as unavailable to skip it when testing reset
3798  * methods.
3799  */
3800 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset);
3801 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset);
3802 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset);
3803 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset);
3804 
3805 /*
3806  * Thunderbolt controllers with broken MSI hotplug signaling:
3807  * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3808  * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3809  */
quirk_thunderbolt_hotplug_msi(struct pci_dev * pdev)3810 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3811 {
3812 	if (pdev->is_hotplug_bridge &&
3813 	    (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3814 	     pdev->revision <= 1))
3815 		pdev->no_msi = 1;
3816 }
3817 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3818 			quirk_thunderbolt_hotplug_msi);
3819 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3820 			quirk_thunderbolt_hotplug_msi);
3821 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3822 			quirk_thunderbolt_hotplug_msi);
3823 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3824 			quirk_thunderbolt_hotplug_msi);
3825 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3826 			quirk_thunderbolt_hotplug_msi);
3827 
3828 #ifdef CONFIG_ACPI
3829 /*
3830  * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3831  *
3832  * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3833  * shutdown before suspend. Otherwise the native host interface (NHI) will not
3834  * be present after resume if a device was plugged in before suspend.
3835  *
3836  * The Thunderbolt controller consists of a PCIe switch with downstream
3837  * bridges leading to the NHI and to the tunnel PCI bridges.
3838  *
3839  * This quirk cuts power to the whole chip. Therefore we have to apply it
3840  * during suspend_noirq of the upstream bridge.
3841  *
3842  * Power is automagically restored before resume. No action is needed.
3843  */
quirk_apple_poweroff_thunderbolt(struct pci_dev * dev)3844 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3845 {
3846 	acpi_handle bridge, SXIO, SXFP, SXLV;
3847 
3848 	if (!x86_apple_machine)
3849 		return;
3850 	if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3851 		return;
3852 
3853 	/*
3854 	 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller.
3855 	 * We don't know how to turn it back on again, but firmware does,
3856 	 * so we can only use SXIO/SXFP/SXLF if we're suspending via
3857 	 * firmware.
3858 	 */
3859 	if (!pm_suspend_via_firmware())
3860 		return;
3861 
3862 	bridge = ACPI_HANDLE(&dev->dev);
3863 	if (!bridge)
3864 		return;
3865 
3866 	/*
3867 	 * SXIO and SXLV are present only on machines requiring this quirk.
3868 	 * Thunderbolt bridges in external devices might have the same
3869 	 * device ID as those on the host, but they will not have the
3870 	 * associated ACPI methods. This implicitly checks that we are at
3871 	 * the right bridge.
3872 	 */
3873 	if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3874 	    || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3875 	    || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3876 		return;
3877 	pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3878 
3879 	/* magic sequence */
3880 	acpi_execute_simple_method(SXIO, NULL, 1);
3881 	acpi_execute_simple_method(SXFP, NULL, 0);
3882 	msleep(300);
3883 	acpi_execute_simple_method(SXLV, NULL, 0);
3884 	acpi_execute_simple_method(SXIO, NULL, 0);
3885 	acpi_execute_simple_method(SXLV, NULL, 0);
3886 }
3887 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3888 			       PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3889 			       quirk_apple_poweroff_thunderbolt);
3890 #endif
3891 
3892 /*
3893  * Following are device-specific reset methods which can be used to
3894  * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3895  * not available.
3896  */
reset_intel_82599_sfp_virtfn(struct pci_dev * dev,bool probe)3897 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe)
3898 {
3899 	/*
3900 	 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3901 	 *
3902 	 * The 82599 supports FLR on VFs, but FLR support is reported only
3903 	 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3904 	 * Thus we must call pcie_flr() directly without first checking if it is
3905 	 * supported.
3906 	 */
3907 	if (!probe)
3908 		pcie_flr(dev);
3909 	return 0;
3910 }
3911 
3912 #define SOUTH_CHICKEN2		0xc2004
3913 #define PCH_PP_STATUS		0xc7200
3914 #define PCH_PP_CONTROL		0xc7204
3915 #define MSG_CTL			0x45010
3916 #define NSDE_PWR_STATE		0xd0100
3917 #define IGD_OPERATION_TIMEOUT	10000     /* set timeout 10 seconds */
3918 
reset_ivb_igd(struct pci_dev * dev,bool probe)3919 static int reset_ivb_igd(struct pci_dev *dev, bool probe)
3920 {
3921 	void __iomem *mmio_base;
3922 	unsigned long timeout;
3923 	u32 val;
3924 
3925 	if (probe)
3926 		return 0;
3927 
3928 	mmio_base = pci_iomap(dev, 0, 0);
3929 	if (!mmio_base)
3930 		return -ENOMEM;
3931 
3932 	iowrite32(0x00000002, mmio_base + MSG_CTL);
3933 
3934 	/*
3935 	 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3936 	 * driver loaded sets the right bits. However, this's a reset and
3937 	 * the bits have been set by i915 previously, so we clobber
3938 	 * SOUTH_CHICKEN2 register directly here.
3939 	 */
3940 	iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3941 
3942 	val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3943 	iowrite32(val, mmio_base + PCH_PP_CONTROL);
3944 
3945 	timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3946 	do {
3947 		val = ioread32(mmio_base + PCH_PP_STATUS);
3948 		if ((val & 0xb0000000) == 0)
3949 			goto reset_complete;
3950 		msleep(10);
3951 	} while (time_before(jiffies, timeout));
3952 	pci_warn(dev, "timeout during reset\n");
3953 
3954 reset_complete:
3955 	iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3956 
3957 	pci_iounmap(dev, mmio_base);
3958 	return 0;
3959 }
3960 
3961 /* Device-specific reset method for Chelsio T4-based adapters */
reset_chelsio_generic_dev(struct pci_dev * dev,bool probe)3962 static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe)
3963 {
3964 	u16 old_command;
3965 	u16 msix_flags;
3966 
3967 	/*
3968 	 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3969 	 * that we have no device-specific reset method.
3970 	 */
3971 	if ((dev->device & 0xf000) != 0x4000)
3972 		return -ENOTTY;
3973 
3974 	/*
3975 	 * If this is the "probe" phase, return 0 indicating that we can
3976 	 * reset this device.
3977 	 */
3978 	if (probe)
3979 		return 0;
3980 
3981 	/*
3982 	 * T4 can wedge if there are DMAs in flight within the chip and Bus
3983 	 * Master has been disabled.  We need to have it on till the Function
3984 	 * Level Reset completes.  (BUS_MASTER is disabled in
3985 	 * pci_reset_function()).
3986 	 */
3987 	pci_read_config_word(dev, PCI_COMMAND, &old_command);
3988 	pci_write_config_word(dev, PCI_COMMAND,
3989 			      old_command | PCI_COMMAND_MASTER);
3990 
3991 	/*
3992 	 * Perform the actual device function reset, saving and restoring
3993 	 * configuration information around the reset.
3994 	 */
3995 	pci_save_state(dev);
3996 
3997 	/*
3998 	 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3999 	 * are disabled when an MSI-X interrupt message needs to be delivered.
4000 	 * So we briefly re-enable MSI-X interrupts for the duration of the
4001 	 * FLR.  The pci_restore_state() below will restore the original
4002 	 * MSI-X state.
4003 	 */
4004 	pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
4005 	if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
4006 		pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
4007 				      msix_flags |
4008 				      PCI_MSIX_FLAGS_ENABLE |
4009 				      PCI_MSIX_FLAGS_MASKALL);
4010 
4011 	pcie_flr(dev);
4012 
4013 	/*
4014 	 * Restore the configuration information (BAR values, etc.) including
4015 	 * the original PCI Configuration Space Command word, and return
4016 	 * success.
4017 	 */
4018 	pci_restore_state(dev);
4019 	pci_write_config_word(dev, PCI_COMMAND, old_command);
4020 	return 0;
4021 }
4022 
4023 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF   0x10ed
4024 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA      0x0156
4025 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA     0x0166
4026 
4027 /*
4028  * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
4029  * FLR where config space reads from the device return -1.  We seem to be
4030  * able to avoid this condition if we disable the NVMe controller prior to
4031  * FLR.  This quirk is generic for any NVMe class device requiring similar
4032  * assistance to quiesce the device prior to FLR.
4033  *
4034  * NVMe specification: https://nvmexpress.org/resources/specifications/
4035  * Revision 1.0e:
4036  *    Chapter 2: Required and optional PCI config registers
4037  *    Chapter 3: NVMe control registers
4038  *    Chapter 7.3: Reset behavior
4039  */
nvme_disable_and_flr(struct pci_dev * dev,bool probe)4040 static int nvme_disable_and_flr(struct pci_dev *dev, bool probe)
4041 {
4042 	void __iomem *bar;
4043 	u16 cmd;
4044 	u32 cfg;
4045 
4046 	if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
4047 	    pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0))
4048 		return -ENOTTY;
4049 
4050 	if (probe)
4051 		return 0;
4052 
4053 	bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
4054 	if (!bar)
4055 		return -ENOTTY;
4056 
4057 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
4058 	pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
4059 
4060 	cfg = readl(bar + NVME_REG_CC);
4061 
4062 	/* Disable controller if enabled */
4063 	if (cfg & NVME_CC_ENABLE) {
4064 		u32 cap = readl(bar + NVME_REG_CAP);
4065 		unsigned long timeout;
4066 
4067 		/*
4068 		 * Per nvme_disable_ctrl() skip shutdown notification as it
4069 		 * could complete commands to the admin queue.  We only intend
4070 		 * to quiesce the device before reset.
4071 		 */
4072 		cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
4073 
4074 		writel(cfg, bar + NVME_REG_CC);
4075 
4076 		/*
4077 		 * Some controllers require an additional delay here, see
4078 		 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY.  None of those are yet
4079 		 * supported by this quirk.
4080 		 */
4081 
4082 		/* Cap register provides max timeout in 500ms increments */
4083 		timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
4084 
4085 		for (;;) {
4086 			u32 status = readl(bar + NVME_REG_CSTS);
4087 
4088 			/* Ready status becomes zero on disable complete */
4089 			if (!(status & NVME_CSTS_RDY))
4090 				break;
4091 
4092 			msleep(100);
4093 
4094 			if (time_after(jiffies, timeout)) {
4095 				pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
4096 				break;
4097 			}
4098 		}
4099 	}
4100 
4101 	pci_iounmap(dev, bar);
4102 
4103 	pcie_flr(dev);
4104 
4105 	return 0;
4106 }
4107 
4108 /*
4109  * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will
4110  * timeout waiting for ready status to change after NVMe enable if the driver
4111  * starts interacting with the device too soon after FLR.  A 250ms delay after
4112  * FLR has heuristically proven to produce reliably working results for device
4113  * assignment cases.
4114  */
delay_250ms_after_flr(struct pci_dev * dev,bool probe)4115 static int delay_250ms_after_flr(struct pci_dev *dev, bool probe)
4116 {
4117 	if (probe)
4118 		return pcie_reset_flr(dev, PCI_RESET_PROBE);
4119 
4120 	pcie_reset_flr(dev, PCI_RESET_DO_RESET);
4121 
4122 	msleep(250);
4123 
4124 	return 0;
4125 }
4126 
4127 #define PCI_DEVICE_ID_HINIC_VF      0x375E
4128 #define HINIC_VF_FLR_TYPE           0x1000
4129 #define HINIC_VF_FLR_CAP_BIT        (1UL << 30)
4130 #define HINIC_VF_OP                 0xE80
4131 #define HINIC_VF_FLR_PROC_BIT       (1UL << 18)
4132 #define HINIC_OPERATION_TIMEOUT     15000	/* 15 seconds */
4133 
4134 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
reset_hinic_vf_dev(struct pci_dev * pdev,bool probe)4135 static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe)
4136 {
4137 	unsigned long timeout;
4138 	void __iomem *bar;
4139 	u32 val;
4140 
4141 	if (probe)
4142 		return 0;
4143 
4144 	bar = pci_iomap(pdev, 0, 0);
4145 	if (!bar)
4146 		return -ENOTTY;
4147 
4148 	/* Get and check firmware capabilities */
4149 	val = ioread32be(bar + HINIC_VF_FLR_TYPE);
4150 	if (!(val & HINIC_VF_FLR_CAP_BIT)) {
4151 		pci_iounmap(pdev, bar);
4152 		return -ENOTTY;
4153 	}
4154 
4155 	/* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
4156 	val = ioread32be(bar + HINIC_VF_OP);
4157 	val = val | HINIC_VF_FLR_PROC_BIT;
4158 	iowrite32be(val, bar + HINIC_VF_OP);
4159 
4160 	pcie_flr(pdev);
4161 
4162 	/*
4163 	 * The device must recapture its Bus and Device Numbers after FLR
4164 	 * in order generate Completions.  Issue a config write to let the
4165 	 * device capture this information.
4166 	 */
4167 	pci_write_config_word(pdev, PCI_VENDOR_ID, 0);
4168 
4169 	/* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
4170 	timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT);
4171 	do {
4172 		val = ioread32be(bar + HINIC_VF_OP);
4173 		if (!(val & HINIC_VF_FLR_PROC_BIT))
4174 			goto reset_complete;
4175 		msleep(20);
4176 	} while (time_before(jiffies, timeout));
4177 
4178 	val = ioread32be(bar + HINIC_VF_OP);
4179 	if (!(val & HINIC_VF_FLR_PROC_BIT))
4180 		goto reset_complete;
4181 
4182 	pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
4183 
4184 reset_complete:
4185 	pci_iounmap(pdev, bar);
4186 
4187 	return 0;
4188 }
4189 
4190 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
4191 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
4192 		 reset_intel_82599_sfp_virtfn },
4193 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
4194 		reset_ivb_igd },
4195 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
4196 		reset_ivb_igd },
4197 	{ PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
4198 	{ PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
4199 	{ PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr },
4200 	{ PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr },
4201 	{ PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4202 		reset_chelsio_generic_dev },
4203 	{ PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
4204 		reset_hinic_vf_dev },
4205 	{ 0 }
4206 };
4207 
4208 /*
4209  * These device-specific reset methods are here rather than in a driver
4210  * because when a host assigns a device to a guest VM, the host may need
4211  * to reset the device but probably doesn't have a driver for it.
4212  */
pci_dev_specific_reset(struct pci_dev * dev,bool probe)4213 int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
4214 {
4215 	const struct pci_dev_reset_methods *i;
4216 
4217 	for (i = pci_dev_reset_methods; i->reset; i++) {
4218 		if ((i->vendor == dev->vendor ||
4219 		     i->vendor == (u16)PCI_ANY_ID) &&
4220 		    (i->device == dev->device ||
4221 		     i->device == (u16)PCI_ANY_ID))
4222 			return i->reset(dev, probe);
4223 	}
4224 
4225 	return -ENOTTY;
4226 }
4227 
quirk_dma_func0_alias(struct pci_dev * dev)4228 static void quirk_dma_func0_alias(struct pci_dev *dev)
4229 {
4230 	if (PCI_FUNC(dev->devfn) != 0)
4231 		pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
4232 }
4233 
4234 /*
4235  * https://bugzilla.redhat.com/show_bug.cgi?id=605888
4236  *
4237  * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4238  */
4239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4241 
quirk_dma_func1_alias(struct pci_dev * dev)4242 static void quirk_dma_func1_alias(struct pci_dev *dev)
4243 {
4244 	if (PCI_FUNC(dev->devfn) != 1)
4245 		pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
4246 }
4247 
4248 /*
4249  * Marvell 88SE9123 uses function 1 as the requester ID for DMA.  In some
4250  * SKUs function 1 is present and is a legacy IDE controller, in other
4251  * SKUs this function is not present, making this a ghost requester.
4252  * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4253  */
4254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4255 			 quirk_dma_func1_alias);
4256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4257 			 quirk_dma_func1_alias);
4258 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */
4259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125,
4260 			 quirk_dma_func1_alias);
4261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4262 			 quirk_dma_func1_alias);
4263 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4264 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4265 			 quirk_dma_func1_alias);
4266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4267 			 quirk_dma_func1_alias);
4268 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4270 			 quirk_dma_func1_alias);
4271 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4273 			 quirk_dma_func1_alias);
4274 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4276 			 quirk_dma_func1_alias);
4277 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4279 			 quirk_dma_func1_alias);
4280 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4282 			 quirk_dma_func1_alias);
4283 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
4284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4285 			 quirk_dma_func1_alias);
4286 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4288 			 quirk_dma_func1_alias);
4289 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4291 			 quirk_dma_func1_alias);
4292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235,
4293 			 quirk_dma_func1_alias);
4294 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4295 			 quirk_dma_func1_alias);
4296 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4297 			 quirk_dma_func1_alias);
4298 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
4300 			 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
4301 			 quirk_dma_func1_alias);
4302 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4303 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4304 			 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4305 			 quirk_dma_func1_alias);
4306 
4307 /*
4308  * Some devices DMA with the wrong devfn, not just the wrong function.
4309  * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4310  * the alias is "fixed" and independent of the device devfn.
4311  *
4312  * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4313  * processor.  To software, this appears as a PCIe-to-PCI/X bridge with a
4314  * single device on the secondary bus.  In reality, the single exposed
4315  * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4316  * that provides a bridge to the internal bus of the I/O processor.  The
4317  * controller supports private devices, which can be hidden from PCI config
4318  * space.  In the case of the Adaptec 3405, a private device at 01.0
4319  * appears to be the DMA engine, which therefore needs to become a DMA
4320  * alias for the device.
4321  */
4322 static const struct pci_device_id fixed_dma_alias_tbl[] = {
4323 	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4324 			 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4325 	  .driver_data = PCI_DEVFN(1, 0) },
4326 	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4327 			 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4328 	  .driver_data = PCI_DEVFN(1, 0) },
4329 	{ 0 }
4330 };
4331 
quirk_fixed_dma_alias(struct pci_dev * dev)4332 static void quirk_fixed_dma_alias(struct pci_dev *dev)
4333 {
4334 	const struct pci_device_id *id;
4335 
4336 	id = pci_match_id(fixed_dma_alias_tbl, dev);
4337 	if (id)
4338 		pci_add_dma_alias(dev, id->driver_data, 1);
4339 }
4340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4341 
4342 /*
4343  * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4344  * using the wrong DMA alias for the device.  Some of these devices can be
4345  * used as either forward or reverse bridges, so we need to test whether the
4346  * device is operating in the correct mode.  We could probably apply this
4347  * quirk to PCI_ANY_ID, but for now we'll just use known offenders.  The test
4348  * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4349  * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4350  */
quirk_use_pcie_bridge_dma_alias(struct pci_dev * pdev)4351 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4352 {
4353 	if (!pci_is_root_bus(pdev->bus) &&
4354 	    pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4355 	    !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4356 	    pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4357 		pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4358 }
4359 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4360 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4361 			 quirk_use_pcie_bridge_dma_alias);
4362 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4363 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4364 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4365 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4366 /* ITE 8893 has the same problem as the 8892 */
4367 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4368 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4369 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4370 
4371 /*
4372  * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4373  * be added as aliases to the DMA device in order to allow buffer access
4374  * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4375  * programmed in the EEPROM.
4376  */
quirk_mic_x200_dma_alias(struct pci_dev * pdev)4377 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4378 {
4379 	pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
4380 	pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
4381 	pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
4382 }
4383 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4384 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4385 
4386 /*
4387  * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4388  * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4389  *
4390  * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4391  * when IOMMU is enabled.  These aliases allow computational unit access to
4392  * host memory.  These aliases mark the whole VCA device as one IOMMU
4393  * group.
4394  *
4395  * All possible slot numbers (0x20) are used, since we are unable to tell
4396  * what slot is used on other side.  This quirk is intended for both host
4397  * and computational unit sides.  The VCA devices have up to five functions
4398  * (four for DMA channels and one additional).
4399  */
quirk_pex_vca_alias(struct pci_dev * pdev)4400 static void quirk_pex_vca_alias(struct pci_dev *pdev)
4401 {
4402 	const unsigned int num_pci_slots = 0x20;
4403 	unsigned int slot;
4404 
4405 	for (slot = 0; slot < num_pci_slots; slot++)
4406 		pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
4407 }
4408 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4409 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4410 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4411 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4412 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4413 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4414 
4415 /*
4416  * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4417  * associated not at the root bus, but at a bridge below. This quirk avoids
4418  * generating invalid DMA aliases.
4419  */
quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev * pdev)4420 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4421 {
4422 	pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4423 }
4424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4425 				quirk_bridge_cavm_thrx2_pcie_root);
4426 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4427 				quirk_bridge_cavm_thrx2_pcie_root);
4428 
4429 /*
4430  * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4431  * class code.  Fix it.
4432  */
quirk_tw686x_class(struct pci_dev * pdev)4433 static void quirk_tw686x_class(struct pci_dev *pdev)
4434 {
4435 	u32 class = pdev->class;
4436 
4437 	/* Use "Multimedia controller" class */
4438 	pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4439 	pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4440 		 class, pdev->class);
4441 }
4442 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4443 			      quirk_tw686x_class);
4444 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4445 			      quirk_tw686x_class);
4446 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4447 			      quirk_tw686x_class);
4448 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4449 			      quirk_tw686x_class);
4450 
4451 /*
4452  * Some devices have problems with Transaction Layer Packets with the Relaxed
4453  * Ordering Attribute set.  Such devices should mark themselves and other
4454  * device drivers should check before sending TLPs with RO set.
4455  */
quirk_relaxedordering_disable(struct pci_dev * dev)4456 static void quirk_relaxedordering_disable(struct pci_dev *dev)
4457 {
4458 	dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4459 	pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4460 }
4461 
4462 /*
4463  * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4464  * Complex have a Flow Control Credit issue which can cause performance
4465  * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4466  */
4467 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4468 			      quirk_relaxedordering_disable);
4469 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4470 			      quirk_relaxedordering_disable);
4471 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4472 			      quirk_relaxedordering_disable);
4473 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4474 			      quirk_relaxedordering_disable);
4475 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4476 			      quirk_relaxedordering_disable);
4477 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4478 			      quirk_relaxedordering_disable);
4479 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4480 			      quirk_relaxedordering_disable);
4481 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4482 			      quirk_relaxedordering_disable);
4483 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4484 			      quirk_relaxedordering_disable);
4485 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4486 			      quirk_relaxedordering_disable);
4487 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4488 			      quirk_relaxedordering_disable);
4489 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4490 			      quirk_relaxedordering_disable);
4491 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4492 			      quirk_relaxedordering_disable);
4493 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4494 			      quirk_relaxedordering_disable);
4495 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4496 			      quirk_relaxedordering_disable);
4497 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4498 			      quirk_relaxedordering_disable);
4499 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4500 			      quirk_relaxedordering_disable);
4501 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4502 			      quirk_relaxedordering_disable);
4503 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4504 			      quirk_relaxedordering_disable);
4505 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4506 			      quirk_relaxedordering_disable);
4507 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4508 			      quirk_relaxedordering_disable);
4509 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4510 			      quirk_relaxedordering_disable);
4511 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4512 			      quirk_relaxedordering_disable);
4513 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4514 			      quirk_relaxedordering_disable);
4515 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4516 			      quirk_relaxedordering_disable);
4517 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4518 			      quirk_relaxedordering_disable);
4519 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4520 			      quirk_relaxedordering_disable);
4521 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4522 			      quirk_relaxedordering_disable);
4523 
4524 /*
4525  * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4526  * where Upstream Transaction Layer Packets with the Relaxed Ordering
4527  * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4528  * set.  This is a violation of the PCIe 3.0 Transaction Ordering Rules
4529  * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4530  * November 10, 2010).  As a result, on this platform we can't use Relaxed
4531  * Ordering for Upstream TLPs.
4532  */
4533 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4534 			      quirk_relaxedordering_disable);
4535 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4536 			      quirk_relaxedordering_disable);
4537 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4538 			      quirk_relaxedordering_disable);
4539 
4540 /*
4541  * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4542  * values for the Attribute as were supplied in the header of the
4543  * corresponding Request, except as explicitly allowed when IDO is used."
4544  *
4545  * If a non-compliant device generates a completion with a different
4546  * attribute than the request, the receiver may accept it (which itself
4547  * seems non-compliant based on sec 2.3.2), or it may handle it as a
4548  * Malformed TLP or an Unexpected Completion, which will probably lead to a
4549  * device access timeout.
4550  *
4551  * If the non-compliant device generates completions with zero attributes
4552  * (instead of copying the attributes from the request), we can work around
4553  * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4554  * upstream devices so they always generate requests with zero attributes.
4555  *
4556  * This affects other devices under the same Root Port, but since these
4557  * attributes are performance hints, there should be no functional problem.
4558  *
4559  * Note that Configuration Space accesses are never supposed to have TLP
4560  * Attributes, so we're safe waiting till after any Configuration Space
4561  * accesses to do the Root Port fixup.
4562  */
quirk_disable_root_port_attributes(struct pci_dev * pdev)4563 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4564 {
4565 	struct pci_dev *root_port = pcie_find_root_port(pdev);
4566 
4567 	if (!root_port) {
4568 		pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4569 		return;
4570 	}
4571 
4572 	pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4573 		 dev_name(&pdev->dev));
4574 	pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4575 					   PCI_EXP_DEVCTL_RELAX_EN |
4576 					   PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4577 }
4578 
4579 /*
4580  * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4581  * Completion it generates.
4582  */
quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev * pdev)4583 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4584 {
4585 	/*
4586 	 * This mask/compare operation selects for Physical Function 4 on a
4587 	 * T5.  We only need to fix up the Root Port once for any of the
4588 	 * PFs.  PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4589 	 * 0x54xx so we use that one.
4590 	 */
4591 	if ((pdev->device & 0xff00) == 0x5400)
4592 		quirk_disable_root_port_attributes(pdev);
4593 }
4594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4595 			 quirk_chelsio_T5_disable_root_port_attributes);
4596 
4597 /*
4598  * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4599  *			  by a device
4600  * @acs_ctrl_req: Bitmask of desired ACS controls
4601  * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4602  *		  the hardware design
4603  *
4604  * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4605  * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4606  * caller desires.  Return 0 otherwise.
4607  */
pci_acs_ctrl_enabled(u16 acs_ctrl_req,u16 acs_ctrl_ena)4608 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4609 {
4610 	if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4611 		return 1;
4612 	return 0;
4613 }
4614 
4615 /*
4616  * AMD has indicated that the devices below do not support peer-to-peer
4617  * in any system where they are found in the southbridge with an AMD
4618  * IOMMU in the system.  Multifunction devices that do not support
4619  * peer-to-peer between functions can claim to support a subset of ACS.
4620  * Such devices effectively enable request redirect (RR) and completion
4621  * redirect (CR) since all transactions are redirected to the upstream
4622  * root complex.
4623  *
4624  * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
4625  * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
4626  * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
4627  *
4628  * 1002:4385 SBx00 SMBus Controller
4629  * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4630  * 1002:4383 SBx00 Azalia (Intel HDA)
4631  * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4632  * 1002:4384 SBx00 PCI to PCI Bridge
4633  * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4634  *
4635  * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4636  *
4637  * 1022:780f [AMD] FCH PCI Bridge
4638  * 1022:7809 [AMD] FCH USB OHCI Controller
4639  */
pci_quirk_amd_sb_acs(struct pci_dev * dev,u16 acs_flags)4640 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4641 {
4642 #ifdef CONFIG_ACPI
4643 	struct acpi_table_header *header = NULL;
4644 	acpi_status status;
4645 
4646 	/* Targeting multifunction devices on the SB (appears on root bus) */
4647 	if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4648 		return -ENODEV;
4649 
4650 	/* The IVRS table describes the AMD IOMMU */
4651 	status = acpi_get_table("IVRS", 0, &header);
4652 	if (ACPI_FAILURE(status))
4653 		return -ENODEV;
4654 
4655 	acpi_put_table(header);
4656 
4657 	/* Filter out flags not applicable to multifunction */
4658 	acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4659 
4660 	return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4661 #else
4662 	return -ENODEV;
4663 #endif
4664 }
4665 
pci_quirk_cavium_acs_match(struct pci_dev * dev)4666 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4667 {
4668 	if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4669 		return false;
4670 
4671 	switch (dev->device) {
4672 	/*
4673 	 * Effectively selects all downstream ports for whole ThunderX1
4674 	 * (which represents 8 SoCs).
4675 	 */
4676 	case 0xa000 ... 0xa7ff: /* ThunderX1 */
4677 	case 0xaf84:  /* ThunderX2 */
4678 	case 0xb884:  /* ThunderX3 */
4679 		return true;
4680 	default:
4681 		return false;
4682 	}
4683 }
4684 
pci_quirk_cavium_acs(struct pci_dev * dev,u16 acs_flags)4685 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4686 {
4687 	if (!pci_quirk_cavium_acs_match(dev))
4688 		return -ENOTTY;
4689 
4690 	/*
4691 	 * Cavium Root Ports don't advertise an ACS capability.  However,
4692 	 * the RTL internally implements similar protection as if ACS had
4693 	 * Source Validation, Request Redirection, Completion Redirection,
4694 	 * and Upstream Forwarding features enabled.  Assert that the
4695 	 * hardware implements and enables equivalent ACS functionality for
4696 	 * these flags.
4697 	 */
4698 	return pci_acs_ctrl_enabled(acs_flags,
4699 		PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4700 }
4701 
pci_quirk_xgene_acs(struct pci_dev * dev,u16 acs_flags)4702 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4703 {
4704 	/*
4705 	 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4706 	 * transactions with others, allowing masking out these bits as if they
4707 	 * were unimplemented in the ACS capability.
4708 	 */
4709 	return pci_acs_ctrl_enabled(acs_flags,
4710 		PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4711 }
4712 
4713 /*
4714  * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4715  * But the implementation could block peer-to-peer transactions between them
4716  * and provide ACS-like functionality.
4717  */
pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev * dev,u16 acs_flags)4718 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4719 {
4720 	if (!pci_is_pcie(dev) ||
4721 	    ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
4722 	     (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
4723 		return -ENOTTY;
4724 
4725 	/*
4726 	 * Future Zhaoxin Root Ports and Switch Downstream Ports will
4727 	 * implement ACS capability in accordance with the PCIe Spec.
4728 	 */
4729 	switch (dev->device) {
4730 	case 0x0710 ... 0x071e:
4731 	case 0x0721:
4732 	case 0x0723 ... 0x0752:
4733 		return pci_acs_ctrl_enabled(acs_flags,
4734 			PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4735 	}
4736 
4737 	return false;
4738 }
4739 
4740 /*
4741  * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4742  * transactions and validate bus numbers in requests, but do not provide an
4743  * actual PCIe ACS capability.  This is the list of device IDs known to fall
4744  * into that category as provided by Intel in Red Hat bugzilla 1037684.
4745  */
4746 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4747 	/* Ibexpeak PCH */
4748 	0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4749 	0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4750 	/* Cougarpoint PCH */
4751 	0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4752 	0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4753 	/* Pantherpoint PCH */
4754 	0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4755 	0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4756 	/* Lynxpoint-H PCH */
4757 	0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4758 	0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4759 	/* Lynxpoint-LP PCH */
4760 	0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4761 	0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4762 	/* Wildcat PCH */
4763 	0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4764 	0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4765 	/* Patsburg (X79) PCH */
4766 	0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4767 	/* Wellsburg (X99) PCH */
4768 	0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4769 	0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4770 	/* Lynx Point (9 series) PCH */
4771 	0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4772 };
4773 
pci_quirk_intel_pch_acs_match(struct pci_dev * dev)4774 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4775 {
4776 	int i;
4777 
4778 	/* Filter out a few obvious non-matches first */
4779 	if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4780 		return false;
4781 
4782 	for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4783 		if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4784 			return true;
4785 
4786 	return false;
4787 }
4788 
pci_quirk_intel_pch_acs(struct pci_dev * dev,u16 acs_flags)4789 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4790 {
4791 	if (!pci_quirk_intel_pch_acs_match(dev))
4792 		return -ENOTTY;
4793 
4794 	if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4795 		return pci_acs_ctrl_enabled(acs_flags,
4796 			PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4797 
4798 	return pci_acs_ctrl_enabled(acs_flags, 0);
4799 }
4800 
4801 /*
4802  * These QCOM Root Ports do provide ACS-like features to disable peer
4803  * transactions and validate bus numbers in requests, but do not provide an
4804  * actual PCIe ACS capability.  Hardware supports source validation but it
4805  * will report the issue as Completer Abort instead of ACS Violation.
4806  * Hardware doesn't support peer-to-peer and each Root Port is a Root
4807  * Complex with unique segment numbers.  It is not possible for one Root
4808  * Port to pass traffic to another Root Port.  All PCIe transactions are
4809  * terminated inside the Root Port.
4810  */
pci_quirk_qcom_rp_acs(struct pci_dev * dev,u16 acs_flags)4811 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4812 {
4813 	return pci_acs_ctrl_enabled(acs_flags,
4814 		PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4815 }
4816 
4817 /*
4818  * Each of these NXP Root Ports is in a Root Complex with a unique segment
4819  * number and does provide isolation features to disable peer transactions
4820  * and validate bus numbers in requests, but does not provide an ACS
4821  * capability.
4822  */
pci_quirk_nxp_rp_acs(struct pci_dev * dev,u16 acs_flags)4823 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags)
4824 {
4825 	return pci_acs_ctrl_enabled(acs_flags,
4826 		PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4827 }
4828 
pci_quirk_al_acs(struct pci_dev * dev,u16 acs_flags)4829 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4830 {
4831 	if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4832 		return -ENOTTY;
4833 
4834 	/*
4835 	 * Amazon's Annapurna Labs root ports don't include an ACS capability,
4836 	 * but do include ACS-like functionality. The hardware doesn't support
4837 	 * peer-to-peer transactions via the root port and each has a unique
4838 	 * segment number.
4839 	 *
4840 	 * Additionally, the root ports cannot send traffic to each other.
4841 	 */
4842 	acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4843 
4844 	return acs_flags ? 0 : 1;
4845 }
4846 
4847 /*
4848  * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4849  * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4850  * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4851  * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4852  * 7.16 ACS Extended Capability).  The bit definitions are correct, but the
4853  * control register is at offset 8 instead of 6 and we should probably use
4854  * dword accesses to them.  This applies to the following PCI Device IDs, as
4855  * found in volume 1 of the datasheet[2]:
4856  *
4857  * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4858  * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4859  *
4860  * N.B. This doesn't fix what lspci shows.
4861  *
4862  * The 100 series chipset specification update includes this as errata #23[3].
4863  *
4864  * The 200 series chipset (Union Point) has the same bug according to the
4865  * specification update (Intel 200 Series Chipset Family Platform Controller
4866  * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4867  * Errata 22)[4].  Per the datasheet[5], root port PCI Device IDs for this
4868  * chipset include:
4869  *
4870  * 0xa290-0xa29f PCI Express Root port #{0-16}
4871  * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4872  *
4873  * Mobile chipsets are also affected, 7th & 8th Generation
4874  * Specification update confirms ACS errata 22, status no fix: (7th Generation
4875  * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4876  * Processor Family I/O for U Quad Core Platforms Specification Update,
4877  * August 2017, Revision 002, Document#: 334660-002)[6]
4878  * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4879  * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4880  * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4881  *
4882  * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4883  *
4884  * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4885  * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4886  * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4887  * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4888  * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4889  * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4890  * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4891  */
pci_quirk_intel_spt_pch_acs_match(struct pci_dev * dev)4892 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4893 {
4894 	if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4895 		return false;
4896 
4897 	switch (dev->device) {
4898 	case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4899 	case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4900 	case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4901 		return true;
4902 	}
4903 
4904 	return false;
4905 }
4906 
4907 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4908 
pci_quirk_intel_spt_pch_acs(struct pci_dev * dev,u16 acs_flags)4909 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4910 {
4911 	int pos;
4912 	u32 cap, ctrl;
4913 
4914 	if (!pci_quirk_intel_spt_pch_acs_match(dev))
4915 		return -ENOTTY;
4916 
4917 	pos = dev->acs_cap;
4918 	if (!pos)
4919 		return -ENOTTY;
4920 
4921 	/* see pci_acs_flags_enabled() */
4922 	pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4923 	acs_flags &= (cap | PCI_ACS_EC);
4924 
4925 	pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4926 
4927 	return pci_acs_ctrl_enabled(acs_flags, ctrl);
4928 }
4929 
pci_quirk_mf_endpoint_acs(struct pci_dev * dev,u16 acs_flags)4930 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4931 {
4932 	/*
4933 	 * SV, TB, and UF are not relevant to multifunction endpoints.
4934 	 *
4935 	 * Multifunction devices are only required to implement RR, CR, and DT
4936 	 * in their ACS capability if they support peer-to-peer transactions.
4937 	 * Devices matching this quirk have been verified by the vendor to not
4938 	 * perform peer-to-peer with other functions, allowing us to mask out
4939 	 * these bits as if they were unimplemented in the ACS capability.
4940 	 */
4941 	return pci_acs_ctrl_enabled(acs_flags,
4942 		PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4943 		PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4944 }
4945 
pci_quirk_rciep_acs(struct pci_dev * dev,u16 acs_flags)4946 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
4947 {
4948 	/*
4949 	 * Intel RCiEP's are required to allow p2p only on translated
4950 	 * addresses.  Refer to Intel VT-d specification, r3.1, sec 3.16,
4951 	 * "Root-Complex Peer to Peer Considerations".
4952 	 */
4953 	if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
4954 		return -ENOTTY;
4955 
4956 	return pci_acs_ctrl_enabled(acs_flags,
4957 		PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4958 }
4959 
pci_quirk_brcm_acs(struct pci_dev * dev,u16 acs_flags)4960 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4961 {
4962 	/*
4963 	 * iProc PAXB Root Ports don't advertise an ACS capability, but
4964 	 * they do not allow peer-to-peer transactions between Root Ports.
4965 	 * Allow each Root Port to be in a separate IOMMU group by masking
4966 	 * SV/RR/CR/UF bits.
4967 	 */
4968 	return pci_acs_ctrl_enabled(acs_flags,
4969 		PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4970 }
4971 
4972 /*
4973  * Wangxun 10G/1G NICs have no ACS capability, and on multi-function
4974  * devices, peer-to-peer transactions are not be used between the functions.
4975  * So add an ACS quirk for below devices to isolate functions.
4976  * SFxxx 1G NICs(em).
4977  * RP1000/RP2000 10G NICs(sp).
4978  */
pci_quirk_wangxun_nic_acs(struct pci_dev * dev,u16 acs_flags)4979 static int  pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags)
4980 {
4981 	switch (dev->device) {
4982 	case 0x0100 ... 0x010F:
4983 	case 0x1001:
4984 	case 0x2001:
4985 		return pci_acs_ctrl_enabled(acs_flags,
4986 			PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4987 	}
4988 
4989 	return false;
4990 }
4991 
4992 static const struct pci_dev_acs_enabled {
4993 	u16 vendor;
4994 	u16 device;
4995 	int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4996 } pci_dev_acs_enabled[] = {
4997 	{ PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4998 	{ PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4999 	{ PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
5000 	{ PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
5001 	{ PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
5002 	{ PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
5003 	{ PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
5004 	{ PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
5005 	{ PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
5006 	{ PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
5007 	{ PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
5008 	{ PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
5009 	{ PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
5010 	{ PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
5011 	{ PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
5012 	{ PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
5013 	{ PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
5014 	{ PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
5015 	{ PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
5016 	{ PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
5017 	{ PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
5018 	{ PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
5019 	{ PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
5020 	{ PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
5021 	{ PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
5022 	{ PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
5023 	{ PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
5024 	{ PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
5025 	{ PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
5026 	{ PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
5027 	{ PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
5028 	/* 82580 */
5029 	{ PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
5030 	{ PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
5031 	{ PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
5032 	{ PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
5033 	{ PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
5034 	{ PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
5035 	{ PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
5036 	/* 82576 */
5037 	{ PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
5038 	{ PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
5039 	{ PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
5040 	{ PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
5041 	{ PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
5042 	{ PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
5043 	{ PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
5044 	{ PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
5045 	/* 82575 */
5046 	{ PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
5047 	{ PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
5048 	{ PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
5049 	/* I350 */
5050 	{ PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
5051 	{ PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
5052 	{ PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
5053 	{ PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
5054 	/* 82571 (Quads omitted due to non-ACS switch) */
5055 	{ PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
5056 	{ PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
5057 	{ PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
5058 	{ PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
5059 	/* I219 */
5060 	{ PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
5061 	{ PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
5062 	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
5063 	/* QCOM QDF2xxx root ports */
5064 	{ PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
5065 	{ PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
5066 	/* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
5067 	{ PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
5068 	/* Intel PCH root ports */
5069 	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
5070 	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
5071 	{ 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
5072 	{ 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
5073 	/* Cavium ThunderX */
5074 	{ PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
5075 	/* Cavium multi-function devices */
5076 	{ PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs },
5077 	{ PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs },
5078 	{ PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs },
5079 	/* APM X-Gene */
5080 	{ PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
5081 	/* Ampere Computing */
5082 	{ PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
5083 	{ PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
5084 	{ PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
5085 	{ PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
5086 	{ PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
5087 	{ PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
5088 	{ PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
5089 	{ PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
5090 	/* Broadcom multi-function device */
5091 	{ PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
5092 	{ PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs },
5093 	{ PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs },
5094 	{ PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs },
5095 	{ PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
5096 	/* Amazon Annapurna Labs */
5097 	{ PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
5098 	/* Zhaoxin multi-function devices */
5099 	{ PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
5100 	{ PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
5101 	{ PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
5102 	/* NXP root ports, xx=16, 12, or 08 cores */
5103 	/* LX2xx0A : without security features + CAN-FD */
5104 	{ PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs },
5105 	{ PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs },
5106 	{ PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs },
5107 	/* LX2xx0C : security features + CAN-FD */
5108 	{ PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs },
5109 	{ PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs },
5110 	{ PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs },
5111 	/* LX2xx0E : security features + CAN */
5112 	{ PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs },
5113 	{ PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs },
5114 	{ PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs },
5115 	/* LX2xx0N : without security features + CAN */
5116 	{ PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs },
5117 	{ PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs },
5118 	{ PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs },
5119 	/* LX2xx2A : without security features + CAN-FD */
5120 	{ PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs },
5121 	{ PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs },
5122 	{ PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs },
5123 	/* LX2xx2C : security features + CAN-FD */
5124 	{ PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs },
5125 	{ PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs },
5126 	{ PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs },
5127 	/* LX2xx2E : security features + CAN */
5128 	{ PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs },
5129 	{ PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs },
5130 	{ PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs },
5131 	/* LX2xx2N : without security features + CAN */
5132 	{ PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs },
5133 	{ PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs },
5134 	{ PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs },
5135 	/* Zhaoxin Root/Downstream Ports */
5136 	{ PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
5137 	/* Wangxun nics */
5138 	{ PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs },
5139 	{ 0 }
5140 };
5141 
5142 /*
5143  * pci_dev_specific_acs_enabled - check whether device provides ACS controls
5144  * @dev:	PCI device
5145  * @acs_flags:	Bitmask of desired ACS controls
5146  *
5147  * Returns:
5148  *   -ENOTTY:	No quirk applies to this device; we can't tell whether the
5149  *		device provides the desired controls
5150  *   0:		Device does not provide all the desired controls
5151  *   >0:	Device provides all the controls in @acs_flags
5152  */
pci_dev_specific_acs_enabled(struct pci_dev * dev,u16 acs_flags)5153 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
5154 {
5155 	const struct pci_dev_acs_enabled *i;
5156 	int ret;
5157 
5158 	/*
5159 	 * Allow devices that do not expose standard PCIe ACS capabilities
5160 	 * or control to indicate their support here.  Multi-function express
5161 	 * devices which do not allow internal peer-to-peer between functions,
5162 	 * but do not implement PCIe ACS may wish to return true here.
5163 	 */
5164 	for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
5165 		if ((i->vendor == dev->vendor ||
5166 		     i->vendor == (u16)PCI_ANY_ID) &&
5167 		    (i->device == dev->device ||
5168 		     i->device == (u16)PCI_ANY_ID)) {
5169 			ret = i->acs_enabled(dev, acs_flags);
5170 			if (ret >= 0)
5171 				return ret;
5172 		}
5173 	}
5174 
5175 	return -ENOTTY;
5176 }
5177 
5178 /* Config space offset of Root Complex Base Address register */
5179 #define INTEL_LPC_RCBA_REG 0xf0
5180 /* 31:14 RCBA address */
5181 #define INTEL_LPC_RCBA_MASK 0xffffc000
5182 /* RCBA Enable */
5183 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
5184 
5185 /* Backbone Scratch Pad Register */
5186 #define INTEL_BSPR_REG 0x1104
5187 /* Backbone Peer Non-Posted Disable */
5188 #define INTEL_BSPR_REG_BPNPD (1 << 8)
5189 /* Backbone Peer Posted Disable */
5190 #define INTEL_BSPR_REG_BPPD  (1 << 9)
5191 
5192 /* Upstream Peer Decode Configuration Register */
5193 #define INTEL_UPDCR_REG 0x1014
5194 /* 5:0 Peer Decode Enable bits */
5195 #define INTEL_UPDCR_REG_MASK 0x3f
5196 
pci_quirk_enable_intel_lpc_acs(struct pci_dev * dev)5197 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
5198 {
5199 	u32 rcba, bspr, updcr;
5200 	void __iomem *rcba_mem;
5201 
5202 	/*
5203 	 * Read the RCBA register from the LPC (D31:F0).  PCH root ports
5204 	 * are D28:F* and therefore get probed before LPC, thus we can't
5205 	 * use pci_get_slot()/pci_read_config_dword() here.
5206 	 */
5207 	pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
5208 				  INTEL_LPC_RCBA_REG, &rcba);
5209 	if (!(rcba & INTEL_LPC_RCBA_ENABLE))
5210 		return -EINVAL;
5211 
5212 	rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK,
5213 				   PAGE_ALIGN(INTEL_UPDCR_REG));
5214 	if (!rcba_mem)
5215 		return -ENOMEM;
5216 
5217 	/*
5218 	 * The BSPR can disallow peer cycles, but it's set by soft strap and
5219 	 * therefore read-only.  If both posted and non-posted peer cycles are
5220 	 * disallowed, we're ok.  If either are allowed, then we need to use
5221 	 * the UPDCR to disable peer decodes for each port.  This provides the
5222 	 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5223 	 */
5224 	bspr = readl(rcba_mem + INTEL_BSPR_REG);
5225 	bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
5226 	if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
5227 		updcr = readl(rcba_mem + INTEL_UPDCR_REG);
5228 		if (updcr & INTEL_UPDCR_REG_MASK) {
5229 			pci_info(dev, "Disabling UPDCR peer decodes\n");
5230 			updcr &= ~INTEL_UPDCR_REG_MASK;
5231 			writel(updcr, rcba_mem + INTEL_UPDCR_REG);
5232 		}
5233 	}
5234 
5235 	iounmap(rcba_mem);
5236 	return 0;
5237 }
5238 
5239 /* Miscellaneous Port Configuration register */
5240 #define INTEL_MPC_REG 0xd8
5241 /* MPC: Invalid Receive Bus Number Check Enable */
5242 #define INTEL_MPC_REG_IRBNCE (1 << 26)
5243 
pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev * dev)5244 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
5245 {
5246 	u32 mpc;
5247 
5248 	/*
5249 	 * When enabled, the IRBNCE bit of the MPC register enables the
5250 	 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
5251 	 * ensures that requester IDs fall within the bus number range
5252 	 * of the bridge.  Enable if not already.
5253 	 */
5254 	pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
5255 	if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
5256 		pci_info(dev, "Enabling MPC IRBNCE\n");
5257 		mpc |= INTEL_MPC_REG_IRBNCE;
5258 		pci_write_config_word(dev, INTEL_MPC_REG, mpc);
5259 	}
5260 }
5261 
5262 /*
5263  * Currently this quirk does the equivalent of
5264  * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
5265  *
5266  * TODO: This quirk also needs to do equivalent of PCI_ACS_TB,
5267  * if dev->external_facing || dev->untrusted
5268  */
pci_quirk_enable_intel_pch_acs(struct pci_dev * dev)5269 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
5270 {
5271 	if (!pci_quirk_intel_pch_acs_match(dev))
5272 		return -ENOTTY;
5273 
5274 	if (pci_quirk_enable_intel_lpc_acs(dev)) {
5275 		pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
5276 		return 0;
5277 	}
5278 
5279 	pci_quirk_enable_intel_rp_mpc_acs(dev);
5280 
5281 	dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
5282 
5283 	pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
5284 
5285 	return 0;
5286 }
5287 
pci_quirk_enable_intel_spt_pch_acs(struct pci_dev * dev)5288 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
5289 {
5290 	int pos;
5291 	u32 cap, ctrl;
5292 
5293 	if (!pci_quirk_intel_spt_pch_acs_match(dev))
5294 		return -ENOTTY;
5295 
5296 	pos = dev->acs_cap;
5297 	if (!pos)
5298 		return -ENOTTY;
5299 
5300 	pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5301 	pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5302 
5303 	ctrl |= (cap & PCI_ACS_SV);
5304 	ctrl |= (cap & PCI_ACS_RR);
5305 	ctrl |= (cap & PCI_ACS_CR);
5306 	ctrl |= (cap & PCI_ACS_UF);
5307 
5308 	if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
5309 		ctrl |= (cap & PCI_ACS_TB);
5310 
5311 	pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5312 
5313 	pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
5314 
5315 	return 0;
5316 }
5317 
pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev * dev)5318 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
5319 {
5320 	int pos;
5321 	u32 cap, ctrl;
5322 
5323 	if (!pci_quirk_intel_spt_pch_acs_match(dev))
5324 		return -ENOTTY;
5325 
5326 	pos = dev->acs_cap;
5327 	if (!pos)
5328 		return -ENOTTY;
5329 
5330 	pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5331 	pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5332 
5333 	ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
5334 
5335 	pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5336 
5337 	pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
5338 
5339 	return 0;
5340 }
5341 
5342 static const struct pci_dev_acs_ops {
5343 	u16 vendor;
5344 	u16 device;
5345 	int (*enable_acs)(struct pci_dev *dev);
5346 	int (*disable_acs_redir)(struct pci_dev *dev);
5347 } pci_dev_acs_ops[] = {
5348 	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5349 	    .enable_acs = pci_quirk_enable_intel_pch_acs,
5350 	},
5351 	{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5352 	    .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
5353 	    .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
5354 	},
5355 };
5356 
pci_dev_specific_enable_acs(struct pci_dev * dev)5357 int pci_dev_specific_enable_acs(struct pci_dev *dev)
5358 {
5359 	const struct pci_dev_acs_ops *p;
5360 	int i, ret;
5361 
5362 	for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5363 		p = &pci_dev_acs_ops[i];
5364 		if ((p->vendor == dev->vendor ||
5365 		     p->vendor == (u16)PCI_ANY_ID) &&
5366 		    (p->device == dev->device ||
5367 		     p->device == (u16)PCI_ANY_ID) &&
5368 		    p->enable_acs) {
5369 			ret = p->enable_acs(dev);
5370 			if (ret >= 0)
5371 				return ret;
5372 		}
5373 	}
5374 
5375 	return -ENOTTY;
5376 }
5377 
pci_dev_specific_disable_acs_redir(struct pci_dev * dev)5378 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
5379 {
5380 	const struct pci_dev_acs_ops *p;
5381 	int i, ret;
5382 
5383 	for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5384 		p = &pci_dev_acs_ops[i];
5385 		if ((p->vendor == dev->vendor ||
5386 		     p->vendor == (u16)PCI_ANY_ID) &&
5387 		    (p->device == dev->device ||
5388 		     p->device == (u16)PCI_ANY_ID) &&
5389 		    p->disable_acs_redir) {
5390 			ret = p->disable_acs_redir(dev);
5391 			if (ret >= 0)
5392 				return ret;
5393 		}
5394 	}
5395 
5396 	return -ENOTTY;
5397 }
5398 
5399 /*
5400  * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5401  * QuickAssist Technology (QAT) is prematurely terminated in hardware.  The
5402  * Next Capability pointer in the MSI Capability Structure should point to
5403  * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5404  * the list.
5405  */
quirk_intel_qat_vf_cap(struct pci_dev * pdev)5406 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
5407 {
5408 	int pos, i = 0, ret;
5409 	u8 next_cap;
5410 	u16 reg16, *cap;
5411 	struct pci_cap_saved_state *state;
5412 
5413 	/* Bail if the hardware bug is fixed */
5414 	if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
5415 		return;
5416 
5417 	/* Bail if MSI Capability Structure is not found for some reason */
5418 	pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
5419 	if (!pos)
5420 		return;
5421 
5422 	/*
5423 	 * Bail if Next Capability pointer in the MSI Capability Structure
5424 	 * is not the expected incorrect 0x00.
5425 	 */
5426 	pci_read_config_byte(pdev, pos + 1, &next_cap);
5427 	if (next_cap)
5428 		return;
5429 
5430 	/*
5431 	 * PCIe Capability Structure is expected to be at 0x50 and should
5432 	 * terminate the list (Next Capability pointer is 0x00).  Verify
5433 	 * Capability Id and Next Capability pointer is as expected.
5434 	 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5435 	 * to correctly set kernel data structures which have already been
5436 	 * set incorrectly due to the hardware bug.
5437 	 */
5438 	pos = 0x50;
5439 	pci_read_config_word(pdev, pos, &reg16);
5440 	if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
5441 		u32 status;
5442 #ifndef PCI_EXP_SAVE_REGS
5443 #define PCI_EXP_SAVE_REGS     7
5444 #endif
5445 		int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5446 
5447 		pdev->pcie_cap = pos;
5448 		pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
5449 		pdev->pcie_flags_reg = reg16;
5450 		pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
5451 		pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5452 
5453 		pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5454 		ret = pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status);
5455 		if ((ret != PCIBIOS_SUCCESSFUL) || (PCI_POSSIBLE_ERROR(status)))
5456 			pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5457 
5458 		if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
5459 			return;
5460 
5461 		/* Save PCIe cap */
5462 		state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5463 		if (!state)
5464 			return;
5465 
5466 		state->cap.cap_nr = PCI_CAP_ID_EXP;
5467 		state->cap.cap_extended = 0;
5468 		state->cap.size = size;
5469 		cap = (u16 *)&state->cap.data[0];
5470 		pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
5471 		pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
5472 		pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
5473 		pcie_capability_read_word(pdev, PCI_EXP_RTCTL,  &cap[i++]);
5474 		pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
5475 		pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
5476 		pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
5477 		hlist_add_head(&state->next, &pdev->saved_cap_space);
5478 	}
5479 }
5480 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5481 
5482 /*
5483  * FLR may cause the following to devices to hang:
5484  *
5485  * AMD Starship/Matisse HD Audio Controller 0x1487
5486  * AMD Starship USB 3.0 Host Controller 0x148c
5487  * AMD Matisse USB 3.0 Host Controller 0x149c
5488  * Intel 82579LM Gigabit Ethernet Controller 0x1502
5489  * Intel 82579V Gigabit Ethernet Controller 0x1503
5490  *
5491  */
quirk_no_flr(struct pci_dev * dev)5492 static void quirk_no_flr(struct pci_dev *dev)
5493 {
5494 	dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5495 }
5496 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5497 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5498 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5499 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr);
5500 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5501 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5502 
5503 /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */
quirk_no_flr_snet(struct pci_dev * dev)5504 static void quirk_no_flr_snet(struct pci_dev *dev)
5505 {
5506 	if (dev->revision == 0x1)
5507 		quirk_no_flr(dev);
5508 }
5509 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet);
5510 
quirk_no_ext_tags(struct pci_dev * pdev)5511 static void quirk_no_ext_tags(struct pci_dev *pdev)
5512 {
5513 	struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5514 
5515 	if (!bridge)
5516 		return;
5517 
5518 	bridge->no_ext_tags = 1;
5519 	pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5520 
5521 	pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5522 }
5523 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5524 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5525 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5526 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5527 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5528 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5529 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5530 
5531 #ifdef CONFIG_PCI_ATS
quirk_no_ats(struct pci_dev * pdev)5532 static void quirk_no_ats(struct pci_dev *pdev)
5533 {
5534 	pci_info(pdev, "disabling ATS\n");
5535 	pdev->ats_cap = 0;
5536 }
5537 
5538 /*
5539  * Some devices require additional driver setup to enable ATS.  Don't use
5540  * ATS for those devices as ATS will be enabled before the driver has had a
5541  * chance to load and configure the device.
5542  */
quirk_amd_harvest_no_ats(struct pci_dev * pdev)5543 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
5544 {
5545 	if (pdev->device == 0x15d8) {
5546 		if (pdev->revision == 0xcf &&
5547 		    pdev->subsystem_vendor == 0xea50 &&
5548 		    (pdev->subsystem_device == 0xce19 ||
5549 		     pdev->subsystem_device == 0xcc10 ||
5550 		     pdev->subsystem_device == 0xcc08))
5551 			quirk_no_ats(pdev);
5552 	} else {
5553 		quirk_no_ats(pdev);
5554 	}
5555 }
5556 
5557 /* AMD Stoney platform GPU */
5558 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5559 /* AMD Iceland dGPU */
5560 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5561 /* AMD Navi10 dGPU */
5562 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats);
5563 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5564 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats);
5565 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats);
5566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats);
5567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats);
5568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats);
5569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats);
5570 /* AMD Navi14 dGPU */
5571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5573 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats);
5574 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats);
5575 /* AMD Raven platform iGPU */
5576 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
5577 
5578 /*
5579  * Intel IPU E2000 revisions before C0 implement incorrect endianness
5580  * in ATS Invalidate Request message body. Disable ATS for those devices.
5581  */
quirk_intel_e2000_no_ats(struct pci_dev * pdev)5582 static void quirk_intel_e2000_no_ats(struct pci_dev *pdev)
5583 {
5584 	if (pdev->revision < 0x20)
5585 		quirk_no_ats(pdev);
5586 }
5587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats);
5588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats);
5589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats);
5590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats);
5591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats);
5592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);
5593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);
5594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);
5595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);
5596 #endif /* CONFIG_PCI_ATS */
5597 
5598 /* Freescale PCIe doesn't support MSI in RC mode */
quirk_fsl_no_msi(struct pci_dev * pdev)5599 static void quirk_fsl_no_msi(struct pci_dev *pdev)
5600 {
5601 	if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5602 		pdev->no_msi = 1;
5603 }
5604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5605 
5606 /*
5607  * Although not allowed by the spec, some multi-function devices have
5608  * dependencies of one function (consumer) on another (supplier).  For the
5609  * consumer to work in D0, the supplier must also be in D0.  Create a
5610  * device link from the consumer to the supplier to enforce this
5611  * dependency.  Runtime PM is allowed by default on the consumer to prevent
5612  * it from permanently keeping the supplier awake.
5613  */
pci_create_device_link(struct pci_dev * pdev,unsigned int consumer,unsigned int supplier,unsigned int class,unsigned int class_shift)5614 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5615 				   unsigned int supplier, unsigned int class,
5616 				   unsigned int class_shift)
5617 {
5618 	struct pci_dev *supplier_pdev;
5619 
5620 	if (PCI_FUNC(pdev->devfn) != consumer)
5621 		return;
5622 
5623 	supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5624 				pdev->bus->number,
5625 				PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5626 	if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5627 		pci_dev_put(supplier_pdev);
5628 		return;
5629 	}
5630 
5631 	if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5632 			    DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5633 		pci_info(pdev, "D0 power state depends on %s\n",
5634 			 pci_name(supplier_pdev));
5635 	else
5636 		pci_err(pdev, "Cannot enforce power dependency on %s\n",
5637 			pci_name(supplier_pdev));
5638 
5639 	pm_runtime_allow(&pdev->dev);
5640 	pci_dev_put(supplier_pdev);
5641 }
5642 
5643 /*
5644  * Create device link for GPUs with integrated HDA controller for streaming
5645  * audio to attached displays.
5646  */
quirk_gpu_hda(struct pci_dev * hda)5647 static void quirk_gpu_hda(struct pci_dev *hda)
5648 {
5649 	pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5650 }
5651 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5652 			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5653 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5654 			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5655 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5656 			      PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5657 
5658 /*
5659  * Create device link for GPUs with integrated USB xHCI Host
5660  * controller to VGA.
5661  */
quirk_gpu_usb(struct pci_dev * usb)5662 static void quirk_gpu_usb(struct pci_dev *usb)
5663 {
5664 	pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5665 }
5666 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5667 			      PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5668 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5669 			      PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5670 
5671 /*
5672  * Create device link for GPUs with integrated Type-C UCSI controller
5673  * to VGA. Currently there is no class code defined for UCSI device over PCI
5674  * so using UNKNOWN class for now and it will be updated when UCSI
5675  * over PCI gets a class code.
5676  */
5677 #define PCI_CLASS_SERIAL_UNKNOWN	0x0c80
quirk_gpu_usb_typec_ucsi(struct pci_dev * ucsi)5678 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5679 {
5680 	pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5681 }
5682 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5683 			      PCI_CLASS_SERIAL_UNKNOWN, 8,
5684 			      quirk_gpu_usb_typec_ucsi);
5685 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5686 			      PCI_CLASS_SERIAL_UNKNOWN, 8,
5687 			      quirk_gpu_usb_typec_ucsi);
5688 
5689 /*
5690  * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5691  * disabled.  https://devtalk.nvidia.com/default/topic/1024022
5692  */
quirk_nvidia_hda(struct pci_dev * gpu)5693 static void quirk_nvidia_hda(struct pci_dev *gpu)
5694 {
5695 	u8 hdr_type;
5696 	u32 val;
5697 
5698 	/* There was no integrated HDA controller before MCP89 */
5699 	if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5700 		return;
5701 
5702 	/* Bit 25 at offset 0x488 enables the HDA controller */
5703 	pci_read_config_dword(gpu, 0x488, &val);
5704 	if (val & BIT(25))
5705 		return;
5706 
5707 	pci_info(gpu, "Enabling HDA controller\n");
5708 	pci_write_config_dword(gpu, 0x488, val | BIT(25));
5709 
5710 	/* The GPU becomes a multi-function device when the HDA is enabled */
5711 	pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5712 	gpu->multifunction = !!(hdr_type & 0x80);
5713 }
5714 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5715 			       PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5716 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5717 			       PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5718 
5719 /*
5720  * Some IDT switches incorrectly flag an ACS Source Validation error on
5721  * completions for config read requests even though PCIe r4.0, sec
5722  * 6.12.1.1, says that completions are never affected by ACS Source
5723  * Validation.  Here's the text of IDT 89H32H8G3-YC, erratum #36:
5724  *
5725  *   Item #36 - Downstream port applies ACS Source Validation to Completions
5726  *   Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5727  *   completions are never affected by ACS Source Validation.  However,
5728  *   completions received by a downstream port of the PCIe switch from a
5729  *   device that has not yet captured a PCIe bus number are incorrectly
5730  *   dropped by ACS Source Validation by the switch downstream port.
5731  *
5732  * The workaround suggested by IDT is to issue a config write to the
5733  * downstream device before issuing the first config read.  This allows the
5734  * downstream device to capture its bus and device numbers (see PCIe r4.0,
5735  * sec 2.2.9), thus avoiding the ACS error on the completion.
5736  *
5737  * However, we don't know when the device is ready to accept the config
5738  * write, so we do config reads until we receive a non-Config Request Retry
5739  * Status, then do the config write.
5740  *
5741  * To avoid hitting the erratum when doing the config reads, we disable ACS
5742  * SV around this process.
5743  */
pci_idt_bus_quirk(struct pci_bus * bus,int devfn,u32 * l,int timeout)5744 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5745 {
5746 	int pos;
5747 	u16 ctrl = 0;
5748 	bool found;
5749 	struct pci_dev *bridge = bus->self;
5750 
5751 	pos = bridge->acs_cap;
5752 
5753 	/* Disable ACS SV before initial config reads */
5754 	if (pos) {
5755 		pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5756 		if (ctrl & PCI_ACS_SV)
5757 			pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5758 					      ctrl & ~PCI_ACS_SV);
5759 	}
5760 
5761 	found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5762 
5763 	/* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5764 	if (found)
5765 		pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5766 
5767 	/* Re-enable ACS_SV if it was previously enabled */
5768 	if (ctrl & PCI_ACS_SV)
5769 		pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5770 
5771 	return found;
5772 }
5773 
5774 /*
5775  * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5776  * NT endpoints via the internal switch fabric. These IDs replace the
5777  * originating Requester ID TLPs which access host memory on peer NTB
5778  * ports. Therefore, all proxy IDs must be aliased to the NTB device
5779  * to permit access when the IOMMU is turned on.
5780  */
quirk_switchtec_ntb_dma_alias(struct pci_dev * pdev)5781 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5782 {
5783 	void __iomem *mmio;
5784 	struct ntb_info_regs __iomem *mmio_ntb;
5785 	struct ntb_ctrl_regs __iomem *mmio_ctrl;
5786 	u64 partition_map;
5787 	u8 partition;
5788 	int pp;
5789 
5790 	if (pci_enable_device(pdev)) {
5791 		pci_err(pdev, "Cannot enable Switchtec device\n");
5792 		return;
5793 	}
5794 
5795 	mmio = pci_iomap(pdev, 0, 0);
5796 	if (mmio == NULL) {
5797 		pci_disable_device(pdev);
5798 		pci_err(pdev, "Cannot iomap Switchtec device\n");
5799 		return;
5800 	}
5801 
5802 	pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5803 
5804 	mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5805 	mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5806 
5807 	partition = ioread8(&mmio_ntb->partition_id);
5808 
5809 	partition_map = ioread32(&mmio_ntb->ep_map);
5810 	partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5811 	partition_map &= ~(1ULL << partition);
5812 
5813 	for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5814 		struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5815 		u32 table_sz = 0;
5816 		int te;
5817 
5818 		if (!(partition_map & (1ULL << pp)))
5819 			continue;
5820 
5821 		pci_dbg(pdev, "Processing partition %d\n", pp);
5822 
5823 		mmio_peer_ctrl = &mmio_ctrl[pp];
5824 
5825 		table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5826 		if (!table_sz) {
5827 			pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5828 			continue;
5829 		}
5830 
5831 		if (table_sz > 512) {
5832 			pci_warn(pdev,
5833 				 "Invalid Switchtec partition %d table_sz %d\n",
5834 				 pp, table_sz);
5835 			continue;
5836 		}
5837 
5838 		for (te = 0; te < table_sz; te++) {
5839 			u32 rid_entry;
5840 			u8 devfn;
5841 
5842 			rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5843 			devfn = (rid_entry >> 1) & 0xFF;
5844 			pci_dbg(pdev,
5845 				"Aliasing Partition %d Proxy ID %02x.%d\n",
5846 				pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5847 			pci_add_dma_alias(pdev, devfn, 1);
5848 		}
5849 	}
5850 
5851 	pci_iounmap(pdev, mmio);
5852 	pci_disable_device(pdev);
5853 }
5854 #define SWITCHTEC_QUIRK(vid) \
5855 	DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5856 		PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5857 
5858 SWITCHTEC_QUIRK(0x8531);  /* PFX 24xG3 */
5859 SWITCHTEC_QUIRK(0x8532);  /* PFX 32xG3 */
5860 SWITCHTEC_QUIRK(0x8533);  /* PFX 48xG3 */
5861 SWITCHTEC_QUIRK(0x8534);  /* PFX 64xG3 */
5862 SWITCHTEC_QUIRK(0x8535);  /* PFX 80xG3 */
5863 SWITCHTEC_QUIRK(0x8536);  /* PFX 96xG3 */
5864 SWITCHTEC_QUIRK(0x8541);  /* PSX 24xG3 */
5865 SWITCHTEC_QUIRK(0x8542);  /* PSX 32xG3 */
5866 SWITCHTEC_QUIRK(0x8543);  /* PSX 48xG3 */
5867 SWITCHTEC_QUIRK(0x8544);  /* PSX 64xG3 */
5868 SWITCHTEC_QUIRK(0x8545);  /* PSX 80xG3 */
5869 SWITCHTEC_QUIRK(0x8546);  /* PSX 96xG3 */
5870 SWITCHTEC_QUIRK(0x8551);  /* PAX 24XG3 */
5871 SWITCHTEC_QUIRK(0x8552);  /* PAX 32XG3 */
5872 SWITCHTEC_QUIRK(0x8553);  /* PAX 48XG3 */
5873 SWITCHTEC_QUIRK(0x8554);  /* PAX 64XG3 */
5874 SWITCHTEC_QUIRK(0x8555);  /* PAX 80XG3 */
5875 SWITCHTEC_QUIRK(0x8556);  /* PAX 96XG3 */
5876 SWITCHTEC_QUIRK(0x8561);  /* PFXL 24XG3 */
5877 SWITCHTEC_QUIRK(0x8562);  /* PFXL 32XG3 */
5878 SWITCHTEC_QUIRK(0x8563);  /* PFXL 48XG3 */
5879 SWITCHTEC_QUIRK(0x8564);  /* PFXL 64XG3 */
5880 SWITCHTEC_QUIRK(0x8565);  /* PFXL 80XG3 */
5881 SWITCHTEC_QUIRK(0x8566);  /* PFXL 96XG3 */
5882 SWITCHTEC_QUIRK(0x8571);  /* PFXI 24XG3 */
5883 SWITCHTEC_QUIRK(0x8572);  /* PFXI 32XG3 */
5884 SWITCHTEC_QUIRK(0x8573);  /* PFXI 48XG3 */
5885 SWITCHTEC_QUIRK(0x8574);  /* PFXI 64XG3 */
5886 SWITCHTEC_QUIRK(0x8575);  /* PFXI 80XG3 */
5887 SWITCHTEC_QUIRK(0x8576);  /* PFXI 96XG3 */
5888 SWITCHTEC_QUIRK(0x4000);  /* PFX 100XG4 */
5889 SWITCHTEC_QUIRK(0x4084);  /* PFX 84XG4  */
5890 SWITCHTEC_QUIRK(0x4068);  /* PFX 68XG4  */
5891 SWITCHTEC_QUIRK(0x4052);  /* PFX 52XG4  */
5892 SWITCHTEC_QUIRK(0x4036);  /* PFX 36XG4  */
5893 SWITCHTEC_QUIRK(0x4028);  /* PFX 28XG4  */
5894 SWITCHTEC_QUIRK(0x4100);  /* PSX 100XG4 */
5895 SWITCHTEC_QUIRK(0x4184);  /* PSX 84XG4  */
5896 SWITCHTEC_QUIRK(0x4168);  /* PSX 68XG4  */
5897 SWITCHTEC_QUIRK(0x4152);  /* PSX 52XG4  */
5898 SWITCHTEC_QUIRK(0x4136);  /* PSX 36XG4  */
5899 SWITCHTEC_QUIRK(0x4128);  /* PSX 28XG4  */
5900 SWITCHTEC_QUIRK(0x4200);  /* PAX 100XG4 */
5901 SWITCHTEC_QUIRK(0x4284);  /* PAX 84XG4  */
5902 SWITCHTEC_QUIRK(0x4268);  /* PAX 68XG4  */
5903 SWITCHTEC_QUIRK(0x4252);  /* PAX 52XG4  */
5904 SWITCHTEC_QUIRK(0x4236);  /* PAX 36XG4  */
5905 SWITCHTEC_QUIRK(0x4228);  /* PAX 28XG4  */
5906 SWITCHTEC_QUIRK(0x4352);  /* PFXA 52XG4 */
5907 SWITCHTEC_QUIRK(0x4336);  /* PFXA 36XG4 */
5908 SWITCHTEC_QUIRK(0x4328);  /* PFXA 28XG4 */
5909 SWITCHTEC_QUIRK(0x4452);  /* PSXA 52XG4 */
5910 SWITCHTEC_QUIRK(0x4436);  /* PSXA 36XG4 */
5911 SWITCHTEC_QUIRK(0x4428);  /* PSXA 28XG4 */
5912 SWITCHTEC_QUIRK(0x4552);  /* PAXA 52XG4 */
5913 SWITCHTEC_QUIRK(0x4536);  /* PAXA 36XG4 */
5914 SWITCHTEC_QUIRK(0x4528);  /* PAXA 28XG4 */
5915 SWITCHTEC_QUIRK(0x5000);  /* PFX 100XG5 */
5916 SWITCHTEC_QUIRK(0x5084);  /* PFX 84XG5 */
5917 SWITCHTEC_QUIRK(0x5068);  /* PFX 68XG5 */
5918 SWITCHTEC_QUIRK(0x5052);  /* PFX 52XG5 */
5919 SWITCHTEC_QUIRK(0x5036);  /* PFX 36XG5 */
5920 SWITCHTEC_QUIRK(0x5028);  /* PFX 28XG5 */
5921 SWITCHTEC_QUIRK(0x5100);  /* PSX 100XG5 */
5922 SWITCHTEC_QUIRK(0x5184);  /* PSX 84XG5 */
5923 SWITCHTEC_QUIRK(0x5168);  /* PSX 68XG5 */
5924 SWITCHTEC_QUIRK(0x5152);  /* PSX 52XG5 */
5925 SWITCHTEC_QUIRK(0x5136);  /* PSX 36XG5 */
5926 SWITCHTEC_QUIRK(0x5128);  /* PSX 28XG5 */
5927 SWITCHTEC_QUIRK(0x5200);  /* PAX 100XG5 */
5928 SWITCHTEC_QUIRK(0x5284);  /* PAX 84XG5 */
5929 SWITCHTEC_QUIRK(0x5268);  /* PAX 68XG5 */
5930 SWITCHTEC_QUIRK(0x5252);  /* PAX 52XG5 */
5931 SWITCHTEC_QUIRK(0x5236);  /* PAX 36XG5 */
5932 SWITCHTEC_QUIRK(0x5228);  /* PAX 28XG5 */
5933 SWITCHTEC_QUIRK(0x5300);  /* PFXA 100XG5 */
5934 SWITCHTEC_QUIRK(0x5384);  /* PFXA 84XG5 */
5935 SWITCHTEC_QUIRK(0x5368);  /* PFXA 68XG5 */
5936 SWITCHTEC_QUIRK(0x5352);  /* PFXA 52XG5 */
5937 SWITCHTEC_QUIRK(0x5336);  /* PFXA 36XG5 */
5938 SWITCHTEC_QUIRK(0x5328);  /* PFXA 28XG5 */
5939 SWITCHTEC_QUIRK(0x5400);  /* PSXA 100XG5 */
5940 SWITCHTEC_QUIRK(0x5484);  /* PSXA 84XG5 */
5941 SWITCHTEC_QUIRK(0x5468);  /* PSXA 68XG5 */
5942 SWITCHTEC_QUIRK(0x5452);  /* PSXA 52XG5 */
5943 SWITCHTEC_QUIRK(0x5436);  /* PSXA 36XG5 */
5944 SWITCHTEC_QUIRK(0x5428);  /* PSXA 28XG5 */
5945 SWITCHTEC_QUIRK(0x5500);  /* PAXA 100XG5 */
5946 SWITCHTEC_QUIRK(0x5584);  /* PAXA 84XG5 */
5947 SWITCHTEC_QUIRK(0x5568);  /* PAXA 68XG5 */
5948 SWITCHTEC_QUIRK(0x5552);  /* PAXA 52XG5 */
5949 SWITCHTEC_QUIRK(0x5536);  /* PAXA 36XG5 */
5950 SWITCHTEC_QUIRK(0x5528);  /* PAXA 28XG5 */
5951 
5952 /*
5953  * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5954  * These IDs are used to forward responses to the originator on the other
5955  * side of the NTB.  Alias all possible IDs to the NTB to permit access when
5956  * the IOMMU is turned on.
5957  */
quirk_plx_ntb_dma_alias(struct pci_dev * pdev)5958 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
5959 {
5960 	pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
5961 	/* PLX NTB may use all 256 devfns */
5962 	pci_add_dma_alias(pdev, 0, 256);
5963 }
5964 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5965 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
5966 
5967 /*
5968  * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5969  * not always reset the secondary Nvidia GPU between reboots if the system
5970  * is configured to use Hybrid Graphics mode.  This results in the GPU
5971  * being left in whatever state it was in during the *previous* boot, which
5972  * causes spurious interrupts from the GPU, which in turn causes us to
5973  * disable the wrong IRQ and end up breaking the touchpad.  Unsurprisingly,
5974  * this also completely breaks nouveau.
5975  *
5976  * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5977  * clean state and fixes all these issues.
5978  *
5979  * When the machine is configured in Dedicated display mode, the issue
5980  * doesn't occur.  Fortunately the GPU advertises NoReset+ when in this
5981  * mode, so we can detect that and avoid resetting it.
5982  */
quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev * pdev)5983 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5984 {
5985 	void __iomem *map;
5986 	int ret;
5987 
5988 	if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5989 	    pdev->subsystem_device != 0x222e ||
5990 	    !pci_reset_supported(pdev))
5991 		return;
5992 
5993 	if (pci_enable_device_mem(pdev))
5994 		return;
5995 
5996 	/*
5997 	 * Based on nvkm_device_ctor() in
5998 	 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5999 	 */
6000 	map = pci_iomap(pdev, 0, 0x23000);
6001 	if (!map) {
6002 		pci_err(pdev, "Can't map MMIO space\n");
6003 		goto out_disable;
6004 	}
6005 
6006 	/*
6007 	 * Make sure the GPU looks like it's been POSTed before resetting
6008 	 * it.
6009 	 */
6010 	if (ioread32(map + 0x2240c) & 0x2) {
6011 		pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
6012 		ret = pci_reset_bus(pdev);
6013 		if (ret < 0)
6014 			pci_err(pdev, "Failed to reset GPU: %d\n", ret);
6015 	}
6016 
6017 	iounmap(map);
6018 out_disable:
6019 	pci_disable_device(pdev);
6020 }
6021 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
6022 			      PCI_CLASS_DISPLAY_VGA, 8,
6023 			      quirk_reset_lenovo_thinkpad_p50_nvgpu);
6024 
6025 /*
6026  * Device [1b21:2142]
6027  * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
6028  */
pci_fixup_no_d0_pme(struct pci_dev * dev)6029 static void pci_fixup_no_d0_pme(struct pci_dev *dev)
6030 {
6031 	pci_info(dev, "PME# does not work under D0, disabling it\n");
6032 	dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
6033 }
6034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
6035 
6036 /*
6037  * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
6038  *
6039  * These devices advertise PME# support in all power states but don't
6040  * reliably assert it.
6041  *
6042  * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
6043  * says "The MSI Function is not implemented on this device" in chapters
6044  * 7.3.27, 7.3.29-7.3.31.
6045  */
pci_fixup_no_msi_no_pme(struct pci_dev * dev)6046 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev)
6047 {
6048 #ifdef CONFIG_PCI_MSI
6049 	pci_info(dev, "MSI is not implemented on this device, disabling it\n");
6050 	dev->no_msi = 1;
6051 #endif
6052 	pci_info(dev, "PME# is unreliable, disabling it\n");
6053 	dev->pme_support = 0;
6054 }
6055 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
6056 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
6057 
apex_pci_fixup_class(struct pci_dev * pdev)6058 static void apex_pci_fixup_class(struct pci_dev *pdev)
6059 {
6060 	pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
6061 }
6062 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
6063 			       PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);
6064 
6065 /*
6066  * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 -
6067  * ACS P2P Request Redirect is not functional
6068  *
6069  * When ACS P2P Request Redirect is enabled and bandwidth is not balanced
6070  * between upstream and downstream ports, packets are queued in an internal
6071  * buffer until CPLD packet. The workaround is to use the switch in store and
6072  * forward mode.
6073  */
6074 #define PI7C9X2Gxxx_MODE_REG		0x74
6075 #define PI7C9X2Gxxx_STORE_FORWARD_MODE	BIT(0)
pci_fixup_pericom_acs_store_forward(struct pci_dev * pdev)6076 static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev)
6077 {
6078 	struct pci_dev *upstream;
6079 	u16 val;
6080 
6081 	/* Downstream ports only */
6082 	if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)
6083 		return;
6084 
6085 	/* Check for ACS P2P Request Redirect use */
6086 	if (!pdev->acs_cap)
6087 		return;
6088 	pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val);
6089 	if (!(val & PCI_ACS_RR))
6090 		return;
6091 
6092 	upstream = pci_upstream_bridge(pdev);
6093 	if (!upstream)
6094 		return;
6095 
6096 	pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val);
6097 	if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) {
6098 		pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n");
6099 		pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val |
6100 				      PI7C9X2Gxxx_STORE_FORWARD_MODE);
6101 	}
6102 }
6103 /*
6104  * Apply fixup on enable and on resume, in order to apply the fix up whenever
6105  * ACS configuration changes or switch mode is reset
6106  */
6107 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404,
6108 			 pci_fixup_pericom_acs_store_forward);
6109 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404,
6110 			 pci_fixup_pericom_acs_store_forward);
6111 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304,
6112 			 pci_fixup_pericom_acs_store_forward);
6113 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304,
6114 			 pci_fixup_pericom_acs_store_forward);
6115 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303,
6116 			 pci_fixup_pericom_acs_store_forward);
6117 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303,
6118 			 pci_fixup_pericom_acs_store_forward);
6119 
nvidia_ion_ahci_fixup(struct pci_dev * pdev)6120 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev)
6121 {
6122 	pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
6123 }
6124 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
6125 
rom_bar_overlap_defect(struct pci_dev * dev)6126 static void rom_bar_overlap_defect(struct pci_dev *dev)
6127 {
6128 	pci_info(dev, "working around ROM BAR overlap defect\n");
6129 	dev->rom_bar_overlap = 1;
6130 }
6131 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect);
6132 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect);
6133 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect);
6134 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect);
6135 
6136 #ifdef CONFIG_PCIEASPM
6137 /*
6138  * Several Intel DG2 graphics devices advertise that they can only tolerate
6139  * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1
6140  * from being enabled.  But in fact these devices can tolerate unlimited
6141  * latency.  Override their Device Capabilities value to allow ASPM L1 to
6142  * be enabled.
6143  */
aspm_l1_acceptable_latency(struct pci_dev * dev)6144 static void aspm_l1_acceptable_latency(struct pci_dev *dev)
6145 {
6146 	u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap);
6147 
6148 	if (l1_lat < 7) {
6149 		dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7);
6150 		pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n",
6151 			 l1_lat);
6152 	}
6153 }
6154 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency);
6155 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency);
6156 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency);
6157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency);
6158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency);
6159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency);
6160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency);
6161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency);
6162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency);
6163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency);
6164 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency);
6165 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency);
6166 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency);
6167 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency);
6168 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency);
6169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency);
6170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency);
6171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency);
6172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency);
6173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency);
6174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency);
6175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency);
6176 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency);
6177 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency);
6178 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency);
6179 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency);
6180 #endif
6181 
6182 #ifdef CONFIG_PCIE_DPC
6183 /*
6184  * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears
6185  * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root
6186  * Ports.
6187  */
dpc_log_size(struct pci_dev * dev)6188 static void dpc_log_size(struct pci_dev *dev)
6189 {
6190 	u16 dpc, val;
6191 
6192 	dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
6193 	if (!dpc)
6194 		return;
6195 
6196 	pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val);
6197 	if (!(val & PCI_EXP_DPC_CAP_RP_EXT))
6198 		return;
6199 
6200 	if (!((val & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8)) {
6201 		pci_info(dev, "Overriding RP PIO Log Size to 4\n");
6202 		dev->dpc_rp_log_size = 4;
6203 	}
6204 }
6205 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size);
6206 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size);
6207 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size);
6208 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size);
6209 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size);
6210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size);
6211 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size);
6212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size);
6213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size);
6214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size);
6215 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size);
6216 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size);
6217 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size);
6218 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size);
6219 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size);
6220 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size);
6221 #endif
6222 
6223 /*
6224  * For a PCI device with multiple downstream devices, its driver may use
6225  * a flattened device tree to describe the downstream devices.
6226  * To overlay the flattened device tree, the PCI device and all its ancestor
6227  * devices need to have device tree nodes on system base device tree. Thus,
6228  * before driver probing, it might need to add a device tree node as the final
6229  * fixup.
6230  */
6231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
6232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
6233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
6234 
6235 /*
6236  * Devices known to require a longer delay before first config space access
6237  * after reset recovery or resume from D3cold:
6238  *
6239  * VideoPropulsion (aka Genroco) Torrent QN16e MPEG QAM Modulator
6240  */
pci_fixup_d3cold_delay_1sec(struct pci_dev * pdev)6241 static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev)
6242 {
6243 	pdev->d3cold_delay = 1000;
6244 }
6245 DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec);
6246