1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34
35 #include <linux/pm_qos.h>
36
37 #include <drm/ttm/ttm_device.h>
38
39 #include "display/intel_display.h"
40 #include "display/intel_display_core.h"
41
42 #include "gem/i915_gem_context_types.h"
43 #include "gem/i915_gem_lmem.h"
44 #include "gem/i915_gem_shrinker.h"
45 #include "gem/i915_gem_stolen.h"
46
47 #include "gt/intel_engine.h"
48 #include "gt/intel_gt_types.h"
49 #include "gt/intel_region_lmem.h"
50 #include "gt/intel_workarounds.h"
51 #include "gt/uc/intel_uc.h"
52
53 #include "i915_drm_client.h"
54 #include "i915_gem.h"
55 #include "i915_gpu_error.h"
56 #include "i915_params.h"
57 #include "i915_perf_types.h"
58 #include "i915_scheduler.h"
59 #include "i915_utils.h"
60 #include "intel_device_info.h"
61 #include "intel_memory_region.h"
62 #include "intel_pch.h"
63 #include "intel_runtime_pm.h"
64 #include "intel_step.h"
65 #include "intel_uncore.h"
66 #include "intel_wopcm.h"
67
68 struct drm_i915_clock_gating_funcs;
69 struct drm_i915_gem_object;
70 struct drm_i915_private;
71 struct intel_connector;
72 struct intel_dp;
73 struct intel_encoder;
74 struct intel_limit;
75 struct intel_overlay_error_state;
76 struct vlv_s0ix_state;
77
78 /* Threshold == 5 for long IRQs, 50 for short */
79 #define HPD_STORM_DEFAULT_THRESHOLD 50
80
81 #define I915_GEM_GPU_DOMAINS \
82 (I915_GEM_DOMAIN_RENDER | \
83 I915_GEM_DOMAIN_SAMPLER | \
84 I915_GEM_DOMAIN_COMMAND | \
85 I915_GEM_DOMAIN_INSTRUCTION | \
86 I915_GEM_DOMAIN_VERTEX)
87
88 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
89
90 #define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
91
92 struct i915_suspend_saved_registers {
93 u32 saveDSPARB;
94 u32 saveSWF0[16];
95 u32 saveSWF1[16];
96 u32 saveSWF3[3];
97 u16 saveGCDGMBUS;
98 };
99
100 #define MAX_L3_SLICES 2
101 struct intel_l3_parity {
102 u32 *remap_info[MAX_L3_SLICES];
103 struct work_struct error_work;
104 int which_slice;
105 };
106
107 struct i915_gem_mm {
108 /*
109 * Shortcut for the stolen region. This points to either
110 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
111 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
112 * support stolen.
113 */
114 struct intel_memory_region *stolen_region;
115 /** Memory allocator for GTT stolen memory */
116 struct drm_mm stolen;
117 /** Protects the usage of the GTT stolen memory allocator. This is
118 * always the inner lock when overlapping with struct_mutex. */
119 struct mutex stolen_lock;
120
121 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
122 spinlock_t obj_lock;
123
124 /**
125 * List of objects which are purgeable.
126 */
127 struct list_head purge_list;
128
129 /**
130 * List of objects which have allocated pages and are shrinkable.
131 */
132 struct list_head shrink_list;
133
134 /**
135 * List of objects which are pending destruction.
136 */
137 struct llist_head free_list;
138 struct work_struct free_work;
139 /**
140 * Count of objects pending destructions. Used to skip needlessly
141 * waiting on an RCU barrier if no objects are waiting to be freed.
142 */
143 atomic_t free_count;
144
145 /**
146 * tmpfs instance used for shmem backed objects
147 */
148 struct vfsmount *gemfs;
149
150 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
151
152 struct notifier_block oom_notifier;
153 struct notifier_block vmap_notifier;
154 struct shrinker shrinker;
155
156 #ifdef CONFIG_MMU_NOTIFIER
157 /**
158 * notifier_lock for mmu notifiers, memory may not be allocated
159 * while holding this lock.
160 */
161 rwlock_t notifier_lock;
162 #endif
163
164 /* shrinker accounting, also useful for userland debugging */
165 u64 shrink_memory;
166 u32 shrink_count;
167 };
168
169 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
170
171 unsigned long i915_fence_context_timeout(const struct drm_i915_private *i915,
172 u64 context);
173
174 static inline unsigned long
i915_fence_timeout(const struct drm_i915_private * i915)175 i915_fence_timeout(const struct drm_i915_private *i915)
176 {
177 return i915_fence_context_timeout(i915, U64_MAX);
178 }
179
180 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
181
182 struct i915_virtual_gpu {
183 struct mutex lock; /* serialises sending of g2v_notify command pkts */
184 bool active;
185 u32 caps;
186 u32 *initial_mmio;
187 u8 *initial_cfg_space;
188 struct list_head entry;
189 };
190
191 struct i915_selftest_stash {
192 atomic_t counter;
193 struct ida mock_region_instances;
194 };
195
196 struct drm_i915_private {
197 struct drm_device drm;
198
199 struct intel_display display;
200
201 /* FIXME: Device release actions should all be moved to drmm_ */
202 bool do_release;
203
204 /* i915 device parameters */
205 struct i915_params params;
206
207 const struct intel_device_info __info; /* Use INTEL_INFO() to access. */
208 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
209 struct intel_driver_caps caps;
210
211 /**
212 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
213 * end of stolen which we can optionally use to create GEM objects
214 * backed by stolen memory. Note that stolen_usable_size tells us
215 * exactly how much of this we are actually allowed to use, given that
216 * some portion of it is in fact reserved for use by hardware functions.
217 */
218 struct resource dsm;
219 /**
220 * Reseved portion of Data Stolen Memory
221 */
222 struct resource dsm_reserved;
223
224 /*
225 * Stolen memory is segmented in hardware with different portions
226 * offlimits to certain functions.
227 *
228 * The drm_mm is initialised to the total accessible range, as found
229 * from the PCI config. On Broadwell+, this is further restricted to
230 * avoid the first page! The upper end of stolen memory is reserved for
231 * hardware functions and similarly removed from the accessible range.
232 */
233 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
234
235 struct intel_uncore uncore;
236 struct intel_uncore_mmio_debug mmio_debug;
237
238 struct i915_virtual_gpu vgpu;
239
240 struct intel_gvt *gvt;
241
242 struct intel_wopcm wopcm;
243
244 struct pci_dev *bridge_dev;
245
246 struct rb_root uabi_engines;
247 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
248
249 struct resource mch_res;
250
251 /* protects the irq masks */
252 spinlock_t irq_lock;
253
254 bool display_irqs_enabled;
255
256 /* Sideband mailbox protection */
257 struct mutex sb_lock;
258 struct pm_qos_request sb_qos;
259
260 /** Cached value of IMR to avoid reads in updating the bitfield */
261 union {
262 u32 irq_mask;
263 u32 de_irq_mask[I915_MAX_PIPES];
264 };
265 u32 pipestat_irq_mask[I915_MAX_PIPES];
266
267 bool preserve_bios_swizzle;
268
269 unsigned int fsb_freq, mem_freq, is_ddr3;
270 unsigned int skl_preferred_vco_freq;
271
272 unsigned int max_dotclk_freq;
273 unsigned int hpll_freq;
274 unsigned int czclk_freq;
275
276 /**
277 * wq - Driver workqueue for GEM.
278 *
279 * NOTE: Work items scheduled here are not allowed to grab any modeset
280 * locks, for otherwise the flushing done in the pageflip code will
281 * result in deadlocks.
282 */
283 struct workqueue_struct *wq;
284
285 /* pm private clock gating functions */
286 const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
287
288 /* PCH chipset type */
289 enum intel_pch pch_type;
290 unsigned short pch_id;
291
292 unsigned long gem_quirks;
293
294 struct drm_atomic_state *modeset_restore_state;
295 struct drm_modeset_acquire_ctx reset_ctx;
296
297 struct i915_gem_mm mm;
298
299 /* Kernel Modesetting */
300
301 struct list_head global_obj_list;
302
303 bool mchbar_need_disable;
304
305 struct intel_l3_parity l3_parity;
306
307 /*
308 * HTI (aka HDPORT) state read during initial hw readout. Most
309 * platforms don't have HTI, so this will just stay 0. Those that do
310 * will use this later to figure out which PLLs and PHYs are unavailable
311 * for driver usage.
312 */
313 u32 hti_state;
314
315 /*
316 * edram size in MB.
317 * Cannot be determined by PCIID. You must always read a register.
318 */
319 u32 edram_size_mb;
320
321 struct i915_gpu_error gpu_error;
322
323 /*
324 * Shadows for CHV DPLL_MD regs to keep the state
325 * checker somewhat working in the presence hardware
326 * crappiness (can't read out DPLL_MD for pipes B & C).
327 */
328 u32 chv_dpll_md[I915_MAX_PIPES];
329 u32 bxt_phy_grc;
330
331 u32 suspend_count;
332 struct i915_suspend_saved_registers regfile;
333 struct vlv_s0ix_state *vlv_s0ix_state;
334
335 struct dram_info {
336 bool wm_lv_0_adjust_needed;
337 u8 num_channels;
338 bool symmetric_memory;
339 enum intel_dram_type {
340 INTEL_DRAM_UNKNOWN,
341 INTEL_DRAM_DDR3,
342 INTEL_DRAM_DDR4,
343 INTEL_DRAM_LPDDR3,
344 INTEL_DRAM_LPDDR4,
345 INTEL_DRAM_DDR5,
346 INTEL_DRAM_LPDDR5,
347 } type;
348 u8 num_qgv_points;
349 u8 num_psf_gv_points;
350 } dram_info;
351
352 struct intel_runtime_pm runtime_pm;
353
354 struct i915_perf perf;
355
356 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
357 struct intel_gt gt0;
358
359 /*
360 * i915->gt[0] == &i915->gt0
361 */
362 #define I915_MAX_GT 4
363 struct intel_gt *gt[I915_MAX_GT];
364
365 struct kobject *sysfs_gt;
366
367 /* Quick lookup of media GT (current platforms only have one) */
368 struct intel_gt *media_gt;
369
370 struct {
371 struct i915_gem_contexts {
372 spinlock_t lock; /* locks list */
373 struct list_head list;
374 } contexts;
375
376 /*
377 * We replace the local file with a global mappings as the
378 * backing storage for the mmap is on the device and not
379 * on the struct file, and we do not want to prolong the
380 * lifetime of the local fd. To minimise the number of
381 * anonymous inodes we create, we use a global singleton to
382 * share the global mapping.
383 */
384 struct file *mmap_singleton;
385 } gem;
386
387 u8 pch_ssc_use;
388
389 /* For i915gm/i945gm vblank irq workaround */
390 u8 vblank_enabled;
391
392 bool irq_enabled;
393
394 /*
395 * DG2: Mask of PHYs that were not calibrated by the firmware
396 * and should not be used.
397 */
398 u8 snps_phy_failed_calibration;
399
400 struct i915_pmu pmu;
401
402 struct i915_drm_clients clients;
403
404 /* The TTM device structure. */
405 struct ttm_device bdev;
406
407 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
408
409 /*
410 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
411 * will be rejected. Instead look for a better place.
412 */
413 };
414
to_i915(const struct drm_device * dev)415 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
416 {
417 return container_of(dev, struct drm_i915_private, drm);
418 }
419
kdev_to_i915(struct device * kdev)420 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
421 {
422 return dev_get_drvdata(kdev);
423 }
424
pdev_to_i915(struct pci_dev * pdev)425 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
426 {
427 return pci_get_drvdata(pdev);
428 }
429
to_gt(struct drm_i915_private * i915)430 static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
431 {
432 return &i915->gt0;
433 }
434
435 /* Simple iterator over all initialised engines */
436 #define for_each_engine(engine__, dev_priv__, id__) \
437 for ((id__) = 0; \
438 (id__) < I915_NUM_ENGINES; \
439 (id__)++) \
440 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
441
442 /* Iterator over subset of engines selected by mask */
443 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
444 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
445 (tmp__) ? \
446 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
447 0;)
448
449 #define rb_to_uabi_engine(rb) \
450 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
451
452 #define for_each_uabi_engine(engine__, i915__) \
453 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
454 (engine__); \
455 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
456
457 #define for_each_uabi_class_engine(engine__, class__, i915__) \
458 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
459 (engine__) && (engine__)->uabi_class == (class__); \
460 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
461
462 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
463 #define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
464 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
465
466 #define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
467
468 #define IP_VER(ver, rel) ((ver) << 8 | (rel))
469
470 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
471 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
472 RUNTIME_INFO(i915)->graphics.ip.rel)
473 #define IS_GRAPHICS_VER(i915, from, until) \
474 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
475
476 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
477 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
478 RUNTIME_INFO(i915)->media.ip.rel)
479 #define IS_MEDIA_VER(i915, from, until) \
480 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
481
482 #define DISPLAY_VER(i915) (RUNTIME_INFO(i915)->display.ip.ver)
483 #define IS_DISPLAY_VER(i915, from, until) \
484 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
485
486 #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
487
488 #define HAS_DSB(dev_priv) (INTEL_INFO(dev_priv)->display.has_dsb)
489
490 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
491 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
492 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
493 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
494
495 #define IS_DISPLAY_STEP(__i915, since, until) \
496 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
497 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
498
499 #define IS_GRAPHICS_STEP(__i915, since, until) \
500 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
501 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
502
503 #define IS_MEDIA_STEP(__i915, since, until) \
504 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
505 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
506
507 #define IS_BASEDIE_STEP(__i915, since, until) \
508 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
509 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
510
511 static __always_inline unsigned int
__platform_mask_index(const struct intel_runtime_info * info,enum intel_platform p)512 __platform_mask_index(const struct intel_runtime_info *info,
513 enum intel_platform p)
514 {
515 const unsigned int pbits =
516 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
517
518 /* Expand the platform_mask array if this fails. */
519 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
520 pbits * ARRAY_SIZE(info->platform_mask));
521
522 return p / pbits;
523 }
524
525 static __always_inline unsigned int
__platform_mask_bit(const struct intel_runtime_info * info,enum intel_platform p)526 __platform_mask_bit(const struct intel_runtime_info *info,
527 enum intel_platform p)
528 {
529 const unsigned int pbits =
530 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
531
532 return p % pbits + INTEL_SUBPLATFORM_BITS;
533 }
534
535 static inline u32
intel_subplatform(const struct intel_runtime_info * info,enum intel_platform p)536 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
537 {
538 const unsigned int pi = __platform_mask_index(info, p);
539
540 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
541 }
542
543 static __always_inline bool
IS_PLATFORM(const struct drm_i915_private * i915,enum intel_platform p)544 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
545 {
546 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
547 const unsigned int pi = __platform_mask_index(info, p);
548 const unsigned int pb = __platform_mask_bit(info, p);
549
550 BUILD_BUG_ON(!__builtin_constant_p(p));
551
552 return info->platform_mask[pi] & BIT(pb);
553 }
554
555 static __always_inline bool
IS_SUBPLATFORM(const struct drm_i915_private * i915,enum intel_platform p,unsigned int s)556 IS_SUBPLATFORM(const struct drm_i915_private *i915,
557 enum intel_platform p, unsigned int s)
558 {
559 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
560 const unsigned int pi = __platform_mask_index(info, p);
561 const unsigned int pb = __platform_mask_bit(info, p);
562 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
563 const u32 mask = info->platform_mask[pi];
564
565 BUILD_BUG_ON(!__builtin_constant_p(p));
566 BUILD_BUG_ON(!__builtin_constant_p(s));
567 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
568
569 /* Shift and test on the MSB position so sign flag can be used. */
570 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
571 }
572
573 #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
574 #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx)
575
576 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
577 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
578 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
579 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
580 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
581 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
582 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
583 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
584 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
585 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
586 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
587 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
588 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
589 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
590 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
591 #define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
592 #define IS_IRONLAKE_M(dev_priv) \
593 (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
594 #define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
595 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
596 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
597 INTEL_INFO(dev_priv)->gt == 1)
598 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
599 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
600 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
601 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
602 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
603 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
604 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
605 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
606 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
607 #define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
608 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
609 #define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
610 IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
611 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
612 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
613 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
614 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
615 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
616 #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
617 #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2)
618 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
619 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
620
621 #define IS_METEORLAKE_M(dev_priv) \
622 IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
623 #define IS_METEORLAKE_P(dev_priv) \
624 IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
625 #define IS_DG2_G10(dev_priv) \
626 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
627 #define IS_DG2_G11(dev_priv) \
628 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
629 #define IS_DG2_G12(dev_priv) \
630 IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
631 #define IS_ADLS_RPLS(dev_priv) \
632 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
633 #define IS_ADLP_N(dev_priv) \
634 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
635 #define IS_ADLP_RPLP(dev_priv) \
636 IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
637 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
638 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
639 #define IS_BDW_ULT(dev_priv) \
640 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
641 #define IS_BDW_ULX(dev_priv) \
642 IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
643 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
644 INTEL_INFO(dev_priv)->gt == 3)
645 #define IS_HSW_ULT(dev_priv) \
646 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
647 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
648 INTEL_INFO(dev_priv)->gt == 3)
649 #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
650 INTEL_INFO(dev_priv)->gt == 1)
651 /* ULX machines are also considered ULT. */
652 #define IS_HSW_ULX(dev_priv) \
653 IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
654 #define IS_SKL_ULT(dev_priv) \
655 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
656 #define IS_SKL_ULX(dev_priv) \
657 IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
658 #define IS_KBL_ULT(dev_priv) \
659 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
660 #define IS_KBL_ULX(dev_priv) \
661 IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
662 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
663 INTEL_INFO(dev_priv)->gt == 2)
664 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
665 INTEL_INFO(dev_priv)->gt == 3)
666 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
667 INTEL_INFO(dev_priv)->gt == 4)
668 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
669 INTEL_INFO(dev_priv)->gt == 2)
670 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
671 INTEL_INFO(dev_priv)->gt == 3)
672 #define IS_CFL_ULT(dev_priv) \
673 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
674 #define IS_CFL_ULX(dev_priv) \
675 IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
676 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
677 INTEL_INFO(dev_priv)->gt == 2)
678 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
679 INTEL_INFO(dev_priv)->gt == 3)
680
681 #define IS_CML_ULT(dev_priv) \
682 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
683 #define IS_CML_ULX(dev_priv) \
684 IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
685 #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \
686 INTEL_INFO(dev_priv)->gt == 2)
687
688 #define IS_ICL_WITH_PORT_F(dev_priv) \
689 IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
690
691 #define IS_TGL_UY(dev_priv) \
692 IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
693
694 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
695
696 #define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \
697 (IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
698 #define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
699 (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
700
701 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
702 (IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
703 #define IS_JSL_EHL_DISPLAY_STEP(p, since, until) \
704 (IS_JSL_EHL(p) && IS_DISPLAY_STEP(p, since, until))
705
706 #define IS_TGL_DISPLAY_STEP(__i915, since, until) \
707 (IS_TIGERLAKE(__i915) && \
708 IS_DISPLAY_STEP(__i915, since, until))
709
710 #define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
711 (IS_TGL_UY(__i915) && \
712 IS_GRAPHICS_STEP(__i915, since, until))
713
714 #define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
715 (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
716 IS_GRAPHICS_STEP(__i915, since, until))
717
718 #define IS_RKL_DISPLAY_STEP(p, since, until) \
719 (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
720
721 #define IS_DG1_GRAPHICS_STEP(p, since, until) \
722 (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
723 #define IS_DG1_DISPLAY_STEP(p, since, until) \
724 (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
725
726 #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
727 (IS_ALDERLAKE_S(__i915) && \
728 IS_DISPLAY_STEP(__i915, since, until))
729
730 #define IS_ADLS_GRAPHICS_STEP(__i915, since, until) \
731 (IS_ALDERLAKE_S(__i915) && \
732 IS_GRAPHICS_STEP(__i915, since, until))
733
734 #define IS_ADLP_DISPLAY_STEP(__i915, since, until) \
735 (IS_ALDERLAKE_P(__i915) && \
736 IS_DISPLAY_STEP(__i915, since, until))
737
738 #define IS_ADLP_GRAPHICS_STEP(__i915, since, until) \
739 (IS_ALDERLAKE_P(__i915) && \
740 IS_GRAPHICS_STEP(__i915, since, until))
741
742 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
743 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
744
745 /*
746 * DG2 hardware steppings are a bit unusual. The hardware design was forked to
747 * create three variants (G10, G11, and G12) which each have distinct
748 * workaround sets. The G11 and G12 forks of the DG2 design reset the GT
749 * stepping back to "A0" for their first iterations, even though they're more
750 * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
751 * functionality and workarounds. However the display stepping does not reset
752 * in the same manner --- a specific stepping like "B0" has a consistent
753 * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
754 *
755 * TLDR: All GT workarounds and stepping-specific logic must be applied in
756 * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
757 * and stepping-specific logic will be applied with a general DG2-wide stepping
758 * number.
759 */
760 #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
761 (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
762 IS_GRAPHICS_STEP(__i915, since, until))
763
764 #define IS_DG2_DISPLAY_STEP(__i915, since, until) \
765 (IS_DG2(__i915) && \
766 IS_DISPLAY_STEP(__i915, since, until))
767
768 #define IS_PVC_BD_STEP(__i915, since, until) \
769 (IS_PONTEVECCHIO(__i915) && \
770 IS_BASEDIE_STEP(__i915, since, until))
771
772 #define IS_PVC_CT_STEP(__i915, since, until) \
773 (IS_PONTEVECCHIO(__i915) && \
774 IS_GRAPHICS_STEP(__i915, since, until))
775
776 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
777 #define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
778 #define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
779
780 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
781 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
782
783 #define ENGINE_INSTANCES_MASK(gt, first, count) ({ \
784 unsigned int first__ = (first); \
785 unsigned int count__ = (count); \
786 ((gt)->info.engine_mask & \
787 GENMASK(first__ + count__ - 1, first__)) >> first__; \
788 })
789 #define RCS_MASK(gt) \
790 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
791 #define BCS_MASK(gt) \
792 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
793 #define VDBOX_MASK(gt) \
794 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
795 #define VEBOX_MASK(gt) \
796 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
797 #define CCS_MASK(gt) \
798 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
799
800 #define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
801
802 /*
803 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
804 * All later gens can run the final buffer from the ppgtt
805 */
806 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
807
808 #define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
809 #define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
810 #define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
811 #define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
812 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
813 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv)
814
815 #define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
816
817 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
818 (INTEL_INFO(dev_priv)->has_logical_ring_contexts)
819 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
820 (INTEL_INFO(dev_priv)->has_logical_ring_elsq)
821
822 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
823
824 #define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
825 #define HAS_PPGTT(dev_priv) \
826 (INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
827 #define HAS_FULL_PPGTT(dev_priv) \
828 (INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
829
830 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
831 GEM_BUG_ON((sizes) == 0); \
832 ((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
833 })
834
835 #define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
836 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
837 (INTEL_INFO(dev_priv)->display.overlay_needs_physical)
838
839 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
840 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
841
842 #define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv) \
843 (IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
844
845 /* WaRsDisableCoarsePowerGating:skl,cnl */
846 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
847 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
848
849 #define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
850 #define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
851 IS_GEMINILAKE(dev_priv) || \
852 IS_KABYLAKE(dev_priv))
853
854 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
855 * rows, which changed the alignment requirements and fence programming.
856 */
857 #define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
858 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
859 #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
860 #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
861
862 #define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2)
863 #define HAS_FBC(dev_priv) (RUNTIME_INFO(dev_priv)->fbc_mask != 0)
864 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
865
866 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
867
868 #define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
869 #define HAS_DP20(dev_priv) (IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
870
871 #define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
872
873 #define HAS_CDCLK_CRAWL(dev_priv) (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
874 #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
875 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
876 #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
877 #define HAS_PSR_HW_TRACKING(dev_priv) \
878 (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
879 #define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12)
880 #define HAS_TRANSCODER(dev_priv, trans) ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
881
882 #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
883 #define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
884 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
885
886 #define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps)
887
888 #define HAS_DMC(dev_priv) (RUNTIME_INFO(dev_priv)->has_dmc)
889
890 #define HAS_HECI_PXP(dev_priv) \
891 (INTEL_INFO(dev_priv)->has_heci_pxp)
892
893 #define HAS_HECI_GSCFI(dev_priv) \
894 (INTEL_INFO(dev_priv)->has_heci_gscfi)
895
896 #define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
897
898 #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
899
900 #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
901 #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
902
903 /*
904 * Set this flag, when platform requires 64K GTT page sizes or larger for
905 * device local memory access.
906 */
907 #define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
908
909 /*
910 * Set this flag when platform doesn't allow both 64k pages and 4k pages in
911 * the same PT. this flag means we need to support compact PT layout for the
912 * ppGTT when using the 64K GTT pages.
913 */
914 #define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
915
916 #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
917
918 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
919 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
920
921 #define HAS_EXTRA_GT_LIST(dev_priv) (INTEL_INFO(dev_priv)->extra_gt_list)
922
923 /*
924 * Platform has the dedicated compression control state for each lmem surfaces
925 * stored in lmem to support the 3D and media compression formats.
926 */
927 #define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs)
928
929 #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
930
931 #define HAS_POOLED_EU(dev_priv) (RUNTIME_INFO(dev_priv)->has_pooled_eu)
932
933 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
934
935 #define HAS_PXP(dev_priv) ((IS_ENABLED(CONFIG_DRM_I915_PXP) && \
936 INTEL_INFO(dev_priv)->has_pxp) && \
937 VDBOX_MASK(to_gt(dev_priv)))
938
939 #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
940
941 #define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
942
943 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
944
945 /* DPF == dynamic parity feature */
946 #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
947 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
948 2 : HAS_L3_DPF(dev_priv))
949
950 #define GT_FREQUENCY_MULTIPLIER 50
951 #define GEN9_FREQ_SCALER 3
952
953 #define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
954
955 #define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
956
957 #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
958
959 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
960
961 /* Only valid when HAS_DISPLAY() is true */
962 #define INTEL_DISPLAY_ENABLED(dev_priv) \
963 (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), \
964 !(dev_priv)->params.disable_display && \
965 !intel_opregion_headless_sku(dev_priv))
966
967 #define HAS_GUC_DEPRIVILEGE(dev_priv) \
968 (INTEL_INFO(dev_priv)->has_guc_deprivilege)
969
970 #define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
971 IS_ALDERLAKE_S(dev_priv))
972
973 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
974
975 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
976
977 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
978
979 /* intel_device_info.c */
980 static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private * dev_priv)981 mkwrite_device_info(struct drm_i915_private *dev_priv)
982 {
983 return (struct intel_device_info *)INTEL_INFO(dev_priv);
984 }
985
986 static inline enum i915_map_type
i915_coherent_map_type(struct drm_i915_private * i915,struct drm_i915_gem_object * obj,bool always_coherent)987 i915_coherent_map_type(struct drm_i915_private *i915,
988 struct drm_i915_gem_object *obj, bool always_coherent)
989 {
990 if (i915_gem_object_is_lmem(obj))
991 return I915_MAP_WC;
992 if (HAS_LLC(i915) || always_coherent)
993 return I915_MAP_WB;
994 else
995 return I915_MAP_WC;
996 }
997
998 #endif
999